URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- This comparison shows the changes necessary to convert path
/
- from Rev 609 to Rev 610
- ↔ Reverse comparison
Rev 609 → Rev 610
/trunk/or1200/rtl/verilog/or1200_sprs.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/19 09:27:49 lampret |
// SR[TEE] should be zero after reset. |
// |
// Revision 1.2 2002/01/18 07:56:00 lampret |
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. |
// |
307,7 → 310,7
// |
always @(posedge clk or posedge rst) |
if (rst) |
sr <= #1 `OR1200_SR_WIDTH'b001; |
sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1}; |
else if (except_started) begin |
sr[`OR1200_SR_SM] <= #1 1'b1; |
sr[`OR1200_SR_TEE] <= #1 1'b0; |
/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
61,6 → 61,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/19 14:10:22 lampret |
// Fixed OR1200_XILINX_RAM32X1D. |
// |
// Revision 1.2 2002/01/15 06:12:22 lampret |
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D |
// |
245,7 → 248,9
reg [4:0] addr_a_r; |
|
always @(posedge clk_a or posedge rst_a) |
if (ce_a) |
if (rst_a) |
addr_a_r <= #1 5'b00000; |
else if (ce_a) |
addr_a_r <= #1 addr_a; |
|
// |
/trunk/or1200/rtl/verilog/or1200_except.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2002/01/18 14:21:43 lampret |
// Fixed 'the NPC single-step fix'. |
// |
// Revision 1.5 2002/01/18 07:56:00 lampret |
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. |
// |
210,7 → 213,8
//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan |
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush; |
assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; |
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; |
//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; |
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot; |
|
// |
// Order defines exception detection priority |
372,7 → 376,7
extend_flush <= #1 1'b0; |
epcr <= #1 32'b0; |
eear <= #1 32'b0; |
esr <= #1 `OR1200_SR_WIDTH'b001; |
esr <= #1 {1'b1, {`OR1200_SR_WIDTH-3{1'b0}}, 2'b11}; |
extend_flush_last <= #1 1'b0; |
end |
else begin |
433,7 → 437,8
end |
13'b0_0001_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_ILLEGAL; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; |
eear <= #1 ex_pc; |
epcr <= #1 ex_dslot ? wb_pc : ex_pc; |
end |
13'b0_0000_1xxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_ALIGN; |
465,7 → 470,8
end |
13'b0_0000_0000_001x: begin |
except_type <= #1 `OR1200_EXCEPT_TRAP; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; |
eear <= #1 32'h0000_0000; |
epcr <= #1 ex_dslot ? wb_pc : ex_pc; |
end |
13'b0_0000_0000_0001: begin |
except_type <= #1 `OR1200_EXCEPT_SYSCALL; |