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Rev 61 → Rev 62
/trunk/or1ksim/mmu/dmmu.c
1,4 → 1,4
/* dmmu.c -- data mmu simulation |
/* dmmu.c -- Data MMU simulation |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
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This file is part of OpenRISC 1000 Architectural Simulator. |
19,145 → 19,147
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/* DMMU model (not functional yet, currently just copy of data cache). */ |
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#include "dmmu.h" |
#include "abstract.h" |
#include "stats.h" |
#include "sprs.h" |
#include "except.h" |
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extern int cont_run; |
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/* Data MMU */ |
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unsigned long dmmu_translate(unsigned long virtaddr) |
{ |
return virtaddr; |
unsigned long phyaddr = dmmu_simulate_tlb(virtaddr); |
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printf("DMMU translate(%x) = %x\n", virtaddr, phyaddr); |
return phyaddr; |
} |
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/* Number of DC sets (power of 2) */ |
#define DC_SETS 256 |
/* Number of DTLB sets used (power of 2, max is 256) */ |
#define DTLB_SETS 16 |
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/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */ |
#define DC_BLOCK_SIZE 4 |
/* Entry size in bytes (8 == two singlewords) */ |
#define DTLB_ENTRY_SIZE 8 |
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/* Number of DC ways (1, 2, 3 etc.). */ |
#define DC_WAYS 1 |
/* Number of DTLB ways (1, 2, 3 etc., max is 4). */ |
#define DTLB_WAYS 2 |
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/* Number of usage states (2, 3, 4 etc.). */ |
#define DC_USTATES 2 |
/* Number of usage states (2, 3, 4 etc., max is 4). */ |
#define DTLB_USTATES 2 |
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struct dc_set { |
struct { |
unsigned long tagaddr; /* tag address */ |
int lru; /* least recently used */ |
} way[DC_WAYS]; |
} dc[DC_SETS]; |
/* Don't change. Defined by mask of PPN/VPN bits in TLB. */ |
#define MIN_PG_SIZE 1024 |
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void xdc_info() |
void dtlb_info() |
{ |
printf("Data cache %dKB: ", DC_SETS * DC_BLOCK_SIZE * DC_WAYS / 1024); |
printf("%d ways, %d sets, block size %d bytes\n", DC_WAYS, DC_SETS, DC_BLOCK_SIZE); |
printf("Data MMU %dKB: ", DTLB_SETS * DTLB_ENTRY_SIZE * DTLB_WAYS / 1024); |
printf("%d ways, %d sets, entry size %d bytes\n", DTLB_WAYS, DTLB_SETS, DTLB_ENTRY_SIZE); |
} |
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/* First check if data is already in the cache and if it is: |
- increment DC read hit stats, |
- set 'lru' at this way to DC_USTATES - 1 and |
/* First check if virtual address is covered by DTLB and if it is: |
- increment DTLB read hit stats, |
- set 'lru' at this way to DTLB_USTATES - 1 and |
decrement 'lru' of other ways unless they have reached 0, |
- check page access attributes and invoke DMMU page fault exception |
handler if necessary |
and if not: |
- increment DC read miss stats |
- find lru way and entry and replace old tag with tag of the 'dataaddr' |
- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other |
- increment DTLB read miss stats |
- find lru way and entry and invoke DTLB miss exception handler |
- set 'lru' with DTLB_USTATES - 1 and decrement 'lru' of other |
ways unless they have reached 0 |
*/ |
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void xdc_simulate_read(unsigned long dataaddr) |
unsigned long dtlb_status(int start_set) |
{ |
int set, way = -1; |
int i; |
unsigned long tagaddr; |
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/* Which set to check out? */ |
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS; |
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS; |
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/* Scan all ways and try to find a matching way. */ |
for (i = 0; i < DC_WAYS; i++) |
if (dc[set].way[i].tagaddr == tagaddr) |
way = i; |
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/* Did we find our cached data? */ |
if (way >= 0) { /* Yes, we did. */ |
dc_stats.readhit++; |
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for (i = 0; i < DC_WAYS; i++) |
if (dc[set].way[i].lru) |
dc[set].way[i].lru--; |
dc[set].way[way].lru = DC_USTATES - 1; |
int set; |
int way; |
int end_set = DTLB_SETS; |
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if ((start_set >= 0) && (start_set < end_set)) |
end_set = start_set + 1; |
else |
start_set = 0; |
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/* Scan set(s) and way(s). */ |
for (set = start_set; set < end_set; set++) { |
printf("\nSet %x: ", set); |
for (way = 0; way < DTLB_WAYS; way++) { |
printf(" way %d: ", way); |
printf("vpn %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_VPN)); |
printf("lru %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU)); |
printf("pl1 %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_PL1)); |
printf("v %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_V)); |
printf("a %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBTR_A)); |
printf("d %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBTR_D)); |
printf("ure %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBTR_URE)); |
printf("uwe %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBTR_UWE)); |
printf("sre %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBTR_SRE)); |
printf("swe %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBTR_SWE)); |
printf("ppn %x ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBTR_PPN)); |
if (way > 0) |
printf("\n"); |
} |
} |
else { /* No, we didn't. */ |
int minlru = DC_USTATES - 1; |
int minway = 0; |
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dc_stats.readmiss++; |
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for (i = 0; i < DC_WAYS; i++) |
if (dc[set].way[i].lru < minlru) |
minway = i; |
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dc[set].way[minway].tagaddr = tagaddr; |
for (i = 0; i < DC_WAYS; i++) |
if (dc[set].way[i].lru) |
dc[set].way[i].lru--; |
dc[set].way[minway].lru = DC_USTATES - 1; |
} |
printf("\n"); |
} |
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/* First check if data is already in the cache and if it is: |
- increment DC write hit stats, |
- set 'lru' at this way to DC_USTATES - 1 and |
decrement 'lru' of other ways unless they have reached 0, |
and if not: |
- increment DC write miss stats |
- find lru way and entry and replace old tag with tag of the 'dataaddr' |
- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other |
ways unless they have reached 0 |
*/ |
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void xdc_simulate_write(unsigned long dataaddr) |
unsigned long dmmu_simulate_tlb(unsigned long virtaddr) |
{ |
int set, way = -1; |
int i; |
unsigned long tagaddr; |
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unsigned long vpn; |
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if (! (mfspr(SPR_SR) & SPR_SR_DME)) |
return virtaddr; |
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/* Which set to check out? */ |
set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS; |
tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS; |
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set = (virtaddr / PAGE_SIZE) % DTLB_SETS; |
tagaddr = (virtaddr / PAGE_SIZE) / DTLB_SETS; |
vpn = virtaddr / MIN_PG_SIZE; |
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/* Scan all ways and try to find a matching way. */ |
for (i = 0; i < DC_WAYS; i++) |
if (dc[set].way[i].tagaddr == tagaddr) |
for (i = 0; i < DTLB_WAYS; i++) |
if ((getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_VPN) == vpn) && |
getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_V)) |
way = i; |
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/* Did we find our cached data? */ |
/* Did we find our tlb entry? */ |
if (way >= 0) { /* Yes, we did. */ |
dc_stats.writehit++; |
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for (i = 0; i < DC_WAYS; i++) |
if (dc[set].way[i].lru) |
dc[set].way[i].lru--; |
dc[set].way[way].lru = DC_USTATES - 1; |
dmmu_stats.loads_tlbhit++; |
debug("DTLB hit (virtaddr=%x).\n", virtaddr); |
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/* Set LRUs */ |
for (i = 0; i < DTLB_WAYS; i++) |
if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU)) |
setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1); |
setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, DTLB_USTATES - 1); |
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return getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_PPN) * MIN_PG_SIZE + (virtaddr % PAGE_SIZE); |
} |
else { /* No, we didn't. */ |
int minlru = DC_USTATES - 1; |
int minlru = DTLB_USTATES - 1; |
int minway = 0; |
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dc_stats.writemiss++; |
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for (i = 0; i < DC_WAYS; i++) |
if (dc[set].way[i].lru < minlru) |
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dmmu_stats.loads_tlbmiss++; |
#if 0 |
for (i = 0; i < DTLB_WAYS; i++) |
if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) < minlru) |
minway = i; |
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dc[set].way[minway].tagaddr = tagaddr; |
for (i = 0; i < DC_WAYS; i++) |
if (dc[set].way[i].lru) |
dc[set].way[i].lru--; |
dc[set].way[minway].lru = DC_USTATES - 1; |
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_VPN, vpn); |
for (i = 0; i < DTLB_WAYS; i++) |
if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU)) |
setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1); |
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_LRU, DTLB_USTATES - 1); |
setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */ |
setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1); |
#endif |
except_handle(EXCEPT_DTLBMISS, virtaddr); |
/* if tlb refill implemented in HW */ |
/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * MIN_PG_SIZE + (virtaddr % PAGE_SIZE); */ |
return 0; |
} |
} |
/trunk/or1ksim/mmu/dmmu.h
1,4 → 1,4
/* dmmu.h -- data mmu header file |
/* dmmu.h -- Data MMU header file |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
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This file is part of OpenRISC 1000 Architectural Simulator. |
18,5 → 18,9
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
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/* more or less useless at the moment */ |
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/* Page size (in bytes) */ |
#define PAGE_SIZE 4096 /* 4KB page size */ |
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unsigned long dmmu_translate(unsigned long virtaddr); |