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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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    from Rev 61 to Rev 62
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Rev 61 → Rev 62

/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
73,6 → 73,7
SDCommandR7 voltageresponse;
SDCommandR1 response;
SDCommandR3 acmd41response;
SDCommandR2 cidresponse;
SDOCR ocr;
// expect CMD0 so that state is clear
129,6 → 130,14
acmd41response = new(ocr);
acmd41response.send(ICmd);
 
// expect CMD2
recv();
assert(recvcmd.id == cSdCmdAllSendCID);
 
// respond with R2
cidresponse = new();
cidresponse.send(ICmd);
 
-> InitDone;
 
endtask
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCommand.sv
184,3 → 184,43
 
endclass
 
include "../../unitSdCardModel/src/SDCID.sv";
class SDCommandR2 extends SDCommandResponse;
local SDCID cid;
function new();
startbit = 0;
transbit = 0;
this.id = 'b111111;
this.cid = new();
this.cid.randomize();
endbit = 1;
endfunction
 
task automatic send(virtual ISdCmd.Card ICmd);
logic data[$];
cidreg_t cidreg;
 
// fill queue
data.push_back(startbit);
data.push_back(transbit);
for (int i = 5; i >= 0; i--)
data.push_back(id[i]);
 
cidreg = cid.get();
for (int i = 127; i >= 1; i--)
data.push_back(cidreg[i]);
 
data.push_back(endbit);
 
foreach(data[i]) begin
@ICmd.cb;
ICmd.cb.Cmd <= data[i];
end
 
@ICmd.cb;
ICmd.cb.Cmd <= 'z;
endtask
endclass
 
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SDCID.sv
0,0 → 1,53
//
// file: unitSdCardModel/src/SDCID.sv
// author: Rainer Kastl
//
// Register CID
//
 
include "../../unitSdCardModel/src/Crc.sv";
 
typedef logic[7:0] manufacturer_id_t;
typedef logic[15:0] app_id_t;
typedef logic[39:0] pname_t;
typedef logic[7:0] prev_t;
typedef logic[31:0] pserialnumber_t;
typedef logic[11:0] manufacturing_date_t;
typedef logic[127:0] cidreg_t;
 
class SDCID;
local rand manufacturer_id_t mid;
local rand app_id_t appid;
local rand pname_t name;
local rand prev_t rev;
local rand pserialnumber_t serialnumber;
local rand manufacturing_date_t date;
 
function new();
endfunction
 
function automatic aCrc getCrc(cidreg_t cid);
logic data[$];
for (int i = 127; i >= 8; i--) begin
data.push_back(cid[i]);
end
return calcCrc(data);
endfunction
 
function automatic cidreg_t get();
cidreg_t temp = 0;
temp[127:120] = mid;
temp[119:104] = appid;
temp[103:64] = name;
temp[63:56] = rev;
temp[55:24] = serialnumber;
temp[23:20] = 0; // reserved
temp[19:8] = date;
temp[7:1] = getCrc(temp); // CRC7
temp[0] = 1;
return temp;
endfunction
 
endclass
 
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/Crc.sv
0,0 → 1,20
//
// file: unitSdCardModel/src/Crc.sv
// author: Rainer Kastl
//
// CRC7 calculation
//
 
 
function automatic aCrc calcCrc(logic data[$]);
aCrc crc = 0;
 
for(int i = 0; i < data.size(); i++) begin
if (((crc[6] & 1)) != data[i])
crc = (crc << 1) ^ 'b10001001;
else
crc <<= 1;
end
return crc;
endfunction
 
/sdhc-sc-core/trunk/src/grpSd/pkgSd/src/Sd-p.vhdl
9,6 → 9,7
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Global.all;
 
package Sd is
 
28,6 → 29,10
arg : aSdCmdArg;
end record aSdCmdContent;
 
constant cDefaultSdCmdContent : aSdCmdContent := (
id => (others => '0'),
arg => (others => '0'));
 
type aSdCmdToken is record
startbit : std_ulogic; -- cSdStartBit
transbit : std_ulogic;
36,10 → 41,55
endbit : std_ulogic; --cSdEndBit
end record aSdCmdToken;
 
-- SD Card Regs
subtype aVoltageWindow is std_ulogic_vector(23 downto 15);
constant cVoltageWindow : aVoltageWindow := (others => '1');
constant cSdR3Id : aSdCmdId := (others => '1');
constant cSdR2Id : aSdCmdId := (others => '1');
 
type aSdRegOCR is record
voltagewindow : aVoltageWindow;
ccs : std_ulogic;
nBusy : std_ulogic;
end record aSdRegOCR;
 
function OCRToArg (ocr : in aSdRegOCR) return aSdCmdArg;
function ArgToOcr (arg : in aSdCmdArg) return aSdRegOCR;
 
subtype aSdCIDMID is std_ulogic_vector(7 downto 0);
subtype aSdCIDOID is std_ulogic_vector(15 downto 0);
subtype aSdCIDPNM is std_ulogic_vector(39 downto 0);
subtype aSdCIDPRV is std_ulogic_vector(7 downto 0);
subtype aSdCIDPSN is std_ulogic_vector(31 downto 0);
subtype aSdCIDMDT is std_ulogic_vector(11 downto 0);
 
type aSdRegCID is record
mid : aSdCIDMID;
oid : aSdCIDOID;
name : aSdCIDPNM;
revision : aSdCIDPRV;
serialnumber : aSdCIDPSN;
date : aSdCIDMDT;
end record;
 
constant cCIDLength : natural := 127;
 
constant cDefaultSdRegCID : aSdRegCID := (
mid => (others => '0'),
oid => (others => '0'),
name => (others => '0'),
revision => (others => '0'),
serialnumber => (others => '0'),
date => (others => '0'));
 
function UpdateCID(icid : in aSdRegCID; data : in std_ulogic; pos : in
natural) return aSdRegCID;
 
-- Types for entities
type aSdCmdFromController is record
Content : aSdCmdContent;
Valid : std_ulogic;
ExpectCID : std_ulogic; -- gets asserted when next response is R2
end record aSdCmdFromController;
 
type aSdCmdToController is record
51,8 → 101,17
-- a cmd was received)
Err : std_ulogic; -- gets asserted when an error occurred during
-- receiving a cmd
Cid : aSdRegCID;
end record aSdCmdToController;
 
constant cDefaultSdCmdToController : aSdCmdToController := (
Ack => cInactivated,
Receiving => cInactivated,
Valid => cInactivated,
Content => cDefaultSdCmdContent,
Err => cInactivated,
Cid => cDefaultSdRegCID);
 
-- constants for Controller
subtype aRCA is std_ulogic_vector(15 downto 0);
constant cSdDefaultRCA : aRCA := (others => '0');
110,19 → 169,6
 
constant cSdCmdACMD41 : aSdCmdId := std_ulogic_vector(to_unsigned(41, cSdCmdIdHigh));
 
subtype aVoltageWindow is std_ulogic_vector(23 downto 15);
constant cVoltageWindow : aVoltageWindow := (others => '1');
constant cSdR3Id : aSdCmdId := (others => '1');
 
type aSdRegOCR is record
voltagewindow : aVoltageWindow;
ccs : std_ulogic;
nBusy : std_ulogic;
end record aSdRegOCR;
 
function OCRToArg (ocr : in aSdRegOCR) return aSdCmdArg;
function ArgToOcr (arg : in aSdCmdArg) return aSdRegOCR;
 
end package Sd;
 
package body Sd is
144,5 → 190,28
return ocr;
end function ArgToOcr;
 
function UpdateCID(icid : in aSdRegCID; data : in std_ulogic; pos : in
natural) return aSdRegCID is
variable cid : aSdRegCID;
begin
cid := icid;
 
if (pos <= 127 and pos >= 120) then
cid.mid(pos-120) := data;
elsif (pos <= 119 and pos >= 104) then
cid.oid(pos-104) := data;
elsif (pos <= 103 and pos >= 64) then
cid.name(pos-64) := data;
elsif (pos <= 63 and pos >= 56) then
cid.revision(pos-56) := data;
elsif (pos <= 55 and pos >= 24) then
cid.serialnumber(pos-24) := data;
elsif (pos <= 19 and pos >= 8) then
cid.date(pos-8) := data;
end if;
 
return cid;
end function UpdateCID;
 
end package body Sd;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
30,7 → 30,7
architecture Rtl of SdCmd is
 
type aSdCmdState is (idle, startbit, transbit, cmdid, arg, crc, endbit,
recvtransbit, recvcmdid, recvarg, recvcrc, recvendbit, recvcrcerror);
recvtransbit, recvcmdid, recvarg, recvcid, recvcrc, recvendbit, recvcrcerror);
 
type aCrcOut is record
Clear : std_ulogic;
38,6 → 38,11
Data : std_ulogic;
end record aCrcOut;
 
constant cDefaultCrcOut : aCrcOut := (
Clear => cInactivated,
DataIn => cInactivated,
Data => cInactivated);
 
type aSdCmdOut is record
Crc : aCrcOut;
Controller : aSdCmdToController;
44,17 → 49,19
Cmd : std_logic;
end record aSdCmdOut;
 
constant cDefaultOut : aSdCmdOut := (
Crc => cDefaultCrcOut,
Controller => cDefaultSdCmdToController,
Cmd => 'Z');
 
 
signal State, NextState : aSdCmdState;
signal SerialCrc, CrcCorrect : std_ulogic;
signal Counter, NextCounter : unsigned(integer(log2(real(32))) - 1 downto 0);
signal Counter, NextCounter : unsigned(integer(log2(real(128))) - 1 downto 0);
signal Output : aSdCmdOut;
 
constant cDefaultOut : aSdCmdOut := ((cInactivated, cInactivated,cInactivated),
(Ack => cInactivated, Receiving => cInactivated, Valid => cInactivated,
Content => (id => (others => '0'), arg => (others => '0')), Err =>
cInactivated), 'Z');
 
signal ReceivedToken, NextReceivedToken : aSdCmdToken;
signal Cid, NextCid : aSdRegCID;
 
begin
 
71,11 → 78,13
State <= NextState;
Counter <= NextCounter;
ReceivedToken <= NextReceivedToken;
Cid <= NextCid;
end if;
end process CmdStateReg;
 
-- Comb. process
NextStateAndOutput : process (iFromController, ioCmd, SerialCrc, CrcCorrect, State, Counter)
NextStateAndOutput : process (iFromController, ioCmd, SerialCrc, CrcCorrect,
State, Counter, ReceivedToken)
 
procedure NextStateWhenAllSent (constant nextlength : in natural; constant toState : in aSdCmdState) is
begin
115,8 → 124,10
NextState <= State;
NextCounter <= Counter;
NextReceivedToken <= ReceivedToken;
NextCid <= Cid;
Output <= cDefaultOut;
Output.Controller.Content <= ReceivedToken.content;
Output.Controller.Cid <= Cid;
 
case State is
when idle =>
171,8 → 182,14
 
when recvcmdid =>
Output.Controller.Receiving <= cActivated;
RecvBitsAndCalcCrc(NextReceivedToken.Content.id, recvarg,
NextReceivedToken.Content.arg'high);
if (iFromController.ExpectCID = cInactivated) then
RecvBitsAndCalcCrc(NextReceivedToken.Content.id, recvarg,
NextReceivedToken.Content.arg'high);
elsif (iFromController.ExpectCID = cActivated) then
RecvBitsAndCalcCrc(NextReceivedToken.Content.id, recvcid,
cCIDLength-8);
Output.Crc.Clear <= cActivated;
end if;
 
when recvarg =>
Output.Controller.Receiving <= cActivated;
179,6 → 196,12
RecvBitsAndCalcCrc(NextReceivedToken.Content.arg, recvcrc,
crc7'high-1);
 
when recvcid =>
Output.Controller.Receiving <= cActivated;
NextCid <= UpdateCID(cid, ioCmd, to_integer(Counter)+8);
ShiftIntoCrc(ioCmd);
NextStateWhenAllSent(crc7'high-1, recvcrc);
 
when recvcrc =>
NextReceivedToken.crc7(to_integer(Counter)) <= ioCmd;
ShiftIntoCrc(ioCmd);
/sdhc-sc-core/trunk/src/grpSd/unitSdController/src/SdController-Rtl-ea.vhdl
26,11 → 26,11
architecture Rtl of SdController is
 
type aSdControllerState is (CMD0, CMD8Ws, CMD8, CMD8Response, CMD55,
CMD55Response, ACMD41, ACMD41Response, CMD2, idle,
invalidCard);
CMD55Response, ACMD41, ACMD41Response, CMD2, CMD2Response, CMD3,
CMD3Response, idle, invalidCard);
constant cDefaultControllerState : aSdControllerState := CMD0;
constant cDefaultoSdCmd : aSdCmdFromController := ((id => (others => '0'),
arg => (others => '0')), Valid => cInactivated);
arg => (others => '0')), Valid => cInactivated, ExpectCID => cInactivated);
 
type aSdControllerReg is record
HCS : std_ulogic;
147,6 → 147,24
end if;
 
when CMD2 =>
oSdCmd.Content.id <= cSdCmdAllSendCID;
oSdCmd.Valid <= cActivated;
if (iSdCmd.Ack = cActivated) then
NextState <= CMD2Response;
end if;
 
when CMD2Response =>
oSdCmd.ExpectCID <= cActivated;
if (iSdCmd.Valid = cActivated) then
NextState <= invalidCard;
 
if (iSdCmd.Content.id = cSdR2Id) then -- Check Response
NextState <= CMD3;
end if;
end if;
 
when CMD3 =>
null;
 
when others =>
154,7 → 172,5
end case;
end process Comb;
 
 
 
end architecture Rtl;
 

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