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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 610 to Rev 611
    ↔ Reverse comparison
  •

Rev 610 → Rev 611

/trunk/or1ksim/cpu/or32/execute.c
544,7 → 544,7
/* Check for range exception */
if (testsprbits (SPR_SR, SPR_SR_OVE) && testsprbits (SPR_SR, SPR_SR_OV))
except_handle (EXCEPT_RANGE, 0);
except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));
 
if (config.cpu.dependstats) {
iqueue[0].insn_index = insn_index;
601,7 → 601,7
delay_insn = next_delay_insn;
if(breakpoint)
except_handle(EXCEPT_TRAP, 0);
except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
}
 
void cpu_reset()
962,12 → 962,12
}
}
void l_sys() {
except_handle(EXCEPT_SYSCALL, 0);
except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE));
}
 
void l_trap() {
/* TODO: some SR related code here! */
except_handle(EXCEPT_TRAP, 0);
except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
}
 
void l_mac() {
/trunk/or1ksim/cpu/common/abstract.c
269,10 → 269,6
mem_cycles += cur_area->delayr * 2;
break;
}
} else {
printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", memaddr);
except_handle(EXCEPT_BUSERR, cur_vadd);
temp = 0;
}
return temp;
}
300,10 → 296,6
temp >>= 16;
break;
}
} else {
printf("EXCEPTION: read out of memory (16-bit access to %.8lx)\n", memaddr);
except_handle(EXCEPT_BUSERR, cur_vadd);
temp = 0;
}
return temp;
}
331,10 → 323,6
temp &= 0xff;
break;
}
} else {
printf("EXCEPTION: read out of memory (8-bit access to %.8lx)\n", memaddr);
except_handle(EXCEPT_BUSERR, cur_vadd);
temp = 0;
}
return temp;
}
349,6 → 337,12
if (config.debug.enabled)
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
temp = evalsim_mem32(memaddr);
if (!cur_area) {
printf("EXCEPTION: read out of memory (16-bit access to %.8lx)\n", memaddr);
except_handle(EXCEPT_BUSERR, cur_vadd);
temp = 0;
}
 
if (!pending.valid && cur_area->log)
fprintf (cur_area->log, "[%08x] -> read %08x\n", memaddr, temp);
if (config.debug.enabled)
379,6 → 373,12
if (config.debug.enabled)
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
temp = evalsim_mem32(memaddr);
if (!cur_area) {
printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", memaddr);
except_handle(EXCEPT_BUSERR, cur_vadd);
temp = 0;
}
 
if (!pending.valid && cur_area->log)
fprintf (cur_area->log, "[%08x] -> read %08x\n", memaddr, temp);
if (config.debug.enabled)
400,6 → 400,12
if (config.debug.enabled)
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
temp = evalsim_mem32(memaddr);
if (!cur_area) {
printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", memaddr);
except_handle(EXCEPT_BUSERR, cur_vadd);
temp = 0;
}
 
if (!pending.valid && cur_area->log)
fprintf (cur_area->log, "[%08x] -> read %08x\n", memaddr, temp);
if (config.debug.enabled)
430,6 → 436,12
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
temp = evalsim_mem16(memaddr);
if (!cur_area) {
printf("EXCEPTION: read out of memory (16-bit access to %.8lx)\n", memaddr);
except_handle(EXCEPT_BUSERR, cur_vadd);
temp = 0;
}
 
if (!pending.valid && cur_area->log)
fprintf (cur_area->log, "[%08x] -> read %08x\n", memaddr, temp);
if (config.debug.enabled)
455,6 → 467,12
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
temp = evalsim_mem8(memaddr);
if (!cur_area) {
printf("EXCEPTION: read out of memory (8-bit access to %.8lx)\n", memaddr);
except_handle(EXCEPT_BUSERR, cur_vadd);
temp = 0;
}
 
if (!pending.valid && cur_area->log)
fprintf (cur_area->log, "[%08x] -> read %08x\n", memaddr, temp);
if (config.debug.enabled)
/trunk/or1ksim/tick/tick.c
67,11 → 67,8
if ((ttcr & SPR_TTCR_PERIOD) == (ttmr & SPR_TTMR_PERIOD)) {
int mode = (ttmr & SPR_TTMR_M) >> 30; /* CZ 04/09/01 */
 
if (ttmr & SPR_TTMR_IE) {
if (ttmr & SPR_TTMR_IE)
setsprbits(SPR_TTMR, SPR_TTMR_IP, 1);
if ((mfspr(SPR_SR) & SPR_SR_TEE) == SPR_SR_TEE)
except_handle(EXCEPT_TICK, 0);
}
 
/* Handle the modes properly.. CZ 04/09/01 */
switch(mode)
90,6 → 87,10
break;
}
}
 
if ((ttmr & SPR_TTMR_IP) && ((mfspr(SPR_SR) & SPR_SR_TEE) == SPR_SR_TEE))
except_handle(EXCEPT_TICK, mfspr(SPR_EEAR_BASE));
 
if (!tt_stopped)
ttcr++;
mtspr(SPR_TTCR, ttcr);
/trunk/or1ksim/pic/pic.c
58,7 → 58,7
return;
 
if(picsr)
except_handle(EXCEPT_INT, 0);
except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
}
 
/* Asserts interrupt to the PIC. */
/trunk/or1ksim/testbench/xess.ld
2,7 → 2,7
{
except : ORIGIN = 0x00000000, LENGTH = 0x00002000
flash : ORIGIN = 0x00002000, LENGTH = 0x001fe000
ram : ORIGIN = 0x40000000, LENGTH = 0x00200000
ram : ORIGIN = 0x80000000, LENGTH = 0x00200000
}
SECTIONS
/trunk/or1ksim/testbench/except_test.cfg
295,7 → 295,7
prof_fn = "sim.profile"
 
history = 1
exe_log = 0
exe_log = 1
exe_log_fn = "executed.log"
clkcycle = 4ns
end
/trunk/or1ksim/testbench/except_test.c
824,7 → 824,6
ASSERT(except_count == 1);
ASSERT(except_mask == (1 << V_TRAP));
ASSERT(except_pc == (unsigned long)(trap));
ASSERT(except_ea == 0);
 
/* Check if there was trap exception */
call ((unsigned long)&b_trap, 0);
831,7 → 830,6
ASSERT(except_count == 2);
ASSERT(except_mask == (1 << V_TRAP));
ASSERT(except_pc == (unsigned long)(b_trap));
ASSERT(except_ea == 0);
 
return 0;
}
859,7 → 857,6
ASSERT(except_count == 2);
ASSERT(except_mask == (1 << V_RANGE));
ASSERT(except_pc == (unsigned long)(b_range));
ASSERT(except_ea == 0);
 
return 0;
}
925,7 → 922,6
ASSERT(except_count == 1);
ASSERT(except_mask == (1 << V_TICK));
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
ASSERT(except_ea == 0);
 
/* Reset except counter */
except_count = 0;
1063,7 → 1059,6
ASSERT(except_count == 1);
ASSERT(except_mask == (1 << V_TRAP));
ASSERT(except_pc == (unsigned long)(trap));
ASSERT(except_ea == 0);
 
#if 0
/* Reset except counter */

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