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https://opencores.org/ocsvn/can/can/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 62 to Rev 63
- ↔ Reverse comparison
Rev 62 → Rev 63
/trunk/bench/verilog/can_testbench.v
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.32 2003/03/12 05:57:36 mohor |
// Bidirectional port_0_i changed to port_0_io. |
// input cs_can changed to cs_can_i. |
// |
// Revision 1.31 2003/03/12 04:40:00 mohor |
// rd_i and wr_i are active high signals. If 8051 is connected, these two signals |
// need to be negated one level higher. |
1638,10 → 1642,12
@ (posedge clk); |
#1; |
cs_can = 1; |
@ (negedge clk); |
#1; |
ale_i = 1; |
port_0_en = 1; |
port_0_o = reg_addr; |
@ (posedge clk); |
@ (negedge clk); |
#1; |
ale_i = 0; |
#90; // 73 - 103 ns |
1692,10 → 1698,12
@ (posedge clk); |
#1; |
cs_can = 1; |
@ (negedge clk); |
#1; |
ale_i = 1; |
port_0_en = 1; |
port_0_o = reg_addr; |
@ (posedge clk); |
@ (negedge clk); |
#1; |
ale_i = 0; |
#90; // 73 - 103 ns |