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/openmsp430/trunk/core/synthesis/altera/design_files.v
0,0 → 1,98
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_fpga_top.v
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 37 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
//----------------------------------------------------------------------------
 
//=============================================================================
// FPGA Specific modules
//=============================================================================
`include "../src/arch.v"
`include "../src/openMSP430_fpga.v"
 
`ifdef CYCLONE_II
`include "../src/megawizard/cyclone2_pmem.v"
`include "../src/megawizard/cyclone2_dmem.v"
`endif
`ifdef CYCLONE_III
`include "../src/megawizard/cyclone3_pmem.v"
`include "../src/megawizard/cyclone3_dmem.v"
`endif
`ifdef CYCLONE_IV_GX
`include "../src/megawizard/cyclone4gx_pmem.v"
`include "../src/megawizard/cyclone4gx_dmem.v"
`endif
`ifdef ARRIA_GX
`include "../src/megawizard/arriagx_pmem.v"
`include "../src/megawizard/arriagx_dmem.v"
`endif
`ifdef ARRIA_II_GX
`include "../src/megawizard/arria2gx_pmem.v"
`include "../src/megawizard/arria2gx_dmem.v"
`endif
`ifdef STRATIX
`include "../src/megawizard/stratix_pmem.v"
`include "../src/megawizard/stratix_dmem.v"
`endif
`ifdef STRATIX_II
`include "../src/megawizard/stratix2_pmem.v"
`include "../src/megawizard/stratix2_dmem.v"
`endif
`ifdef STRATIX_III
`include "../src/megawizard/stratix3_pmem.v"
`include "../src/megawizard/stratix3_dmem.v"
`endif
 
 
//=============================================================================
// openMSP430
//=============================================================================
 
`include "../../../rtl/verilog/openMSP430.v"
`include "../../../rtl/verilog/omsp_frontend.v"
`include "../../../rtl/verilog/omsp_execution_unit.v"
`include "../../../rtl/verilog/omsp_register_file.v"
`include "../../../rtl/verilog/omsp_alu.v"
`include "../../../rtl/verilog/omsp_mem_backbone.v"
`include "../../../rtl/verilog/omsp_clock_module.v"
`include "../../../rtl/verilog/omsp_sfr.v"
`include "../../../rtl/verilog/omsp_watchdog.v"
 
`include "../src/openMSP430_defines.v"
`ifdef DBG_EN
`include "../../../rtl/verilog/omsp_dbg.v"
`include "../../../rtl/verilog/omsp_dbg_uart.v"
`include "../src/openMSP430_defines.v"
`ifdef DBG_HWBRK_0
`include "../../../rtl/verilog/omsp_dbg_hwbrk.v"
`endif
`endif
openmsp430/trunk/core/synthesis/altera/design_files.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/openMSP430_fpga.tcl =================================================================== --- openmsp430/trunk/core/synthesis/altera/openMSP430_fpga.tcl (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/openMSP430_fpga.tcl (revision 63) @@ -0,0 +1,67 @@ +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: openMSP430_fpga.tcl +# Generated on: Tue Jan 19 23:11:05 2010 + +# Load Quartus II Tcl packages +package require ::quartus::project +package require ::quartus::flow + + +# Create project +project_new -revision openMSP430_fpga openMSP430_fpga + + +# Make assignments +set_global_assignment -name DEVICE +set_global_assignment -name FAMILY "" + +set_global_assignment -name VERILOG_FILE ..\\design_files.v +set_global_assignment -name SEARCH_PATH ..\\src/ + +set_global_assignment -name FMAX_REQUIREMENT "240 MHz" -section_id main_clock +set_instance_assignment -name CLOCK_SETTINGS main_clock -to dco_clk + +set_global_assignment -name OPTIMIZATION_TECHNIQUE +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name CDF_FILE Chain1.cdf +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +# Commit assignments +export_assignments + +# Run synthesis +execute_flow -compile
openmsp430/trunk/core/synthesis/altera/openMSP430_fpga.tcl Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/run_analysis.speed.log =================================================================== --- openmsp430/trunk/core/synthesis/altera/run_analysis.speed.log (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/run_analysis.speed.log (revision 63) @@ -0,0 +1,4146 @@ +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -18.008 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 45.10 MHz ( period = 22.174 ns ) + +==================================================================================== +Total logic elements : 1,660 / 18,752 ( 9 % ) + Total combinational functions : 1,620 / 18,752 ( 9 % ) + Dedicated logic registers : 467 / 18,752 ( 2 % ) +Total registers : 467 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -20.507 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 40.53 MHz ( period = 24.673 ns ) + +==================================================================================== +Total logic elements : 1,651 / 18,752 ( 9 % ) + Total combinational functions : 1,620 / 18,752 ( 9 % ) + Dedicated logic registers : 467 / 18,752 ( 2 % ) +Total registers : 467 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.074 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 33.07 MHz ( period = 30.240 ns ) + +==================================================================================== +Total logic elements : 1,658 / 18,752 ( 9 % ) + Total combinational functions : 1,620 / 18,752 ( 9 % ) + Dedicated logic registers : 467 / 18,752 ( 2 % ) +Total registers : 467 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 51.87 MHz ; 51.87 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,640 / 55,856 ( 3 % ) + Total combinational functions : 1,626 / 55,856 ( 3 % ) + Dedicated logic registers : 467 / 55,856 ( < 1 % ) +Total registers : 467 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 46.25 MHz ; 46.25 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,639 / 55,856 ( 3 % ) + Total combinational functions : 1,624 / 55,856 ( 3 % ) + Dedicated logic registers : 467 / 55,856 ( < 1 % ) +Total registers : 467 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 40.56 MHz ; 40.56 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,638 / 55,856 ( 3 % ) + Total combinational functions : 1,624 / 55,856 ( 3 % ) + Dedicated logic registers : 467 / 55,856 ( < 1 % ) +Total registers : 467 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 50.58 MHz ; 50.58 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,645 / 21,280 ( 8 % ) + Total combinational functions : 1,630 / 21,280 ( 8 % ) + Dedicated logic registers : 467 / 21,280 ( 2 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 47.09 MHz ; 47.09 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,639 / 21,280 ( 8 % ) + Total combinational functions : 1,622 / 21,280 ( 8 % ) + Dedicated logic registers : 467 / 21,280 ( 2 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 40.09 MHz ; 40.09 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,632 / 21,280 ( 8 % ) + Total combinational functions : 1,621 / 21,280 ( 8 % ) + Dedicated logic registers : 467 / 21,280 ( 2 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 48.71 MHz ; 48.71 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,124 / 40,128 ( 3 % ) + Dedicated logic registers : 468 / 40,128 ( 1 % ) +Total registers : 468 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 84.37 MHz ; 84.37 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,126 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 468 / 36,100 ( 1 % ) +Total registers : 468 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 76.17 MHz ; 76.17 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,126 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 468 / 36,100 ( 1 % ) +Total registers : 468 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 62.63 MHz ; 62.63 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,124 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 468 / 36,100 ( 1 % ) +Total registers : 468 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -18.562 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 44.00 MHz ( period = 22.728 ns ) + +==================================================================================== +Total logic elements : 1,712 / 10,570 ( 16 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -20.912 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 39.88 MHz ( period = 25.078 ns ) + +==================================================================================== +Total logic elements : 1,712 / 10,570 ( 16 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.163 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 32.97 MHz ( period = 30.329 ns ) + +==================================================================================== +Total logic elements : 1,712 / 10,570 ( 16 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -9.386 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 73.79 MHz ( period = 13.552 ns ) + +==================================================================================== +Logic utilization : 14 % + Combinational ALUTs : 1,198 / 12,480 ( 10 % ) + Dedicated logic registers : 469 / 12,480 ( 4 % ) +Total registers : 469 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -11.521 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 63.75 MHz ( period = 15.687 ns ) + +==================================================================================== +Logic utilization : 14 % + Combinational ALUTs : 1,199 / 12,480 ( 10 % ) + Dedicated logic registers : 476 / 12,480 ( 4 % ) +Total registers : 476 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -14.338 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 54.04 MHz ( period = 18.504 ns ) + +==================================================================================== +Logic utilization : 14 % + Combinational ALUTs : 1,195 / 12,480 ( 10 % ) + Dedicated logic registers : 472 / 12,480 ( 4 % ) +Total registers : 472 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 93.84 MHz ; 93.84 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,126 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 470 / 38,000 ( 1 % ) +Total registers : 470 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 83.68 MHz ; 83.68 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,128 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 467 / 38,000 ( 1 % ) +Total registers : 467 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 73.17 MHz ; 73.17 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,127 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 468 / 38,000 ( 1 % ) +Total registers : 468 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -19.203 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 42.79 MHz ( period = 23.369 ns ) + +==================================================================================== +Total logic elements : 2,151 / 18,752 ( 11 % ) + Total combinational functions : 2,093 / 18,752 ( 11 % ) + Dedicated logic registers : 610 / 18,752 ( 3 % ) +Total registers : 610 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.582 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 37.39 MHz ( period = 26.748 ns ) + +==================================================================================== +Total logic elements : 2,151 / 18,752 ( 11 % ) + Total combinational functions : 2,093 / 18,752 ( 11 % ) + Dedicated logic registers : 610 / 18,752 ( 3 % ) +Total registers : 610 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -27.081 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 32.00 MHz ( period = 31.247 ns ) + +==================================================================================== +Total logic elements : 2,154 / 18,752 ( 11 % ) + Total combinational functions : 2,093 / 18,752 ( 11 % ) + Dedicated logic registers : 610 / 18,752 ( 3 % ) +Total registers : 610 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 48.26 MHz ; 48.26 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,135 / 55,856 ( 4 % ) + Total combinational functions : 2,102 / 55,856 ( 4 % ) + Dedicated logic registers : 610 / 55,856 ( 1 % ) +Total registers : 610 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 44.28 MHz ; 44.28 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,136 / 55,856 ( 4 % ) + Total combinational functions : 2,104 / 55,856 ( 4 % ) + Dedicated logic registers : 610 / 55,856 ( 1 % ) +Total registers : 610 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 38.0 MHz ; 38.0 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,135 / 55,856 ( 4 % ) + Total combinational functions : 2,104 / 55,856 ( 4 % ) + Dedicated logic registers : 610 / 55,856 ( 1 % ) +Total registers : 610 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 51.16 MHz ; 51.16 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,130 / 21,280 ( 10 % ) + Total combinational functions : 2,100 / 21,280 ( 10 % ) + Dedicated logic registers : 610 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 44.43 MHz ; 44.43 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,135 / 21,280 ( 10 % ) + Total combinational functions : 2,100 / 21,280 ( 10 % ) + Dedicated logic registers : 610 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 39.76 MHz ; 39.76 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,125 / 21,280 ( 10 % ) + Total combinational functions : 2,096 / 21,280 ( 10 % ) + Dedicated logic registers : 610 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 44.58 MHz ; 44.58 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,490 / 40,128 ( 4 % ) + Dedicated logic registers : 611 / 40,128 ( 2 % ) +Total registers : 611 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 78.81 MHz ; 78.81 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,506 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 612 / 36,100 ( 2 % ) +Total registers : 612 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 68.86 MHz ; 68.86 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,510 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 611 / 36,100 ( 2 % ) +Total registers : 611 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 59.66 MHz ; 59.66 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,524 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 612 / 36,100 ( 2 % ) +Total registers : 612 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -18.748 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 43.64 MHz ( period = 22.914 ns ) + +==================================================================================== +Total logic elements : 2,294 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -20.944 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 39.82 MHz ( period = 25.110 ns ) + +==================================================================================== +Total logic elements : 2,295 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -25.893 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 33.27 MHz ( period = 30.059 ns ) + +==================================================================================== +Total logic elements : 2,295 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -9.650 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 72.38 MHz ( period = 13.816 ns ) + +==================================================================================== +Logic utilization : 17 % + Combinational ALUTs : 1,643 / 12,480 ( 13 % ) + Dedicated logic registers : 617 / 12,480 ( 5 % ) +Total registers : 617 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -12.416 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 60.31 MHz ( period = 16.582 ns ) + +==================================================================================== +Logic utilization : 17 % + Combinational ALUTs : 1,638 / 12,480 ( 13 % ) + Dedicated logic registers : 616 / 12,480 ( 5 % ) +Total registers : 616 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -15.104 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 51.89 MHz ( period = 19.270 ns ) + +==================================================================================== +Logic utilization : 17 % + Combinational ALUTs : 1,644 / 12,480 ( 13 % ) + Dedicated logic registers : 615 / 12,480 ( 5 % ) +Total registers : 615 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 89.59 MHz ; 89.59 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,527 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 612 / 38,000 ( 2 % ) +Total registers : 612 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 75.77 MHz ; 75.77 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,528 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 611 / 38,000 ( 2 % ) +Total registers : 611 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 72.63 MHz ; 72.63 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,526 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 611 / 38,000 ( 2 % ) +Total registers : 611 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -18.661 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 43.81 MHz ( period = 22.827 ns ) + +==================================================================================== +Total logic elements : 2,309 / 18,752 ( 12 % ) + Total combinational functions : 2,247 / 18,752 ( 12 % ) + Dedicated logic registers : 653 / 18,752 ( 3 % ) +Total registers : 653 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -21.881 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 38.39 MHz ( period = 26.047 ns ) + +==================================================================================== +Total logic elements : 2,295 / 18,752 ( 12 % ) + Total combinational functions : 2,247 / 18,752 ( 12 % ) + Dedicated logic registers : 653 / 18,752 ( 3 % ) +Total registers : 653 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -28.496 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 30.62 MHz ( period = 32.662 ns ) + +==================================================================================== +Total logic elements : 2,301 / 18,752 ( 12 % ) + Total combinational functions : 2,247 / 18,752 ( 12 % ) + Dedicated logic registers : 653 / 18,752 ( 3 % ) +Total registers : 653 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 49.95 MHz ; 49.95 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,289 / 55,856 ( 4 % ) + Total combinational functions : 2,261 / 55,856 ( 4 % ) + Dedicated logic registers : 653 / 55,856 ( 1 % ) +Total registers : 653 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 41.64 MHz ; 41.64 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,324 / 55,856 ( 4 % ) + Total combinational functions : 2,301 / 55,856 ( 4 % ) + Dedicated logic registers : 653 / 55,856 ( 1 % ) +Total registers : 653 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 38.38 MHz ; 38.38 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,318 / 55,856 ( 4 % ) + Total combinational functions : 2,297 / 55,856 ( 4 % ) + Dedicated logic registers : 653 / 55,856 ( 1 % ) +Total registers : 653 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 49.6 MHz ; 49.6 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,273 / 21,280 ( 11 % ) + Total combinational functions : 2,248 / 21,280 ( 11 % ) + Dedicated logic registers : 653 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.63 MHz ; 42.63 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,314 / 21,280 ( 11 % ) + Total combinational functions : 2,289 / 21,280 ( 11 % ) + Dedicated logic registers : 653 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 36.86 MHz ; 36.86 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,308 / 21,280 ( 11 % ) + Total combinational functions : 2,282 / 21,280 ( 11 % ) + Dedicated logic registers : 653 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 44.38 MHz ; 44.38 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,805 / 40,128 ( 4 % ) + Dedicated logic registers : 662 / 40,128 ( 2 % ) +Total registers : 662 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 75.19 MHz ; 75.19 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,801 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 657 / 36,100 ( 2 % ) +Total registers : 657 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 65.58 MHz ; 65.58 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,809 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 656 / 36,100 ( 2 % ) +Total registers : 656 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 57.2 MHz ; 57.2 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,804 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 660 / 36,100 ( 2 % ) +Total registers : 660 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -19.132 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 42.92 MHz ( period = 23.298 ns ) + +==================================================================================== +Total logic elements : 2,482 / 10,570 ( 23 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.731 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 37.18 MHz ( period = 26.897 ns ) + +==================================================================================== +Total logic elements : 2,483 / 10,570 ( 23 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.296 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 32.83 MHz ( period = 30.462 ns ) + +==================================================================================== +Total logic elements : 2,483 / 10,570 ( 23 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -11.010 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 65.89 MHz ( period = 15.176 ns ) + +==================================================================================== +Logic utilization : 20 % + Combinational ALUTs : 1,878 / 12,480 ( 15 % ) + Dedicated logic registers : 655 / 12,480 ( 5 % ) +Total registers : 655 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -13.046 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 58.10 MHz ( period = 17.212 ns ) + +==================================================================================== +Logic utilization : 21 % + Combinational ALUTs : 1,877 / 12,480 ( 15 % ) + Dedicated logic registers : 660 / 12,480 ( 5 % ) +Total registers : 660 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -15.517 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 50.81 MHz ( period = 19.683 ns ) + +==================================================================================== +Logic utilization : 20 % + Combinational ALUTs : 1,878 / 12,480 ( 15 % ) + Dedicated logic registers : 657 / 12,480 ( 5 % ) +Total registers : 657 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 84.5 MHz ; 84.5 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,794 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 656 / 38,000 ( 2 % ) +Total registers : 656 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 71.9 MHz ; 71.9 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,792 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 658 / 38,000 ( 2 % ) +Total registers : 658 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 66.91 MHz ; 66.91 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,798 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 657 / 38,000 ( 2 % ) +Total registers : 657 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -19.890 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 41.57 MHz ( period = 24.056 ns ) + +==================================================================================== +Total logic elements : 2,453 / 18,752 ( 13 % ) + Total combinational functions : 2,351 / 18,752 ( 13 % ) + Dedicated logic registers : 695 / 18,752 ( 4 % ) +Total registers : 695 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -25.052 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 34.23 MHz ( period = 29.218 ns ) + +==================================================================================== +Total logic elements : 2,439 / 18,752 ( 13 % ) + Total combinational functions : 2,351 / 18,752 ( 13 % ) + Dedicated logic registers : 695 / 18,752 ( 4 % ) +Total registers : 695 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -29.410 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 29.78 MHz ( period = 33.576 ns ) + +==================================================================================== +Total logic elements : 2,442 / 18,752 ( 13 % ) + Total combinational functions : 2,351 / 18,752 ( 13 % ) + Dedicated logic registers : 695 / 18,752 ( 4 % ) +Total registers : 695 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 48.39 MHz ; 48.39 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,414 / 55,856 ( 4 % ) + Total combinational functions : 2,378 / 55,856 ( 4 % ) + Dedicated logic registers : 695 / 55,856 ( 1 % ) +Total registers : 695 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 39.18 MHz ; 39.18 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,469 / 55,856 ( 4 % ) + Total combinational functions : 2,414 / 55,856 ( 4 % ) + Dedicated logic registers : 695 / 55,856 ( 1 % ) +Total registers : 695 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 33.94 MHz ; 33.94 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,462 / 55,856 ( 4 % ) + Total combinational functions : 2,411 / 55,856 ( 4 % ) + Dedicated logic registers : 695 / 55,856 ( 1 % ) +Total registers : 695 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 47.38 MHz ; 47.38 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,414 / 21,280 ( 11 % ) + Total combinational functions : 2,376 / 21,280 ( 11 % ) + Dedicated logic registers : 695 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.49 MHz ; 42.49 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,439 / 21,280 ( 11 % ) + Total combinational functions : 2,406 / 21,280 ( 11 % ) + Dedicated logic registers : 695 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 37.27 MHz ; 37.27 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,430 / 21,280 ( 11 % ) + Total combinational functions : 2,401 / 21,280 ( 11 % ) + Dedicated logic registers : 695 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 41.88 MHz ; 41.88 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,892 / 40,128 ( 5 % ) + Dedicated logic registers : 711 / 40,128 ( 2 % ) +Total registers : 711 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 75.75 MHz ; 75.75 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,895 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 708 / 36,100 ( 2 % ) +Total registers : 708 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 67.96 MHz ; 67.96 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,916 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 705 / 36,100 ( 2 % ) +Total registers : 705 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 55.76 MHz ; 55.76 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,906 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 706 / 36,100 ( 2 % ) +Total registers : 706 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -20.474 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 40.58 MHz ( period = 24.640 ns ) + +==================================================================================== +Total logic elements : 2,622 / 10,570 ( 25 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.555 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 37.42 MHz ( period = 26.721 ns ) + +==================================================================================== +Total logic elements : 2,623 / 10,570 ( 25 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.083 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 33.06 MHz ( period = 30.249 ns ) + +==================================================================================== +Total logic elements : 2,623 / 10,570 ( 25 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -10.736 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 67.11 MHz ( period = 14.902 ns ) + +==================================================================================== +Logic utilization : 22 % + Combinational ALUTs : 1,988 / 12,480 ( 16 % ) + Dedicated logic registers : 699 / 12,480 ( 6 % ) +Total registers : 699 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -13.427 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 56.84 MHz ( period = 17.593 ns ) + +==================================================================================== +Logic utilization : 22 % + Combinational ALUTs : 1,981 / 12,480 ( 16 % ) + Dedicated logic registers : 703 / 12,480 ( 6 % ) +Total registers : 703 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -15.877 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 49.89 MHz ( period = 20.043 ns ) + +==================================================================================== +Logic utilization : 22 % + Combinational ALUTs : 1,983 / 12,480 ( 16 % ) + Dedicated logic registers : 704 / 12,480 ( 6 % ) +Total registers : 704 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 86.24 MHz ; 86.24 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,898 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 709 / 38,000 ( 2 % ) +Total registers : 709 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 76.64 MHz ; 76.64 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,902 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 705 / 38,000 ( 2 % ) +Total registers : 705 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 68.49 MHz ; 68.49 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,903 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 712 / 38,000 ( 2 % ) +Total registers : 712 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -19.589 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 42.10 MHz ( period = 23.755 ns ) + +==================================================================================== +Total logic elements : 2,560 / 18,752 ( 14 % ) + Total combinational functions : 2,467 / 18,752 ( 13 % ) + Dedicated logic registers : 737 / 18,752 ( 4 % ) +Total registers : 737 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -23.968 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 35.54 MHz ( period = 28.134 ns ) + +==================================================================================== +Total logic elements : 2,566 / 18,752 ( 14 % ) + Total combinational functions : 2,467 / 18,752 ( 13 % ) + Dedicated logic registers : 737 / 18,752 ( 4 % ) +Total registers : 737 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -29.584 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 29.63 MHz ( period = 33.750 ns ) + +==================================================================================== +Total logic elements : 2,573 / 18,752 ( 14 % ) + Total combinational functions : 2,467 / 18,752 ( 13 % ) + Dedicated logic registers : 737 / 18,752 ( 4 % ) +Total registers : 737 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 48.43 MHz ; 48.43 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,544 / 55,856 ( 5 % ) + Total combinational functions : 2,490 / 55,856 ( 4 % ) + Dedicated logic registers : 737 / 55,856 ( 1 % ) +Total registers : 737 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 40.59 MHz ; 40.59 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,574 / 55,856 ( 5 % ) + Total combinational functions : 2,536 / 55,856 ( 5 % ) + Dedicated logic registers : 737 / 55,856 ( 1 % ) +Total registers : 737 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 33.57 MHz ; 33.57 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,563 / 55,856 ( 5 % ) + Total combinational functions : 2,533 / 55,856 ( 5 % ) + Dedicated logic registers : 737 / 55,856 ( 1 % ) +Total registers : 737 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 47.07 MHz ; 47.07 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,538 / 21,280 ( 12 % ) + Total combinational functions : 2,491 / 21,280 ( 12 % ) + Dedicated logic registers : 737 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 41.6 MHz ; 41.6 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,566 / 21,280 ( 12 % ) + Total combinational functions : 2,529 / 21,280 ( 12 % ) + Dedicated logic registers : 737 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 34.69 MHz ; 34.69 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,590 / 21,280 ( 12 % ) + Total combinational functions : 2,524 / 21,280 ( 12 % ) + Dedicated logic registers : 737 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.51 MHz ; 42.51 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,956 / 40,128 ( 5 % ) + Dedicated logic registers : 755 / 40,128 ( 2 % ) +Total registers : 755 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 76.3 MHz ; 76.3 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 1,985 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 754 / 36,100 ( 2 % ) +Total registers : 754 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 66.81 MHz ; 66.81 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 1,986 / 36,100 ( 6 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 759 / 36,100 ( 2 % ) +Total registers : 759 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 59.04 MHz ; 59.04 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 1,980 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 761 / 36,100 ( 2 % ) +Total registers : 761 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -19.816 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 41.70 MHz ( period = 23.982 ns ) + +==================================================================================== +Total logic elements : 2,742 / 10,570 ( 26 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.881 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 36.97 MHz ( period = 27.047 ns ) + +==================================================================================== +Total logic elements : 2,743 / 10,570 ( 26 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -27.543 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 31.54 MHz ( period = 31.709 ns ) + +==================================================================================== +Total logic elements : 2,743 / 10,570 ( 26 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -10.966 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 66.09 MHz ( period = 15.132 ns ) + +==================================================================================== +Logic utilization : 23 % + Combinational ALUTs : 2,050 / 12,480 ( 16 % ) + Dedicated logic registers : 742 / 12,480 ( 6 % ) +Total registers : 742 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -12.621 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 59.57 MHz ( period = 16.787 ns ) + +==================================================================================== +Logic utilization : 23 % + Combinational ALUTs : 2,070 / 12,480 ( 17 % ) + Dedicated logic registers : 746 / 12,480 ( 6 % ) +Total registers : 746 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -15.826 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 50.02 MHz ( period = 19.992 ns ) + +==================================================================================== +Logic utilization : 23 % + Combinational ALUTs : 2,067 / 12,480 ( 17 % ) + Dedicated logic registers : 745 / 12,480 ( 6 % ) +Total registers : 745 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 86.72 MHz ; 86.72 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,994 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 762 / 38,000 ( 2 % ) +Total registers : 762 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 73.49 MHz ; 73.49 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,986 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 757 / 38,000 ( 2 % ) +Total registers : 757 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 65.19 MHz ; 65.19 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,991 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 755 / 38,000 ( 2 % ) +Total registers : 755 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -20.396 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 40.71 MHz ( period = 24.562 ns ) + +==================================================================================== +Total logic elements : 2,690 / 18,752 ( 14 % ) + Total combinational functions : 2,578 / 18,752 ( 14 % ) + Dedicated logic registers : 779 / 18,752 ( 4 % ) +Total registers : 779 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -25.280 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 33.96 MHz ( period = 29.446 ns ) + +==================================================================================== +Total logic elements : 2,682 / 18,752 ( 14 % ) + Total combinational functions : 2,578 / 18,752 ( 14 % ) + Dedicated logic registers : 779 / 18,752 ( 4 % ) +Total registers : 779 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -33.745 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 26.38 MHz ( period = 37.911 ns ) + +==================================================================================== +Total logic elements : 2,694 / 18,752 ( 14 % ) + Total combinational functions : 2,578 / 18,752 ( 14 % ) + Dedicated logic registers : 779 / 18,752 ( 4 % ) +Total registers : 779 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 45.61 MHz ; 45.61 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,671 / 55,856 ( 5 % ) + Total combinational functions : 2,616 / 55,856 ( 5 % ) + Dedicated logic registers : 779 / 55,856 ( 1 % ) +Total registers : 779 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 40.86 MHz ; 40.86 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,701 / 55,856 ( 5 % ) + Total combinational functions : 2,656 / 55,856 ( 5 % ) + Dedicated logic registers : 779 / 55,856 ( 1 % ) +Total registers : 779 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 32.86 MHz ; 32.86 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,714 / 55,856 ( 5 % ) + Total combinational functions : 2,655 / 55,856 ( 5 % ) + Dedicated logic registers : 779 / 55,856 ( 1 % ) +Total registers : 779 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 46.67 MHz ; 46.67 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,638 / 21,280 ( 12 % ) + Total combinational functions : 2,601 / 21,280 ( 12 % ) + Dedicated logic registers : 779 / 21,280 ( 4 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 39.03 MHz ; 39.03 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,685 / 21,280 ( 13 % ) + Total combinational functions : 2,643 / 21,280 ( 12 % ) + Dedicated logic registers : 779 / 21,280 ( 4 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 37.03 MHz ; 37.03 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,678 / 21,280 ( 13 % ) + Total combinational functions : 2,646 / 21,280 ( 12 % ) + Dedicated logic registers : 779 / 21,280 ( 4 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.18 MHz ; 42.18 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 2,084 / 40,128 ( 5 % ) + Dedicated logic registers : 806 / 40,128 ( 2 % ) +Total registers : 806 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 79.81 MHz ; 79.81 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 2,062 / 36,100 ( 6 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 798 / 36,100 ( 2 % ) +Total registers : 798 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 65.35 MHz ; 65.35 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 2,050 / 36,100 ( 6 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 795 / 36,100 ( 2 % ) +Total registers : 795 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 57.41 MHz ; 57.41 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 2,059 / 36,100 ( 6 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 800 / 36,100 ( 2 % ) +Total registers : 800 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -21.015 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 39.71 MHz ( period = 25.181 ns ) + +==================================================================================== +Total logic elements : 2,855 / 10,570 ( 27 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.997 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 36.81 MHz ( period = 27.163 ns ) + +==================================================================================== +Total logic elements : 2,856 / 10,570 ( 27 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -28.446 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 30.66 MHz ( period = 32.612 ns ) + +==================================================================================== +Total logic elements : 2,856 / 10,570 ( 27 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -11.043 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 65.75 MHz ( period = 15.209 ns ) + +==================================================================================== +Logic utilization : 24 % + Combinational ALUTs : 2,176 / 12,480 ( 17 % ) + Dedicated logic registers : 792 / 12,480 ( 6 % ) +Total registers : 792 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -12.709 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 59.26 MHz ( period = 16.875 ns ) + +==================================================================================== +Logic utilization : 24 % + Combinational ALUTs : 2,176 / 12,480 ( 17 % ) + Dedicated logic registers : 788 / 12,480 ( 6 % ) +Total registers : 788 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -16.114 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 49.31 MHz ( period = 20.280 ns ) + +==================================================================================== +Logic utilization : 24 % + Combinational ALUTs : 2,165 / 12,480 ( 17 % ) + Dedicated logic registers : 787 / 12,480 ( 6 % ) +Total registers : 787 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 85.01 MHz ; 85.01 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 2,049 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 798 / 38,000 ( 2 % ) +Total registers : 798 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 75.35 MHz ; 75.35 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 2,048 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 797 / 38,000 ( 2 % ) +Total registers : 797 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (SPEED optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 68.43 MHz ; 68.43 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 8 % + Combinational ALUTs : 2,054 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 804 / 38,000 ( 2 % ) +Total registers : 804 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### +
openmsp430/trunk/core/synthesis/altera/run_analysis.speed.log Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/arch.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/arch.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/arch.v (revision 63) @@ -0,0 +1,3 @@ + +`define CYCLONE_II +
openmsp430/trunk/core/synthesis/altera/src/arch.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/openMSP430_defines.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/openMSP430_defines.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/openMSP430_defines.v (revision 63) @@ -0,0 +1,300 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430_defines.v +// +// *Module Description: +// openMSP430 Configuration file +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 57 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mon, 01 Feb 2010) $ +//---------------------------------------------------------------------------- +`include "openMSP430_undefines.v" + +//---------------------------------------------------------------------------- +// SYSTEM CONFIGURATION +//---------------------------------------------------------------------------- + +// Program Memory Size: +// 9 -> 1 kB +// 10 -> 2 kB +// 11 -> 4 kB +// 12 -> 8 kB +// 13 -> 16 kB +// 14 -> 32 kB +`define PMEM_AWIDTH 12 + +// Data Memory Size: +// 6 -> 128 B +// 7 -> 256 B +// 8 -> 512 B +// 9 -> 1 kB +// 10 -> 2 kB +// 11 -> 4 kB +// 12 -> 8 kB +// 13 -> 16 kB +// 14 -> 32 kB +`define DMEM_AWIDTH 10 + +//---------------------------------------------------------------------------- +// REMOTE DEBUGGING INTERFACE CONFIGURATION +//---------------------------------------------------------------------------- + +// Include Debug interface +//`define DBG_EN + +// Debug interface selection +// `define DBG_UART -> Enable UART (8N1) debug interface +// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED +// +`define DBG_UART +//`define DBG_JTAG + +// Number of hardware breakpoints (each unit contains 2 hw address breakpoints) +// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0 +// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1 +// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2 +// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3 +// +//`define DBG_HWBRK_0 +//`define DBG_HWBRK_1 +//`define DBG_HWBRK_2 +//`define DBG_HWBRK_3 + + +//==========================================================================// +//==========================================================================// +//==========================================================================// +//==========================================================================// +//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// +//==========================================================================// +//==========================================================================// +//==========================================================================// +//==========================================================================// + +// Program and Data Memory sizes +`define PMEM_SIZE (2 << `PMEM_AWIDTH) +`define DMEM_SIZE (2 << `DMEM_AWIDTH) + +// Data Memory Base Adresses +`define DMEM_BASE 16'h0200 + +// Program & Data Memory most significant address bit (for 16 bit words) +`define PMEM_MSB `PMEM_AWIDTH-1 +`define DMEM_MSB `DMEM_AWIDTH-1 + + +// Instructions type +`define INST_SO 0 +`define INST_JMP 1 +`define INST_TO 2 + +// Single-operand arithmetic +`define RRC 0 +`define SWPB 1 +`define RRA 2 +`define SXT 3 +`define PUSH 4 +`define CALL 5 +`define RETI 6 +`define IRQ 7 + +// Conditional jump +`define JNE 0 +`define JEQ 1 +`define JNC 2 +`define JC 3 +`define JN 4 +`define JGE 5 +`define JL 6 +`define JMP 7 + +// Two-operand arithmetic +`define MOV 0 +`define ADD 1 +`define ADDC 2 +`define SUBC 3 +`define SUB 4 +`define CMP 5 +`define DADD 6 +`define BIT 7 +`define BIC 8 +`define BIS 9 +`define XOR 10 +`define AND 11 + +// Addressing modes +`define DIR 0 +`define IDX 1 +`define INDIR 2 +`define INDIR_I 3 +`define SYMB 4 +`define IMM 5 +`define ABS 6 +`define CONST 7 + +// Execution state machine +`define E_IRQ_0 4'h0 +`define E_IRQ_1 4'h1 +`define E_IRQ_2 4'h2 +`define E_IRQ_3 4'h3 +`define E_IRQ_4 4'h4 +`define E_SRC_AD 4'h5 +`define E_SRC_RD 4'h6 +`define E_SRC_WR 4'h7 +`define E_DST_AD 4'h8 +`define E_DST_RD 4'h9 +`define E_DST_WR 4'hA +`define E_EXEC 4'hB +`define E_JUMP 4'hC +`define E_IDLE 4'hD + +// ALU control signals +`define ALU_SRC_INV 0 +`define ALU_INC 1 +`define ALU_INC_C 2 +`define ALU_ADD 3 +`define ALU_AND 4 +`define ALU_OR 5 +`define ALU_XOR 6 +`define ALU_DADD 7 +`define ALU_STAT_7 8 +`define ALU_STAT_F 9 +`define ALU_SHIFT 10 +`define EXEC_NO_WR 11 + +// Debug interface +`define DBG_UART_WR 18 +`define DBG_UART_BW 17 +`define DBG_UART_ADDR 16:11 + +// Debug interface CPU_CTL register +`define HALT 0 +`define RUN 1 +`define ISTEP 2 +`define SW_BRK_EN 3 +`define FRZ_BRK_EN 4 +`define RST_BRK_EN 5 +`define CPU_RST 6 + +// Debug interface CPU_STAT register +`define HALT_RUN 0 +`define PUC_PND 1 +`define SWBRK_PND 3 +`define HWBRK0_PND 4 +`define HWBRK1_PND 5 + +// Debug interface BRKx_CTL register +`define BRK_MODE_RD 0 +`define BRK_MODE_WR 1 +`define BRK_MODE 1:0 +`define BRK_EN 2 +`define BRK_I_EN 3 +`define BRK_RANGE 4 + +// Basic clock module: BCSCTL1 Control Register +`define DIVAx 5:4 + +// Basic clock module: BCSCTL2 Control Register +`define SELS 3 +`define DIVSx 2:1 + +// Timer A: TACTL Control Register +`define TASSELx 9:8 +`define TAIDx 7:6 +`define TAMCx 5:4 +`define TACLR 2 +`define TAIE 1 +`define TAIFG 0 + +// Timer A: TACCTLx Capture/Compare Control Register +`define TACMx 15:14 +`define TACCISx 13:12 +`define TASCS 11 +`define TASCCI 10 +`define TACAP 8 +`define TAOUTMODx 7:5 +`define TACCIE 4 +`define TACCI 3 +`define TAOUT 2 +`define TACOV 1 +`define TACCIFG 0 + +// +// DEBUG INTERFACE EXTRA CONFIGURATION +//====================================== + +// Debug interface: Software breakpoint opcode +`define DBG_SWBRK_OP 16'h4343 + +// Debug interface ID +`define DBG_ID 24'h4D5350 + +// Debug UART interface auto data synchronization +// If the following define is commented out, then +// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly +// defined. +`define DBG_UART_AUTO_SYNC + +// Debug UART interface data rate +// In order to properly setup the UART debug interface, you +// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and +// the chosen BAUD rate from the UART interface. +// +//`define DBG_UART_BAUD 9600 +//`define DBG_UART_BAUD 19200 +//`define DBG_UART_BAUD 38400 +//`define DBG_UART_BAUD 57600 +//`define DBG_UART_BAUD 115200 +//`define DBG_UART_BAUD 230400 +//`define DBG_UART_BAUD 460800 +//`define DBG_UART_BAUD 576000 +//`define DBG_UART_BAUD 921600 +`define DBG_UART_BAUD 2000000 +`define DBG_DCO_FREQ 20000000 +`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1) + +// Enable/Disable the hardware breakpoint RANGE mode +`define HWBRK_RANGE 1'b0 + +// Check configuration +`ifdef DBG_EN + `ifdef DBG_UART + `ifdef DBG_JTAG +CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED + `endif + `else + `ifdef DBG_JTAG +CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED + `else +CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED + `endif + `endif +`endif +
openmsp430/trunk/core/synthesis/altera/src/openMSP430_defines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/openMSP430_fpga.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/openMSP430_fpga.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/openMSP430_fpga.v (revision 63) @@ -0,0 +1,190 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430_fpga.v +// +// *Module Description: +// openMSP430 FPGA Top-level for the Xilinx synthesis. +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 37 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $ +//---------------------------------------------------------------------------- +`include "arch.v" +`include "timescale.v" +`include "openMSP430_defines.v" + +module openMSP430_fpga ( + +// OUTPUTs + aclk_en, // ACLK enable + dbg_freeze, // Freeze peripherals + dbg_uart_txd, // Debug interface: UART TXD + irq_acc, // Interrupt request accepted (one-hot signal) + per_addr, // Peripheral address + per_din, // Peripheral data input + per_wen, // Peripheral write enable (high active) + per_en, // Peripheral enable (high active) + smclk_en, // SMCLK enable + +// INPUTs + dbg_uart_rxd, // Debug interface: UART RXD + dco_clk, // Fast oscillator (fast clock) + irq, // Maskable interrupts + lfxt_clk, // Low frequency oscillator (typ 32kHz) + nmi, // Non-maskable interrupt (asynchronous) + per_dout, // Peripheral data output + reset_n // Reset Pin (low active) +); + +// OUTPUTs +//========= +output aclk_en; // ACLK enable +output dbg_freeze; // Freeze peripherals +output dbg_uart_txd; // Debug interface: UART TXD +output [13:0] irq_acc; // Interrupt request accepted (one-hot signal) +output [7:0] per_addr; // Peripheral address +output [15:0] per_din; // Peripheral data input +output [1:0] per_wen; // Peripheral write enable (high active) +output per_en; // Peripheral enable (high active) +output smclk_en; // SMCLK enable + + +// INPUTs +//========= +input dbg_uart_rxd; // Debug interface: UART RXD +input dco_clk; // Fast oscillator (fast clock) +input [13:0] irq; // Maskable interrupts +input lfxt_clk; // Low frequency oscillator (typ 32kHz) +input nmi; // Non-maskable interrupt (asynchronous) +input [15:0] per_dout; // Peripheral data output +input reset_n; // Reset Pin (active low) + + +//============================================================================= +// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION +//============================================================================= + +wire [`DMEM_MSB:0] dmem_addr; +wire dmem_cen; +wire [15:0] dmem_din; +wire [1:0] dmem_wen; +wire [15:0] dmem_dout; + +wire [`PMEM_MSB:0] pmem_addr; +wire pmem_cen; +wire [15:0] pmem_din; +wire [1:0] pmem_wen; +wire [15:0] pmem_dout; + +wire mclk; +wire puc; + + +//============================================================================= +// 2) PROGRAM AND DATA MEMORIES +//============================================================================= + +`ifdef CYCLONE_II + cyclone2_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout)); + cyclone2_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout)); +`endif +`ifdef CYCLONE_III + cyclone3_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout)); + cyclone3_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout)); +`endif +`ifdef CYCLONE_IV_GX + cyclone4gx_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout)); + cyclone4gx_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout)); +`endif +`ifdef ARRIA_GX + arriagx_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout)); + arriagx_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout)); +`endif +`ifdef ARRIA_II_GX + arria2gx_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout)); + arria2gx_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout)); +`endif +`ifdef STRATIX + stratix_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout)); + stratix_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout)); +`endif +`ifdef STRATIX_II + stratix2_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout)); + stratix2_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout)); +`endif +`ifdef STRATIX_III + stratix3_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout)); + stratix3_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout)); +`endif + + + +//============================================================================= +// 3) OPENMSP430 +//============================================================================= + +openMSP430 openMSP430_0 ( + +// OUTPUTs + .aclk_en (aclk_en), // ACLK enable + .dbg_freeze (dbg_freeze), // Freeze peripherals + .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD + .dmem_addr (dmem_addr), // Data Memory address + .dmem_cen (dmem_cen), // Data Memory chip enable (low active) + .dmem_din (dmem_din), // Data Memory data input + .dmem_wen (dmem_wen), // Data Memory write enable (low active) + .irq_acc (irq_acc), // Interrupt request accepted (one-hot signal) + .mclk (mclk), // Main system clock + .per_addr (per_addr), // Peripheral address + .per_din (per_din), // Peripheral data input + .per_wen (per_wen), // Peripheral write enable (high active) + .per_en (per_en), // Peripheral enable (high active) + .pmem_addr (pmem_addr), // Program Memory address + .pmem_cen (pmem_cen), // Program Memory chip enable (low active) + .pmem_din (pmem_din), // Program Memory data input (optional) + .pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional) + .puc (puc), // Main system reset + .smclk_en (smclk_en), // SMCLK enable + +// INPUTs + .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD + .dco_clk (dco_clk), // Fast oscillator (fast clock) + .dmem_dout (dmem_dout), // Data Memory data output + .irq (irq), // Maskable interrupts + .lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz) + .nmi (nmi), // Non-maskable interrupt (asynchronous) + .per_dout (per_dout), // Peripheral data output + .pmem_dout (pmem_dout), // Program Memory data output + .reset_n (reset_n) // Reset Pin (low active) +); + + + +endmodule // openMSP430_fpga +
openmsp430/trunk/core/synthesis/altera/src/openMSP430_fpga.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_pmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_pmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_pmem.v (revision 63) @@ -0,0 +1,184 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: arriagx_pmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module arriagx_pmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [11:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Arria GX", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_pmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_pmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_pmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_pmem.v (revision 63) @@ -0,0 +1,188 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: stratix_pmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module stratix_pmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [11:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.byteena_aclr_a = "NONE", + altsyncram_component.byte_size = 8, + altsyncram_component.indata_aclr_a = "NONE", + altsyncram_component.intended_device_family = "Stratix", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2, + altsyncram_component.wrcontrol_aclr_a = "NONE"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: BYTEENA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_pmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_dmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_dmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_dmem.v (revision 63) @@ -0,0 +1,184 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cyclone2_dmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module cyclone2_dmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [9:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone II", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_dmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_dmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_dmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_dmem.v (revision 63) @@ -0,0 +1,186 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: arria2gx_dmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module arria2gx_dmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [9:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Arria II GX", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_dmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_dmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_dmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_dmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_dmem.v (revision 63) @@ -0,0 +1,186 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cyclone3_dmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module cyclone3_dmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [9:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_dmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_dmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_dmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_dmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_dmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_dmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_dmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_dmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_dmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_dmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_dmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_dmem.v (revision 63) @@ -0,0 +1,186 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cyclone4gx_dmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module cyclone4gx_dmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [9:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone IV GX", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_dmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_dmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_dmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_dmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_dmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_dmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_dmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_dmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_dmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_dmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_dmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_dmem.v (revision 63) @@ -0,0 +1,184 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: stratix2_dmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module stratix2_dmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [9:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Stratix II", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_dmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_dmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_dmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_dmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_dmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_dmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_dmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_dmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_dmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_dmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_dmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_dmem.v (revision 63) @@ -0,0 +1,186 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: stratix3_dmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module stratix3_dmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [9:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Stratix III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_dmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_dmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_dmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_dmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_dmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_dmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_dmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_dmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_dmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_pmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_pmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_pmem.v (revision 63) @@ -0,0 +1,184 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cyclone2_pmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module cyclone2_pmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [11:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone II", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_pmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_pmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_pmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_pmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_pmem.v (revision 63) @@ -0,0 +1,186 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: arria2gx_pmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module arria2gx_pmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [11:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Arria II GX", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_pmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_pmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_pmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_pmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_pmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_pmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_pmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arria2gx_pmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_pmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_pmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_pmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_pmem.v (revision 63) @@ -0,0 +1,186 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cyclone3_pmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module cyclone3_pmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [11:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_pmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_pmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_pmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_pmem.v (revision 63) @@ -0,0 +1,186 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cyclone4gx_pmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module cyclone4gx_pmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [11:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone IV GX", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone4gx_pmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_pmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_pmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_pmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_pmem.v (revision 63) @@ -0,0 +1,184 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: stratix2_pmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module stratix2_pmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [11:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Stratix II", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_pmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_pmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_pmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_pmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_pmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_pmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_pmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix2_pmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_pmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_dmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_dmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_dmem.v (revision 63) @@ -0,0 +1,184 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: arriagx_dmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module arriagx_dmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [9:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Arria GX", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_dmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_pmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_pmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_pmem.v (revision 63) @@ -0,0 +1,186 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: stratix3_pmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module stratix3_pmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [11:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Stratix III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_pmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_dmem.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_dmem.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_dmem.v (revision 63) @@ -0,0 +1,188 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: stratix_dmem.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module stratix_dmem ( + address, + byteena, + clken, + clock, + data, + wren, + q); + + input [9:0] address; + input [1:0] byteena; + input clken; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena; + tri1 clken; + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .clocken0 (clken), + .wren_a (wren), + .clock0 (clock), + .byteena_a (byteena), + .address_a (address), + .data_a (data), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.byteena_aclr_a = "NONE", + altsyncram_component.byte_size = 8, + altsyncram_component.indata_aclr_a = "NONE", + altsyncram_component.intended_device_family = "Stratix", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 2, + altsyncram_component.wrcontrol_aclr_a = "NONE"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: BYTEENA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] +// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0] +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_dmem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_dmem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_dmem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_dmem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_dmem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_dmem_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_dmem_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_dmem_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf
openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_dmem.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/timescale.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/timescale.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/timescale.v (revision 63) @@ -0,0 +1 @@ +`timescale 1ns / 100ps
openmsp430/trunk/core/synthesis/altera/src/timescale.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/src/openMSP430_undefines.v =================================================================== --- openmsp430/trunk/core/synthesis/altera/src/openMSP430_undefines.v (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/src/openMSP430_undefines.v (revision 63) @@ -0,0 +1,493 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430_undefines.v +// +// *Module Description: +// openMSP430 Verilog `undef file +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 23 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ +//---------------------------------------------------------------------------- + +//---------------------------------------------------------------------------- +// SYSTEM CONFIGURATION +//---------------------------------------------------------------------------- + +// Program Memory Size: +`ifdef PMEM_AWIDTH +`undef PMEM_AWIDTH +`endif + +// Data Memory Size: +`ifdef DMEM_AWIDTH +`undef DMEM_AWIDTH +`endif + +//---------------------------------------------------------------------------- +// REMOTE DEBUGGING INTERFACE CONFIGURATION +//---------------------------------------------------------------------------- + +// Include Debug interface +`ifdef DBG_EN +`undef DBG_EN +`endif + +// Debug interface selection +`ifdef DBG_UART +`undef DBG_UART +`endif +`ifdef DBG_JTAG +`undef DBG_JTAG +`endif + +// Number of hardware breakpoints +`ifdef DBG_HWBRK_0 +`undef DBG_HWBRK_0 +`endif +`ifdef DBG_HWBRK_1 +`undef DBG_HWBRK_1 +`endif +`ifdef DBG_HWBRK_2 +`undef DBG_HWBRK_2 +`endif +`ifdef DBG_HWBRK_3 +`undef DBG_HWBRK_3 +`endif + + +//==========================================================================// +//==========================================================================// +//==========================================================================// +//==========================================================================// +//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// +//==========================================================================// +//==========================================================================// +//==========================================================================// +//==========================================================================// + +// Program and Data Memory sizes +`ifdef PMEM_SIZE +`undef PMEM_SIZE +`endif +`ifdef DMEM_SIZE +`undef DMEM_SIZE +`endif + +// Data Memory Base Adresses +`ifdef DMEM_BASE +`undef DMEM_BASE +`endif + +// Program & Data Memory most significant address bit (for 16 bit words) +`ifdef PMEM_MSB +`undef PMEM_MSB +`endif +`ifdef DMEM_MSB +`undef DMEM_MSB +`endif + + +// Instructions type +`ifdef INST_SO +`undef INST_SO +`endif +`ifdef INST_JMP +`undef INST_JMP +`endif +`ifdef INST_TO +`undef INST_TO +`endif + +// Single-operand arithmetic +`ifdef RRC +`undef RRC +`endif +`ifdef SWPB +`undef SWPB +`endif +`ifdef RRA +`undef RRA +`endif +`ifdef SXT +`undef SXT +`endif +`ifdef PUSH +`undef PUSH +`endif +`ifdef CALL +`undef CALL +`endif +`ifdef RETI +`undef RETI +`endif +`ifdef IRQ +`undef IRQ +`endif + +// Conditional jump +`ifdef JNE +`undef JNE +`endif +`ifdef JEQ +`undef JEQ +`endif +`ifdef JNC +`undef JNC +`endif +`ifdef JC +`undef JC +`endif +`ifdef JN +`undef JN +`endif +`ifdef JGE +`undef JGE +`endif +`ifdef JL +`undef JL +`endif +`ifdef JMP +`undef JMP +`endif + +// Two-operand arithmetic +`ifdef MOV +`undef MOV +`endif +`ifdef ADD +`undef ADD +`endif +`ifdef ADDC +`undef ADDC +`endif +`ifdef SUBC +`undef SUBC +`endif +`ifdef SUB +`undef SUB +`endif +`ifdef CMP +`undef CMP +`endif +`ifdef DADD +`undef DADD +`endif +`ifdef BIT +`undef BIT +`endif +`ifdef BIC +`undef BIC +`endif +`ifdef BIS +`undef BIS +`endif +`ifdef XOR +`undef XOR +`endif +`ifdef AND +`undef AND +`endif + +// Addressing modes +`ifdef DIR +`undef DIR +`endif +`ifdef IDX +`undef IDX +`endif +`ifdef INDIR +`undef INDIR +`endif +`ifdef INDIR_I +`undef INDIR_I +`endif +`ifdef SYMB +`undef SYMB +`endif +`ifdef IMM +`undef IMM +`endif +`ifdef ABS +`undef ABS +`endif +`ifdef CONST +`undef CONST +`endif + +// Execution state machine +`ifdef E_IRQ_0 +`undef E_IRQ_0 +`endif +`ifdef E_IRQ_1 +`undef E_IRQ_1 +`endif +`ifdef E_IRQ_2 +`undef E_IRQ_2 +`endif +`ifdef E_IRQ_3 +`undef E_IRQ_3 +`endif +`ifdef E_IRQ_4 +`undef E_IRQ_4 +`endif +`ifdef E_SRC_AD +`undef E_SRC_AD +`endif +`ifdef E_SRC_RD +`undef E_SRC_RD +`endif +`ifdef E_SRC_WR +`undef E_SRC_WR +`endif +`ifdef E_DST_AD +`undef E_DST_AD +`endif +`ifdef E_DST_RD +`undef E_DST_RD +`endif +`ifdef E_DST_WR +`undef E_DST_WR +`endif +`ifdef E_EXEC +`undef E_EXEC +`endif +`ifdef E_JUMP +`undef E_JUMP +`endif +`ifdef E_IDLE +`undef E_IDLE +`endif + +// ALU control signals +`ifdef ALU_SRC_INV +`undef ALU_SRC_INV +`endif +`ifdef ALU_INC +`undef ALU_INC +`endif +`ifdef ALU_INC_C +`undef ALU_INC_C +`endif +`ifdef ALU_ADD +`undef ALU_ADD +`endif +`ifdef ALU_AND +`undef ALU_AND +`endif +`ifdef ALU_OR +`undef ALU_OR +`endif +`ifdef ALU_XOR +`undef ALU_XOR +`endif +`ifdef ALU_DADD +`undef ALU_DADD +`endif +`ifdef ALU_STAT_7 +`undef ALU_STAT_7 +`endif +`ifdef ALU_STAT_F +`undef ALU_STAT_F +`endif +`ifdef ALU_SHIFT +`undef ALU_SHIFT +`endif +`ifdef EXEC_NO_WR +`undef EXEC_NO_WR +`endif + +// Debug interface +`ifdef DBG_UART_WR +`undef DBG_UART_WR +`endif +`ifdef DBG_UART_BW +`undef DBG_UART_BW +`endif +`ifdef DBG_UART_ADDR +`undef DBG_UART_ADDR +`endif + +// Debug interface CPU_CTL register +`ifdef HALT +`undef HALT +`endif +`ifdef RUN +`undef RUN +`endif +`ifdef ISTEP +`undef ISTEP +`endif +`ifdef SW_BRK_EN +`undef SW_BRK_EN +`endif +`ifdef FRZ_BRK_EN +`undef FRZ_BRK_EN +`endif +`ifdef RST_BRK_EN +`undef RST_BRK_EN +`endif +`ifdef CPU_RST +`undef CPU_RST +`endif + +// Debug interface CPU_STAT register +`ifdef HALT_RUN +`undef HALT_RUN +`endif +`ifdef PUC_PND +`undef PUC_PND +`endif +`ifdef SWBRK_PND +`undef SWBRK_PND +`endif +`ifdef HWBRK0_PND +`undef HWBRK0_PND +`endif +`ifdef HWBRK1_PND +`undef HWBRK1_PND +`endif + +// Debug interface BRKx_CTL register +`ifdef BRK_MODE_RD +`undef BRK_MODE_RD +`endif +`ifdef BRK_MODE_WR +`undef BRK_MODE_WR +`endif +`ifdef BRK_MODE +`undef BRK_MODE +`endif +`ifdef BRK_EN +`undef BRK_EN +`endif +`ifdef BRK_I_EN +`undef BRK_I_EN +`endif +`ifdef BRK_RANGE +`undef BRK_RANGE +`endif + +// Basic clock module: BCSCTL1 Control Register +`ifdef DIVAx +`undef DIVAx +`endif + +// Basic clock module: BCSCTL2 Control Register +`ifdef SELS +`undef SELS +`endif +`ifdef DIVSx +`undef DIVSx +`endif + +// Timer A: TACTL Control Register +`ifdef TASSELx +`undef TASSELx +`endif +`ifdef TAIDx +`undef TAIDx +`endif +`ifdef TAMCx +`undef TAMCx +`endif +`ifdef TACLR +`undef TACLR +`endif +`ifdef TAIE +`undef TAIE +`endif +`ifdef TAIFG +`undef TAIFG +`endif + +// Timer A: TACCTLx Capture/Compare Control Register +`ifdef TACMx +`undef TACMx +`endif +`ifdef TACCISx +`undef TACCISx +`endif +`ifdef TASCS +`undef TASCS +`endif +`ifdef TASCCI +`undef TASCCI +`endif +`ifdef TACAP +`undef TACAP +`endif +`ifdef TAOUTMODx +`undef TAOUTMODx +`endif +`ifdef TACCIE +`undef TACCIE +`endif +`ifdef TACCI +`undef TACCI +`endif +`ifdef TAOUT +`undef TAOUT +`endif +`ifdef TACOV +`undef TACOV +`endif +`ifdef TACCIFG +`undef TACCIFG +`endif + +// +// DEBUG INTERFACE EXTRA CONFIGURATION +//====================================== + +// Debug interface: Software breakpoint opcode +`ifdef DBG_SWBRK_OP +`undef DBG_SWBRK_OP +`endif + +// Debug interface ID +`ifdef DBG_ID +`undef DBG_ID +`endif + +// Debug UART interface auto data synchronization +`ifdef DBG_UART_AUTO_SYNC +`undef DBG_UART_AUTO_SYNC +`endif + +// Debug UART interface data rate +`ifdef DBG_UART_BAUD +`undef DBG_UART_BAUD +`endif +`ifdef DBG_DCO_FREQ +`undef DBG_DCO_FREQ +`endif +`ifdef DBG_UART_CNT +`undef DBG_UART_CNT +`endif
openmsp430/trunk/core/synthesis/altera/src/openMSP430_undefines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/run_analysis.tcl =================================================================== --- openmsp430/trunk/core/synthesis/altera/run_analysis.tcl (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/run_analysis.tcl (revision 63) @@ -0,0 +1,198 @@ +#!/usr/bin/tclsh +#------------------------------------------------------------------------------ +# Copyright (C) 2001 Authors +# +# This source file may be used and distributed without restriction provided +# that this copyright statement is not removed from the file and that any +# derivative work contains the original copyright notice and the associated +# disclaimer. +# +# This source file is free software; you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published +# by the Free Software Foundation; either version 2.1 of the License, or +# (at your option) any later version. +# +# This source is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +# License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this source; if not, write to the Free Software Foundation, +# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +# +#------------------------------------------------------------------------------ +# +# File Name: run_analysis.tcl +# +# Author(s): +# - Olivier Girard, olgirard@gmail.com +# +#------------------------------------------------------------------------------ +# $Rev: 17 $ +# $LastChangedBy: olivier.girard $ +# $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ +#------------------------------------------------------------------------------ + +############################################################################### +# SET SOME GLOBAL VARIABLES # +############################################################################### + +# Analysis type +set analysisType SPEED +#set analysisType AREA + +# Set the different FPGA architectures & models to be checked +set fpgaConfigs {{"Cyclone II" EP2C20F484C {6 7 8}} + {"Cyclone III" EP3C55F484C {6 7 8}} + {"Cyclone IV GX" EP4CGX22CF19C {6 7 8}} + {"Arria GX" EP1AGX50CF484C {6}} + {"Arria II GX" EP2AGX45DF29C {4 5 6}} + {"Stratix" EP1S10F484C {5 6 7}} + {"Stratix II" EP2S15F484C {3 4 5}} + {"Stratix III" EP3SE50F484C {2 3 4}}} +set fpgaConfigs {{"Cyclone II" EP2C20F484C {7}}} + + +# Set the different RTL configurations to be analysed +set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3} +set rtlConfigs {{ 12 10 0 0 0 0 0 } + { 12 10 1 0 0 0 0 } + { 12 10 1 1 0 0 0 } + { 12 10 1 1 1 0 0 } + { 12 10 1 1 1 1 0 } + { 12 10 1 1 1 1 1 }} +set rtlConfigs {{ 12 10 0 0 0 0 0 }} + + +# RTL configuration files +set omspConfigFile "../../rtl/verilog/openMSP430_defines.v" +set rtlConfigFile "./src/arch.v" + + +############################################################################### +# PERFORM ANALYSIS # +############################################################################### + + +foreach rtlConfig $rtlConfigs { + + #-------------------------------------------------------------------------# + # Generate RTL configuration # + #-------------------------------------------------------------------------# + + # Read original define file + if [catch {open $omspConfigFile r} f_omspConfigFile] { + puts "ERROR: Cannot open file $omspConfigFile" + exit 1 + } + set configFile [read $f_omspConfigFile] + close $f_omspConfigFile + + + # Update defines + set idx 0 + foreach rtlDefine $rtlDefines { + + if {[regsub "`define\\s+$rtlDefine\\s+\\d+" $configFile "`define $rtlDefine [lindex $rtlConfig $idx]" configFile]} { + } else { + if {[lindex $rtlConfig $idx]==0} { + regsub "\\n`define\\s+$rtlDefine" $configFile "\n//`define $rtlDefine" configFile + } + } + set idx [expr $idx+1] + } + + + # Write the new file + set f_configFile [open "./src/[file tail $omspConfigFile]" w] + puts $f_configFile $configFile + close $f_configFile + + + #-------------------------------------------------------------------------# + # Perform analysis for each FPGA # + #-------------------------------------------------------------------------# + foreach fpgaConfig $fpgaConfigs { + foreach speedGrade [lindex $fpgaConfig 2] { + + # Create verilog arch define + set f_configFile [open $rtlConfigFile w] + regsub -all {\s} [lindex $fpgaConfig 0] {_} defineName + set defineName [string toupper $defineName] + puts $f_configFile "\n`define $defineName\n" + close $f_configFile + + # Cleanup + file delete -force ./WORK + file mkdir ./WORK + cd ./WORK + + # Copy Quartus tcl command file + if [catch {open "../openMSP430_fpga.tcl" r} f_quartus_tcl] { + puts "ERROR: Cannot open Quartus command file file ../openMSP430_fpga.tcl" + exit 1 + } + set quartus_tcl [read $f_quartus_tcl] + close $f_quartus_tcl + + set fpgaName "[lindex $fpgaConfig 1]$speedGrade" + + regsub -all {} $quartus_tcl "$fpgaName" quartus_tcl + regsub -all {} $quartus_tcl "[lindex $fpgaConfig 0]" quartus_tcl + regsub -all {} $quartus_tcl "$analysisType" quartus_tcl + + set f_quartus_tcl [open "openMSP430_fpga.tcl" w] + puts $f_quartus_tcl $quartus_tcl + close $f_quartus_tcl + + # Run synthesis + puts "#####################################################################################" + puts "# START SYNTHESIS ($analysisType optimized)" + puts "#====================================================================================" + puts "# [lindex $fpgaConfig 0] ([lindex $fpgaConfig 1]), speedgrade: -$speedGrade" + puts "#====================================================================================" + puts "# $rtlDefines" + puts "# $rtlConfig" + puts "#====================================================================================" + if {[catch "exec quartus_sh -t openMSP430_fpga.tcl | tee quartus_sh.log"]} { + puts "ERROR: Synthesis error !!!!!!" + exit 1 + } + + # Extract timing information + if [catch {open "openMSP430_fpga.tan.summary" r} f_timing] { + if [catch {open "openMSP430_fpga.sta.rpt" r} f_timing] { + puts "ERROR: Cannot open timing file" + exit 1 + } + } + set timingFile [read $f_timing] + close $f_timing + if {![regexp {(Type\s+?: Clock Setup: 'dco_clk'.*?)From} $timingFile whole_match timing]} { + regexp {([^\n]+?\n;\s+Slow .*?Model Fmax Summary[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n[^\n]+?\n)} $timingFile whole_match timing + } + puts $timing + puts "====================================================================================" + + # Extract size information + if [catch {open "openMSP430_fpga.fit.summary" r} f_log] { + puts "ERROR: Cannot open timing file openMSP430_fpga.fit.summary" + exit 1 + } + set logFile [read $f_log] + close $f_log + regexp {Timing Models[^\n]+\n(.+)} $logFile whole_match area + puts $area + puts "====================================================================================" + + puts "# SYNTHESIS DONE" + puts "#####################################################################################" + puts "" + cd ../ + } + } + +} + +exit 0
openmsp430/trunk/core/synthesis/altera/run_analysis.tcl Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: openmsp430/trunk/core/synthesis/altera/run_analysis.area.log =================================================================== --- openmsp430/trunk/core/synthesis/altera/run_analysis.area.log (nonexistent) +++ openmsp430/trunk/core/synthesis/altera/run_analysis.area.log (revision 63) @@ -0,0 +1,4146 @@ +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -18.233 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 44.64 MHz ( period = 22.399 ns ) + +==================================================================================== +Total logic elements : 1,552 / 18,752 ( 8 % ) + Total combinational functions : 1,524 / 18,752 ( 8 % ) + Dedicated logic registers : 467 / 18,752 ( 2 % ) +Total registers : 467 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -21.942 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 38.30 MHz ( period = 26.108 ns ) + +==================================================================================== +Total logic elements : 1,556 / 18,752 ( 8 % ) + Total combinational functions : 1,524 / 18,752 ( 8 % ) + Dedicated logic registers : 467 / 18,752 ( 2 % ) +Total registers : 467 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -27.052 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 32.03 MHz ( period = 31.218 ns ) + +==================================================================================== +Total logic elements : 1,555 / 18,752 ( 8 % ) + Total combinational functions : 1,524 / 18,752 ( 8 % ) + Dedicated logic registers : 467 / 18,752 ( 2 % ) +Total registers : 467 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 50.83 MHz ; 50.83 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,539 / 55,856 ( 3 % ) + Total combinational functions : 1,524 / 55,856 ( 3 % ) + Dedicated logic registers : 467 / 55,856 ( < 1 % ) +Total registers : 467 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.52 MHz ; 42.52 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,539 / 55,856 ( 3 % ) + Total combinational functions : 1,524 / 55,856 ( 3 % ) + Dedicated logic registers : 467 / 55,856 ( < 1 % ) +Total registers : 467 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 36.44 MHz ; 36.44 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,542 / 55,856 ( 3 % ) + Total combinational functions : 1,524 / 55,856 ( 3 % ) + Dedicated logic registers : 467 / 55,856 ( < 1 % ) +Total registers : 467 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 49.46 MHz ; 49.46 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,541 / 21,280 ( 7 % ) + Total combinational functions : 1,524 / 21,280 ( 7 % ) + Dedicated logic registers : 467 / 21,280 ( 2 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.15 MHz ; 42.15 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,540 / 21,280 ( 7 % ) + Total combinational functions : 1,524 / 21,280 ( 7 % ) + Dedicated logic registers : 467 / 21,280 ( 2 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 38.23 MHz ; 38.23 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 1,544 / 21,280 ( 7 % ) + Total combinational functions : 1,524 / 21,280 ( 7 % ) + Dedicated logic registers : 467 / 21,280 ( 2 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 44.91 MHz ; 44.91 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,044 / 40,128 ( 3 % ) + Dedicated logic registers : 468 / 40,128 ( 1 % ) +Total registers : 468 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 78.7 MHz ; 78.7 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,031 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 469 / 36,100 ( 1 % ) +Total registers : 469 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 69.33 MHz ; 69.33 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,025 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 467 / 36,100 ( 1 % ) +Total registers : 467 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 58.82 MHz ; 58.82 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,032 / 36,100 ( 3 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 469 / 36,100 ( 1 % ) +Total registers : 469 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -19.609 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 42.06 MHz ( period = 23.775 ns ) + +==================================================================================== +Total logic elements : 1,525 / 10,570 ( 14 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.451 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 37.57 MHz ( period = 26.617 ns ) + +==================================================================================== +Total logic elements : 1,525 / 10,570 ( 14 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.100 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 33.04 MHz ( period = 30.266 ns ) + +==================================================================================== +Total logic elements : 1,525 / 10,570 ( 14 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -10.537 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 68.01 MHz ( period = 14.703 ns ) + +==================================================================================== +Logic utilization : 12 % + Combinational ALUTs : 1,040 / 12,480 ( 8 % ) + Dedicated logic registers : 469 / 12,480 ( 4 % ) +Total registers : 469 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -12.314 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 60.68 MHz ( period = 16.480 ns ) + +==================================================================================== +Logic utilization : 12 % + Combinational ALUTs : 1,039 / 12,480 ( 8 % ) + Dedicated logic registers : 469 / 12,480 ( 4 % ) +Total registers : 469 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -15.259 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 51.48 MHz ( period = 19.425 ns ) + +==================================================================================== +Logic utilization : 12 % + Combinational ALUTs : 1,039 / 12,480 ( 8 % ) + Dedicated logic registers : 469 / 12,480 ( 4 % ) +Total registers : 469 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 95.14 MHz ; 95.14 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,029 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 468 / 38,000 ( 1 % ) +Total registers : 468 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 77.32 MHz ; 77.32 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,033 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 469 / 38,000 ( 1 % ) +Total registers : 469 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 0 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 67.02 MHz ; 67.02 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 4 % + Combinational ALUTs : 1,030 / 38,000 ( 3 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 469 / 38,000 ( 1 % ) +Total registers : 469 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -19.465 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 42.32 MHz ( period = 23.631 ns ) + +==================================================================================== +Total logic elements : 2,040 / 18,752 ( 11 % ) + Total combinational functions : 1,986 / 18,752 ( 11 % ) + Dedicated logic registers : 610 / 18,752 ( 3 % ) +Total registers : 610 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.845 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 37.02 MHz ( period = 27.011 ns ) + +==================================================================================== +Total logic elements : 2,049 / 18,752 ( 11 % ) + Total combinational functions : 1,986 / 18,752 ( 11 % ) + Dedicated logic registers : 610 / 18,752 ( 3 % ) +Total registers : 610 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -28.597 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 30.52 MHz ( period = 32.763 ns ) + +==================================================================================== +Total logic elements : 2,047 / 18,752 ( 11 % ) + Total combinational functions : 1,986 / 18,752 ( 11 % ) + Dedicated logic registers : 610 / 18,752 ( 3 % ) +Total registers : 610 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 47.44 MHz ; 47.44 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,021 / 55,856 ( 4 % ) + Total combinational functions : 1,986 / 55,856 ( 4 % ) + Dedicated logic registers : 610 / 55,856 ( 1 % ) +Total registers : 610 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 40.75 MHz ; 40.75 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,022 / 55,856 ( 4 % ) + Total combinational functions : 1,986 / 55,856 ( 4 % ) + Dedicated logic registers : 610 / 55,856 ( 1 % ) +Total registers : 610 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 34.93 MHz ; 34.93 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,020 / 55,856 ( 4 % ) + Total combinational functions : 1,986 / 55,856 ( 4 % ) + Dedicated logic registers : 610 / 55,856 ( 1 % ) +Total registers : 610 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 43.79 MHz ; 43.79 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,024 / 21,280 ( 10 % ) + Total combinational functions : 1,986 / 21,280 ( 9 % ) + Dedicated logic registers : 610 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 40.19 MHz ; 40.19 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,024 / 21,280 ( 10 % ) + Total combinational functions : 1,986 / 21,280 ( 9 % ) + Dedicated logic registers : 610 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 35.17 MHz ; 35.17 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,020 / 21,280 ( 9 % ) + Total combinational functions : 1,986 / 21,280 ( 9 % ) + Dedicated logic registers : 610 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.58 MHz ; 42.58 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,414 / 40,128 ( 4 % ) + Dedicated logic registers : 612 / 40,128 ( 2 % ) +Total registers : 612 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 75.35 MHz ; 75.35 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,407 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 611 / 36,100 ( 2 % ) +Total registers : 611 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 64.68 MHz ; 64.68 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,404 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 612 / 36,100 ( 2 % ) +Total registers : 612 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 56.88 MHz ; 56.88 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,403 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 611 / 36,100 ( 2 % ) +Total registers : 611 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -19.716 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 41.87 MHz ( period = 23.882 ns ) + +==================================================================================== +Total logic elements : 1,989 / 10,570 ( 19 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.375 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 37.68 MHz ( period = 26.541 ns ) + +==================================================================================== +Total logic elements : 1,989 / 10,570 ( 19 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.629 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 32.47 MHz ( period = 30.795 ns ) + +==================================================================================== +Total logic elements : 1,989 / 10,570 ( 19 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -11.102 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 65.50 MHz ( period = 15.268 ns ) + +==================================================================================== +Logic utilization : 15 % + Combinational ALUTs : 1,422 / 12,480 ( 11 % ) + Dedicated logic registers : 610 / 12,480 ( 5 % ) +Total registers : 610 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -13.025 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 58.17 MHz ( period = 17.191 ns ) + +==================================================================================== +Logic utilization : 15 % + Combinational ALUTs : 1,424 / 12,480 ( 11 % ) + Dedicated logic registers : 613 / 12,480 ( 5 % ) +Total registers : 613 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -16.270 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 48.93 MHz ( period = 20.436 ns ) + +==================================================================================== +Logic utilization : 15 % + Combinational ALUTs : 1,419 / 12,480 ( 11 % ) + Dedicated logic registers : 617 / 12,480 ( 5 % ) +Total registers : 617 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 85.01 MHz ; 85.01 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,408 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 611 / 38,000 ( 2 % ) +Total registers : 611 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 76.03 MHz ; 76.03 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,414 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 610 / 38,000 ( 2 % ) +Total registers : 610 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 0 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 68.06 MHz ; 68.06 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,411 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 614 / 38,000 ( 2 % ) +Total registers : 614 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -20.249 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 40.96 MHz ( period = 24.415 ns ) + +==================================================================================== +Total logic elements : 2,179 / 18,752 ( 12 % ) + Total combinational functions : 2,115 / 18,752 ( 11 % ) + Dedicated logic registers : 653 / 18,752 ( 3 % ) +Total registers : 653 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -25.336 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 33.90 MHz ( period = 29.502 ns ) + +==================================================================================== +Total logic elements : 2,191 / 18,752 ( 12 % ) + Total combinational functions : 2,115 / 18,752 ( 11 % ) + Dedicated logic registers : 653 / 18,752 ( 3 % ) +Total registers : 653 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -29.981 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 29.29 MHz ( period = 34.147 ns ) + +==================================================================================== +Total logic elements : 2,192 / 18,752 ( 12 % ) + Total combinational functions : 2,115 / 18,752 ( 11 % ) + Dedicated logic registers : 653 / 18,752 ( 3 % ) +Total registers : 653 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 45.18 MHz ; 45.18 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,148 / 55,856 ( 4 % ) + Total combinational functions : 2,115 / 55,856 ( 4 % ) + Dedicated logic registers : 653 / 55,856 ( 1 % ) +Total registers : 653 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 41.13 MHz ; 41.13 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,147 / 55,856 ( 4 % ) + Total combinational functions : 2,115 / 55,856 ( 4 % ) + Dedicated logic registers : 653 / 55,856 ( 1 % ) +Total registers : 653 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 35.94 MHz ; 35.94 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,158 / 55,856 ( 4 % ) + Total combinational functions : 2,115 / 55,856 ( 4 % ) + Dedicated logic registers : 653 / 55,856 ( 1 % ) +Total registers : 653 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 48.58 MHz ; 48.58 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,148 / 21,280 ( 10 % ) + Total combinational functions : 2,115 / 21,280 ( 10 % ) + Dedicated logic registers : 653 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 41.31 MHz ; 41.31 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,148 / 21,280 ( 10 % ) + Total combinational functions : 2,115 / 21,280 ( 10 % ) + Dedicated logic registers : 653 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 36.91 MHz ; 36.91 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,147 / 21,280 ( 10 % ) + Total combinational functions : 2,115 / 21,280 ( 10 % ) + Dedicated logic registers : 653 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 40.31 MHz ; 40.31 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,525 / 40,128 ( 4 % ) + Dedicated logic registers : 656 / 40,128 ( 2 % ) +Total registers : 656 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 71.15 MHz ; 71.15 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,507 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 654 / 36,100 ( 2 % ) +Total registers : 654 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 64.7 MHz ; 64.7 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,503 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 654 / 36,100 ( 2 % ) +Total registers : 654 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 55.27 MHz ; 55.27 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,506 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 659 / 36,100 ( 2 % ) +Total registers : 659 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -20.449 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 40.63 MHz ( period = 24.615 ns ) + +==================================================================================== +Total logic elements : 2,081 / 10,570 ( 20 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -24.172 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 35.29 MHz ( period = 28.338 ns ) + +==================================================================================== +Total logic elements : 2,081 / 10,570 ( 20 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -28.410 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 30.70 MHz ( period = 32.576 ns ) + +==================================================================================== +Total logic elements : 2,081 / 10,570 ( 20 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -11.138 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 65.34 MHz ( period = 15.304 ns ) + +==================================================================================== +Logic utilization : 16 % + Combinational ALUTs : 1,523 / 12,480 ( 12 % ) + Dedicated logic registers : 655 / 12,480 ( 5 % ) +Total registers : 655 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -13.500 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 56.61 MHz ( period = 17.666 ns ) + +==================================================================================== +Logic utilization : 16 % + Combinational ALUTs : 1,529 / 12,480 ( 12 % ) + Dedicated logic registers : 658 / 12,480 ( 5 % ) +Total registers : 658 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -16.427 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 48.56 MHz ( period = 20.593 ns ) + +==================================================================================== +Logic utilization : 16 % + Combinational ALUTs : 1,527 / 12,480 ( 12 % ) + Dedicated logic registers : 655 / 12,480 ( 5 % ) +Total registers : 655 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 79.65 MHz ; 79.65 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,511 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 656 / 38,000 ( 2 % ) +Total registers : 656 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 72.71 MHz ; 72.71 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,506 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 656 / 38,000 ( 2 % ) +Total registers : 656 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 0 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 66.57 MHz ; 66.57 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,505 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 658 / 38,000 ( 2 % ) +Total registers : 658 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.023 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 38.18 MHz ( period = 26.189 ns ) + +==================================================================================== +Total logic elements : 2,286 / 18,752 ( 12 % ) + Total combinational functions : 2,208 / 18,752 ( 12 % ) + Dedicated logic registers : 695 / 18,752 ( 4 % ) +Total registers : 695 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.679 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 32.42 MHz ( period = 30.845 ns ) + +==================================================================================== +Total logic elements : 2,298 / 18,752 ( 12 % ) + Total combinational functions : 2,208 / 18,752 ( 12 % ) + Dedicated logic registers : 695 / 18,752 ( 4 % ) +Total registers : 695 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -33.074 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 26.85 MHz ( period = 37.240 ns ) + +==================================================================================== +Total logic elements : 2,290 / 18,752 ( 12 % ) + Total combinational functions : 2,208 / 18,752 ( 12 % ) + Dedicated logic registers : 695 / 18,752 ( 4 % ) +Total registers : 695 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 45.33 MHz ; 45.33 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,251 / 55,856 ( 4 % ) + Total combinational functions : 2,208 / 55,856 ( 4 % ) + Dedicated logic registers : 695 / 55,856 ( 1 % ) +Total registers : 695 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 40.39 MHz ; 40.39 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,244 / 55,856 ( 4 % ) + Total combinational functions : 2,208 / 55,856 ( 4 % ) + Dedicated logic registers : 695 / 55,856 ( 1 % ) +Total registers : 695 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 34.44 MHz ; 34.44 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,243 / 55,856 ( 4 % ) + Total combinational functions : 2,208 / 55,856 ( 4 % ) + Dedicated logic registers : 695 / 55,856 ( 1 % ) +Total registers : 695 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 47.56 MHz ; 47.56 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,246 / 21,280 ( 11 % ) + Total combinational functions : 2,208 / 21,280 ( 10 % ) + Dedicated logic registers : 695 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 39.75 MHz ; 39.75 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,247 / 21,280 ( 11 % ) + Total combinational functions : 2,208 / 21,280 ( 10 % ) + Dedicated logic registers : 695 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 36.35 MHz ; 36.35 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,244 / 21,280 ( 11 % ) + Total combinational functions : 2,208 / 21,280 ( 10 % ) + Dedicated logic registers : 695 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.28 MHz ; 42.28 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,588 / 40,128 ( 4 % ) + Dedicated logic registers : 708 / 40,128 ( 2 % ) +Total registers : 708 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 71.18 MHz ; 71.18 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,577 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 706 / 36,100 ( 2 % ) +Total registers : 706 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 67.53 MHz ; 67.53 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,600 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 708 / 36,100 ( 2 % ) +Total registers : 708 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 57.64 MHz ; 57.64 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,590 / 36,100 ( 4 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 704 / 36,100 ( 2 % ) +Total registers : 704 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -22.306 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 37.78 MHz ( period = 26.472 ns ) + +==================================================================================== +Total logic elements : 2,185 / 10,570 ( 21 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -25.123 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 34.14 MHz ( period = 29.289 ns ) + +==================================================================================== +Total logic elements : 2,185 / 10,570 ( 21 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -29.818 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 29.43 MHz ( period = 33.984 ns ) + +==================================================================================== +Total logic elements : 2,185 / 10,570 ( 21 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -11.982 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 61.93 MHz ( period = 16.148 ns ) + +==================================================================================== +Logic utilization : 17 % + Combinational ALUTs : 1,590 / 12,480 ( 13 % ) + Dedicated logic registers : 698 / 12,480 ( 6 % ) +Total registers : 698 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -14.069 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 54.84 MHz ( period = 18.235 ns ) + +==================================================================================== +Logic utilization : 17 % + Combinational ALUTs : 1,601 / 12,480 ( 13 % ) + Dedicated logic registers : 699 / 12,480 ( 6 % ) +Total registers : 699 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -17.377 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 46.42 MHz ( period = 21.543 ns ) + +==================================================================================== +Logic utilization : 17 % + Combinational ALUTs : 1,592 / 12,480 ( 13 % ) + Dedicated logic registers : 698 / 12,480 ( 6 % ) +Total registers : 698 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 83.39 MHz ; 83.39 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,597 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 702 / 38,000 ( 2 % ) +Total registers : 702 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 72.2 MHz ; 72.2 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,588 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 699 / 38,000 ( 2 % ) +Total registers : 699 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 0 0 +#==================================================================================== ++------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 65.3 MHz ; 65.3 MHz ; dco_clk ; ; ++----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,587 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 700 / 38,000 ( 2 % ) +Total registers : 700 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -21.828 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 38.47 MHz ( period = 25.994 ns ) + +==================================================================================== +Total logic elements : 2,418 / 18,752 ( 13 % ) + Total combinational functions : 2,321 / 18,752 ( 12 % ) + Dedicated logic registers : 737 / 18,752 ( 4 % ) +Total registers : 737 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -25.495 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 33.71 MHz ( period = 29.661 ns ) + +==================================================================================== +Total logic elements : 2,414 / 18,752 ( 13 % ) + Total combinational functions : 2,321 / 18,752 ( 12 % ) + Dedicated logic registers : 737 / 18,752 ( 4 % ) +Total registers : 737 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -31.011 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 28.43 MHz ( period = 35.177 ns ) + +==================================================================================== +Total logic elements : 2,406 / 18,752 ( 13 % ) + Total combinational functions : 2,321 / 18,752 ( 12 % ) + Dedicated logic registers : 737 / 18,752 ( 4 % ) +Total registers : 737 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 42.84 MHz ; 42.84 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,357 / 55,856 ( 4 % ) + Total combinational functions : 2,321 / 55,856 ( 4 % ) + Dedicated logic registers : 737 / 55,856 ( 1 % ) +Total registers : 737 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 38.45 MHz ; 38.45 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,363 / 55,856 ( 4 % ) + Total combinational functions : 2,321 / 55,856 ( 4 % ) + Dedicated logic registers : 737 / 55,856 ( 1 % ) +Total registers : 737 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 32.46 MHz ; 32.46 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,380 / 55,856 ( 4 % ) + Total combinational functions : 2,321 / 55,856 ( 4 % ) + Dedicated logic registers : 737 / 55,856 ( 1 % ) +Total registers : 737 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 45.52 MHz ; 45.52 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,364 / 21,280 ( 11 % ) + Total combinational functions : 2,321 / 21,280 ( 11 % ) + Dedicated logic registers : 737 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 39.03 MHz ; 39.03 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,366 / 21,280 ( 11 % ) + Total combinational functions : 2,321 / 21,280 ( 11 % ) + Dedicated logic registers : 737 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 33.57 MHz ; 33.57 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,363 / 21,280 ( 11 % ) + Total combinational functions : 2,321 / 21,280 ( 11 % ) + Dedicated logic registers : 737 / 21,280 ( 3 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 41.54 MHz ; 41.54 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 5 % + Combinational ALUTs : 1,675 / 40,128 ( 4 % ) + Dedicated logic registers : 744 / 40,128 ( 2 % ) +Total registers : 744 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 75.35 MHz ; 75.35 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,668 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 749 / 36,100 ( 2 % ) +Total registers : 749 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 64.23 MHz ; 64.23 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,670 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 744 / 36,100 ( 2 % ) +Total registers : 744 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 53.69 MHz ; 53.69 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,677 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 753 / 36,100 ( 2 % ) +Total registers : 753 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -21.281 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 39.30 MHz ( period = 25.447 ns ) + +==================================================================================== +Total logic elements : 2,279 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -24.434 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 34.97 MHz ( period = 28.600 ns ) + +==================================================================================== +Total logic elements : 2,279 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -27.769 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 31.31 MHz ( period = 31.935 ns ) + +==================================================================================== +Total logic elements : 2,279 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -11.395 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 64.26 MHz ( period = 15.561 ns ) + +==================================================================================== +Logic utilization : 18 % + Combinational ALUTs : 1,665 / 12,480 ( 13 % ) + Dedicated logic registers : 739 / 12,480 ( 6 % ) +Total registers : 739 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -13.731 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 55.88 MHz ( period = 17.897 ns ) + +==================================================================================== +Logic utilization : 18 % + Combinational ALUTs : 1,671 / 12,480 ( 13 % ) + Dedicated logic registers : 741 / 12,480 ( 6 % ) +Total registers : 741 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -16.325 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 48.80 MHz ( period = 20.491 ns ) + +==================================================================================== +Logic utilization : 17 % + Combinational ALUTs : 1,678 / 12,480 ( 13 % ) + Dedicated logic registers : 741 / 12,480 ( 6 % ) +Total registers : 741 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 80.04 MHz ; 80.04 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,666 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 752 / 38,000 ( 2 % ) +Total registers : 752 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 73.58 MHz ; 73.58 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,675 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 753 / 38,000 ( 2 % ) +Total registers : 753 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 0 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 63.16 MHz ; 63.16 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,670 / 38,000 ( 4 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 754 / 38,000 ( 2 % ) +Total registers : 754 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -21.627 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 38.77 MHz ( period = 25.793 ns ) + +==================================================================================== +Total logic elements : 2,507 / 18,752 ( 13 % ) + Total combinational functions : 2,391 / 18,752 ( 13 % ) + Dedicated logic registers : 779 / 18,752 ( 4 % ) +Total registers : 779 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -26.226 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 32.90 MHz ( period = 30.392 ns ) + +==================================================================================== +Total logic elements : 2,508 / 18,752 ( 13 % ) + Total combinational functions : 2,391 / 18,752 ( 13 % ) + Dedicated logic registers : 779 / 18,752 ( 4 % ) +Total registers : 779 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone II (EP2C20F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -30.704 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 28.68 MHz ( period = 34.870 ns ) + +==================================================================================== +Total logic elements : 2,524 / 18,752 ( 13 % ) + Total combinational functions : 2,391 / 18,752 ( 13 % ) + Dedicated logic registers : 779 / 18,752 ( 4 % ) +Total registers : 779 +Total pins : 80 / 315 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 239,616 ( 34 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 43.28 MHz ; 43.28 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,450 / 55,856 ( 4 % ) + Total combinational functions : 2,391 / 55,856 ( 4 % ) + Dedicated logic registers : 779 / 55,856 ( 1 % ) +Total registers : 779 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 37.12 MHz ; 37.12 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,443 / 55,856 ( 4 % ) + Total combinational functions : 2,391 / 55,856 ( 4 % ) + Dedicated logic registers : 779 / 55,856 ( 1 % ) +Total registers : 779 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone III (EP3C55F484C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 33.03 MHz ; 33.03 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,448 / 55,856 ( 4 % ) + Total combinational functions : 2,391 / 55,856 ( 4 % ) + Dedicated logic registers : 779 / 55,856 ( 1 % ) +Total registers : 779 +Total pins : 80 / 328 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 2,396,160 ( 3 % ) +Embedded Multiplier 9-bit elements : 0 / 312 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 43.56 MHz ; 43.56 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,459 / 21,280 ( 12 % ) + Total combinational functions : 2,391 / 21,280 ( 11 % ) + Dedicated logic registers : 779 / 21,280 ( 4 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 39.87 MHz ; 39.87 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,448 / 21,280 ( 12 % ) + Total combinational functions : 2,391 / 21,280 ( 11 % ) + Dedicated logic registers : 779 / 21,280 ( 4 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Cyclone IV GX (EP4CGX22CF19C), speedgrade: -8 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 34.18 MHz ; 34.18 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Total logic elements : 2,444 / 21,280 ( 11 % ) + Total combinational functions : 2,391 / 21,280 ( 11 % ) + Dedicated logic registers : 779 / 21,280 ( 4 % ) +Total registers : 0 +Total pins : 80 / 167 ( 48 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 774,144 ( 11 % ) +Embedded Multiplier 9-bit elements : 0 / 80 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria GX (EP1AGX50CF484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 41.08 MHz ; 41.08 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,765 / 40,128 ( 4 % ) + Dedicated logic registers : 791 / 40,128 ( 2 % ) +Total registers : 791 +Total pins : 80 / 254 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,475,072 ( 3 % ) +DSP block 9-bit elements : 0 / 208 ( 0 % ) +Total GXB Receiver Channels : 0 / 4 ( 0 % ) +Total GXB Transmitter Channels : 0 / 4 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 72.68 MHz ; 72.68 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,754 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 793 / 36,100 ( 2 % ) +Total registers : 793 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 62.77 MHz ; 62.77 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,742 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 805 / 36,100 ( 2 % ) +Total registers : 805 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Arria II GX (EP2AGX45DF29C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 900mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 57.46 MHz ; 57.46 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 7 % + Combinational ALUTs : 1,755 / 36,100 ( 5 % ) + Memory ALUTs : 0 / 18,050 ( 0 % ) + Dedicated logic registers : 793 / 36,100 ( 2 % ) +Total registers : 793 +Total pins : 80 / 404 ( 20 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 2,939,904 ( 3 % ) +DSP block 18-bit elements : 0 / 232 ( 0 % ) +Total GXB Receiver Channel PCS : 0 / 8 ( 0 % ) +Total GXB Receiver Channel PMA : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PCS : 0 / 8 ( 0 % ) +Total GXB Transmitter Channel PMA : 0 / 8 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -21.713 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 38.64 MHz ( period = 25.879 ns ) + +==================================================================================== +Total logic elements : 2,378 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -6 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -24.014 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 35.49 MHz ( period = 28.180 ns ) + +==================================================================================== +Total logic elements : 2,378 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix (EP1S10F484C), speedgrade: -7 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -29.029 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 30.13 MHz ( period = 33.195 ns ) + +==================================================================================== +Total logic elements : 2,378 / 10,570 ( 22 % ) +Total pins : 80 / 336 ( 24 % ) +Total virtual pins : 0 +Total memory bits : 81,920 / 920,448 ( 9 % ) +DSP block 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -11.976 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 61.95 MHz ( period = 16.142 ns ) + +==================================================================================== +Logic utilization : 19 % + Combinational ALUTs : 1,753 / 12,480 ( 14 % ) + Dedicated logic registers : 783 / 12,480 ( 6 % ) +Total registers : 783 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -14.897 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 52.46 MHz ( period = 19.063 ns ) + +==================================================================================== +Logic utilization : 19 % + Combinational ALUTs : 1,762 / 12,480 ( 14 % ) + Dedicated logic registers : 781 / 12,480 ( 6 % ) +Total registers : 781 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix II (EP2S15F484C), speedgrade: -5 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== +Type : Clock Setup: 'dco_clk' +Slack : -17.945 ns +Required Time : 240.04 MHz ( period = 4.166 ns ) +Actual Time : 45.23 MHz ( period = 22.111 ns ) + +==================================================================================== +Logic utilization : 19 % + Combinational ALUTs : 1,763 / 12,480 ( 14 % ) + Dedicated logic registers : 783 / 12,480 ( 6 % ) +Total registers : 783 +Total pins : 80 / 343 ( 23 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 419,328 ( 20 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -2 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 77.83 MHz ; 77.83 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,748 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 799 / 38,000 ( 2 % ) +Total registers : 799 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -3 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 69.56 MHz ; 69.56 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,754 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 807 / 38,000 ( 2 % ) +Total registers : 807 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### + +##################################################################################### +# START SYNTHESIS (AREA optimized) +#==================================================================================== +# Stratix III (EP3SE50F484C), speedgrade: -4 +#==================================================================================== +# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 +# 12 10 1 1 1 1 1 +#==================================================================================== ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 63.22 MHz ; 63.22 MHz ; dco_clk ; ; ++-----------+-----------------+------------+------+ + +==================================================================================== +Logic utilization : 6 % + Combinational ALUTs : 1,760 / 38,000 ( 5 % ) + Memory ALUTs : 0 / 19,000 ( 0 % ) + Dedicated logic registers : 803 / 38,000 ( 2 % ) +Total registers : 803 +Total pins : 80 / 296 ( 27 % ) +Total virtual pins : 0 +Total block memory bits : 81,920 / 5,455,872 ( 2 % ) +DSP block 18-bit elements : 0 / 384 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) + +==================================================================================== +# SYNTHESIS DONE +##################################################################################### +
openmsp430/trunk/core/synthesis/altera/run_analysis.area.log Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property

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