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URL https://opencores.org/ocsvn/pci/pci/trunk

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Rev 62 → Rev 63

/trunk/bench/verilog/system.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2002/10/08 17:17:02 mihad
// Added BIST signals for RAMs.
//
// Revision 1.8 2002/09/25 09:54:47 mihad
// Added completion expiration test for WB Slave unit. Changed expiration signalling
//
141,6 → 144,7
`ifdef PCI_BIST
wire SO ;
reg SI ;
wire trst = reset_wb ;
reg shift_DR ;
reg capture_DR ;
reg extest ;
210,6 → 214,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
570,19 → 575,36
`endif
 
// pci clock generator
always
`ifdef PCI33
#15 pci_clock = ~pci_clock ;
`ifdef PCI_CLOCK_FOLLOWS_WB_CLOCK
always@(posedge wb_clock)
#`PCI_CLOCK_FOLLOWS_WB_CLOCK pci_clock = 1'b1 ;
 
always@(negedge wb_clock)
#`PCI_CLOCK_FOLLOWS_WB_CLOCK pci_clock = 1'b0 ;
`else
`ifdef PCI66
#7.5 pci_clock = ~pci_clock ;
always
`ifdef PCI33
#15 pci_clock = ~pci_clock ;
`else
`ifdef PCI66
#7.5 pci_clock = ~pci_clock ;
`endif
`endif
`endif
`endif
 
// WISHBONE clock generation
always
#(((1/`WB_FREQ)/2)) wb_clock = ~wb_clock ;
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK
always@(posedge pci_clock)
#`WB_CLOCK_FOLLOWS_PCI_CLOCK wb_clock = 1'b1 ;
 
always@(negedge pci_clock)
#`WB_CLOCK_FOLLOWS_PCI_CLOCK wb_clock = 1'b0 ;
 
`else
always
#(((1/`WB_FREQ)/2)) wb_clock = !wb_clock ;
`endif
 
// Make test name visible when the Master starts working on it
reg [79:0] present_test_name;
reg [79:0] next_test_name;
900,7 → 922,10
 
end
 
`ifdef DISABLE_COMPLETION_EXPIRED_TESTS
`else
master_completion_expiration ;
`endif
 
$display(" ") ;
$display("WB slave images' tests finished!") ;
974,12 → 999,38
 
transaction_ordering ;
 
`ifdef DISABLE_COMPLETION_EXPIRED_TESTS
`else
target_completion_expiration ;
`endif
 
$display(" ") ;
$display("PCI transaction ordering tests finished!") ;
end
end
 
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK
test_target_response[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1 ;
test_target_response[`TARGET_ENCODED_INIT_WAITSTATES] = 0 ;
test_target_response[`TARGET_ENCODED_SUBS_WAITSTATES] = 0 ;
test_target_response[`TARGET_ENCODED_DEVSEL_SPEED] = 0 ;
 
`ifdef HOST
configure_bridge_target ;
`endif
 
@(posedge pci_clock) ;
configure_target(1) ;
@(posedge pci_clock) ;
configure_target(2) ;
 
`ifdef GUEST
configure_bridge_target ;
`endif
 
target_special_corner_case_test ;
`endif
 
test_summary ;
 
$fclose(wbu_mon_log_file_desc | pciu_mon_log_file_desc | pci_mon_log_file_desc) ;
9237,7 → 9288,7
while( CYC_O !== 1 )
@(posedge wb_clock) ;
 
while( CYC_O === 1 )
while( (CYC_O === 1) && ((transfer_counter <= `PCIW_DEPTH) || (transfer_counter <= `PCIR_DEPTH)) )
begin
if ( (STB_O === 1) && (ACK_I === 1) )
transfer_counter = transfer_counter + 1 ;
17987,6 → 18038,8
end
endtask // target_unsupported_cmds
 
`ifdef DISABLE_COMPLETION_EXPIRED_TESTS
`else
task target_completion_expiration ;
reg [11:0] pci_ctrl_offset ;
reg [11:0] pci_ba_offset ;
18885,6 → 18938,7
end
end
endtask // master_completion_expiration
`endif
 
task config_write ;
input [11:0] offset ;
19141,6 → 19195,454
endtask // run_bist_test
`endif
 
`ifdef WB_CLOCK_FOLLOWS_PCI_CLOCK
task target_special_corner_case_test ;
reg [11:0] pci_ctrl_offset ;
reg [11:0] ctrl_offset ;
reg [11:0] ba_offset ;
reg [11:0] am_offset ;
reg ok_wb ;
reg ok_pci ;
reg test_mem ;
reg master_check_data_previous ;
begin:main
master_check_data_previous = master1_check_received_data ;
master1_check_received_data = 1'b1 ;
pci_ctrl_offset = 12'h4 ;
// use image 1 for this test
ctrl_offset = {4'h1, `P_IMG_CTRL1_ADDR, 2'b00} ;
ba_offset = {4'h1, `P_BA1_ADDR, 2'b00} ;
am_offset = {4'h1, `P_AM1_ADDR, 2'b00} ;
 
// set behavioral slave cycle response
`ifdef REGISTER_WBM_OUTPUTS
wishbone_slave.cycle_response
(
3'b100, // {ACK, ERR, RTY}
0, // wait cycles
8'h0 // num of retries before termination
);
`else
wishbone_slave.cycle_response
(
3'b100, // {ACK, ERR, RTY}
1, // wait cycles
8'h0 // num of retries before termination
);
`endif
`ifdef HOST
test_mem = 1 ;
`else
test_mem = `PCI_BA1_MEM_IO ;
test_mem = !test_mem ;
`endif
 
test_name = "PCI TARGET UNIT SPECIAL CORNER CASE" ;
 
// Set Base Address of IMAGE
config_write( ba_offset, Target_Base_Addr_R[1], 4'hF, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("Image testing failed! Failed to write P_BA1 register! Time %t ", $time);
test_fail("PCI Base Address register 1 could not be written") ;
#1 ;
disable main ;
end
 
// Set Address Mask of IMAGE
config_write( am_offset, Target_Addr_Mask_R[1], 4'hF, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("Image testing failed! Failed to write P_AM1 register! Time %t ", $time);
test_fail("PCI Address Mask register 1 could not be written") ;
#1 ;
disable main ;
end
 
// Disable all the features of the PCI Image 1
config_write( ctrl_offset, 0, 4'hF, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("Image testing failed! Failed to write P_CTRL1 register! Time %t ", $time);
test_fail("PCI Image Control register 1 could not be written") ;
#1 ;
disable main ;
end
 
// set waits to max, which means 0 on PCI
tb_init_waits = 4 ;
tb_subseq_waits = 4 ;
 
// do one dummy write, to receive a GNT park
if (test_mem)
begin
PCIU_MEM_WRITE
(
"MEM_WRITE ", // just the name
`Test_Master_1, // Behavioral Master to use for reference
Target_Base_Addr_R[1], // Address of this transaction
32'hAAAA_AAAA, // Data For the transaction
4'h0, // Byte enables
1, // length of transfer
`Test_One_Zero_Master_WS, // Master Waits - don't care
`Test_One_Zero_Target_WS, // Expected Target Wait State Response
`Test_Devsel_Medium, // Expected Target DEVSEL Speed Response
`Test_Target_Normal_Completion // Expected Target Termination Response
);
end
else
begin
PCIU_IO_WRITE
(
`Test_Master_1, // Behavioral Master to use for reference
Target_Base_Addr_R[1], // Address of this transaction
32'hAAAA_AAAA, // Data For the transaction
4'h0, // Byte enables
1, // Size of transfer
`Test_Target_Normal_Completion // Expected Target Termination Response
) ;
end
 
do_pause( 1 ) ;
wb_transaction_progress_monitor
(
Target_Base_Addr_R[1], // expected address
1'b1, // expected operation R/W
1, // 1
1'b1, // turn checking of transfers ON/OFF
ok_wb // succeeded/failed
) ;
 
if (ok_wb !== 1'b1)
begin
test_fail("WB Transaction Monitor detected invalid transaction on WB bus after posted memory write through target") ;
#1 ;
disable main ;
end
 
fork
begin
if (test_mem)
begin
PCIU_MEM_WRITE
(
"MEM_WRITE ", // just the name
`Test_Master_1, // Behavioral Master to use for reference
Target_Base_Addr_R[1] + 64, // Address of this transaction
32'hF0F0_F0F0, // Data For the transaction
4'h0, // Byte enables
1, // length of transfer
`Test_One_Zero_Master_WS, // Master Waits - don't care
`Test_One_Zero_Target_WS, // Expected Target Wait State Response
`Test_Devsel_Medium, // Expected Target DEVSEL Speed Response
`Test_Target_Normal_Completion // Expected Target Termination Response
);
end
else
begin
PCIU_IO_WRITE
(
`Test_Master_1, // Behavioral Master to use for reference
Target_Base_Addr_R[1] + 64, // Address of this transaction
32'hF0F0_F0F0, // Data For the transaction
4'h0, // Byte enables
1, // Size of transfer
`Test_Target_Normal_Completion // Expected Target Termination Response
) ;
end
 
do_pause( 1 ) ;
 
if (test_mem)
begin
PCIU_MEM_WRITE
(
"MEM_WRITE ", // just the name
`Test_Master_1, // Behavioral Master to use for reference
Target_Base_Addr_R[1] + 128, // Address of this transaction
32'h0F0F_0F0F, // Data For the transaction
4'h0, // Byte enables
1, // length of transfer
`Test_One_Zero_Master_WS, // Master Waits - don't care
`Test_One_Zero_Target_WS, // Expected Target Wait State Response
`Test_Devsel_Medium, // Expected Target DEVSEL Speed Response
`Test_Target_Normal_Completion // Expected Target Termination Response
);
end
else
begin
PCIU_IO_WRITE
(
`Test_Master_1, // Behavioral Master to use for reference
Target_Base_Addr_R[1] + 128, // Address of this transaction
32'h0F0F_0F0F, // Data For the transaction
4'h0, // Byte enables
1, // Size of transfer
`Test_Target_Normal_Completion // Expected Target Termination Response
) ;
end
 
do_pause( 1 ) ;
end
begin
wb_transaction_progress_monitor
(
Target_Base_Addr_R[1] + 64, // expected address
1'b1, // expected operation R/W
1, // expected number of transfers
1'b1, // turn checking of transfers ON/OFF
ok_wb // succeeded/failed
) ;
 
if ( ok_wb === 1 )
begin
 
wb_transaction_progress_monitor
(
Target_Base_Addr_R[1] + 128, // expected address
1'b1, // expected operation R/W
1, // expected number of transfers
1'b1, // turn checking of transfers ON/OFF
ok_wb // succeeded/failed
) ;
end
 
@(posedge pci_clock) ;
#1 ;
disable pci_error_mon1 ;
end
begin:pci_error_mon1
ok_pci = 1 ;
@(error_event_int) ;
ok_pci = 0 ;
end
join
if ( ok_wb !== 1'b1 )
begin
test_fail("WB Master started invalid transaction or none at all after Target write was posted") ;
end
 
if ( ok_pci !== 1'b1)
begin
test_fail("PCI Behavioral Master or Monitor signaled an error during write to PCI Bridge Target") ;
end
 
if ((ok_pci !== 1'b1) || (ok_wb !== 1'b1))
begin
#1 ;
disable main ;
end
 
if ( test_mem )
begin
PCIU_MEM_READ
(
"MEM_READ ", // description
`Test_Master_1, // behavioral master selection
Target_Base_Addr_R[1] + 64, // address of access
32'hF0F0_F0F0, // expected read data
1, // number of transfers
8'h7_0, // don't care (wait cycles)
`Test_One_Zero_Target_WS, // expected Target Wait Cycles
`Test_Devsel_Medium, // expected Target DEVSEL speed
`Test_Target_Retry_On // expected Target termination
);
end
else
begin
PCIU_IO_READ
(
`Test_Master_1, // behavioral master selection
Target_Base_Addr_R[1] + 64, // address of access
32'hF0F0_F0F0, // expected read data
4'h0, // byte enables
1, // number of transfers
`Test_Target_Retry_On // expected target termination
) ;
end
 
wb_transaction_progress_monitor
(
Target_Base_Addr_R[1] + 64, // expected address
1'b0, // expected operation R/W
1, // expected number transfers
1'b1, // turn checking of transfers ON/OFF
ok_wb // succeeded/failed
) ;
 
// wait for 3 pci cycles for delayed read to become available in pci clock domain
repeat(3)
@(posedge pci_clock) ;
 
// now read data
fork
begin
if ( test_mem )
begin
PCIU_MEM_READ
(
"MEM_READ ", // description
`Test_Master_1, // behavioral master selection
Target_Base_Addr_R[1] + 64, // address of access
32'hF0F0_F0F0, // expected read data
1, // number of transfers
8'h7_0, // don't care (wait cycles)
`Test_One_Zero_Target_WS, // expected Target Wait Cycles
`Test_Devsel_Medium, // expected Target DEVSEL speed
`Test_Target_Normal_Completion // expected Target termination
);
end
else
begin
PCIU_IO_READ
(
`Test_Master_1, // behavioral master selection
Target_Base_Addr_R[1] + 64, // address of access
32'hF0F0_F0F0, // expected read data
4'h0, // byte enables
1, // number of transfers
`Test_Target_Normal_Completion // expected target termination
) ;
end
 
@(posedge pci_clock) ;
while (FRAME !== 1'b1 || IRDY !== 1'b1)
@(posedge pci_clock) ;
 
@(posedge pci_clock) ;
#1 ;
disable pci_error_mon2 ;
end
begin:pci_error_mon2
ok_pci = 1 ;
@(error_event_int) ;
ok_pci = 0 ;
end
join
 
if ( ok_wb !== 1'b1 )
begin
test_fail("WB Master started invalid transaction or none at all after Target write was posted") ;
end
 
if ( ok_pci !== 1'b1)
begin
test_fail("PCI Behavioral Master or Monitor signaled an error during write to PCI Bridge Target") ;
end
 
if ((ok_pci !== 1'b1) || (ok_wb !== 1'b1))
begin
#1 ;
disable main ;
end
 
if ( test_mem )
begin
PCIU_MEM_READ
(
"MEM_READ ", // description
`Test_Master_1, // behavioral master selection
Target_Base_Addr_R[1] + 128, // address of access
32'h0F0F_0F0F, // expected read data
1, // number of transfers
8'h7_0, // don't care (wait cycles)
`Test_One_Zero_Target_WS, // expected Target Wait Cycles
`Test_Devsel_Medium, // expected Target DEVSEL speed
`Test_Target_Retry_On // expected Target termination
);
end
else
begin
PCIU_IO_READ
(
`Test_Master_1, // behavioral master selection
Target_Base_Addr_R[1] + 128, // address of access
32'h0F0F_0F0F, // expected read data
4'h0, // byte enables
1, // number of transfers
`Test_Target_Retry_On // expected target termination
) ;
end
 
wb_transaction_progress_monitor
(
Target_Base_Addr_R[1] + 128, // expected address
1'b0, // expected operation R/W
1, // expected number transfers
1'b1, // turn checking of transfers ON/OFF
ok_wb // succeeded/failed
) ;
 
// wait for 3 pci cycles for delayed read to become available in pci clock domain
repeat(3)
@(posedge pci_clock) ;
 
// now read data
fork
begin
if ( test_mem )
begin
PCIU_MEM_READ
(
"MEM_READ ", // description
`Test_Master_1, // behavioral master selection
Target_Base_Addr_R[1] + 128, // address of access
32'h0F0F_0F0F, // expected read data
1, // number of transfers
8'h7_0, // don't care (wait cycles)
`Test_One_Zero_Target_WS, // expected Target Wait Cycles
`Test_Devsel_Medium, // expected Target DEVSEL speed
`Test_Target_Normal_Completion // expected Target termination
);
end
else
begin
PCIU_IO_READ
(
`Test_Master_1, // behavioral master selection
Target_Base_Addr_R[1] + 128, // address of access
32'h0F0F_0F0F, // expected read data
4'h0, // byte enables
1, // number of transfers
`Test_Target_Normal_Completion // expected target termination
) ;
end
 
@(posedge pci_clock) ;
while (FRAME !== 1'b1 || IRDY !== 1'b1)
@(posedge pci_clock) ;
 
@(posedge pci_clock) ;
#1 ;
disable pci_error_mon3 ;
end
begin:pci_error_mon3
ok_pci = 1 ;
@(error_event_int) ;
ok_pci = 0 ;
end
join
 
if ((ok_wb === 1'b1) && (ok_pci === 1'b1))
test_ok ;
 
if ( ok_wb !== 1'b1 )
begin
test_fail("WB Master started invalid transaction or none at all after Target read was requested") ;
end
 
if ( ok_pci !== 1'b1)
begin
test_fail("PCI Behavioral Master or Monitor signaled an error during read from PCI Bridge Target") ;
end
master1_check_received_data = master_check_data_previous ;
end
endtask // target_special_corner_case_test
`endif
 
task test_fail ;
input [7999:0] failure_reason ;
reg [8007:0] display_failure ;
19156,12 → 19658,13
while ( display_test[799:792] == 0 )
display_test = display_test << 8 ;
 
$fdisplay( tb_log_file, "*****************************************************************************************" ) ;
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
$fdisplay( tb_log_file, " At time %t ", $time ) ;
$fdisplay( tb_log_file, " Test %s", display_test ) ;
$fdisplay( tb_log_file, " *FAILED* because") ;
$fdisplay( tb_log_file, " %s", display_failure ) ;
$fdisplay( tb_log_file, "*****************************************************************************************" ) ;
current_test_parameters ;
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
$fdisplay( tb_log_file, " " ) ;
 
`ifdef STOP_ON_FAILURE
19179,11 → 19682,12
while ( display_test[799:792] == 0 )
display_test = display_test << 8 ;
 
$fdisplay( tb_log_file, "*****************************************************************************************" ) ;
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
$fdisplay( tb_log_file, " At time %t ", $time ) ;
$fdisplay( tb_log_file, " Test %s", display_test ) ;
$fdisplay( tb_log_file, " reported *SUCCESSFULL*! ") ;
$fdisplay( tb_log_file, "*****************************************************************************************" ) ;
current_test_parameters ;
$fdisplay( tb_log_file, "************************************************************************************************************************************************************" ) ;
$fdisplay( tb_log_file, " " ) ;
end
endtask // test_ok
19190,6 → 19694,7
 
task test_summary;
begin
$fdisplay(tb_log_file, "\n \n");
$fdisplay(tb_log_file, "******************************* PCI Testcase summary *******************************") ;
$fdisplay(tb_log_file, "Tests performed: %d", tests_successfull + tests_failed) ;
$fdisplay(tb_log_file, "Failed tests : %d", tests_failed) ;
19199,4 → 19704,24
end
endtask
 
task current_test_parameters ;
reg [87:0] decode_speed_text ;
begin
case (tb_target_decode_speed)
3'b000: decode_speed_text = "FAST " ;
3'b001: decode_speed_text = "MEDIUM " ;
3'b010: decode_speed_text = "SLOW " ;
3'b011: decode_speed_text = "SUBTRACTIVE" ;
endcase
 
$fdisplay( tb_log_file, "TEST PARAMETERS:") ;
$fdisplay( tb_log_file, " - PCI Behavioral Devices' Initial Wait States = %d", (3'd4 - tb_init_waits)) ;
$fdisplay( tb_log_file, " - PCI Behavioral Devices' Subsequent Wait States = %d", (3'd4 - tb_subseq_waits)) ;
$fdisplay( tb_log_file, " - PCI Behavioral Devices' DEVSEL speed = %s", decode_speed_text) ;
 
$fdisplay( tb_log_file, " - WISHBONE Behavioral Devices' Initial Wait States = %d", tb_init_waits) ;
$fdisplay( tb_log_file, " - WISHBONE Behavioral Devices' Subsequent Wait States = %d", tb_subseq_waits) ;
end
endtask
 
endmodule
/trunk/bench/verilog/wb_slave_behavioral.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/03/06 09:10:56 mihad
// Added missing include statements
//
// Revision 1.1 2002/02/01 13:39:43 mihad
// Initial testbench import. Still under development
//
50,6 → 53,7
`include "pci_testbench_defines.v"
`include "timescale.v"
`include "pci_constants.v"
 
module WB_SLAVE_BEHAVIORAL
(
CLK_I,
67,285 → 71,386
CAB_I
);
 
/*----------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------------------------------
WISHBONE signals
----------------------------------------------------------------------------------------------------------------------*/
input CLK_I ;
input RST_I ;
output ACK_O ;
input `WB_ADDR_TYPE ADR_I ;
input CYC_I ;
output `WB_DATA_TYPE DAT_O ;
input `WB_DATA_TYPE DAT_I ;
output ERR_O ;
output RTY_O ;
input `WB_SEL_TYPE SEL_I ;
input STB_I ;
input WE_I ;
input CAB_I ;
------------------------------------------------------------------------------------------------------*/
input CLK_I;
input RST_I;
output ACK_O;
input `WB_ADDR_TYPE ADR_I;
input CYC_I;
output `WB_DATA_TYPE DAT_O;
input `WB_DATA_TYPE DAT_I;
output ERR_O;
output RTY_O;
input `WB_SEL_TYPE SEL_I;
input STB_I;
input WE_I;
input CAB_I;
 
//reg ACK_O ;
//reg ERR_O ;
//reg RTY_O ;
reg [31:0] DAT_O ;
reg `WB_DATA_TYPE DAT_O;
 
/*----------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------------------------------
Asynchronous dual-port RAM signals for storing and fetching the data
----------------------------------------------------------------------------------------------------------------------*/
reg [31:0] wb_memory [0:1023] ; // data for WB memory - 16 LSB addresses are connected
reg [31:0] mem_wr_data_out ;
reg [31:0] mem_rd_data_in ;
------------------------------------------------------------------------------------------------------*/
//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
reg `WB_DATA_TYPE mem_wr_data_out;
reg `WB_DATA_TYPE mem_rd_data_in;
 
/*----------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------------------------------
Maximum values for WAIT and RETRY counters and which response !!!
----------------------------------------------------------------------------------------------------------------------*/
reg [2:0] a_e_r_resp ; // tells with which cycle_termination_signal must wb_slave respond !
reg wait_cyc ;
reg [7:0] max_retry ;
------------------------------------------------------------------------------------------------------*/
reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
reg [3:0] wait_cyc;
reg [7:0] max_retry;
 
// assign registers to default state while in reset
always@(RST_I)
begin
if (RST_I)
begin
a_e_r_resp <= 3'b000 ; // do not respond
wait_cyc <= 1'b0 ; // no wait cycles
max_retry <= 8'h0 ; // no retries
end
if (RST_I)
begin
a_e_r_resp <= 3'b000; // do not respond
wait_cyc <= 4'b0; // no wait cycles
max_retry <= 8'h0; // no retries
end
end //reset
 
task cycle_response ;
input [2:0] ack_err_rty_resp ; // acknowledge, error or retry response input flags
input wait_cycles ; // if wait cycles before each data termination cycle (ack, err or rty)
input [7:0] retry_cycles ; // noumber of retry cycles before acknowledge cycle
task cycle_response;
input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
input [3:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
begin
// assign values
a_e_r_resp <= #1 ack_err_rty_resp ;
wait_cyc <= #1 wait_cycles ;
max_retry <= #1 retry_cycles ;
// assign values
a_e_r_resp <= #1 ack_err_rty_resp;
wait_cyc <= #1 wait_cycles;
max_retry <= #1 retry_cycles;
end
endtask // cycle_response
 
/*----------------------------------------------------------------------------------------------------------------------
Internal signals and logic
----------------------------------------------------------------------------------------------------------------------*/
reg calc_ack ;
reg calc_err ;
reg calc_rty ;
/*------------------------------------------------------------------------------------------------------
Tasks for writing and reading to and from memory !!!
------------------------------------------------------------------------------------------------------*/
reg `WB_ADDR_TYPE task_wr_adr_i;
reg `WB_ADDR_TYPE task_rd_adr_i;
reg `WB_DATA_TYPE task_dat_i;
reg `WB_DATA_TYPE task_dat_o;
reg `WB_SEL_TYPE task_sel_i;
reg task_wr_data;
reg task_data_written;
reg `WB_DATA_TYPE task_mem_wr_data;
 
reg [7:0] retry_cnt ;
reg [7:0] retry_num ;
reg retry_expired ;
reg retry_rst ;
// write to memory
task wr_mem;
input `WB_ADDR_TYPE adr_i;
input `WB_DATA_TYPE dat_i;
input `WB_SEL_TYPE sel_i;
integer current_byte ;
integer current_bit ;
begin
/*
task_data_written = 0;
task_wr_adr_i = adr_i;
task_dat_i = dat_i;
task_sel_i = sel_i;
task_wr_data = 1;
wait(task_data_written);
task_wr_data = 0;
*/
task_mem_wr_data = wb_memory[adr_i[21:2]];
 
// RESET retry counter
always@(posedge RST_I or posedge CLK_I)
for (current_byte = 0 ; current_byte < `WB_DATA_WIDTH / 8 ; current_byte = current_byte + 1'b1)
begin
// check sel_i for every byte
if (sel_i[current_byte])
begin
// have to write a bit at a time, because dynamic range bouds are not allowed
for (current_bit = 0 ; current_bit < 8 ; current_bit = current_bit + 1'b1)
task_mem_wr_data[current_byte * 8 + current_bit] = dat_i[current_byte * 8 + current_bit] ;
end
end
/*if (sel_i[3])
task_mem_wr_data[31:24] = dat_i[31:24];
if (sel_i[2])
task_mem_wr_data[23:16] = dat_i[23:16];
if (sel_i[1])
task_mem_wr_data[15: 8] = dat_i[15: 8];
if (sel_i[0])
task_mem_wr_data[ 7: 0] = dat_i[ 7: 0];
*/
wb_memory[adr_i[21:2]] = task_mem_wr_data; // write data
end
endtask
 
// read from memory
task rd_mem;
input `WB_ADDR_TYPE adr_i;
output `WB_DATA_TYPE dat_o;
input `WB_SEL_TYPE sel_i;
begin
if (RST_I)
retry_rst <= 1'b1 ;
else
retry_rst <= calc_ack || calc_err ;
task_rd_adr_i = adr_i;
task_sel_i = sel_i;
#1;
dat_o = task_dat_o;
end
endtask
 
/*------------------------------------------------------------------------------------------------------
Internal signals and logic
------------------------------------------------------------------------------------------------------*/
reg calc_ack;
reg calc_err;
reg calc_rty;
 
reg [7:0] retry_cnt;
reg [7:0] retry_num;
reg retry_expired;
 
// Retry counter
always@(posedge retry_rst or negedge calc_rty)
always@(posedge RST_I or posedge CLK_I)
begin
if (retry_rst)
retry_cnt <= #`FF_DELAY 8'h00 ;
else
retry_cnt <= #`FF_DELAY retry_num ;
if (RST_I)
retry_cnt <= #1 8'h00;
else
begin
if (calc_ack || calc_err)
retry_cnt <= #1 8'h00;
else if (calc_rty)
retry_cnt <= #1 retry_num;
end
end
 
always@(retry_cnt or max_retry)
begin
if (retry_cnt < max_retry)
begin
retry_num = retry_cnt + 1'b1 ;
retry_expired = #10 1'b0 ;
end
else
begin
retry_num = retry_cnt ;
retry_expired = #10 1'b1 ;
end
if (retry_cnt < max_retry)
begin
retry_num = retry_cnt + 1'b1;
retry_expired = 1'b0;
end
else
begin
retry_num = retry_cnt;
retry_expired = 1'b1;
end
end
 
reg [1:0] wait_cnt ;
reg [1:0] wait_num ;
reg wait_expired ;
reg reset_wait ;
reg [3:0] wait_cnt;
reg [3:0] wait_num;
reg wait_expired;
 
// Wait counter
always@(posedge RST_I or posedge CLK_I)
begin
if (RST_I)
reset_wait <= #`FF_DELAY 1'b1 ;
else
reset_wait <= #`FF_DELAY (wait_expired || ~STB_I) ;
if (RST_I)
wait_cnt <= #1 4'h0;
else
begin
if (wait_expired || ~STB_I)
wait_cnt <= #1 4'h0;
else
wait_cnt <= #1 wait_num;
end
end
 
// Wait counter
always@(posedge reset_wait or posedge CLK_I)
begin
if (reset_wait)
wait_cnt <= #`FF_DELAY 4'h0 ;
else
wait_cnt <= #`FF_DELAY wait_num ;
end
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
begin
if ((wait_cyc) && (STB_I))
begin
if (wait_cnt < 2'h2)
begin
wait_num = wait_cnt + 1'b1 ;
wait_expired = 1'b0 ;
calc_ack = 1'b0 ;
calc_err = 1'b0 ;
calc_rty = 1'b0 ;
end
else
begin
wait_num = wait_cnt ;
wait_expired = 1'b1 ;
if (a_e_r_resp == 3'b100)
begin
calc_ack = 1'b1 ;
calc_err = 1'b0 ;
calc_rty = 1'b0 ;
end
else
if (a_e_r_resp == 3'b010)
begin
calc_ack = 1'b0 ;
calc_err = 1'b1 ;
calc_rty = 1'b0 ;
end
else
if (a_e_r_resp == 3'b001)
begin
calc_err = 1'b0 ;
if (retry_expired)
begin
calc_ack = 1'b1 ;
calc_rty = 1'b0 ;
end
else
begin
calc_ack = 1'b0 ;
calc_rty = 1'b1 ;
end
end
else
begin
calc_ack = 1'b0 ;
calc_err = 1'b0 ;
calc_rty = 1'b0 ;
end
end
end
else
if ((~wait_cyc) && (STB_I))
begin
wait_num = 2'h0 ;
wait_expired = 1'b1 ;
if (a_e_r_resp == 3'b100)
begin
calc_ack = 1'b1 ;
calc_err = 1'b0 ;
calc_rty = 1'b0 ;
end
else
if (a_e_r_resp == 3'b010)
begin
calc_ack = 1'b0 ;
calc_err = 1'b1 ;
calc_rty = 1'b0 ;
end
else
if (a_e_r_resp == 3'b001)
begin
calc_err = 1'b0 ;
if (retry_expired)
begin
calc_ack = 1'b1 ;
calc_rty = 1'b0 ;
end
else
begin
calc_ack = 1'b0 ;
calc_rty = 1'b1 ;
end
end
else
begin
calc_ack = 1'b0 ;
calc_err = 1'b0 ;
calc_rty = 1'b0 ;
end
end
else
begin
wait_num = 2'h0 ;
wait_expired = 1'b0 ;
calc_ack = 1'b0 ;
calc_err = 1'b0 ;
calc_rty = 1'b0 ;
end
if ((wait_cyc > 0) && (STB_I))
begin
if (wait_cnt < wait_cyc) // 4'h2)
begin
wait_num = wait_cnt + 1'b1;
wait_expired = 1'b0;
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else
begin
wait_num = wait_cnt;
wait_expired = 1'b1;
if (a_e_r_resp == 3'b100)
begin
calc_ack = 1'b1;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else
if (a_e_r_resp == 3'b010)
begin
calc_ack = 1'b0;
calc_err = 1'b1;
calc_rty = 1'b0;
end
else
if (a_e_r_resp == 3'b001)
begin
calc_err = 1'b0;
if (retry_expired)
begin
calc_ack = 1'b1;
calc_rty = 1'b0;
end
else
begin
calc_ack = 1'b0;
calc_rty = 1'b1;
end
end
else
begin
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
end
else
if ((wait_cyc == 0) && (STB_I))
begin
wait_num = 2'h0;
wait_expired = 1'b1;
if (a_e_r_resp == 3'b100)
begin
calc_ack = 1'b1;
calc_err = 1'b0;
calc_rty = 1'b0;
end
else if (a_e_r_resp == 3'b010)
begin
calc_ack = 1'b0;
calc_err = 1'b1;
calc_rty = 1'b0;
end
else if (a_e_r_resp == 3'b001)
begin
calc_err = 1'b0;
if (retry_expired)
begin
calc_ack = 1'b1;
calc_rty = 1'b0;
end
else
begin
calc_ack = 1'b0;
calc_rty = 1'b1;
end
end
else
begin
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
else
begin
wait_num = 2'h0;
wait_expired = 1'b0;
calc_ack = 1'b0;
calc_err = 1'b0;
calc_rty = 1'b0;
end
end
 
wire rd_sel = (CYC_I && STB_I && ~WE_I) ;
wire wr_sel = (CYC_I && STB_I && WE_I) ;
wire rd_sel = (CYC_I && STB_I && ~WE_I);
wire wr_sel = (CYC_I && STB_I && WE_I);
 
// Generate cycle termination signals
assign ACK_O = calc_ack && STB_I ;
assign ERR_O = calc_err && STB_I ;
assign RTY_O = calc_rty && STB_I ;
assign ACK_O = calc_ack && STB_I && CYC_I;
assign ERR_O = calc_err && STB_I && CYC_I;
assign RTY_O = calc_rty && STB_I && CYC_I;
 
// Assign address to asynchronous memory
always@(ADR_I or RST_I)
always@(RST_I or ADR_I)
begin
if (RST_I) // this is added because at start of test bench we need address change in order to get data!
mem_rd_data_in = 32'hxxxx_xxxx ;
else
mem_rd_data_in = wb_memory[ADR_I[11:2]] ;
if (RST_I) // this is added because at start of test bench we need address change in order to get data!
begin
#1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
end
else
begin
// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];
#1 mem_rd_data_in = wb_memory[ADR_I[21:2]];
end
end
 
// assign outputs to unknown state while in reset
always@(RST_I)
/*// Data input/output interface
always@(rd_sel or mem_rd_data_in or RST_I)
begin
if (RST_I)
begin
DAT_O <= 32'hxxxx_xxxx ;
end
end //reset
if (RST_I)
DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset
else if (rd_sel)
DAT_O <=#1 mem_rd_data_in;
else
DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
end
*/
always@
(
RST_I or
ACK_O or
WE_I or
ADR_I
)
begin
if ((ACK_O === 1'b1) && (RST_I === 1'b0) && (WE_I === 1'b0))
DAT_O <= #1 wb_memory[ADR_I[21:2]] ;
else
DAT_O <= #1 {`WB_DATA_WIDTH{1'bx}} ;
end
 
// Data input/output interface
always@(rd_sel or wr_sel or mem_rd_data_in or DAT_I or SEL_I or mem_wr_data_out)
always@(RST_I or task_rd_adr_i)
begin
if (rd_sel)
begin
DAT_O = mem_rd_data_in ;
end
if (RST_I)
task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
else
task_dat_o = wb_memory[task_rd_adr_i[21:2]];
end
always@(posedge CLK_I)
 
/*always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
mem_wr_data_out or DAT_I or task_dat_i or
SEL_I or task_sel_i)
begin
if (wr_sel)
begin
mem_wr_data_out = wb_memory[ADR_I[11:2]] ;
if (task_wr_data)
begin
task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];
 
if ( SEL_I[3] )
mem_wr_data_out[31:24] = DAT_I[31:24] ;
if (task_sel_i[3])
task_mem_wr_data[31:24] = task_dat_i[31:24];
if (task_sel_i[2])
task_mem_wr_data[23:16] = task_dat_i[23:16];
if (task_sel_i[1])
task_mem_wr_data[15: 8] = task_dat_i[15: 8];
if (task_sel_i[0])
task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
 
if ( SEL_I[2] )
mem_wr_data_out[23:16] = DAT_I[23:16] ;
wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
task_data_written = 1;
end
else if (wr_sel && CLK_I)
begin
// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
 
if ( SEL_I[1] )
mem_wr_data_out[15: 8] = DAT_I[15: 8] ;
if (SEL_I[3])
mem_wr_data_out[31:24] = DAT_I[31:24];
if (SEL_I[2])
mem_wr_data_out[23:16] = DAT_I[23:16];
if (SEL_I[1])
mem_wr_data_out[15: 8] = DAT_I[15: 8];
if (SEL_I[0])
mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];
 
if ( SEL_I[0] )
mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0] ;
 
wb_memory[ADR_I[11:2]] <= mem_wr_data_out ;
end
// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data
wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data
end
end
*/
always@(posedge CLK_I)
begin
if (CYC_I && STB_I && WE_I && ACK_O)
wr_mem(ADR_I, DAT_I, SEL_I) ;
end
 
endmodule
/trunk/bench/verilog/pci_testbench_defines.v
8,8 → 8,16
 
`ifdef REGRESSION
`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
 
// next two defines are used to generate clocks
// only one at the time can be defined, otherwise testbench won't work
// they are used to generate both clocks with same period and phase shift of define's value in nano seconds
 
//`define PCI_CLOCK_FOLLOWS_WB_CLOCK 1
`define WB_CLOCK_FOLLOWS_PCI_CLOCK 2
// wishbone frequncy in GHz
`define WB_FREQ 0.05
`define WB_FREQ 0.033
// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
`define TAR0_BASE_ADDR_0 32'h1000_0000
58,6 → 66,8
`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
 
`define DISABLE_COMPLETION_EXPIRED_TESTS
`endif
 
//===================================================================================
158,4 → 168,3
`define WB_TRANSFER_CAB [9]
`define INIT_WAITS [3:0]
`define SUBSEQ_WAITS [7:4]
 
/trunk/rtl/verilog/pci_tpram.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
// Revision 1.3 2002/09/30 17:22:27 mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
100,6 → 103,7
`ifdef PCI_BIST
,
// debug chain signals
trst,
SO,
SI,
shift_DR,
137,6 → 141,7
 
`ifdef PCI_BIST
// debug chain signals
input trst ;
output SO ;
input SI ;
input shift_DR ;
168,7 → 173,7
`ifdef PCI_BIST
,
// reset
.rst (rst_a),
.trst (trst),
 
// debug chain signals
.SO (SO),
/trunk/rtl/verilog/pci_bridge32.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/10/08 17:17:05 mihad
// Added BIST signals for RAMs.
//
// Revision 1.3 2002/02/01 15:25:12 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
163,6 → 166,7
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
270,6 → 274,7
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
795,6 → 800,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO_internal),
.SI (SI),
.shift_DR (shift_DR),
978,6 → 984,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI_internal),
.shift_DR (shift_DR),
/trunk/rtl/verilog/wbw_wbr_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
// Revision 1.5 2002/09/30 16:03:04 mihad
// Added meta flop module for easier meta stable FF identification during synthesis
//
97,6 → 100,7
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
208,6 → 212,7
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
357,6 → 362,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO_internal),
.SI (SI),
.shift_DR (shift_DR),
389,6 → 395,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI_internal),
.shift_DR (shift_DR),
453,6 → 460,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
/trunk/rtl/verilog/top.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
// Revision 1.4 2002/03/21 07:36:04 mihad
// Files updated with missing includes, resolved some race conditions in test bench
//
118,6 → 121,7
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
181,6 → 185,7
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
342,6 → 347,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
/trunk/rtl/verilog/pciw_pcir_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
// Revision 1.6 2002/09/30 16:03:04 mihad
// Added meta flop module for easier meta stable FF identification during synthesis
//
105,6 → 108,7
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
226,6 → 230,7
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
383,6 → 388,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO_internal),
.SI (SI),
.shift_DR (shift_DR),
415,6 → 421,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI_internal),
.shift_DR (shift_DR),
479,6 → 486,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
/trunk/rtl/verilog/wb_tpram.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
// Revision 1.3 2002/09/30 17:22:27 mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
100,6 → 103,7
`ifdef PCI_BIST
,
// debug chain signals
trst,
SO,
SI,
shift_DR,
137,6 → 141,7
 
`ifdef PCI_BIST
// debug chain signals
input trst ;
output SO ;
input SI ;
input shift_DR ;
168,7 → 173,7
`ifdef PCI_BIST
,
// reset
.rst (rst_a),
.trst (trst),
 
// debug chain signals
.SO (SO),
/trunk/rtl/verilog/pci_target_unit.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/10/08 17:17:05 mihad
// Added BIST signals for RAMs.
//
// Revision 1.6 2002/09/25 15:53:52 mihad
// Removed all logic from asynchronous reset network
//
160,6 → 163,7
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
268,6 → 272,7
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
556,6 → 561,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
/trunk/rtl/verilog/wb_slave_unit.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
// Revision 1.4 2002/09/25 15:53:52 mihad
// Removed all logic from asynchronous reset network
//
153,6 → 156,7
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
265,6 → 269,7
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
574,6 → 579,7
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr
31,11 → 31,16
set arg_artisan = 0;
set arg_waves = 0;
set arg_vs_hdtp = 0
set arg_dis_comp_exp_test = 0
 
@ arg_num = 1
set arg_check = 0
 
while($arg_num <= $#argv)
if ($argv[$arg_num] == "help") then
goto help
endif
 
if ($argv[$arg_num] == "regression") then
@ arg_regression = 1
@ arg_check = $arg_check + 1
61,9 → 66,15
@ arg_check = $arg_check + 1
endif
 
if ($argv[$arg_num] == "disable_completion_expired_tests") then
@ arg_dis_comp_exp_test = 1
@ arg_check = $arg_check + 1
endif
 
if ($arg_check != $arg_num) then
echo "Invalid argument found"
exit
echo "Invalid argument found: $argv[$arg_num]"
echo
goto help
endif
@ arg_num = $arg_num + 1
end
170,6 → 181,10
echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
echo "-DEFINE REGRESSION -DEFINE GUEST -DEFINE REGR_FIFO_LARGE_GENERIC -DEFINE WB_DECODE_MEDIUM -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MED -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_HIGH_OE -DEFINE WB_CNF_BASE_ZERO -DEFINE NO_CNF_IMAGE -DEFINE WB_IMAGE2 -DEFINE WB_IMAGE3 -DEFINE WB_IMAGE4 -DEFINE WB_IMAGE5" > ./defines.args
endif
 
if ($arg_dis_comp_exp_test) then
echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
endif
else
if (($arg_xilinx == 0) && ($arg_artisan == 1)) then
if ($iter == 1) then
584,4 → 599,26
echo "<<< ../log/*ncsim.log "
echo "<<<"
endif
exit
 
help:
echo ""
echo "Script arguments:"
echo ""
echo "regression : run all implemented regression iterations on PCI Bridge Design"
echo ""
echo "xilinx : if you want to run simulation with xilinx RAM primitives. You have to provide RAM16X1D.v, RAMB4_S16_S16.v and glbl.v simulation files."
echo " : you have to edit ../bin/xilinx_file_list.lst file with the correct paths to these files. Leave other paths as they are!"
echo ""
echo "artisan : if you want to run simulation with artisan ASIC library vendor RAM primitives. You have to provide simulation models for these, edit ../bin/artisan_file_list.lst,"
echo " : and optionaly ../../../rtl/verilog/pci_user_constants.v, ../../../bench/verilog/pci_regression_constants.v, ../../../rtl/verilog/wb_tpram.v and ../../../rtl/verilog/pci_tpram.v"
echo ""
echo "waves : if you want to dump all the signals in the testbench to the signalscan output file in ../out/ directory"
echo ""
echo "vs_two_port : if you want to run simulation with virtual silicon ASIC library vendor RAM primitives. You have to provide simulation models for these, edit ../bin/vs_file_list.lst,"
echo " : and optionaly ../../../rtl/verilog/pci_user_constants.v, ../../../bench/verilog/pci_regression_constants.v, ../../../rtl/verilog/wb_tpram.v and ../../../rtl/verilog/pci_tpram.v"
echo ""
echo "disable_completion_expired_tests : if you want to disable completion expiration testing during regression run, because these are time consuming tests"
echo ""
exit
 

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