URL
https://opencores.org/ocsvn/or1k_old/or1k_old/trunk
Subversion Repositories or1k_old
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 620 to Rev 621
- ↔ Reverse comparison
Rev 620 → Rev 621
/trunk/or1ksim/testbench/Makefile.in
148,9 → 148,9
@OR1K_EXCEPT_FALSE@flag_SOURCES = |
@OR1K_EXCEPT_TRUE@flag_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld |
@OR1K_EXCEPT_TRUE@flag_LDADD = |
@OR1K_EXCEPT_TRUE@cache_SOURCES = $(OR1K_SUPPORT_S) support.h cache.c |
@OR1K_EXCEPT_TRUE@cache_SOURCES = $(OR1K_SUPPORT_S) support.h cache.c cache_asm.S |
@OR1K_EXCEPT_FALSE@cache_SOURCES = |
@OR1K_EXCEPT_TRUE@cache_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld |
@OR1K_EXCEPT_TRUE@cache_LDFLAGS = -T$(OR1K_SRCDIR)/cache.ld |
@OR1K_EXCEPT_TRUE@cfg_SOURCES = cfg.S spr_defs.h |
@OR1K_EXCEPT_FALSE@cfg_SOURCES = |
@OR1K_EXCEPT_TRUE@cfg_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld |
229,7 → 229,7
@OR1K_EXCEPT_TRUE@basic_OBJECTS = basic.o |
@OR1K_EXCEPT_FALSE@basic_OBJECTS = |
@OR1K_EXCEPT_TRUE@basic_DEPENDENCIES = |
@OR1K_EXCEPT_TRUE@cache_OBJECTS = except.o cache.o |
@OR1K_EXCEPT_TRUE@cache_OBJECTS = except.o cache.o cache_asm.o |
@OR1K_EXCEPT_FALSE@cache_OBJECTS = |
cache_LDADD = $(LDADD) |
cache_DEPENDENCIES = support/libsupport.a |
292,10 → 292,10
GZIP_ENV = --best |
DIST_SUBDIRS = support uos support |
DEP_FILES = .deps/acv_gpio.P .deps/acv_uart.P .deps/basic.P \ |
.deps/cache.P .deps/cbasic.P .deps/cfg.P .deps/dhry.P .deps/dmatest.P \ |
.deps/eth.P .deps/except.P .deps/except_mc.P .deps/except_test.P \ |
.deps/except_test_s.P .deps/exit.P .deps/flag.P .deps/functest.P \ |
.deps/int_test.P .deps/local_global.P .deps/mc_async.P \ |
.deps/cache.P .deps/cache_asm.P .deps/cbasic.P .deps/cfg.P .deps/dhry.P \ |
.deps/dmatest.P .deps/eth.P .deps/except.P .deps/except_mc.P \ |
.deps/except_test.P .deps/except_test_s.P .deps/exit.P .deps/flag.P \ |
.deps/functest.P .deps/int_test.P .deps/local_global.P .deps/mc_async.P \ |
.deps/mc_common.P .deps/mc_dram.P .deps/mc_ssram.P .deps/mc_sync.P \ |
.deps/mem_test.P .deps/mmu.P .deps/mmu_asm.P .deps/mul.P \ |
.deps/mycompress.P |
/trunk/or1ksim/testbench/cache.c
2,11 → 2,19
#include "support.h" |
#include "spr_defs.h" |
|
#define MEM_RAM 0x40100000 |
#define OR1KSIM 1 |
|
#ifdef OR1KSIM |
#undef UART |
#else |
#define UART 1 |
#endif |
|
#define MEM_RAM 0x00100000 |
|
/* Number of IC sets (power of 2) */ |
#define IC_SETS 512 |
#define DC_SETS 512 |
#define IC_SETS 256 |
#define DC_SETS 256 |
|
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */ |
#define IC_BLOCK_SIZE 16 |
25,6 → 33,112
#define REG16(add) *((volatile unsigned short *)(add)) |
#define REG32(add) *((volatile unsigned long *)(add)) |
|
#if UART |
#include "uart.h" |
#define IN_CLK 20000000 |
#define UART_BASE 0x9c000000 |
#define UART_BAUD_RATE 9600 |
|
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
|
#define WAIT_FOR_XMITR \ |
do { \ |
lsr = REG8(UART_BASE + UART_LSR); \ |
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY) |
|
#define WAIT_FOR_THRE \ |
do { \ |
lsr = REG8(UART_BASE + UART_LSR); \ |
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE) |
|
#define CHECK_FOR_CHAR \ |
(REG8(UART_BASE + UART_LSR) & UART_LSR_DR) |
|
#define WAIT_FOR_CHAR \ |
do { \ |
lsr = REG8(UART_BASE + UART_LSR); \ |
} while ((lsr & UART_LSR_DR) != UART_LSR_DR) |
|
#define UART_TX_BUFF_LEN 32 |
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1) |
|
#define print_n(x) \ |
{ \ |
uart_putc(s[((x) >> 28) & 0x0f]); \ |
uart_putc(s[((x) >> 24) & 0x0f]); \ |
uart_putc(s[((x) >> 20) & 0x0f]); \ |
uart_putc(s[((x) >> 16) & 0x0f]); \ |
uart_putc(s[((x) >> 12) & 0x0f]); \ |
uart_putc(s[((x) >> 8) & 0x0f]); \ |
uart_putc(s[((x) >> 4) & 0x0f]); \ |
uart_putc(s[((x) >> 0) & 0x0f]); \ |
} |
|
const char s[] = "0123456789abcdef"; |
|
void uart_init(void) |
{ |
int devisor; |
|
/* Reset receiver and transmiter */ |
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14; |
|
/* Disable all interrupts */ |
REG8(UART_BASE + UART_IER) = 0x00; |
|
/* Set 8 bit char, 1 stop bit, no parity */ |
REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY); |
|
/* Set baud rate */ |
devisor = IN_CLK/(16 * UART_BAUD_RATE); |
REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB; |
REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff; |
REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff; |
REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB); |
|
return; |
} |
|
static inline void uart_putc(char c) |
{ |
unsigned char lsr; |
|
WAIT_FOR_THRE; |
REG8(UART_BASE + UART_TX) = c; |
if(c == '\n') { |
WAIT_FOR_THRE; |
REG8(UART_BASE + UART_TX) = '\r'; |
} |
WAIT_FOR_XMITR; |
} |
|
static inline void print_str(char *str) |
{ |
while(*str != 0) { |
uart_putc(*str); |
str++; |
} |
} |
|
static inline char uart_getc() |
{ |
unsigned char lsr; |
char c; |
|
WAIT_FOR_CHAR; |
c = REG8(UART_BASE + UART_RX); |
return c; |
} |
#endif |
|
extern void ic_enable(void); |
extern void ic_disable(void); |
extern void dc_enable(void); |
extern void dc_disable(void); |
extern void dc_inv(void); |
extern unsigned long ic_inv_test(void); |
extern unsigned long dc_inv_test(unsigned long); |
|
extern void (*jalr)(void); |
extern void (*jr)(void); |
|
55,7 → 169,7
/* Jump to that address */ |
asm("l.jr\t\tr3") ; |
/* Report that we succeeded */ |
asm("l.nop\t2"); |
asm("l.nop\t0"); |
} |
|
void copy_jr(unsigned long add) |
71,44 → 185,6
asm("l.nop" : :); |
} |
|
void icache_enable(void) |
{ |
unsigned long add; |
|
/* First invalidate the cache. As at this point cache is disabled, |
the cache acts as it contains image of lowest memory block */ |
for(add = 1; add <= IC_SIZE; add += IC_BLOCK_SIZE) |
mtspr(SPR_ICBIR, add); |
|
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE); |
} |
|
void dcache_enable(void) |
{ |
unsigned long add; |
|
/* First invalidate the cache. As at this point cache is disabled, |
the cache acts as it contains image of lowest memory block */ |
for(add = 1; add <= DC_SIZE; add += DC_BLOCK_SIZE) |
mtspr(SPR_DCBIR, add); |
|
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE); |
} |
|
void icache_disable(void) |
{ |
|
/* This is write trough cache so we dont have to flush it */ |
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE); |
} |
|
void dcache_disable(void) |
{ |
|
/* This is write trough cache so we dont have to flush it */ |
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE); |
} |
|
int dc_test(void) |
{ |
int i; |
116,15 → 192,15
|
base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE; |
|
dcache_enable(); |
dc_enable(); |
|
/* Cache miss r */ |
add = base; |
for(i = 0; i < DC_WAYS; i++) { |
ul = REG32(add); |
ul = REG32(add + DC_BLOCK_SIZE); |
ul = REG32(add + 2*DC_BLOCK_SIZE); |
ul = REG32(add + 3*DC_BLOCK_SIZE); |
ul = REG32(add + DC_BLOCK_SIZE + 4); |
ul = REG32(add + 2*DC_BLOCK_SIZE + 8); |
ul = REG32(add + 3*DC_BLOCK_SIZE + 12); |
add += DC_SETS*DC_BLOCK_SIZE; |
} |
|
132,8 → 208,20
add = base; |
for(i = 0; i < DC_WAYS; i++) { |
REG32(add + 0) = 0x00000001; |
REG32(add + 4) = 0x00000000; |
REG32(add + 8) = 0x00000000; |
REG32(add + 12) = 0x00000000; |
REG32(add + DC_BLOCK_SIZE + 0) = 0x00000000; |
REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002; |
REG32(add + DC_BLOCK_SIZE + 8) = 0x00000000; |
REG32(add + DC_BLOCK_SIZE + 12) = 0x00000000; |
REG32(add + 2*DC_BLOCK_SIZE + 0) = 0x00000000; |
REG32(add + 2*DC_BLOCK_SIZE + 4) = 0x00000000; |
REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003; |
REG32(add + 2*DC_BLOCK_SIZE + 12) = 0x00000000; |
REG32(add + 3*DC_BLOCK_SIZE + 0) = 0x00000000; |
REG32(add + 3*DC_BLOCK_SIZE + 4) = 0x00000000; |
REG32(add + 3*DC_BLOCK_SIZE + 8) = 0x00000000; |
REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004; |
add += DC_SETS*DC_BLOCK_SIZE; |
} |
187,7 → 275,7
add += DC_SETS*DC_BLOCK_SIZE; |
} |
|
dcache_disable(); |
dc_disable(); |
|
return ul; |
} |
243,34 → 331,86
jump_add[15*i] = (unsigned long)&jalr; |
|
/* Initilalize table index */ |
jump_indx = &jump_add[0]; |
jump_indx = (unsigned long)&jump_add[0]; |
|
icache_enable(); |
ic_enable(); |
|
/* Go */ |
call(base); |
|
icache_disable(); |
ic_disable(); |
|
return 0xdeaddead; |
return 0; |
} |
|
int main(void) |
{ |
int rc; |
unsigned long rc, ret = 0; |
|
#ifdef UART |
/* Initialize controller */ |
uart_init(); |
#endif |
|
#ifdef UART |
print_str("DC test : "); |
#endif |
rc = dc_test(); |
ret += rc; |
#ifdef UART |
print_n(rc+0xdeaddca1); |
print_str("\n"); |
#else |
report(rc + 0xdeaddca1); |
#endif |
|
/* Be aware that this test doesn't report result troug report call. |
It writes to spr 0x1234 directly (in jump function)!!! |
#ifndef OR1KSIM |
#ifdef UART |
print_str("DC invalidate test : "); |
#endif |
rc = dc_inv_test(MEM_RAM); |
ret += rc; |
#ifdef UART |
print_n(rc + 0x9e8daa91); |
print_str("\n"); |
#else |
report(rc + 0x9e8daa91); |
#endif |
#endif |
|
This test can not be run on or1ksim. */ |
#ifdef UART |
print_str("IC test : "); |
#endif |
rc = ic_test(); |
report(rc); |
|
exit(0); |
ret += rc; |
#ifdef UART |
print_n(rc + 0xdeaddead); |
print_str("\n"); |
#else |
report(rc + 0xdeaddead); |
#endif |
|
|
#ifndef OR1KSIM |
#ifdef UART |
print_str("IC invalidate test : "); |
#endif |
ic_enable(); |
rc = ic_inv_test(); |
ret += rc; |
#ifdef UART |
print_n(rc + 0xdeadde8f); |
print_str("\n"); |
while(1); |
#else |
report(rc + 0xdeadde8f); |
#endif |
#endif |
|
|
report(ret + 0xdeaddca1); |
exit(0); |
|
return 0; |
} |
|
/trunk/or1ksim/testbench/cache.cfg
4,24 → 4,15
pattern = 0x00 |
type = unknown /* Fastest */ |
|
nmemories = 2 |
nmemories = 1 |
device 0 |
name = "RAM" |
ce = 0 |
baseaddr = 0x40000000 |
baseaddr = 0x00000000 |
size = 0x00200000 |
delayr = 1 |
delayw = 2 |
enddevice |
|
device 1 |
name = "FLASH" |
ce = 1 |
baseaddr = 0x00000000 |
size = 0x00200000 |
delayr = 10 |
delayw = -1 |
enddevice |
end |
|
section immu |
40,7 → 31,7
|
section ic |
enabled = 1 |
nsets = 512 |
nsets = 256 |
nways = 1 |
blocksize = 16 |
end |
47,7 → 38,7
|
section dc |
enabled = 1 |
nsets = 512 |
nsets = 256 |
nways = 1 |
blocksize = 16 |
end |
/trunk/or1ksim/testbench/cache_asm.S
0,0 → 1,196
#include "spr_defs.h" |
|
#define IC_ENABLE 0 |
#define DC_ENABLE 0 |
|
.global _ic_enable |
.global _ic_disable |
.global _dc_enable |
.global _dc_disable |
.global _dc_inv |
.global _ic_inv_test |
.global _dc_inv_test |
|
_ic_enable: |
/* Disable IC */ |
l.mfspr r13,r0,SPR_SR |
l.addi r11,r0,-1 |
l.xori r11,r11,SPR_SR_ICE |
l.and r11,r13,r11 |
l.mtspr r0,r11,SPR_SR |
|
/* Invalidate IC */ |
l.addi r13,r0,0 |
l.addi r11,r0,8192 |
1: |
l.mtspr r0,r13,SPR_ICBIR |
l.sfne r13,r11 |
l.bf 1b |
l.addi r13,r13,16 |
|
/* Enable IC */ |
l.mfspr r13,r0,SPR_SR |
l.ori r13,r13,SPR_SR_ICE |
l.mtspr r0,r13,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
l.jr r9 |
l.nop |
|
_ic_disable: |
/* Disable IC */ |
l.mfspr r13,r0,SPR_SR |
l.addi r11,r0,-1 |
l.xori r11,r11,SPR_SR_ICE |
l.and r11,r13,r11 |
l.mtspr r0,r11,SPR_SR |
|
l.jr r9 |
l.nop |
|
_dc_enable: |
/* Disable DC */ |
l.mfspr r13,r0,SPR_SR |
l.addi r11,r0,-1 |
l.xori r11,r11,SPR_SR_DCE |
l.and r11,r13,r11 |
l.mtspr r0,r11,SPR_SR |
|
/* Flush DC */ |
l.addi r13,r0,0 |
l.addi r11,r0,8192 |
1: |
l.mtspr r0,r13,SPR_DCBIR |
l.sfne r13,r11 |
l.bf 1b |
l.addi r13,r13,16 |
|
/* Enable DC */ |
l.mfspr r13,r0,SPR_SR |
l.ori r13,r13,SPR_SR_DCE |
l.mtspr r0,r13,SPR_SR |
|
l.jr r9 |
l.nop |
|
_dc_disable: |
/* Disable DC */ |
l.mfspr r13,r0,SPR_SR |
l.addi r11,r0,-1 |
l.xori r11,r11,SPR_SR_DCE |
l.and r11,r13,r11 |
l.mtspr r0,r11,SPR_SR |
|
l.jr r9 |
l.nop |
|
_dc_inv: |
l.mfspr r4,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r4,r5 |
l.mtspr r0,r5,SPR_SR |
l.mtspr r0,r3,SPR_DCBIR |
l.mtspr r0,r4,SPR_SR |
l.jr r9 |
l.nop |
|
.align 0x10 |
_ic_inv_test: |
l.movhi r7,hi(_ic_test_1) |
l.ori r7,r7,lo(_ic_test_1) |
l.addi r3,r0,0 |
l.addi r4,r0,0 |
l.addi r5,r0,0 |
l.nop |
l.nop |
l.nop |
|
_ic_test_1: |
3: l.addi r3,r3,1 |
|
l.sfeqi r4,0x01 |
l.bnf 1f |
l.nop |
|
l.mfspr r8,r0,SPR_SR |
l.addi r11,r0,-1 |
l.xori r11,r11,SPR_SR_ICE |
l.and r11,r8,r11 |
l.mtspr r0,r11,SPR_SR |
l.mtspr r0,r7,SPR_ICBIR |
l.mtspr r0,r8,SPR_SR |
l.bf 2f |
l.nop |
|
1: l.lwz r6,0(r7) |
l.addi r6,r6,1 |
l.sw 0(r7),r6 |
|
2: l.addi r5,r5,1 |
l.sfeqi r5,10 |
l.bnf 3b |
l.xori r4,r4,0x01 |
|
l.addi r11,r3,0 |
l.jr r9 |
l.nop |
|
_dc_inv_test: |
l.movhi r4,hi(0x08040201) |
l.ori r4,r4,lo(0x08040201) |
l.sw 0x00(r3),r4 |
l.slli r4,r4,1 |
l.sw 0x14(r3),r4 |
l.slli r4,r4,1 |
l.sw 0x28(r3),r4 |
|
l.addi r8,r9,0 |
l.jal _dc_enable |
l.nop |
l.addi r9,r8,0 |
|
l.lbz r4,0x03(r3) |
l.lhz r5,0x16(r3) |
l.add r4,r4,r5 |
l.lwz r5,0x28(r3) |
l.add r4,r4,r5 |
|
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
l.addi r7,r3,0x10 |
l.mtspr r0,r7,SPR_DCBIR |
|
l.lwz r5,0(r3) |
l.slli r5,r5,3 |
l.sw 0x00(r3),r5 |
l.slli r5,r5,1 |
l.sw 0x14(r3),r5 |
l.slli r5,r5,1 |
l.sw 0x28(r3),r5 |
|
l.mtspr r0,r6,SPR_SR |
|
l.lbz r5,0x03(r3) |
l.add r4,r4,r5 |
l.lhz r5,0x16(r3) |
l.add r4,r4,r5 |
l.lwz r5,0x28(r3) |
l.add r4,r4,r5 |
|
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
|
l.addi r11,r4,0x0 |
1: |
l.jr r9 |
l.nop |
/trunk/or1ksim/testbench/Makefile.am
77,7 → 77,7
flag_SOURCES = flag.S spr_defs.h |
flag_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld |
flag_LDADD = |
cache_SOURCES = $(OR1K_SUPPORT_S) support.h cache.c |
cache_SOURCES = $(OR1K_SUPPORT_S) support.h cache.c cache_asm.S |
cache_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld |
cfg_SOURCES = cfg.S spr_defs.h |
cfg_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld |