URL
https://opencores.org/ocsvn/or1k_old/or1k_old/trunk
Subversion Repositories or1k_old
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- This comparison shows the changes necessary to convert path
/
- from Rev 63 to Rev 64
- ↔ Reverse comparison
Rev 63 → Rev 64
/trunk/or1ksim/cpu/or1k/except.c
39,7 → 39,7
printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except)); |
printf("Iqueue[0].insn_addr: 0x%x Eff ADDR: 0x%x\n", iqueue[0].insn_addr, ea); |
printf(" pctemp: 0x%x pc: 0x%x\n", pctemp, pc); |
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|
#if ONLY_VIRTUAL_MACHINE |
printf("WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n"); |
cont_run = 0; |
50,8 → 50,7
decode(&iqueue[0]); |
execute(); |
} |
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/* cont_run = 0; */ |
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if (!(mfspr(SPR_SR) & SPR_SR_EXR)) { |
printf("ABORT: Exception occured while exception detection was disabled.\n"); |
cont_run = 0; |
58,10 → 57,15
return; |
} |
|
pc_saved = (pc & ~0x3) | |
(mfspr(SPR_SR) & (SPR_SR_SUPV | SPR_SR_EXR)); |
pc_saved = pc & ~0x3; |
mtspr(SPR_EPCR_BASE, pc_saved); |
mtspr(SPR_EEAR_BASE, ea); |
mtspr(SPR_ESR_BASE, mfspr(SPR_SR)); |
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/* Address translation is always disabled when starting exception. */ |
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME)); |
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME)); |
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */ |
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */ |
pc = (unsigned long)except; |
/trunk/or1ksim/cpu/or1k/spr_defs.h
0,0 → 1,190
/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
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This file is part of OpenRISC 1000 Architectural Simulator. |
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This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
/* This file is also used by microkernel test bench. Among |
others it is also used in assembly file(s). */ |
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/* Definition of special-purpose registers (SPRs) */ |
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#define MAX_GRPS 32 |
#define MAX_SPRS_PER_GRP 0x1000 |
#define MAX_SPRS (MAX_GRPS * 0x1000000 / MAX_SPRS_PER_GRP) |
|
/* Base addresses for the groups */ |
#define SPRGROUP_SYS 0x00000000 |
#define SPRGROUP_DMMU 0x01000000 |
#define SPRGROUP_IMMU 0x02000000 |
#define SPRGROUP_DC 0x03000000 |
#define SPRGROUP_IC 0x04000000 |
#define SPRGROUP_MAC 0x05000000 |
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/* System control and status group */ |
#define SPR_VR (SPRGROUP_SYS + 0) |
#define SPR_MPR (SPRGROUP_SYS + 1) |
#define SPR_SR (SPRGROUP_SYS + 2) |
#define SPR_EPCR_BASE (SPRGROUP_SYS + 16) |
#define SPR_EPCR_LAST (SPRGROUP_SYS + 31) |
#define SPR_CTR_BASE (SPRGROUP_SYS + 32) |
#define SPR_CTR_LAST (SPRGROUP_SYS + 47) |
#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) |
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) |
#define SPR_ESR_BASE (SPRGROUP_SYS + 64) |
#define SPR_ESR_LAST (SPRGROUP_SYS + 79) |
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/* Data MMU group */ |
#define SPR_DMMUCR (SPRGROUP_DMMU + 0) |
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200) |
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200) |
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200) |
#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200) |
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/* Instruction MMU group */ |
#define SPR_IMMUCR (SPRGROUP_IMMU + 0) |
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200) |
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200) |
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200) |
#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200) |
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/* Data cache group */ |
#define SPR_DCCR (SPRGROUP_DC + 0) |
#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) |
#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) |
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/* Instruction cache group */ |
#define SPR_ICCR (SPRGROUP_IC + 0) |
#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) |
#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) |
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/* MAC group */ |
#define SPR_MACLO (SPRGROUP_MAC + 1) |
#define SPR_MACHI (SPRGROUP_MAC + 2) |
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/* |
* Bit definitions for the Version Register |
* |
*/ |
#define SPR_VR_VER 0xffff0000 /* Processor version */ |
#define SPR_VR_PT 0x0000f000 /* Predefined template */ |
#define SPR_VR_REV 0x0000003f /* Processor revision */ |
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/* |
* Bit definitions for the Module Present Register |
* |
*/ |
#define SPR_MPR_SYS 0x00000001 /* System control and status module */ |
#define SPR_MPR_DMMU 0x00000002 /* Data MMU module */ |
#define SPR_MPR_IMMU 0x00000004 /* Instruction MMU module */ |
#define SPR_MPR_DC 0x00000008 /* Data cache module */ |
#define SPR_MPR_IC 0x00000010 /* Instruction cache module */ |
#define SPR_MPR_MAC 0x00000020 /* MAC module */ |
#define SPR_MPR_RES 0xffffffc0 /* Custom and future modules */ |
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/* |
* Bit definitions for the Supervision Register |
* |
*/ |
#define SPR_SR_CID 0xf0000000 /* Context ID */ |
#define SPR_SR_CF 0x00000100 /* Condition Flag */ |
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ |
#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ |
#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ |
#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ |
#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ |
#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */ |
#define SPR_SR_EXR 0x00000002 /* Exception Recognition */ |
#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */ |
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/* |
* Bit definitions for the Condition Code Register |
* |
*/ |
#define SPR_CCR_OVERFL 0x00000004 /* Overflow */ |
#define SPR_CCR_CARRY 0x00000002 /* Carry */ |
#define SPR_CCR_FLAG 0x00000001 /* Compare Flag */ |
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/* |
* Bit definitions for the Data MMU Control Register |
* |
*/ |
#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
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/* |
* Bit definitions for the Instruction MMU Control Register |
* |
*/ |
#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
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/* |
* Bit definitions for the Data TLB Match Register |
* |
*/ |
#define SPR_DTLBMR_V 0x00000001 /* Valid */ |
#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_DTLBMR_VPN 0xfffffc00 /* Virtual Page Number */ |
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/* |
* Bit definitions for the Data TLB Translate Register |
* |
*/ |
#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ |
#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ |
#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ |
#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ |
#define SPR_DTLBTR_A 0x00000010 /* Accessed */ |
#define SPR_DTLBTR_D 0x00000020 /* Dirty */ |
#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ |
#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ |
#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ |
#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ |
#define SPR_DTLBTR_PPN 0xfffffc00 /* Physical Page Number */ |
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/* |
* Bit definitions for the Instruction TLB Match Register |
* |
*/ |
#define SPR_ITLBMR_V 0x00000001 /* Valid */ |
#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_ITLBMR_VPN 0xfffffc00 /* Virtual Page Number */ |
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/* |
* Bit definitions for the Instruction TLB Translate Register |
* |
*/ |
#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ |
#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ |
#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ |
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ |
#define SPR_ITLBTR_A 0x00000010 /* Accessed */ |
#define SPR_ITLBTR_D 0x00000020 /* Dirty */ |
#define SPR_ITLBTR_URE 0x00000040 /* User Read Enable */ |
#define SPR_ITLBTR_UWE 0x00000080 /* User Write Enable */ |
#define SPR_ITLBTR_SRE 0x00000100 /* Supervisor Read Enable */ |
#define SPR_ITLBTR_SWE 0x00000200 /* Supervisor Write Enable (not used actually) */ |
#define SPR_ITLBTR_PPN 0xfffffc00 /* Physical Page Number */ |
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/trunk/or1ksim/cpu/or1k/sprs.h
17,6 → 17,8
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
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#include "spr_defs.h" |
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typedef unsigned long sprword; |
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/* Prototypes */ |
26,161 → 28,3
int getsprbit(int regno, int bitnum); |
void sprs_status(); |
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/* Definition of special-purpose registers (SPRs) */ |
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#define MAX_GRPS 32 |
#define MAX_SPRS_PER_GRP 0x1000 |
#define MAX_SPRS (MAX_GRPS * 0x1000000 / MAX_SPRS_PER_GRP) |
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/* Base addresses for the groups */ |
#define SPRGROUP_SYS 0x00000000 |
#define SPRGROUP_DMMU 0x01000000 |
#define SPRGROUP_IMMU 0x02000000 |
#define SPRGROUP_DC 0x03000000 |
#define SPRGROUP_IC 0x04000000 |
#define SPRGROUP_MAC 0x05000000 |
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/* System control and status group */ |
#define SPR_VR (SPRGROUP_SYS + 0) |
#define SPR_MPR (SPRGROUP_SYS + 1) |
#define SPR_SR (SPRGROUP_SYS + 2) |
#define SPR_CCR (SPRGROUP_SYS + 3) |
#define SPR_EPCR_BASE (SPRGROUP_SYS + 16) |
#define SPR_EPCR_LAST (SPRGROUP_SYS + 31) |
#define SPR_CTR_BASE (SPRGROUP_SYS + 32) |
#define SPR_CTR_LAST (SPRGROUP_SYS + 47) |
#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) |
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) |
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/* Data MMU group */ |
#define SPR_DTLBMR_BASE (SPRGROUP_DMMU + 0) |
#define SPR_DTLBMR_LAST (SPRGROUP_DMMU + 255) |
#define SPR_DTLBTR_BASE (SPRGROUP_DMMU + 256) |
#define SPR_DTLBTR_LAST (SPRGROUP_DMMU + 511) |
#define SPR_DMMUCR (SPRGROUP_DMMU + 512) |
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/* Instruction MMU group */ |
#define SPR_ITLBMR_BASE (SPRGROUP_IMMU + 0) |
#define SPR_ITLBMR_LAST (SPRGROUP_IMMU + 255) |
#define SPR_ITLBTR_BASE (SPRGROUP_IMMU + 256) |
#define SPR_ITLBTR_LAST (SPRGROUP_IMMU + 511) |
#define SPR_IMMUCR (SPRGROUP_IMMU + 512) |
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/* Data cache group */ |
#define SPR_DCR_BASE (SPRGROUP_DC + 0) |
#define SPR_DCR_LAST (SPRGROUP_DC + 511) |
#define SPR_DCCR (SPRGROUP_DC + 512) |
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/* Instruction cache group */ |
#define SPR_ICR_BASE (SPRGROUP_IC + 0) |
#define SPR_ICR_LAST (SPRGROUP_IC + 511) |
#define SPR_ICCR (SPRGROUP_IC + 512) |
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/* MAC group */ |
#define SPR_MACLO (SPRGROUP_MAC + 1) |
#define SPR_MACHI (SPRGROUP_MAC + 2) |
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/* |
* Bit definitions for the Version Register |
* |
*/ |
#define SPR_VR_VER 0xffff0000 /* Processor version */ |
#define SPR_VR_PT 0x0000f000 /* Predefined template */ |
#define SPR_VR_REV 0x0000003f /* Processor revision */ |
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/* |
* Bit definitions for the Module Present Register |
* |
*/ |
#define SPR_MPR_SYS 0x00000001 /* System control and status module */ |
#define SPR_MPR_DMMU 0x00000002 /* Data MMU module */ |
#define SPR_MPR_IMMU 0x00000004 /* Instruction MMU module */ |
#define SPR_MPR_DC 0x00000008 /* Data cache module */ |
#define SPR_MPR_IC 0x00000010 /* Instruction cache module */ |
#define SPR_MPR_MAC 0x00000020 /* MAC module */ |
#define SPR_MPR_RES 0xffffffc0 /* Custom and future modules */ |
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/* |
* Bit definitions for the Supervision Register |
* |
*/ |
#define SPR_SR_CID 0xf0000000 /* Context ID */ |
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ |
#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ |
#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ |
#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ |
#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ |
#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */ |
#define SPR_SR_EXR 0x00000002 /* Exception Recognition */ |
#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */ |
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/* |
* Bit definitions for the Condition Code Register |
* |
*/ |
#define SPR_CCR_OVERFL 0x00000004 /* Overflow */ |
#define SPR_CCR_CARRY 0x00000002 /* Carry */ |
#define SPR_CCR_FLAG 0x00000001 /* Compare Flag */ |
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/* |
* Bit definitions for the Data MMU Control Register |
* |
*/ |
#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
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/* |
* Bit definitions for the Instruction MMU Control Register |
* |
*/ |
#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
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/* |
* Bit definitions for the Data TLB Match Register |
* |
*/ |
#define SPR_DTLBMR_PL1 0x00000001 /* Page Level 1 (if 0 then PL2)*/ |
#define SPR_DTLBMR_CID 0x0000001e /* Context ID */ |
#define SPR_DTLBMR_VPN 0xfffffc00 /* Virtual Page Number */ |
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/* |
* Bit definitions for the Data TLB Translate Register |
* |
*/ |
#define SPR_DTLBTR_V 0x00000001 /* Valid */ |
#define SPR_DTLBTR_CC 0x00000002 /* Cache Coherency */ |
#define SPR_DTLBTR_CI 0x00000004 /* Cache Inhibit */ |
#define SPR_DTLBTR_WBC 0x00000008 /* Write-Back Cache*/ |
#define SPR_DTLBTR_WOM 0x00000010 /* Weakly-Ordered Memory */ |
#define SPR_DTLBTR_A 0x00000020 /* Accessed */ |
#define SPR_DTLBTR_D 0x00000040 /* Dirty */ |
#define SPR_DTLBTR_PPI 0x00000380 /* Page Protection Index */ |
#define SPR_DTLBTR_PPN 0xfffffc00 /* Physical Page Number */ |
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/* |
* Bit definitions for the Instruction TLB Match Register |
* |
*/ |
#define SPR_ITLBMR_PL1 0x00000001 /* Page Level 1 (if 0 then PL2)*/ |
#define SPR_ITLBMR_CID 0x0000001e /* Context ID */ |
#define SPR_ITLBMR_VPN 0xfffffc00 /* Virtual Page Number */ |
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/* |
* Bit definitions for the Instruction TLB Translate Register |
* |
*/ |
#define SPR_ITLBTR_V 0x00000001 /* Valid */ |
#define SPR_ITLBTR_CC 0x00000002 /* Cache Coherency */ |
#define SPR_ITLBTR_CI 0x00000004 /* Cache Inhibit */ |
#define SPR_ITLBTR_WBC 0x00000008 /* Write-Back Cache*/ |
#define SPR_ITLBTR_WOM 0x00000010 /* Weakly-Ordered Memory */ |
#define SPR_ITLBTR_A 0x00000020 /* Accessed */ |
#define SPR_ITLBTR_D 0x00000040 /* Dirty */ |
#define SPR_ITLBTR_PPI 0x00000380 /* Page Protection Index */ |
#define SPR_ITLBTR_PPN 0xfffffc00 /* Physical Page Number */ |
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/trunk/or1ksim/cpu/or1k/except.h
22,7 → 22,7
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/* Define if you want pure virtual machine simulation (no exceptions etc.) */ |
#define ONLY_VIRTUAL_MACHINE 1 |
#undef ONLY_VIRTUAL_MACHINE |
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/* Definition of OR1K exceptions */ |
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