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URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

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Rev 64 → Rev 65

/trunk/rtl/verilog/dbg_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.30 2003/08/28 13:55:22 simons
// Three more chains added for cpu debug access.
//
// Revision 1.29 2003/07/31 12:19:49 simons
// Multiple cpu support added.
//
418,6 → 421,7
wire [73:0] WISHBONE_Data;
wire [12:0] chain_sel_data;
wire wb_Access_wbClk;
wire [1:0] wb_cntl_o;
 
 
reg select_crc_out;
667,13 → 671,25
end
 
 
assign wb_adr_o = ADDR;
assign wb_we_o = RW;
assign wb_dat_o = DataOut;
assign wb_sel_o[3:0] = 4'hf;
assign wb_adr_o = ADDR & {32{wb_cyc_o}};
assign wb_we_o = RW & wb_cyc_o;
assign wb_dat_o = DataOut & {32{wb_cyc_o}};
assign wb_cab_o = 1'b0;
 
reg [3:0] wb_sel_o;
always @(ADDR[1:0] or wb_cntl_o or wb_cyc_o)
begin
if(wb_cyc_o)
case (wb_cntl_o)
2'b00: wb_sel_o = 4'hf;
2'b01: wb_sel_o = ADDR[1] ? 4'h3 : 4'hc;
2'b10: wb_sel_o = ADDR[1] ? (ADDR[0] ? 4'h1 : 4'h2) : (ADDR[0] ? 4'h4 : 4'h8);
default: wb_sel_o = 4'hf;
endcase
else
wb_sel_o = 4'hf;
end
// Synchronizing the RegAccess signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(RegAccessTck), .sync_out(RegAccess)
993,7 → 1009,7
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
`endif
.risc_stall(RiscStall_reg), .risc_stall_all(risc_stall_all_o), .risc_sel(risc_sel_o),
.risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o)
.risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o), .wb_cntl_o(wb_cntl_o)
 
);
 
/trunk/rtl/verilog/dbg_registers.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2003/07/31 14:01:53 simons
// Lapsus fixed.
//
// Revision 1.9 2003/07/31 12:19:49 simons
// Multiple cpu support added.
//
102,7 → 105,7
WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
LSSStopValid, IStopValid,
`endif
risc_stall, risc_stall_all, risc_sel, risc_reset, mon_cntl_o
risc_stall, risc_stall_all, risc_sel, risc_reset, mon_cntl_o, wb_cntl_o
);
 
parameter Tp = 1;
170,11 → 173,13
output [`RISC_NUM-1:0] risc_sel;
output risc_reset;
output [3:0] mon_cntl_o;
output [1:0] wb_cntl_o;
 
wire MODER_Acc = (address == `MODER_ADR) & access;
wire RISCOP_Acc = (address == `RISCOP_ADR) & access;
wire RISCSEL_Acc = (address == `RISCSEL_ADR) & access;
wire MON_CNTL_Acc = (address == `MON_CNTL_ADR) & access;
wire WB_CNTL_Acc = (address == `WB_CNTL_ADR) & access;
`ifdef TRACE_ENABLED
wire TSEL_Acc = (address == `TSEL_ADR) & access;
wire QSEL_Acc = (address == `QSEL_ADR) & access;
187,6 → 192,7
wire RISCOP_Wr = RISCOP_Acc & rw;
wire RISCSEL_Wr = RISCSEL_Acc & rw;
wire MON_CNTL_Wr = MON_CNTL_Acc & rw;
wire WB_CNTL_Wr = WB_CNTL_Acc & rw;
`ifdef TRACE_ENABLED
wire TSEL_Wr = TSEL_Acc & rw;
wire QSEL_Wr = QSEL_Acc & rw;
200,6 → 206,7
wire RISCOP_Rd = RISCOP_Acc & ~rw;
wire RISCSEL_Rd = RISCSEL_Acc & ~rw;
wire MON_CNTL_Rd = MON_CNTL_Acc & ~rw;
wire WB_CNTL_Rd = WB_CNTL_Acc & ~rw;
`ifdef TRACE_ENABLED
wire TSEL_Rd = TSEL_Acc & ~rw;
wire QSEL_Rd = QSEL_Acc & ~rw;
212,6 → 219,7
wire [2:1] RISCOPOut;
wire [`RISC_NUM-1:0] RISCSELOut;
wire [3:0] MONCNTLOut;
wire [1:0] WB_CNTLOut;
 
`ifdef TRACE_ENABLED
wire [31:0] TSELOut;
245,6 → 253,7
dbg_register #(2, 0) RISCOP (.data_in(data_in[2:1]), .data_out(RISCOPOut[2:1]), .write(RISCOP_Wr), .clk(clk), .reset(reset));
dbg_register #(`RISC_NUM, 1) RISCSEL (.data_in(data_in[`RISC_NUM-1:0]), .data_out(RISCSELOut), .write(RISCSEL_Wr), .clk(clk), .reset(reset));
dbg_register #(4, `MON_CNTL_DEF) MONCNTL (.data_in(data_in[3:0]), .data_out(MONCNTLOut[3:0]), .write(MON_CNTL_Wr), .clk(clk), .reset(reset));
dbg_register #(2, 0) WBCNTL (.data_in(data_in[1:0]), .data_out(WB_CNTLOut[1:0]), .write(WB_CNTL_Wr), .clk(clk), .reset(reset));
 
 
`ifdef TRACE_ENABLED
266,6 → 275,8
if(RISCSEL_Rd) data_out<= #Tp {{(32-`RISC_NUM){1'b0}}, RISCSELOut};
else
if(MON_CNTL_Rd) data_out<= #Tp {28'h0, MONCNTLOut};
else
if(WB_CNTL_Rd) data_out<= #Tp {30'h0, WB_CNTLOut};
`ifdef TRACE_ENABLED
else
if(TSEL_Rd) data_out<= #Tp TSELOut;
328,5 → 339,6
assign risc_sel = RISCSELOut;
assign risc_reset = RISCOPOut[1];
assign mon_cntl_o = MONCNTLOut;
assign wb_cntl_o = WB_CNTLOut;
 
endmodule
/trunk/rtl/verilog/dbg_defines.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2003/08/28 13:55:21 simons
// Three more chains added for cpu debug access.
//
// Revision 1.10 2003/07/31 12:19:49 simons
// Multiple cpu support added.
//
176,6 → 179,7
`define RISCSEL_ADR 5'h05
`define RECSEL_ADR 5'h10
`define MON_CNTL_ADR 5'h11
`define WB_CNTL_ADR 5'h12
 
 
// Registers default values (after reset)

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