URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 64 to Rev 65
- ↔ Reverse comparison
Rev 64 → Rev 65
/mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd
162,6 → 162,7
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
577,6 → 578,7
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_FIFO_DEPTH => C_FIFO_DEPTH, |
-- MAP USER GENERICS ABOVE THIS LINE --------------- |
|
C_SLV_AWIDTH => USER_SLV_AWIDTH, |
/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
100,6 → 100,7
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_FIFO_DEPTH : integer := 32; |
-- ADD USER GENERICS ABOVE THIS LINE --------------- |
|
-- DO NOT EDIT BELOW THIS LINE --------------------- |
183,6 → 184,7
signal core_x_sel_single : std_logic_vector(1 downto 0); |
signal core_y_sel_single : std_logic_vector(1 downto 0); |
signal core_flags : std_logic_vector(15 downto 0); |
signal core_modulus_sel : std_logic_vector(0 downto 0); |
|
------------------------------------------------------------------ |
-- Signals for multiplier core memory space |
384,12 → 386,14
------------------------------------------ |
-- Map slv_reg0 bits to core control signals |
------------------------------------------ |
core_start <= slv_reg0(8); |
core_exp_m <= slv_reg0(9); |
|
core_p_sel <= slv_reg0(0 to 1); |
core_dest_op_single <= slv_reg0(2 to 3); |
core_x_sel_single <= slv_reg0(4 to 5); |
core_y_sel_single <= slv_reg0(6 to 7); |
core_start <= slv_reg0(8); |
core_exp_m <= slv_reg0(9); |
core_modulus_sel <= slv_reg0(10 to 10); |
|
------------------------------------------ |
-- Multiplier core instance |
399,7 → 403,10
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL, |
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL, |
C_NR_STAGES_LOW => C_NR_STAGES_LOW, |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE |
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE, |
C_NR_OP => 4, |
C_NR_M => 2, |
C_FIFO_DEPTH => C_FIFO_DEPTH |
) |
port map( |
clk => Bus2IP_Clk, |
423,7 → 430,8
y_sel_single => core_y_sel_single, |
dest_op_single => core_dest_op_single, |
p_sel => core_p_sel, |
calc_time => calc_time |
calc_time => calc_time, |
modulus_sel => core_modulus_sel |
); |
|
|
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
773,10 → 773,13
-- |
component mod_sim_exp_core is |
generic( |
C_NR_BITS_TOTAL : integer := 1536; |
C_NR_BITS_TOTAL : integer := 1536; |
C_NR_STAGES_TOTAL : integer := 96; |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true |
C_NR_STAGES_LOW : integer := 32; |
C_SPLIT_PIPELINE : boolean := true; |
C_NR_OP : integer := 4; |
C_NR_M : integer := 2; |
C_FIFO_DEPTH : integer := 32 |
); |
port( |
clk : in std_logic; |
800,8 → 803,10
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection |
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection |
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection |
calc_time : out std_logic |
calc_time : out std_logic; |
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) |
); |
end component mod_sim_exp_core; |
|
|
end package mod_sim_exp_pkg; |
/mod_sim_exp/trunk/sim/Makefile
1,13 → 1,21
#VCOM = /usr/local/bin/vcom |
VCOMOPS = -explicit -check_synthesis -2002 -quiet |
VCOMOPS = -explicit -check_synthesis -2002 -quiet |
VLOGOPS = -vopt -nocovercells |
#MAKEFLAGS = --silent |
HDL_DIR = ../rtl/vhdl/ |
VER_DIR = ../rtl/verilog/ |
|
|
## |
# avs_aes hdl files |
## |
CORE_SRC =$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \ |
CORE_SRC =$(HDL_DIR)/core/std_functions.vhd \ |
$(HDL_DIR)/core/mod_sim_exp_pkg.vhd \ |
$(HDL_DIR)/ram/dpram_generic.vhd \ |
$(HDL_DIR)/ram/tdpram_generic.vhd \ |
$(HDL_DIR)/core/fifo_generic.vhd \ |
$(HDL_DIR)/core/modulus_ram_gen.vhd \ |
$(HDL_DIR)/core/operand_ram_gen.vhd \ |
$(HDL_DIR)/core/adder_block.vhd \ |
$(HDL_DIR)/core/autorun_cntrl.vhd \ |
$(HDL_DIR)/core/cell_1b_adder.vhd \ |
34,6 → 42,11
$(HDL_DIR)/core/sys_pipeline.vhd \ |
$(HDL_DIR)/core/mont_multiplier.vhd \ |
|
VER_SRC =$(VER_DIR)generic_spram.v \ |
$(VER_DIR)generic_dpram.v \ |
$(VER_DIR)generic_tpram.v \ |
$(VER_DIR)generic_fifo_sc_a.v \ |
$(VER_DIR)generic_fifo_sc_b.v \ |
|
## |
# Testbench HDL file |
59,7 → 72,9
#echo -- |
#echo building Modular Exponentiation Core |
#echo -- |
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC) |
#vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC) |
vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC) |
#echo Done! |
|
mod_sim_exp_tb: work_lib |
#echo -- |