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Rev 64 → Rev 65

/trunk/rtl/simple_gmii/simple_gmii.v File deleted
/trunk/rtl/simple_gmii/simple_gmii_regs.v
0,0 → 1,131
module simple_gmii_regs (
clk,reset,addr,wr_data,rd_data,doe,rd_n,wr_n,iorq_n,status_set,status_msk,control,control_clr,rx_len0,rx_len1,rx_data,rx_data_stb,tx_data,tx_data_stb,config,int_n);
input clk;
input reset;
input [15:0] addr;
input [7:0] wr_data;
output [7:0] rd_data;
output doe;
input rd_n;
input wr_n;
input iorq_n;
input [1:0] status_set;
output [1:0] status_msk;
output control;
input control_clr;
input [7:0] rx_len0;
input [7:0] rx_len1;
input [7:0] rx_data;
output rx_data_stb;
output [7:0] tx_data;
output tx_data_stb;
output config;
output int_n;
reg [7:0] rd_data;
reg block_select;
reg doe;
reg status_rd_sel;
reg [1:0] status;
reg status_wr_sel;
reg status_int;
reg [1:0] status_msk;
reg status_msk_rd_sel;
reg status_msk_wr_sel;
reg control;
reg control_rd_sel;
reg control_wr_sel;
reg rx_len0_rd_sel;
reg rx_len1_rd_sel;
reg rx_data_rd_sel;
reg rx_data_stb;
reg [7:0] tx_data;
reg tx_data_rd_sel;
reg tx_data_wr_sel;
reg tx_data_stb;
reg config;
reg config_rd_sel;
reg config_wr_sel;
reg int_n;
reg [7:0] int_vec;
always @*
begin
block_select = (addr[7:3] == 1) & !iorq_n;
status_rd_sel = block_select & (addr[2:0] == 0) & !rd_n;
status_wr_sel = block_select & (addr[2:0] == 0) & !wr_n;
status_msk_rd_sel = block_select & (addr[2:0] == 1) & !rd_n;
status_msk_wr_sel = block_select & (addr[2:0] == 1) & !wr_n;
control_rd_sel = block_select & (addr[2:0] == 2) & !rd_n;
control_wr_sel = block_select & (addr[2:0] == 2) & !wr_n;
rx_len0_rd_sel = block_select & (addr[2:0] == 3) & !rd_n;
rx_len1_rd_sel = block_select & (addr[2:0] == 4) & !rd_n;
rx_data_rd_sel = block_select & (addr[2:0] == 5) & !rd_n;
tx_data_rd_sel = block_select & (addr[2:0] == 6) & !rd_n;
tx_data_wr_sel = block_select & (addr[2:0] == 6) & !wr_n;
config_rd_sel = block_select & (addr[2:0] == 7) & !rd_n;
config_wr_sel = block_select & (addr[2:0] == 7) & !wr_n;
end
always @*
begin
case (1'b1)
status_int : int_vec = 207;
default : int_vec = 8'bx;
endcase
case (1'b1)
status_rd_sel : rd_data = status;
status_msk_rd_sel : rd_data = status_msk;
control_rd_sel : rd_data = control;
rx_len0_rd_sel : rd_data = rx_len0;
rx_len1_rd_sel : rd_data = rx_len1;
rx_data_rd_sel : rd_data = rx_data;
tx_data_rd_sel : rd_data = tx_data;
config_rd_sel : rd_data = config;
default : rd_data = int_vec;
endcase
doe = status_rd_sel | status_msk_rd_sel | control_rd_sel | rx_len0_rd_sel | rx_len1_rd_sel | rx_data_rd_sel | tx_data_rd_sel | config_rd_sel;
end
always @*
begin
int_n = ~(status_int);
end
// register: status
always @(posedge clk)
begin
if (reset) status <= 0;
else status <= (status_set | status) & ~( {2{status_wr_sel}} & wr_data);
if (reset) status_int <= 0;
else status_int <= |(status & ~status_msk);
end
// register: status_msk
always @(posedge clk)
begin
if (reset) status_msk <= 0;
else if (status_msk_wr_sel) status_msk <= wr_data;
end
// register: control
always @(posedge clk)
begin
if (reset) control <= 0;
else control <= ( ({1{control_wr_sel}} & wr_data) | control) & ~(control_clr);
end
// register: rx_data
always @(posedge clk)
begin
if (reset) rx_data_stb <= 0;
else if (rx_data_rd_sel) rx_data_stb <= 1;
else rx_data_stb <= 0;
end
always @(posedge clk)
begin
if (reset) tx_data <= 0;
else if (tx_data_wr_sel) tx_data <= wr_data;
if (reset) tx_data_stb <= 0;
else if (tx_data_wr_sel) tx_data_stb <= 1;
else tx_data_stb <= 0;
end
// register: config
always @(posedge clk)
begin
if (reset) config <= 0;
else if (config_wr_sel) config <= wr_data;
end
endmodule
/trunk/rtl/simple_gmii/simple_gmii_top.v
0,0 → 1,167
//
// Simple GMII-Like Interface for TV80
//
// Copyright (c) 2005 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
module simple_gmii_top (/*AUTOARG*/
// Outputs
rd_data, doe, int_n, tx_data, tx_dv, tx_er,
// Inputs
clk, reset, iorq_n, rd_n, addr, wr_data, wr_n, rx_clk, rx_data,
rx_dv, rx_er, tx_clk
);
 
parameter txbuf_sz = 512, rxbuf_sz = 512;
parameter wr_ptr_sz = 10;
 
input clk; // To core0 of simple_gmii_core.v, ...
input reset; // To core0 of simple_gmii_core.v, ...
 
// TV80 Controls
input iorq_n; // To regs0 of simple_gmii_regs.v
input rd_n; // To regs0 of simple_gmii_regs.v
input [15:0] addr; // To regs0 of simple_gmii_regs.v
input [7:0] wr_data; // To regs0 of simple_gmii_regs.v
output [7:0] rd_data; // From regs0 of simple_gmii_regs.v
input wr_n; // To regs0 of simple_gmii_regs.v
output doe; // From regs0 of simple_gmii_regs.v
output int_n; // From regs0 of simple_gmii_regs.v
 
// GMII RX
input rx_clk; // To core0 of simple_gmii_core.v
input [7:0] rx_data; // To core0 of simple_gmii_core.v, ...
input rx_dv; // To core0 of simple_gmii_core.v
input rx_er; // To core0 of simple_gmii_core.v
 
// GMII TX
input tx_clk; // To core0 of simple_gmii_core.v
output [7:0] tx_data;
output tx_dv;
output tx_er;
wire [1:0] status_set;
wire [15:0] rx_len;
wire [7:0] rx_rd_data;
wire [7:0] tx_wr_data;
wire tx_wr_stb;
wire en_preamble;
wire start_transmit;
wire rx_rd_stb;
// RX Buf RAM
wire rxbuf_we;
wire [wr_ptr_sz-1:0] rx_wr_ptr;
wire [wr_ptr_sz-1:0] rx_rd_ptr;
wire [7:0] rxbuf_data;
 
// TX Buf RAM
wire wr_sel_tx_data;
wire [wr_ptr_sz-1:0] txi_wr_ptr;
wire [7:0] io_data_in;
wire [wr_ptr_sz-1:0] txo_xm_ptr;
wire [7:0] txbuf_data;
 
simple_gmii_core #(txbuf_sz, rxbuf_sz, wr_ptr_sz) core0
(
// Outputs
.status_set (status_set),
.rx_len (rx_len),
.rx_rd_data (rx_rd_data),
 
// GMII TX Interface
.tx_clk (tx_clk),
.tx_data (tx_data),
.tx_dv (tx_dv),
.tx_er (tx_er),
 
// GMII RX Interface
.rx_data (rx_data),
.rx_clk (rx_clk),
.rx_dv (rx_dv),
.rx_er (rx_er),
 
// RX Buf RAM
.rxbuf_we (rxbuf_we),
.rx_wr_ptr (rx_wr_ptr),
.rx_rd_ptr (rx_rd_ptr),
.rxbuf_data (rxbuf_data),
 
// TX Buf RAM
.wr_sel_tx_data (wr_sel_tx_data),
.txi_wr_ptr (txi_wr_ptr),
//.io_data_in (io_data_in),
.txo_xm_ptr (txo_xm_ptr),
.txbuf_data (txbuf_data),
// Register Interface
.clk (clk),
.reset (reset),
.start_transmit (start_transmit),
.rx_rd_stb (rx_rd_stb),
//.tx_wr_data (tx_wr_data),
.tx_wr_stb (tx_wr_stb),
.en_preamble (en_preamble));
 
ram_1r_1w #(8, rxbuf_sz, wr_ptr_sz) rxbuf
(.clk (rx_clk),
.wr_en (rxbuf_we),
.wr_addr (rx_wr_ptr),
.wr_data (rx_data),
 
.rd_addr (rx_rd_ptr),
.rd_data (rxbuf_data));
 
ram_1r_1w #(8, txbuf_sz, wr_ptr_sz) txbuf
(.clk (clk),
.wr_en (wr_sel_tx_data),
.wr_addr (txi_wr_ptr),
.wr_data (tx_wr_data),
 
.rd_addr (txo_xm_ptr),
.rd_data (txbuf_data));
 
simple_gmii_regs regs0
(
// Outputs
.rd_data (rd_data),
.doe (doe),
.status_msk (),
.control (start_transmit),
.rx_data_stb (rx_rd_stb),
.tx_data (tx_wr_data),
.tx_data_stb (tx_wr_stb),
.config (en_preamble),
.int_n (int_n),
// Inputs
.clk (clk),
.reset (reset),
.addr (addr[15:0]),
.wr_data (wr_data),
.rd_n (rd_n),
.wr_n (wr_n),
.iorq_n (iorq_n),
.status_set (status_set[1:0]),
.control_clr (start_transmit), // auto-clear when set
.rx_len0 (rx_len[7:0]),
.rx_len1 (rx_len[15:8]),
.rx_data (rx_rd_data));
 
endmodule // simple_gmii
/trunk/rtl/simple_gmii/simple_gmii.trg
0,0 → 1,48
<!-- comment block
// Copyright (c) 2005 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
// IO-interface:
// R0 - Status register
// R1 - Control register
// R2 - RX Length (low)
// R3 - RX Length (high)
// R4 - RX Data
// R5 - TX Data
// R6 - Configuration
 
// Status bits:
// [0] RX Packet Ready
// [1] TX Transmit Complete
 
// Control bits:
// [0] Send TX Packet
-->
<tv_registers name="simple_gmii_regs" addr_sz="8" base_addr="8">
<register name="status" type="int_fixed" width="2" int_value="8'hcf" default="0">
Interrupt register, vector is set to "RST 8" instruction
</register>
<register name="control" type="soft_set" width="1" default="0"/>
<register name="rx_len0" width="8" type="status"/>
<register name="rx_len1" width="8" type="status"/>
<register name="rx_data" width="8" type="read_stb"/>
<register name="tx_data" width="8" type="write_stb"/>
<register name="config" width="1" type="config" default="0"/>
</tv_registers>
/trunk/rtl/simple_gmii/simple_gmii_core.v
0,0 → 1,508
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
//----------------------------------------------------------------------
// Simple network interface
//
// Implements a GMII-like byte-wide interface on one side, and
// an IO-mapped interface to the tv80.
 
// IO-interface:
// R0 -- Status register
// R1 -- Control register
// R2 -- RX Length (low)
// R3 -- RX Length (high)
// R4 -- RX Data
// R5 -- TX Data
// R6 -- Configuration
 
// Status bits:
// [0] RX Packet Ready
// [1] TX Transmit Complete
 
// Control bits:
// [0] Send TX Packet
//----------------------------------------------------------------------
 
module simple_gmii_core
#(parameter txbuf_sz = 512,
parameter rxbuf_sz = 512,
parameter wr_ptr_sz = 10)
(
input clk,
input reset,
 
// GMII Interface
input [7:0] rx_data,
input rx_clk,
input rx_dv,
input rx_er,
 
output reg [7:0] tx_data,
input tx_clk,
output reg tx_dv,
output reg tx_er,
 
// RX Buf RAM
output reg rxbuf_we,
output reg [wr_ptr_sz-1:0] rx_wr_ptr,
output reg [wr_ptr_sz-1:0] rx_rd_ptr,
input [7:0] rxbuf_data,
 
// TX Buf RAM
output reg wr_sel_tx_data,
output reg [wr_ptr_sz-1:0] txi_wr_ptr,
//input [7:0] io_data_in,
output reg [wr_ptr_sz-1:0] txo_xm_ptr,
input [7:0] txbuf_data,
 
// Register interface
output [1:0] status_set,
input start_transmit, // control[0]
output [15:0] rx_len,
output [7:0] rx_rd_data,
input rx_rd_stb,
//input [7:0] tx_wr_data,
input tx_wr_stb,
input en_preamble // config[0]
);
//parameter io_base_addr = 8'hA0;
//parameter txbuf_sz = 512, rxbuf_sz = 512;
//parameter wr_ptr_sz = 10;
//parameter st_tx_idle = 0, st_tx_xmit = 1;
parameter st_txi_idle = 1'b0, st_txi_xmit = 1'b1;
parameter st_txo_idle = 2'b0, st_txo_pre = 2'b10, st_txo_xmit = 2'b11, st_txo_wait = 2'b01;
parameter st_rxo_idle = 2'b00,
st_rxo_ready = 2'b01,
st_rxo_ack = 2'b11;
parameter st_rxin_idle = 2'b00,
st_rxin_pre = 2'b01,
st_rxin_receive = 2'b11,
st_rxin_hold = 2'b10;
 
parameter SFD = 8'hD5;
//reg [wr_ptr_sz-1:0] tx_wr_ptr, tx_xm_ptr;
reg [wr_ptr_sz-1:0] rx_count;
reg txi_state;
reg [1:0] txo_state;
reg txi_start;
wire txo_start;
reg txo_done;
wire txi_done;
reg [wr_ptr_sz-1:0] txo_wr_ptr;
 
reg stat_tx_complete;
 
reg stat_rx_avail;
 
reg [1:0] rxin_state;
reg rxin_complete;
reg [1:0] nxt_rxin_state;
reg nxt_rxin_complete;
reg [wr_ptr_sz-1:0] nxt_rx_wr_ptr;
reg rd_sel_rx_data;
reg [1:0] rxo_state;
wire rxo_complete;
reg rxo_ack;
wire rxin_ack;
//assign io_select = ((io_base_addr >> 3) == addr[7:3]);
 
//------------------------------
// IO Read Mux
//------------------------------
 
assign rx_len = { {16-wr_ptr_sz{1'b0}}, rx_count };
assign status_set = { stat_tx_complete, stat_rx_avail };
assign rx_rd_data = rxbuf_data;
//------------------------------
// Receive Logic
//------------------------------
 
always @*
begin
rd_sel_rx_data = rx_rd_stb;
//rxbuf_we = ((rxin_state == st_rxin_idle) | (rxin_state == st_rxin_receive)) & rx_dv;
end
/*
ram_1r_1w #(8, rxbuf_sz, wr_ptr_sz) rxbuf
(.clk (rx_clk),
.wr_en (rxbuf_we),
.wr_addr (rx_wr_ptr),
.wr_data (rx_data),
 
.rd_addr (rx_rd_ptr),
.rd_data (rxbuf_data));
*/
 
always @*
begin
rxbuf_we = 0;
nxt_rxin_complete = rxin_complete;
nxt_rxin_state = rxin_state;
nxt_rx_wr_ptr = rx_wr_ptr;
case (rxin_state)
st_rxin_idle :
begin
if (rx_dv)
begin
nxt_rxin_complete = 0;
if (en_preamble & (rx_data != SFD))
nxt_rxin_state = st_rxin_pre;
else
begin
nxt_rx_wr_ptr = rx_wr_ptr + 1;
nxt_rxin_state = st_rxin_receive;
rxbuf_we = 1;
end
end
else
begin
nxt_rx_wr_ptr = 0;
end
end // case: st_rxin_idle
 
st_rxin_pre :
begin
if (rx_data == SFD)
nxt_rxin_state = st_rxin_receive;
end
st_rxin_receive :
begin
if (rx_dv)
begin
nxt_rx_wr_ptr = rx_wr_ptr + 1;
rxbuf_we = 1;
end
else
begin
nxt_rxin_state = st_rxin_hold;
nxt_rxin_complete = 1;
end
end
 
st_rxin_hold :
begin
if (rxin_ack & !rx_dv)
begin
nxt_rxin_state = st_rxin_idle;
nxt_rxin_complete = 0;
end
end
 
default :
nxt_rxin_state = st_rxin_idle;
endcase // case(rxin_state)
end // always @ *
always @(posedge rx_clk)
begin
if (reset)
begin
rxin_state <= #1 st_rxin_idle;
rxin_complete <= #1 0;
rx_wr_ptr <= #1 0;
end
else
begin
rxin_state <= #1 nxt_rxin_state;
rxin_complete <= #1 nxt_rxin_complete;
rx_wr_ptr <= #1 nxt_rx_wr_ptr;
end // else: !if(reset)
end // always @ (posedge rx_clk)
/*
always @(posedge rx_clk)
begin
if (reset)
begin
rxin_state <= #1 st_rxin_idle;
rxin_complete <= #1 0;
rx_wr_ptr <= #1 0;
end
else
begin
case (rxin_state)
st_rxin_idle :
begin
if (rx_dv)
begin
rxin_complete <= #1 0;
if (en_preamble & (rx_data != SFD))
rxin_state <= #1 st_rxin_pre;
else
begin
rx_wr_ptr <= #1 rx_wr_ptr + 1;
rxin_state <= #1 st_rxin_receive;
end
end
else
begin
rx_wr_ptr <= #1 0;
end
end // case: st_rxin_idle
 
st_rxin_pre :
begin
if (rx_data == SFD)
rxin_state <= #1 st_rxin_receive;
end
st_rxin_receive :
begin
if (rx_dv)
rx_wr_ptr <= #1 rx_wr_ptr + 1;
else
begin
rxin_state <= #1 st_rxin_hold;
rxin_complete <= #1 1;
end
end
 
st_rxin_hold :
begin
if (rxin_ack & !rx_dv)
begin
rxin_state <= #1 st_rxin_idle;
rxin_complete <= #1 0;
end
end
 
default :
rxin_state <= #1 st_rxin_idle;
endcase // case(rxin_state)
end // else: !if(reset)
end // always @ (posedge rx_clk)
*/
sync2 comp_sync (clk, rxin_complete, rxo_complete);
sync2 ack_sync (rx_clk, rxo_ack, rxin_ack);
 
always @(posedge clk)
begin
if (reset)
begin
rx_count <= #1 0;
rxo_state <= #1 st_rxo_idle;
stat_rx_avail <= #1 0;
rxo_ack <= #1 0;
end
else
begin
case (rxo_state)
st_rxo_idle :
begin
rx_rd_ptr <= #1 0;
if (rxin_complete)
begin
rxo_state <= #1 st_rxo_ready;
stat_rx_avail <= #1 1;
rx_count <= #1 rx_wr_ptr;
end
end
 
st_rxo_ready :
begin
if (rd_sel_rx_data)
rx_rd_ptr <= #1 rx_rd_ptr + 1;
 
if (rx_rd_ptr == rx_count)
begin
rxo_ack <= #1 1;
rxo_state <= #1 st_rxo_ack;
stat_rx_avail <= #1 0;
end
end // case: st_rxo_ready
 
st_rxo_ack :
begin
if (!rxo_complete)
rxo_state <= #1 st_rxo_idle;
end
 
default :
rxo_state <= #1 st_rxo_idle;
endcase // case(rxo_state)
end // else: !if(reset)
end // always @ (posedge clk)
//------------------------------
// Transmit Logic
//------------------------------
 
always @*
begin
wr_sel_tx_data = tx_wr_stb;
end
 
/*
ram_1r_1w #(8, txbuf_sz, wr_ptr_sz) txbuf
(.clk (clk),
.wr_en (wr_sel_tx_data),
.wr_addr (txi_wr_ptr),
.wr_data (io_data_in),
 
.rd_addr (txo_xm_ptr),
.rd_data (txbuf_data));
*/
 
always @(posedge clk)
begin
if (reset)
begin
txi_state <= #1 st_txi_idle;
txi_start <= #1 0;
txi_wr_ptr <= #1 0;
stat_tx_complete <= #1 0;
end
else
begin
case (txi_state)
st_txi_idle :
begin
stat_tx_complete <= #1 0;
if (start_transmit)
begin
txi_state <= #1 st_txi_xmit;
txi_start <= #1 1;
end
else if (wr_sel_tx_data)
begin
txi_wr_ptr <= #1 txi_wr_ptr + 1;
end
end
 
st_txi_xmit :
begin
if (txi_done)
begin
txi_start <= #1 0;
txi_state <= #1 st_txi_idle;
txi_wr_ptr <= #1 0;
stat_tx_complete <= #1 1;
end
end
 
default :
txi_state <= #1 st_txi_idle;
endcase // case(txi_state)
end
end // always @ (posedge clk)
 
sync2 tx_start_sync (tx_clk, txi_start, txo_start);
sync2 tx_done_sync (clk, txo_done, txi_done);
 
 
always @(posedge tx_clk)
begin
if (reset)
begin
txo_state <= #1 st_txo_idle;
txo_wr_ptr <= #1 0;
txo_xm_ptr <= #1 0;
tx_data <= #1 0;
tx_dv <= #1 0;
tx_er <= #1 0;
txo_done <= #1 0;
end
else
begin
case (txo_state)
st_txo_idle :
begin
txo_xm_ptr <= #1 0;
tx_dv <= #1 0;
tx_er <= #1 0;
if (txo_start)
begin
if (en_preamble)
txo_state <= #1 st_txo_pre;
else
txo_state <= #1 st_txo_xmit;
txo_wr_ptr <= #1 txi_wr_ptr;
end
end
 
st_txo_pre :
begin
tx_er <= #1 0;
tx_dv <= #1 1;
if (txo_xm_ptr == 7)
begin
txo_xm_ptr <= #1 0;
txo_state <= #1 st_txo_xmit;
tx_data <= #1 8'hd5;
end
else
begin
txo_xm_ptr <= #1 txo_xm_ptr + 1;
tx_data <= #1 8'h55;
end
end
st_txo_xmit :
begin
if (txo_xm_ptr == txo_wr_ptr)
begin
tx_dv <= #1 0;
tx_er <= #1 0;
txo_state <= #1 st_txo_wait;
txo_wr_ptr <= #1 0;
txo_done <= #1 1;
end
else
begin
tx_data <= #1 txbuf_data;
tx_dv <= #1 1;
tx_er <= #1 0;
txo_xm_ptr <= #1 txo_xm_ptr + 1;
end
end // case: st_txo_xmit
 
st_txo_wait :
begin
if (!txo_start)
begin
txo_done <= #1 0;
txo_state <= #1 st_txo_idle;
end
end
 
default :
begin
txo_state <= #1 st_txo_idle;
end
endcase // case(tx_state)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
 

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