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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/
- from Rev 66 to Rev 67
- ↔ Reverse comparison
Rev 66 → Rev 67
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
489,16 → 489,19
|
initial // Timeout |
begin |
`ifdef LONG_TIMEOUT |
#5000000; |
`else |
#500000; |
`ifdef NO_TIMEOUT |
`else |
`ifdef LONG_TIMEOUT |
#5000000; |
`else |
#500000; |
`endif |
$display(" ==============================================="); |
$display("| SIMULATION FAILED |"); |
$display("| (simulation Timeout) |"); |
$display(" ==============================================="); |
$finish; |
`endif |
$display(" ==============================================="); |
$display("| SIMULATION FAILED |"); |
$display("| (simulation Timeout) |"); |
$display(" ==============================================="); |
$finish; |
end |
|
initial // Normal end of test |
/openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v
0,0 → 1,341
|
//---------------------------------------------------------------------------- |
// Copyright (C) 2001 Authors |
// |
// This source file may be used and distributed without restriction provided |
// that this copyright statement is not removed from the file and that any |
// derivative work contains the original copyright notice and the associated |
// disclaimer. |
// |
// This source file is free software; you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation; either version 2.1 of the License, or |
// (at your option) any later version. |
// |
// This source is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public |
// License for more details. |
// |
// You should have received a copy of the GNU Lesser General Public License |
// along with this source; if not, write to the Free Software Foundation, |
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
// |
//---------------------------------------------------------------------------- |
// |
// *File Name: omsp_multiplier.v |
// |
// *Module Description: |
// 16x16 Hardware multiplier. |
// |
// *Author(s): |
// - Olivier Girard, olgirard@gmail.com |
// |
//---------------------------------------------------------------------------- |
// $Rev: 23 $ |
// $LastChangedBy: olivier.girard $ |
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $ |
//---------------------------------------------------------------------------- |
`include "timescale.v" |
`include "openMSP430_defines.v" |
|
module omsp_multiplier ( |
|
// OUTPUTs |
per_dout, // Peripheral data output |
|
// INPUTs |
mclk, // Main system clock |
per_addr, // Peripheral address |
per_din, // Peripheral data input |
per_en, // Peripheral enable (high active) |
per_wen, // Peripheral write enable (high active) |
puc // Main system reset |
); |
|
// OUTPUTs |
//========= |
output [15:0] per_dout; // Peripheral data output |
|
// INPUTs |
//========= |
input mclk; // Main system clock |
input [7:0] per_addr; // Peripheral address |
input [15:0] per_din; // Peripheral data input |
input per_en; // Peripheral enable (high active) |
input [1:0] per_wen; // Peripheral write enable (high active) |
input puc; // Main system reset |
|
|
//============================================================================= |
// 1) PARAMETER/REGISTERS & WIRE DECLARATION |
//============================================================================= |
|
// Register addresses |
parameter OP1_MPY = 9'h130; |
parameter OP1_MPYS = 9'h132; |
parameter OP1_MAC = 9'h134; |
parameter OP1_MACS = 9'h136; |
parameter OP2 = 9'h138; |
parameter RESLO = 9'h13A; |
parameter RESHI = 9'h13C; |
parameter SUMEXT = 9'h13E; |
|
|
// Register one-hot decoder |
parameter OP1_MPY_D = (512'h1 << OP1_MPY); |
parameter OP1_MPYS_D = (512'h1 << OP1_MPYS); |
parameter OP1_MAC_D = (512'h1 << OP1_MAC); |
parameter OP1_MACS_D = (512'h1 << OP1_MACS); |
parameter OP2_D = (512'h1 << OP2); |
parameter RESLO_D = (512'h1 << RESLO); |
parameter RESHI_D = (512'h1 << RESHI); |
parameter SUMEXT_D = (512'h1 << SUMEXT); |
|
|
// Wire pre-declarations |
wire result_wr; |
wire result_clr; |
wire early_read; |
|
|
//============================================================================ |
// 2) REGISTER DECODER |
//============================================================================ |
|
// Register address decode |
reg [511:0] reg_dec; |
always @(per_addr) |
case ({per_addr,1'b0}) |
OP1_MPY : reg_dec = OP1_MPY_D; |
OP1_MPYS : reg_dec = OP1_MPYS_D; |
OP1_MAC : reg_dec = OP1_MAC_D; |
OP1_MACS : reg_dec = OP1_MACS_D; |
OP2 : reg_dec = OP2_D; |
RESLO : reg_dec = RESLO_D; |
RESHI : reg_dec = RESHI_D; |
SUMEXT : reg_dec = SUMEXT_D; |
default : reg_dec = {512{1'b0}}; |
endcase |
|
// Read/Write probes |
wire reg_write = |per_wen & per_en; |
wire reg_read = ~|per_wen & per_en; |
|
// Read/Write vectors |
wire [511:0] reg_wr = reg_dec & {512{reg_write}}; |
wire [511:0] reg_rd = reg_dec & {512{reg_read}}; |
|
|
//============================================================================ |
// 3) REGISTERS |
//============================================================================ |
|
// OP1 Register |
//----------------- |
reg [15:0] op1; |
|
wire op1_wr = reg_wr[OP1_MPY] | |
reg_wr[OP1_MPYS] | |
reg_wr[OP1_MAC] | |
reg_wr[OP1_MACS]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) op1 <= 16'h0000; |
else if (op1_wr) op1 <= per_din; |
|
wire [15:0] op1_rd = op1; |
|
|
// OP2 Register |
//----------------- |
reg [15:0] op2; |
|
wire op2_wr = reg_wr[OP2]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) op2 <= 16'h0000; |
else if (op2_wr) op2 <= per_din; |
|
wire [15:0] op2_rd = op2; |
|
|
// RESLO Register |
//----------------- |
reg [15:0] reslo; |
|
wire [15:0] reslo_nxt; |
wire reslo_wr = reg_wr[RESLO]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) reslo <= 16'h0000; |
else if (reslo_wr) reslo <= per_din; |
else if (result_clr) reslo <= 16'h0000; |
else if (result_wr) reslo <= reslo_nxt; |
|
wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo; |
|
|
// RESHI Register |
//----------------- |
reg [15:0] reshi; |
|
wire [15:0] reshi_nxt; |
wire reshi_wr = reg_wr[RESHI]; |
|
always @ (posedge mclk or posedge puc) |
if (puc) reshi <= 16'h0000; |
else if (reshi_wr) reshi <= per_din; |
else if (result_clr) reshi <= 16'h0000; |
else if (result_wr) reshi <= reshi_nxt; |
|
wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi; |
|
|
// SUMEXT Register |
//----------------- |
reg [1:0] sumext_s; |
|
wire [1:0] sumext_s_nxt; |
|
always @ (posedge mclk or posedge puc) |
if (puc) sumext_s <= 2'b00; |
else if (op2_wr) sumext_s <= 2'b00; |
else if (result_wr) sumext_s <= sumext_s_nxt; |
|
wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt}; |
wire [15:0] sumext = {{14{sumext_s[1]}}, sumext_s}; |
wire [15:0] sumext_rd = early_read ? sumext_nxt : sumext; |
|
|
//============================================================================ |
// 4) DATA OUTPUT GENERATION |
//============================================================================ |
|
// Data output mux |
wire [15:0] op1_mux = op1_rd & {16{reg_rd[OP1_MPY] | |
reg_rd[OP1_MPYS] | |
reg_rd[OP1_MAC] | |
reg_rd[OP1_MACS]}}; |
wire [15:0] op2_mux = op2_rd & {16{reg_rd[OP2]}}; |
wire [15:0] reslo_mux = reslo_rd & {16{reg_rd[RESLO]}}; |
wire [15:0] reshi_mux = reshi_rd & {16{reg_rd[RESHI]}}; |
wire [15:0] sumext_mux = sumext_rd & {16{reg_rd[SUMEXT]}}; |
|
wire [15:0] per_dout = op1_mux | |
op2_mux | |
reslo_mux | |
reshi_mux | |
sumext_mux; |
|
|
//============================================================================ |
// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC |
//============================================================================ |
|
// Multiplier configuration |
//-------------------------- |
|
// Detect signed mode |
reg sign_sel; |
always @ (posedge mclk or posedge puc) |
if (puc) sign_sel <= 1'b0; |
else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS]; |
|
|
// Detect accumulate mode |
reg acc_sel; |
always @ (posedge mclk or posedge puc) |
if (puc) acc_sel <= 1'b0; |
else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS]; |
|
|
// Detect whenever the RESHI and RESLO registers should be cleared |
assign result_clr = op2_wr & ~acc_sel; |
|
// Combine RESHI & RESLO |
wire [31:0] result = {reshi, reslo}; |
|
|
// 16x16 Multiplier (result computed in 1 clock cycle) |
//----------------------------------------------------- |
`ifdef MPY_16x16 |
|
// Detect start of a multiplication |
reg cycle; |
always @ (posedge mclk or posedge puc) |
if (puc) cycle <= 1'b0; |
else cycle <= op2_wr; |
|
assign result_wr = cycle; |
|
// Expand the operands to support signed & unsigned operations |
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1}; |
wire signed [16:0] op2_xp = {sign_sel & op2[15], op2}; |
|
|
// 17x17 signed multiplication |
wire signed [33:0] product = op1_xp * op2_xp; |
|
// Accumulate |
wire [32:0] result_nxt = {1'b0, result} + {1'b0, product[31:0]}; |
|
|
// Next register values |
assign reslo_nxt = result_nxt[15:0]; |
assign reshi_nxt = result_nxt[31:16]; |
assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} : |
{1'b0, result_nxt[32]}; |
|
|
// Since the MAC is completed within 1 clock cycle, |
// an early read can't happen. |
assign early_read = 1'b0; |
|
|
// 16x8 Multiplier (result computed in 2 clock cycles) |
//----------------------------------------------------- |
`else |
|
// Detect start of a multiplication |
reg [1:0] cycle; |
always @ (posedge mclk or posedge puc) |
if (puc) cycle <= 2'b00; |
else cycle <= {cycle[0], op2_wr}; |
|
assign result_wr = |cycle; |
|
|
// Expand the operands to support signed & unsigned operations |
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1}; |
wire signed [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]}; |
wire signed [8:0] op2_lo_xp = { 1'b0, op2[7:0]}; |
wire signed [8:0] op2_xp = cycle[0] ? op2_hi_xp : op2_lo_xp; |
|
|
// 17x9 signed multiplication |
wire signed [25:0] product = op1_xp * op2_xp; |
|
wire [31:0] product_xp = cycle[0] ? {product[23:0], 8'h00} : |
{{8{sign_sel & product[23]}}, product[23:0]}; |
|
// Accumulate |
wire [32:0] result_nxt = {1'b0, result} + {1'b0, product_xp[31:0]}; |
|
|
// Next register values |
assign reslo_nxt = result_nxt[15:0]; |
assign reshi_nxt = result_nxt[31:16]; |
assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} : |
{1'b0, result_nxt[32] | sumext_s[0]}; |
|
// Since the MAC is completed within 2 clock cycle, |
// an early read can happen during the second cycle. |
assign early_read = cycle[1]; |
|
`endif |
|
|
endmodule // omsp_multiplier |
|
`include "openMSP430_undefines.v" |
openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
===================================================================
--- openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v (revision 66)
+++ openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v (revision 67)
@@ -62,6 +62,10 @@
// 14 -> 32 kB
`define DMEM_AWIDTH 6
+// Include/Exclude Hardware Multiplier
+`define MULTIPLIER
+
+
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
@@ -297,3 +301,13 @@
`endif
`endif
`endif
+
+//
+// MULTIPLIER CONFIGURATION
+//======================================
+
+// If uncommented, the following define selects
+// the 16x16 multiplier (1 cycle) instead of the
+// default 16x8 multplier (2 cycles)
+//`define MPY_16x16
+
\ No newline at end of file
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
50,6 → 50,11
`undef DMEM_AWIDTH |
`endif |
|
// Include/Exclude Hardware Multiplier |
`ifdef MULTIPLIER |
`undef MULTIPLIER |
`endif |
|
//---------------------------------------------------------------------------- |
// REMOTE DEBUGGING INTERFACE CONFIGURATION |
//---------------------------------------------------------------------------- |
495,4 → 500,12
// Enable/Disable the hardware breakpoint RANGE mode |
`ifdef HWBRK_RANGE |
`undef HWBRK_RANGE |
`endif |
`endif |
|
// |
// MULTIPLIER CONFIGURATION |
//====================================== |
|
`ifdef MPY_16x16 |
`undef MPY_16x16 |
`endif |
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
148,6 → 148,7
wire [15:0] per_dout_or; |
wire [15:0] per_dout_sfr; |
wire [15:0] per_dout_wdog; |
wire [15:0] per_dout_mpy; |
wire [15:0] per_dout_clk; |
|
|
375,17 → 376,39
|
|
//============================================================================= |
// 8) PERIPHERALS' OUTPUT BUS |
// 8) HARDWARE MULTIPLIER |
//============================================================================= |
`ifdef MULTIPLIER |
omsp_multiplier multiplier_0 ( |
|
// OUTPUTs |
.per_dout (per_dout_mpy), // Peripheral data output |
|
// INPUTs |
.mclk (mclk), // Main system clock |
.per_addr (per_addr), // Peripheral address |
.per_din (per_din), // Peripheral data input |
.per_en (per_en), // Peripheral enable (high active) |
.per_wen (per_wen), // Peripheral write enable (high active) |
.puc (puc) // Main system reset |
); |
`else |
assign per_dout_mpy = 16'h0000; |
`endif |
|
//============================================================================= |
// 9) PERIPHERALS' OUTPUT BUS |
//============================================================================= |
|
assign per_dout_or = per_dout | |
per_dout_clk | |
per_dout_sfr | |
per_dout_wdog; |
per_dout_wdog | |
per_dout_mpy; |
|
|
//============================================================================= |
// 9) DEBUG INTERFACE |
// 10) DEBUG INTERFACE |
//============================================================================= |
|
`ifdef DBG_EN |
/openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy
0,0 → 1,35
#!/bin/sh |
|
# Enable/Disable waveform dumping |
OMSP_NODUMP=1 |
export OMSP_NODUMP |
|
rm -rf *.log |
echo "" |
echo " ====================================================" |
echo "| WARNING: Complete Hardware Multiplier verification |" |
echo "| regression might take several hours. |" |
echo " ====================================================" |
echo "" |
|
# Hardware multiplier test patterns |
../bin/msp430sim mpy_basic | tee mpy_basic.log |
../bin/msp430sim mpy_mpy | tee mpy_mpy.log |
../bin/msp430sim mpy_mpys | tee mpy_mpys.log |
../bin/msp430sim mpy_mac | tee mpy_mac.log |
../bin/msp430sim mpy_macs | tee mpy_macs.log |
|
grep FAILED *.log |
echo "" |
echo " ================================" |
echo -n "| Number of passed patterns: " |
cat *.log | grep -c PASSED |
echo -n "| Number of failed patterns: " |
cat *.log | grep -c FAILED |
echo "|--------------------------------" |
echo -n "| Number of patterns: " |
ls -1 *.log | wc -l |
echo " ================================" |
echo " Make sure passed == total" |
echo "" |
echo "" |
openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/run/run
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/run/run (revision 66)
+++ openmsp430/trunk/core/sim/rtl_sim/run/run (revision 67)
@@ -1,3 +1,7 @@
#!/bin/sh
-../bin/msp430sim dbg_cpu
+# Enable/Disable waveform dumping
+OMSP_NODUMP=0
+export OMSP_NODUMP
+
+../bin/msp430sim mpy_basic
/openmsp430/trunk/core/sim/rtl_sim/run/run_all
82,7 → 82,10
../bin/msp430sim tA_clkmux | tee tA_clkmux.log |
|
|
# Hardware multiplier test patterns |
../bin/msp430sim mpy_basic | tee mpy_basic.log |
|
|
grep FAILED *.log |
echo "" |
echo " ================================" |
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.s43
0,0 → 1,146
/*===========================================================================*/ |
/* Copyright (C) 2001 Authors */ |
/* */ |
/* This source file may be used and distributed without restriction provided */ |
/* that this copyright statement is not removed from the file and that any */ |
/* derivative work contains the original copyright notice and the associated */ |
/* disclaimer. */ |
/* */ |
/* This source file is free software; you can redistribute it and/or modify */ |
/* it under the terms of the GNU Lesser General Public License as published */ |
/* by the Free Software Foundation; either version 2.1 of the License, or */ |
/* (at your option) any later version. */ |
/* */ |
/* This source is distributed in the hope that it will be useful, but WITHOUT*/ |
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ |
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */ |
/* License for more details. */ |
/* */ |
/* You should have received a copy of the GNU Lesser General Public License */ |
/* along with this source; if not, write to the Free Software Foundation, */ |
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ |
/* */ |
/*===========================================================================*/ |
/* HARDWARE MULTIPLIER */ |
/*---------------------------------------------------------------------------*/ |
/* Test the hardware multiplier: */ |
/* - MPYS mode. */ |
/* */ |
/* Author(s): */ |
/* - Olivier Girard, olgirard@gmail.com */ |
/* */ |
/*---------------------------------------------------------------------------*/ |
/* $Rev: 18 $ */ |
/* $LastChangedBy: olivier.girard $ */ |
/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */ |
/*===========================================================================*/ |
|
.global main |
|
.set WDTCTL, 0x0120 |
|
.set MPY, 0x0130 |
.set MPYS, 0x0132 |
.set MAC, 0x0134 |
.set MACS, 0x0136 |
.set OP2, 0x0138 |
.set RESLO, 0x013A |
.set RESHI, 0x013C |
.set SUMEXT, 0x013E |
|
|
main: |
|
/* -------------- SIGNED MULTIPLICATION --------------- */ |
|
;; Disable watchdog |
mov #0x5A80, &WDTCTL |
|
;; Initialize variables |
mov #0x0000, R15 |
mov #0x0000, R8 |
mov #0x0000, R9 |
|
mpy_loop: |
|
;; Initialize RESLO and RESHI to make sure it is overwritten |
mov #0x0000, &RESLO |
mov #0xC000, &RESHI |
|
;; Perform unsigned R8*R9 |
mov R8, &MPYS |
mov R9, &OP2 |
|
;; Read result |
mov &RESLO, R10 |
mov &RESHI, R11 |
mov &SUMEXT, R12 |
|
;; Notify verilog checker |
add #1, R15 |
|
;; Update next OP1 (R8) |
cmp #0xF0F0, R8 |
jeq op2_update |
|
mov #0x00FF, R7 |
and R8, R7 |
cmp #0x00F0, R7 |
jeq op1_hi_update |
|
add #0x0010, R8 |
jmp mpy_loop |
op1_hi_update: |
and #0xff00, R8 |
add #0x1000, R8 |
jmp mpy_loop |
|
|
;; Update next OP2 (R9) |
op2_update: |
cmp #0xF0F0, R9 |
jeq end_of_test |
|
mov #0x0000, R8 |
|
mov #0x00FF, R7 |
and R9, R7 |
cmp #0x00F0, R7 |
jeq op2_hi_update |
|
add #0x0010, R9 |
jmp mpy_loop |
op2_hi_update: |
and #0xff00, R9 |
add #0x1000, R9 |
jmp mpy_loop |
|
|
|
/* ---------------------- END OF TEST --------------- */ |
end_of_test: |
nop |
br #0xffff |
|
|
|
|
/* ---------------------- INTERRUPT VECTORS --------------- */ |
|
.section .vectors, "a" |
.word end_of_test ; Interrupt 0 (lowest priority) <unused> |
.word end_of_test ; Interrupt 1 <unused> |
.word end_of_test ; Interrupt 2 <unused> |
.word end_of_test ; Interrupt 3 <unused> |
.word end_of_test ; Interrupt 4 <unused> |
.word end_of_test ; Interrupt 5 <unused> |
.word end_of_test ; Interrupt 6 <unused> |
.word end_of_test ; Interrupt 7 <unused> |
.word end_of_test ; Interrupt 8 <unused> |
.word end_of_test ; Interrupt 9 <unused> |
.word end_of_test ; Interrupt 10 Watchdog timer |
.word end_of_test ; Interrupt 11 <unused> |
.word end_of_test ; Interrupt 12 <unused> |
.word end_of_test ; Interrupt 13 <unused> |
.word end_of_test ; Interrupt 14 NMI |
.word main ; Interrupt 15 (highest priority) RESET |
openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v (revision 67)
@@ -0,0 +1,87 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MAC mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define NO_TIMEOUT
+
+integer i;
+reg [32:0] result;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+ i = 0;
+
+
+ for ( i=0; i < 'h10000; i=i+1)
+ begin
+ @(r15);
+ result = 32'hC000_0000 + (r8*r9);
+ if (r10 !== result[15:0])
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {15'h0000, result[32]}, result[31:16], result[15:0]);
+ tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO =====");
+ end
+ if (r11 !== result[31:16])
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {15'h0000, result[32]}, result[31:16], result[15:0]);
+ tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI =====");
+ end
+ if (r12 !== {15'h0000, result[32]})
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {15'h0000, result[32]}, result[31:16], result[15:0]);
+ tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT =====");
+ end
+
+ if (r15[7:0]==8'h00)
+ $display("OP2 = 0x%h done", r9);
+ end
+
+
+
+ stimulus_done = 1;
+ end
+
openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43 (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43 (revision 67)
@@ -0,0 +1,668 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MPY mode. */
+/* - MPYS mode. */
+/* - MAC mode. */
+/* - MACS mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set MPY, 0x0130
+.set MPYS, 0x0132
+.set MAC, 0x0134
+.set MACS, 0x0136
+.set OP2, 0x0138
+.set RESLO, 0x013A
+.set RESHI, 0x013C
+.set SUMEXT, 0x013E
+
+
+main:
+
+ /* -------------- UNSIGNED MULTIPLICATION --------------- */
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x3104, &MPY ; 0x3104 * 0x0285 = 0x007B_7F14, ext=0x0000
+ mov #0x0285, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0001, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x0000, &MPY ; 0x0000 * 0x0000 = 0x0000_0000, ext=0x0000
+ mov #0x0000, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0002, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x0001, &MPY ; 0x0001 * 0x0001 = 0x0000_0001, ext=0x0000
+ mov #0x0001, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0003, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x7FFF, &MPY ; 0x7FFF * 0x7FFF = 0x3FFF_0001, ext=0x0000
+ mov #0x7FFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0004, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0xFFFF, &MPY ; 0xFFFF * 0xFFFF = 0xFFFE_0001, ext=0x0000
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0005, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x7FFF, &MPY ; 0x7FFF * 0xFFFF = 0x7FFE_8001, ext=0x0000
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0006, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MPY ; 0x8000 * 0x7FFF = 0x3FFF_8000, ext=0x0000
+ mov #0x7FFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0007, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MPY ; 0x8000 * 0xFFFF = 0x7FFF_8000, ext=0x0000
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0008, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MPY ; 0x8000 * 0x8000 = 0x4000_0000, ext=0x0000
+ mov #0x8000, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0009, R15
+ nop
+ nop
+ nop
+ nop
+
+ /* -------------- SIGNED MULTIPLICATION --------------- */
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x3104, &MPYS ; 0x3104 * 0x8285 = 0xE7F9_7F14, ext=0xFFFF
+ mov #0x8285, &OP2 ; 12548 * -32123
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0001, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x0000, &MPYS ; 0x0000 * 0x0000 = 0x0000_0000, ext=0x0000
+ mov #0x0000, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0002, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x0001, &MPYS ; 0x0001 * 0x0001 = 0x0000_0001, ext=0x0000
+ mov #0x0001, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0003, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x7FFF, &MPYS ; 0x7FFF * 0x7FFF = 0x3FFF_0001, ext=0x0000
+ mov #0x7FFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0004, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0xFFFF, &MPYS ; 0xFFFF * 0xFFFF = 0x0000_0001, ext=0x0000
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0005, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x7FFF, &MPYS ; 0x7FFF * 0xFFFF = 0xFFFF_8001, ext=0xFFFF
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0006, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MPYS ; 0x8000 * 0x7FFF = 0xC000_8000, ext=0xFFFF
+ mov #0x7FFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0007, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MPYS ; 0x8000 * 0xFFFF = 0x0000_8000, ext=0x0000
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0008, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MPYS ; 0x8000 * 0x8000 = 0x4000_0000, ext=0x0000
+ mov #0x8000, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0009, R15
+ nop
+ nop
+ nop
+ nop
+
+ /* -------------- UNSIGNED MULTIPLY-ACCUMULATE --------------- */
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x3104, &MAC ; 0xC000_0000 + (0x3104 * 0x0285) = 0x007B_7F14, ext=0x0000
+ mov #0x0285, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0001, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x0000, &MAC ; 0xC000_0000 + (0x0000 * 0x0000) = 0xC000_0000, ext=0x0000
+ mov #0x0000, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0002, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x0001, &MAC ; 0xC000_0000 + (0x0001 * 0x0001) = 0xC000_0001, ext=0x0000
+ mov #0x0001, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0003, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x7FFF, &MAC ; 0xC000_0000 + (0x7FFF * 0x7FFF) = 0xFFFF_0001, ext=0x0000
+ mov #0x7FFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0004, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0xFFFF, &MAC ; 0xC000_0000 + (0xFFFF * 0xFFFF) = 0xBFFE_0001, ext=0x0001
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0005, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x7FFF, &MAC ; 0xC000_0000 + (0x7FFF * 0xFFFF) = 0x3FFE_8001, ext=0x0001
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0006, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MAC ; 0xC000_0000 + (0x8000 * 0x7FFF) = 0xFFFF_8000, ext=0x0000
+ mov #0x7FFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0007, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MAC ; 0xC000_0000 + (0x8000 * 0xFFFF) = 0x3FFF_8000, ext=0x0001
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0008, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MAC ; 0xC000_0000 + (0x8000 * 0x8000) = 0x0000_0000, ext=0x0001
+ mov #0x8000, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0009, R15
+ nop
+ nop
+ nop
+ nop
+
+
+ /* -------------- SIGNED MULTIPLY-ACCUMULATE --------------- */
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x3104, &MACS ; 0xC000_0000 + (0x3104 * 0x8285) = 0xA7F9_7F14, ext=0xFFFF
+ mov #0x8285, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0001, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x0000, &MACS ; 0xC000_0000 + (0x0000 * 0x0000) = 0xC000_0000, ext=0xFFFF
+ mov #0x0000, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0002, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x0001, &MACS ; 0xC000_0000 + (0x0001 * 0x0001) = 0xC000_0001, ext=0xFFFF
+ mov #0x0001, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0003, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x7FFF, &MACS ; 0xC000_0000 + (0x7FFF * 0x7FFF) = 0xFFFF_0001, ext=0xFFFF
+ mov #0x7FFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0004, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0xFFFF, &MACS ; 0xC000_0000 + (0xFFFF * 0xFFFF) = 0xC000_0001, ext=0xFFFF
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0005, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x7FFF, &MACS ; 0xC000_0000 + (0x7FFF * 0xFFFF = 0xBFFF_8001, ext=0xFFFF
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0006, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MACS ; 0xC000_0000 + (0x8000 * 0x7FFF) = 0x8000_8000, ext=0xFFFF
+ mov #0x7FFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0007, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MACS ; 0xC000_0000 + (0x8000 * 0xFFFF) = 0xC000_8000, ext=0xFFFF
+ mov #0xFFFF, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0008, R15
+ nop
+ nop
+ nop
+ nop
+
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ mov #0x8000, &MACS ; 0xC000_0000 + (0x8000 * 0x8000) = 0x0000_0000, ext=0x0000
+ mov #0x8000, &OP2
+
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+ nop
+ mov #0x0009, R15
+ nop
+ nop
+ nop
+ nop
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.s43
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.s43 (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.s43 (revision 67)
@@ -0,0 +1,146 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MAC mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set WDTCTL, 0x0120
+
+.set MPY, 0x0130
+.set MPYS, 0x0132
+.set MAC, 0x0134
+.set MACS, 0x0136
+.set OP2, 0x0138
+.set RESLO, 0x013A
+.set RESHI, 0x013C
+.set SUMEXT, 0x013E
+
+
+main:
+
+ /* -------------- UNSIGNED MULTIPLY ACCUMULATE --------------- */
+
+ ;; Disable watchdog
+ mov #0x5A80, &WDTCTL
+
+ ;; Initialize variables
+ mov #0x0000, R15
+ mov #0x0000, R8
+ mov #0x0000, R9
+
+mpy_loop:
+
+ ;; Initialize RESLO and RESHI to make sure it is added
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ ;; Perform unsigned R8*R9
+ mov R8, &MAC
+ mov R9, &OP2
+
+ ;; Read result
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+
+ ;; Notify verilog checker
+ add #1, R15
+
+ ;; Update next OP1 (R8)
+ cmp #0xF0F0, R8
+ jeq op2_update
+
+ mov #0x00FF, R7
+ and R8, R7
+ cmp #0x00F0, R7
+ jeq op1_hi_update
+
+ add #0x0010, R8
+ jmp mpy_loop
+ op1_hi_update:
+ and #0xff00, R8
+ add #0x1000, R8
+ jmp mpy_loop
+
+
+ ;; Update next OP2 (R9)
+ op2_update:
+ cmp #0xF0F0, R9
+ jeq end_of_test
+
+ mov #0x0000, R8
+
+ mov #0x00FF, R7
+ and R9, R7
+ cmp #0x00F0, R7
+ jeq op2_hi_update
+
+ add #0x0010, R9
+ jmp mpy_loop
+ op2_hi_update:
+ and #0xff00, R9
+ add #0x1000, R9
+ jmp mpy_loop
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.s43
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.s43 (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.s43 (revision 67)
@@ -0,0 +1,146 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MPY mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set WDTCTL, 0x0120
+
+.set MPY, 0x0130
+.set MPYS, 0x0132
+.set MAC, 0x0134
+.set MACS, 0x0136
+.set OP2, 0x0138
+.set RESLO, 0x013A
+.set RESHI, 0x013C
+.set SUMEXT, 0x013E
+
+
+main:
+
+ /* -------------- UNSIGNED MULTIPLICATION --------------- */
+
+ ;; Disable watchdog
+ mov #0x5A80, &WDTCTL
+
+ ;; Initialize variables
+ mov #0x0000, R15
+ mov #0x0000, R8
+ mov #0x0000, R9
+
+mpy_loop:
+
+ ;; Initialize RESLO and RESHI to make sure it is overwritten
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ ;; Perform unsigned R8*R9
+ mov R8, &MPY
+ mov R9, &OP2
+
+ ;; Read result
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+
+ ;; Notify verilog checker
+ add #1, R15
+
+ ;; Update next OP1 (R8)
+ cmp #0xF0F0, R8
+ jeq op2_update
+
+ mov #0x00FF, R7
+ and R8, R7
+ cmp #0x00F0, R7
+ jeq op1_hi_update
+
+ add #0x0010, R8
+ jmp mpy_loop
+ op1_hi_update:
+ and #0xff00, R8
+ add #0x1000, R8
+ jmp mpy_loop
+
+
+ ;; Update next OP2 (R9)
+ op2_update:
+ cmp #0xF0F0, R9
+ jeq end_of_test
+
+ mov #0x0000, R8
+
+ mov #0x00FF, R7
+ and R9, R7
+ cmp #0x00F0, R7
+ jeq op2_hi_update
+
+ add #0x0010, R9
+ jmp mpy_loop
+ op2_hi_update:
+ and #0xff00, R9
+ add #0x1000, R9
+ jmp mpy_loop
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v (revision 67)
@@ -0,0 +1,256 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MPY mode. */
+/* - MPYS mode. */
+/* - MAC mode. */
+/* - MACS mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+
+
+ // UNSIGNED MULTIPLICATION
+ //--------------------------------------------------------
+
+ @(r15===16'h0001);
+ if (r10 !== 16'h7F14) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (1) =====");
+ if (r11 !== 16'h007B) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (1) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (1) =====");
+
+ @(r15===16'h0002);
+ if (r10 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (2) =====");
+ if (r11 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (2) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (2) =====");
+
+ @(r15===16'h0003);
+ if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (3) =====");
+ if (r11 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (3) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (3) =====");
+
+ @(r15===16'h0004);
+ if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (4) =====");
+ if (r11 !== 16'h3FFF) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (4) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (4) =====");
+
+ @(r15===16'h0005);
+ if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (5) =====");
+ if (r11 !== 16'hFFFE) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (5) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (5) =====");
+
+ @(r15===16'h0006);
+ if (r10 !== 16'h8001) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (6) =====");
+ if (r11 !== 16'h7FFE) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (6) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (6) =====");
+
+ @(r15===16'h0007);
+ if (r10 !== 16'h8000) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (7) =====");
+ if (r11 !== 16'h3FFF) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (7) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (7) =====");
+
+ @(r15===16'h0008);
+ if (r10 !== 16'h8000) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (8) =====");
+ if (r11 !== 16'h7FFF) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (8) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (8) =====");
+
+ @(r15===16'h0009);
+ if (r10 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: RESLO (9) =====");
+ if (r11 !== 16'h4000) tb_error("====== UNSIGNED MULTIPLICATION: RESHI (9) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (9) =====");
+
+ $display("Unsigned Multiplication test completed (MPY mode).");
+
+ // SIGNED MULTIPLICATION
+ //--------------------------------------------------------
+
+ @(r15===16'h0001);
+ if (r10 !== 16'h7F14) tb_error("====== SIGNED MULTIPLICATION: RESLO (1) =====");
+ if (r11 !== 16'hE7F9) tb_error("====== SIGNED MULTIPLICATION: RESHI (1) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (1) =====");
+
+ @(r15===16'h0002);
+ if (r10 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESLO (2) =====");
+ if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESHI (2) =====");
+ if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (2) =====");
+
+ @(r15===16'h0003);
+ if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLICATION: RESLO (3) =====");
+ if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESHI (3) =====");
+ if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (3) =====");
+
+ @(r15===16'h0004);
+ if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLICATION: RESLO (4) =====");
+ if (r11 !== 16'h3FFF) tb_error("====== SIGNED MULTIPLICATION: RESHI (4) =====");
+ if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (4) =====");
+
+ @(r15===16'h0005);
+ if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLICATION: RESLO (5) =====");
+ if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESHI (5) =====");
+ if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (5) =====");
+
+ @(r15===16'h0006);
+ if (r10 !== 16'h8001) tb_error("====== SIGNED MULTIPLICATION: RESLO (6) =====");
+ if (r11 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLICATION: RESHI (6) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (6) =====");
+
+ @(r15===16'h0007);
+ if (r10 !== 16'h8000) tb_error("====== SIGNED MULTIPLICATION: RESLO (7) =====");
+ if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLICATION: RESHI (7) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (7) =====");
+
+ @(r15===16'h0008);
+ if (r10 !== 16'h8000) tb_error("====== SIGNED MULTIPLICATION: RESLO (8) =====");
+ if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESHI (8) =====");
+ if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (8) =====");
+
+ @(r15===16'h0009);
+ if (r10 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESLO (9) =====");
+ if (r11 !== 16'h4000) tb_error("====== SIGNED MULTIPLICATION: RESHI (9) =====");
+ if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (9) =====");
+
+ $display("Signed Multiplication test completed (MPYS mode)");
+
+
+ // UNSIGNED MULTIPLY ACCUMULATE
+ //--------------------------------------------------------
+
+ @(r15===16'h0001);
+ if (r10 !== 16'h7F14) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (1) =====");
+ if (r11 !== 16'hC07B) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (1) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (1) =====");
+
+ @(r15===16'h0002);
+ if (r10 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (2) =====");
+ if (r11 !== 16'hC000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (2) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (2) =====");
+
+ @(r15===16'h0003);
+ if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (3) =====");
+ if (r11 !== 16'hC000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (3) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (3) =====");
+
+ @(r15===16'h0004);
+ if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (4) =====");
+ if (r11 !== 16'hFFFF) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (4) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (4) =====");
+
+ @(r15===16'h0005);
+ if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (5) =====");
+ if (r11 !== 16'hBFFE) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (5) =====");
+ if (r12 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (5) =====");
+
+ @(r15===16'h0006);
+ if (r10 !== 16'h8001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (6) =====");
+ if (r11 !== 16'h3FFE) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (6) =====");
+ if (r12 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (6) =====");
+
+ @(r15===16'h0007);
+ if (r10 !== 16'h8000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (7) =====");
+ if (r11 !== 16'hFFFF) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (7) =====");
+ if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (7) =====");
+
+ @(r15===16'h0008);
+ if (r10 !== 16'h8000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (8) =====");
+ if (r11 !== 16'h3FFF) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (8) =====");
+ if (r12 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (8) =====");
+
+ @(r15===16'h0009);
+ if (r10 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO (9) =====");
+ if (r11 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI (9) =====");
+ if (r12 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (9) =====");
+
+ $display("Unsigned Multiply Accumulate test completed (MAC mode)");
+
+
+ // SIGNED MULTIPLY ACCUMULATE
+ //--------------------------------------------------------
+
+ @(r15===16'h0001);
+ if (r10 !== 16'h7F14) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (1) =====");
+ if (r11 !== 16'hA7F9) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (1) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (1) =====");
+
+ @(r15===16'h0002);
+ if (r10 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (2) =====");
+ if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (2) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (2) =====");
+
+ @(r15===16'h0003);
+ if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (3) =====");
+ if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (3) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (3) =====");
+
+ @(r15===16'h0004);
+ if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (4) =====");
+ if (r11 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (4) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (4) =====");
+
+ @(r15===16'h0005);
+ if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (5) =====");
+ if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (5) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (5) =====");
+
+ @(r15===16'h0006);
+ if (r10 !== 16'h8001) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (6) =====");
+ if (r11 !== 16'hBFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (6) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (6) =====");
+
+ @(r15===16'h0007);
+ if (r10 !== 16'h8000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (7) =====");
+ if (r11 !== 16'h8000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (7) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (7) =====");
+
+ @(r15===16'h0008);
+ if (r10 !== 16'h8000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (8) =====");
+ if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (8) =====");
+ if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (8) =====");
+
+ @(r15===16'h0009);
+ if (r10 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO (9) =====");
+ if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI (9) =====");
+ if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (9) =====");
+
+ $display("Signed Multiply Accumulate test completed (MACS mode)");
+
+
+ stimulus_done = 1;
+ end
+
openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v (revision 67)
@@ -0,0 +1,87 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MPY mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define NO_TIMEOUT
+
+integer i;
+reg [31:0] result;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+ i = 0;
+
+
+ for ( i=0; i < 'h10000; i=i+1)
+ begin
+ @(r15);
+ result = r8*r9;
+ if (r10 !== result[15:0])
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", 0, result[31:16], result[15:0]);
+ tb_error("====== UNSIGNED MULTIPLICATION: RESLO =====");
+ end
+ if (r11 !== result[31:16])
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", 0, result[31:16], result[15:0]);
+ tb_error("====== UNSIGNED MULTIPLICATION: RESHI =====");
+ end
+ if (r12 !== 16'h0000)
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", 0, result[31:16], result[15:0]);
+ tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT =====");
+ end
+
+ if (r15[7:0]==8'h00)
+ $display("OP2 = 0x%h done", r9);
+ end
+
+
+
+ stimulus_done = 1;
+ end
+
openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.s43
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.s43 (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.s43 (revision 67)
@@ -0,0 +1,146 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MACS mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+.global main
+
+.set WDTCTL, 0x0120
+
+.set MPY, 0x0130
+.set MPYS, 0x0132
+.set MAC, 0x0134
+.set MACS, 0x0136
+.set OP2, 0x0138
+.set RESLO, 0x013A
+.set RESHI, 0x013C
+.set SUMEXT, 0x013E
+
+
+main:
+
+ /* -------------- SIGNED MULTIPLY ACCUMULATE --------------- */
+
+ ;; Disable watchdog
+ mov #0x5A80, &WDTCTL
+
+ ;; Initialize variables
+ mov #0x0000, R15
+ mov #0x0000, R8
+ mov #0x0000, R9
+
+mpy_loop:
+
+ ;; Initialize RESLO and RESHI to make sure it is added
+ mov #0x0000, &RESLO
+ mov #0xC000, &RESHI
+
+ ;; Perform unsigned R8*R9
+ mov R8, &MACS
+ mov R9, &OP2
+
+ ;; Read result
+ mov &RESLO, R10
+ mov &RESHI, R11
+ mov &SUMEXT, R12
+
+ ;; Notify verilog checker
+ add #1, R15
+
+ ;; Update next OP1 (R8)
+ cmp #0xF0F0, R8
+ jeq op2_update
+
+ mov #0x00FF, R7
+ and R8, R7
+ cmp #0x00F0, R7
+ jeq op1_hi_update
+
+ add #0x0010, R8
+ jmp mpy_loop
+ op1_hi_update:
+ and #0xff00, R8
+ add #0x1000, R8
+ jmp mpy_loop
+
+
+ ;; Update next OP2 (R9)
+ op2_update:
+ cmp #0xF0F0, R9
+ jeq end_of_test
+
+ mov #0x0000, R8
+
+ mov #0x00FF, R7
+ and R9, R7
+ cmp #0x00F0, R7
+ jeq op2_hi_update
+
+ add #0x0010, R9
+ jmp mpy_loop
+ op2_hi_update:
+ and #0xff00, R9
+ add #0x1000, R9
+ jmp mpy_loop
+
+
+
+ /* ---------------------- END OF TEST --------------- */
+end_of_test:
+ nop
+ br #0xffff
+
+
+
+
+ /* ---------------------- INTERRUPT VECTORS --------------- */
+
+.section .vectors, "a"
+.word end_of_test ; Interrupt 0 (lowest priority)
+.word end_of_test ; Interrupt 1
+.word end_of_test ; Interrupt 2
+.word end_of_test ; Interrupt 3
+.word end_of_test ; Interrupt 4
+.word end_of_test ; Interrupt 5
+.word end_of_test ; Interrupt 6
+.word end_of_test ; Interrupt 7
+.word end_of_test ; Interrupt 8
+.word end_of_test ; Interrupt 9
+.word end_of_test ; Interrupt 10 Watchdog timer
+.word end_of_test ; Interrupt 11
+.word end_of_test ; Interrupt 12
+.word end_of_test ; Interrupt 13
+.word end_of_test ; Interrupt 14 NMI
+.word main ; Interrupt 15 (highest priority) RESET
openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.s43
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v (revision 67)
@@ -0,0 +1,89 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MPYS mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define NO_TIMEOUT
+
+integer i;
+reg signed [31:0] result;
+wire signed [15:0] r8_s = r8;
+wire signed [15:0] r9_s = r9;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+ i = 0;
+
+
+ for ( i=0; i < 'h10000; i=i+1)
+ begin
+ @(r15);
+ result = r8_s*r9_s;
+ if (r10 !== result[15:0])
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {16{result[31]}}, result[31:16], result[15:0]);
+ tb_error("====== SIGNED MULTIPLICATION: RESLO =====");
+ end
+ if (r11 !== result[31:16])
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {16{result[31]}}, result[31:16], result[15:0]);
+ tb_error("====== SIGNED MULTIPLICATION: RESHI =====");
+ end
+ if (r12 !== {16{result[31]}})
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {16{result[31]}}, result[31:16], result[15:0]);
+ tb_error("====== SIGNED MULTIPLICATION: SUMEXT =====");
+ end
+
+ if (r15[7:0]==8'h00)
+ $display("OP2 = 0x%h done", r9);
+ end
+
+
+
+ stimulus_done = 1;
+ end
+
openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Index: openmsp430/trunk/core/sim/rtl_sim/src/submit.f
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/submit.f (revision 66)
+++ openmsp430/trunk/core/sim/rtl_sim/src/submit.f (revision 67)
@@ -50,6 +50,7 @@
../../../rtl/verilog/omsp_dbg_hwbrk.v
../../../rtl/verilog/omsp_dbg_uart.v
../../../rtl/verilog/omsp_watchdog.v
+../../../rtl/verilog/omsp_multiplier.v
../../../rtl/verilog/periph/omsp_gpio.v
../../../rtl/verilog/periph/omsp_timerA.v
../../../rtl/verilog/periph/template_periph_8b.v
Index: openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v
===================================================================
--- openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v (nonexistent)
+++ openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v (revision 67)
@@ -0,0 +1,90 @@
+/*===========================================================================*/
+/* Copyright (C) 2001 Authors */
+/* */
+/* This source file may be used and distributed without restriction provided */
+/* that this copyright statement is not removed from the file and that any */
+/* derivative work contains the original copyright notice and the associated */
+/* disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU Lesser General Public License as published */
+/* by the Free Software Foundation; either version 2.1 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This source is distributed in the hope that it will be useful, but WITHOUT*/
+/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
+/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
+/* License for more details. */
+/* */
+/* You should have received a copy of the GNU Lesser General Public License */
+/* along with this source; if not, write to the Free Software Foundation, */
+/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
+/* */
+/*===========================================================================*/
+/* HARDWARE MULTIPLIER */
+/*---------------------------------------------------------------------------*/
+/* Test the hardware multiplier: */
+/* - MACS mode. */
+/* */
+/* Author(s): */
+/* - Olivier Girard, olgirard@gmail.com */
+/* */
+/*---------------------------------------------------------------------------*/
+/* $Rev: 18 $ */
+/* $LastChangedBy: olivier.girard $ */
+/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
+/*===========================================================================*/
+
+`define NO_TIMEOUT
+
+integer i;
+reg signed [31:0] result;
+wire signed [15:0] r8_s = r8;
+wire signed [15:0] r9_s = r9;
+
+initial
+ begin
+ $display(" ===============================================");
+ $display("| START SIMULATION |");
+ $display(" ===============================================");
+ repeat(5) @(posedge mclk);
+ stimulus_done = 0;
+ i = 0;
+
+
+ for ( i=0; i < 'h10000; i=i+1)
+ begin
+ @(r15);
+ result = r8_s*r9_s;
+ result = 32'hC000_0000 + result;
+ if (r10 !== result[15:0])
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {16{result[31]}}, result[31:16], result[15:0]);
+ tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO =====");
+ end
+ if (r11 !== result[31:16])
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {16{result[31]}}, result[31:16], result[15:0]);
+ tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI =====");
+ end
+ if (r12 !== {16{result[31]}})
+ begin
+ $display("ERROR: OP1 = 0x%h / OP2 = 0x%h", r8, r9);
+ $display("ERROR: Result is: SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", r12, r11, r10);
+ $display("ERROR: Expected : SUMEXT = 0x%h / RESHI = 0x%h / RESLO = 0x%h", {16{result[31]}}, result[31:16], result[15:0]);
+ tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT =====");
+ end
+
+ if (r15[7:0]==8'h00)
+ $display("OP2 = 0x%h done", r9);
+ end
+
+
+
+ stimulus_done = 1;
+ end
+
openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property