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/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/vhd/basic_tester_rx.vhd
0,0 → 1,369
-------------------------------------------------------------------------------
-- Title : A block which reads and checks data coming via HIBI
-- Project :
-------------------------------------------------------------------------------
-- File : basic_test_rx.vhd
-- Author : ege
-- Created : 2010-03-30
-- Last update: 2011-11-25
--
-- Description: Reads ASCII file where each line describes reception of 1 word.
-- Each transfers needs 4 hexadecimal parameters:
-- - 4 max delay (clock cycles) after previous
-- - expected incoming address
-- - expected incoming data value
-- - expected incoming command
-- Mismatches will be reported into stdout.
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011 1.0 ege First version
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
 
library std;
use std.textio.all;
use work.txt_util.all; -- for function sgtr(std_log_vec)
 
use work.basic_test_pkg.all; -- read_conf_file()
 
entity basic_test_rx is
 
generic (
conf_file_g : string := "";
comm_width_g : integer := 3;
data_width_g : integer := 0
);
port (
clk : in std_logic;
rst_n : in std_logic;
 
done_out : out std_logic; -- if this has finished
 
-- HIBI wrapper ports
agent_av_in : in std_logic;
agent_data_in : in std_logic_vector(data_width_g-1 downto 0);
agent_comm_in : in std_logic_vector (comm_width_g-1 downto 0);
agent_re_out : out std_logic;
agent_empty_in : in std_logic;
agent_one_d_in : in std_logic
);
 
end basic_test_rx;
 
 
architecture rtl of basic_test_rx is
 
constant allow_more_data_than_in_file_c : integer := 0;
 
type control_states is (read_conf, wait_data, rd_addr, rd_data, finish);
signal curr_state_r : control_states := read_conf;
 
signal re_r : std_logic;
signal last_addr_r : std_logic_vector (data_width_g-1 downto 0);
signal cycle_counter_r : integer;
 
signal delay_r : integer;
signal dst_addr_r : integer;
signal data_val_r : integer;
signal comm_r : integer;
 
signal n_addr_r : integer;
signal n_data_r : integer;
signal addr_correct_r : std_logic; -- 2010-10-08
signal error_r : std_logic;
 
-- Registers may be reset to 'Z' to 'X' so that reset state is clearly
-- distinguished from active state. Using dbg_level+Rst_Value array, the rst value may
-- be easily set to '0' for synthesis.
constant dbg_level : integer range 0 to 3 := 0; -- 0= no debug
constant rst_value_arr : std_logic_vector (6 downto 0) := 'X' & 'Z' & 'X' & 'Z' & 'X' & 'Z' & '0';
-- Right now gives a lot of warnings when other than 0
 
begin -- rtl
 
agent_re_out <= re_r;
 
main : process (clk, rst_n)
file conf_data_file : text open read_mode is conf_file_g;
 
-- The read values from file are stored into these
variable delay_v : integer;
variable dst_ag_v : integer;
variable data_val_v : integer;
variable cmd_v : integer;
 
begin -- process main
if rst_n = '0' then -- asynchronous reset (active low)
curr_state_r <= read_conf;
last_addr_r <= (others => rst_value_arr (dbg_level * 1));
cycle_counter_r <= 0;
re_r <= '0';
done_out <= '0';
 
n_addr_r <= 0;
n_data_r <= 0;
addr_correct_r <= '0';
error_r <= '0';
 
delay_v := 0;
dst_ag_v := 0;
data_val_v := 0;
cmd_v := 0;
 
elsif clk'event and clk = '1' then -- rising clock edge
 
case curr_state_r is
when read_conf =>
-- Read the file to see what data should arrive next
if endfile(conf_data_file) then
curr_state_r <= finish;
re_r <= '1';
addr_correct_r <= '0';
error_r <= '0';
assert false report "End of the configuration file reached" severity note;
else
read_conf_file (
delay => delay_v,
dest_agent_n => dst_ag_v,
value => data_val_v,
cmd => cmd_v,
conf_dat => conf_data_file);
 
delay_r <= delay_v;
dst_addr_r <= dst_ag_v;
data_val_r <= data_val_v;
comm_r <= cmd_v;
error_r <= '0';
re_r <= '0';
cycle_counter_r <= 0;
curr_state_r <= wait_data;
 
 
if dst_ag_v /= 0 then
addr_correct_r <= '0';
-- else keep the the old value
end if;
 
end if; -- endfile
 
when wait_data =>
 
if agent_empty_in = '0' then
if agent_av_in = '1' then
curr_state_r <= rd_addr;
else
if addr_correct_r = '1' then
curr_state_r <= rd_data;
else
error_r <= '1';
assert false report "Data received but addr could not be checked" severity warning;
curr_state_r <= read_conf;
end if;
end if;
re_r <= '1';
else
re_r <= '0';
end if;
 
-- Increment the delay counter
cycle_counter_r <= cycle_counter_r +1;
 
when rd_addr =>
 
-- Check the address
addr_correct_r <= '1'; -- default that may be overriden
 
 
if dst_addr_r = 0 then
-- Assume that addr has not changed
if agent_data_in /= last_addr_r then
addr_correct_r <= '0';
error_r <= '1';
 
--assert agent_data_in = last_addr_r
assert false
report "Addr does not match. Expected " & str(to_integer(signed(last_addr_r))) & " but got " & str(to_integer(unsigned(agent_data_in)))
severity warning;
 
end if;
 
elsif dst_addr_r /= -1 then
-- Expected addr was given in the file
 
if to_integer(unsigned(agent_data_in)) /= dst_addr_r then
addr_correct_r <= '0';
error_r <= '1';
 
--assert to_integer(unsigned(agent_data_in)) = dst_addr_r
assert false
report "Addr does not match. Expected 0d" & str(dst_addr_r) & " but got 0d" & str(to_integer(unsigned(agent_data_in)))
severity warning;
 
end if;
end if;
 
if comm_r /= -1 then
 
if to_integer(unsigned(agent_comm_in)) /= comm_r then
error_r <= '1';
-- assert to_integer(unsigned(agent_comm_in)) = comm_r
assert false
report "Comm does not match Expected 0d" & str(comm_r) & " but got 0d" & str(to_integer(unsigned(agent_comm_in)))
severity warning;
end if;
end if;
 
 
last_addr_r <= agent_data_in;
n_addr_r <= n_addr_r +1;
cycle_counter_r <= cycle_counter_r +1;
 
 
if agent_empty_in = '0' then
re_r <= '1';
curr_state_r <= rd_data;
else
re_r <= '0';
curr_state_r <= wait_data;
end if;
 
 
 
 
when rd_data =>
if agent_empty_in = '0' then
 
re_r <= '0';
n_data_r <= n_data_r +1;
curr_state_r <= read_conf;
 
-- Check
-- a) if data arrived before wait time has expired
if delay_r /= -1 then
 
if delay_r < cycle_counter_r then
error_r <= '1';
 
--assert delay_r >= cycle_counter_r
assert false
report "Data arrived too late. Expected duration " & str(delay_r) & " cycles, but it took " & str(cycle_counter_r) & " cycles."
severity warning;
end if;
end if;
 
-- b) if value is as expected
if data_val_r /= -1 then
if to_integer(signed(agent_data_in)) /= data_val_r then
error_r <= '1';
--assert to_integer(signed(agent_data_in)) = data_val_r
assert false
report "Wrong data value. Expected 0d" & str(data_val_r) & " but got 0d" & str(to_integer(unsigned(agent_data_in)))
severity warning;
end if;
end if;
 
-- c) command is as expected
 
if comm_r /= -1 then
 
if to_integer(unsigned(agent_comm_in)) /= comm_r then
error_r <= '1';
-- assert to_integer(unsigned(agent_comm_in)) = comm_r
assert false
report "Comm does not match Expected 0d" & str(comm_r) & " but got 0d" & str(to_integer(unsigned(agent_comm_in)))
severity warning;
end if;
end if;
end if;
 
when finish =>
-- Notify that we're done.
done_out <= '1';
cycle_counter_r <= 0;
delay_r <= 0;
dst_addr_r <= 0;
data_val_r <= 0;
comm_r <= 0;
re_r <= '1';
 
if allow_more_data_than_in_file_c = 1 then
-- Keep reading if some data still arrives
-- but cannot check anything
 
if agent_empty_in = '0' and re_r = '1' then
if agent_av_in = '1' then
n_addr_r <= n_addr_r +1;
last_addr_r <= agent_data_in;
else
n_data_r <= n_data_r +1;
end if;
end if;
else
-- There should not be anymore data
if agent_empty_in = '0' then
error_r <= '1';
--assert agent_empty_in = '1' report "Unexpected data arrives" severity warning;
assert false report "Unexpected data arrives" severity warning;
end if;
end if;
 
when others => null;
end case;
 
 
end if;
end process main;
 
end rtl;
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/vhd/basic_tester_tx.vhd
0,0 → 1,251
-------------------------------------------------------------------------------
-- Title : A block which sends data to HIBI ver 2 and 3
-- Project : Nocbench & Funbase
-------------------------------------------------------------------------------
-- File : basic_test_tx.vhd
-- Author : ege
-- Created : 2010-03-24
-- Last update: 2011-11-25
-- Description: Reads ASCII file where each line describes transfer of 1 word.
-- Each transfers needs 4 hexadecimal parameters:
-- - delay (clock cycles) after previous tx
-- - dst address
-- - data value
-- - command
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- April 2010 1.0 ege First version
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
use std.textio.all;
use ieee.std_logic_textio.all; -- 2010-10-06 for hread
 
use work.basic_test_pkg.all; -- read_conf_file()
 
entity basic_test_tx is
 
generic (
conf_file_g : string := "";
comm_width_g : integer := 3;
data_width_g : integer := 0
);
port (
clk : in std_logic;
rst_n : in std_logic;
 
done_out : out std_logic; -- if this has finished
 
-- HIBI wrapper ports
agent_av_out : out std_logic;
agent_data_out : out std_logic_vector(data_width_g-1 downto 0);
agent_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
agent_we_out : out std_logic;
agent_full_in : in std_logic;
agent_one_p_in : in std_logic
);
 
end basic_test_tx;
 
 
architecture rtl of basic_test_tx is
 
 
type control_states is (read_conf, wait_sending, wr_addr, wr_data, finish);
signal curr_state_r : control_states := read_conf;
 
signal delay_r : integer;
 
 
 
 
-- Registers may be reset to 'Z' to 'X' so that reset state is clearly
-- distinguished from active state. Using dbg_level+Rst_Value array, the rst value may
-- be easily set to '0' for synthesis.
constant dbg_level : integer range 0 to 3 := 0; -- 0= no debug
constant rst_value_arr : std_logic_vector (6 downto 0) := 'X' & 'Z' & 'X' & 'Z' & 'X' & 'Z' & '0';
-- Right now gives a lot of warnings when other than 0
 
begin -- rtl
 
main : process (clk, rst_n)
file conf_data_file : text open read_mode is conf_file_g;
 
variable delay_v : integer;
variable dst_ag_v : integer;
variable data_val_v : integer;
variable cmd_v : integer;
 
begin -- process main
if rst_n = '0' then -- asynchronous reset (active low)
curr_state_r <= read_conf;
agent_av_out <= '0';
agent_data_out <= (others => rst_value_arr(dbg_level*1));
agent_comm_out <= (others => rst_value_arr(dbg_level*1));
agent_we_out <= '0';
done_out <= '0';
 
delay_r <= 0; -- ES 2011-09-30
delay_v := 0;
dst_ag_v := 0;
data_val_v := 0;
cmd_v := 0;
 
elsif clk'event and clk = '1' then -- rising clock edge
 
case curr_state_r is
when read_conf =>
if agent_full_in = '0' then
-- Read next transfer from file if FIFO has space
-- and the whole file has not yet been read
if endfile(conf_data_file) then
curr_state_r <= finish;
assert false report "End of the configuration file reached" severity note;
else
read_conf_file (
delay => delay_v,
dest_agent_n => dst_ag_v,
value => data_val_v,
cmd => cmd_v,
conf_dat => conf_data_file);
 
-- report "delay = " & integer'image(delay_v) & ", dst = " & integer'image(dst_ag_v) &
-- ", value = " & integer'image(data_val_v) & ", cmd = " & integer'image(cmd_v);
-- FSM causes few empty cycles, compensate by decrementing delay_v
delay_v := delay_v -1;
 
if cmd_v = -1 then
cmd_v := 2; --use write as default
end if;
if delay_v < 1 then
if dst_ag_v = 0 then
curr_state_r <= wr_data;
else
curr_state_r <= wr_addr;
end if;
else
curr_state_r <= wait_sending;
end if; -- delay_v
end if; -- endfile
agent_av_out <= '0';
agent_data_out <= (others => rst_value_arr(dbg_level*1));
agent_comm_out <= (others => rst_value_arr(dbg_level*1));
agent_we_out <= '0';
 
delay_r <= delay_v;
 
else
-- Keep the old values
-- i.e. either the reset values or keep sending
curr_state_r <= read_conf;
end if;
 
when wait_sending =>
-- Wait for a given num of cycles before sending
-- delay_v := delay_v-1;
-- if delay_r = 0 then
delay_r <= delay_r-1;
if delay_r < 2 then
if dst_ag_v = 0 then
-- Skip the address and send data directly
curr_state_r <= wr_data;
else
curr_state_r <= wr_addr;
end if;
else
curr_state_r <= wait_sending;
end if;
 
when wr_addr =>
if agent_full_in = '0' then
-- Write the address if there is room in HIBI's tx FIFO
agent_av_out <= '1';
agent_data_out <= std_logic_vector (to_signed(dst_ag_v, data_width_g));
agent_comm_out <= std_logic_vector (to_signed(cmd_v, comm_width_g));
agent_we_out <= '1';
curr_state_r <= wr_data;
else
-- Don't start yet, wait that there is space in FIFO
agent_av_out <= '0';
agent_data_out <= (others => rst_value_arr(dbg_level*1));
agent_comm_out <= (others => rst_value_arr(dbg_level*1));
agent_we_out <= '0';
curr_state_r <= wr_addr;
end if;
 
 
 
when wr_data =>
if agent_full_in = '0' then
-- Write the requested data value if there is room in HIBI's tx FIFO
agent_av_out <= '0';
agent_data_out <= std_logic_vector (to_signed(data_val_v, data_width_g));
agent_comm_out <= std_logic_vector (to_signed(cmd_v, comm_width_g));
agent_we_out <= '1';
curr_state_r <= read_conf;
else
-- Keep the old values (=adst ddress) and stay in this state
curr_state_r <= wr_data;
end if;
 
 
when finish =>
-- Notify that we're done.
done_out <= '1';
agent_av_out <= '0';
agent_data_out <= (others => rst_value_arr(dbg_level*1));
agent_comm_out <= (others => rst_value_arr(dbg_level*1));
agent_we_out <= '0';
 
when others => null;
end case;
 
 
end if;
end process main;
 
end rtl;
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/vhd/basic_tester_pkg.vhd
0,0 → 1,132
-------------------------------------------------------------------------------
-- Title : A block which sends data to HIBI ver B.
-- Project :
-------------------------------------------------------------------------------
-- File : basic_test_tx.vhd
-- Author : ege
-- Created : 2010-03-24
-- Last update: 2011-11-25
--
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
use std.textio.all;
use ieee.std_logic_textio.all; -- 2010-10-06 for hread
 
 
package basic_test_pkg is
procedure read_conf_file (
variable delay : out integer;
variable dest_agent_n : out integer;
variable value : out integer;
variable cmd : out integer;
file conf_dat : text);
 
end basic_test_pkg;
 
package body basic_test_pkg is
 
 
-- Reads the (opened) file given. the file line structure is as follows:
-- 1st integer: delay cycles before sending
-- 2nd integer: destination addr
-- 3rd integer: data value to be sent.
-- 4th integer: HIBI command (optional)
procedure read_conf_file (
delay : out integer;
dest_agent_n : out integer;
value : out integer;
cmd : out integer;
file conf_dat : text) is
 
variable file_row : line;
variable delay_var : integer;
-- variable dest_agent_n_var : integer;
-- variable data_val_var : integer;
-- variable cmd_var : integer;
 
variable delay2_var : std_logic_vector (16-1 downto 0);
variable dest_agent_n_var : std_logic_vector (32-1 downto 0);
variable data_val_var : std_logic_vector (32-1 downto 0);
variable cmd_var : std_logic_vector (8-1 downto 0);
 
variable delay_ok : boolean := FALSE;
variable cmd_ok : boolean := FALSE;
begin -- read_conf_file
 
-- Loop until finding a line that is not a comment
while delay_ok = false and not(endfile(conf_dat)) loop
readline(conf_dat, file_row);
hread (file_row, delay2_var, delay_ok);
 
if delay_ok = FALSE then
--Reading of the delay value failed
--=> assume that this line is comment or empty, and skip other it
-- assert false report "Skipped a line" severity note;
next; -- start new loop interation
end if;
 
delay_var := to_integer(signed(delay2_var));
--assert false report "tx viive: " & integer'image (delay_var) severity note;
hread (file_row, dest_agent_n_var);
hread (file_row, data_val_var);
hread (file_row, cmd_var, cmd_ok);
if cmd_ok = FALSE then
cmd_var := x"FF";
end if;
 
-- Return the values
delay := delay_var;
dest_agent_n := to_integer( signed (dest_agent_n_var));
value := to_integer( signed (data_val_var));
cmd := to_integer( signed (cmd_var));
end loop;
 
end read_conf_file;
 
 
 
end basic_test_pkg;
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/vhd/txt_util.vhd
0,0 → 1,641
-- -------------------------------------------------------------------
-- Design:
--
-- Package for VHDL text output
--
-- Note:
-- -----
-- This package uses the VHDL 95 standard.
-- If VHDL 95 is not supported by your simulator
-- you need to comment out the file access functions.
--
-- The package provides a means to output text and
-- manipulate strings.
--
-- The basic usage is like this: >> print(s); <<
-- (where s is any string)
-- To print something which is not a string it has to be converted
-- into a string first. For this purpose the package contains
-- conversion functions called >> str(...) <<.
-- For example a std_logic_vector slv would be printed like this:
-- >> print(str(slv)); <<. To print several items on one line the
-- items have to concatenated as strings with the "&" operator eg:
-- >> print("The value of slv is "& str(slv)); <<
-- The string functions can also be used in assert statements as shown
-- in the example below:
-- >> assert DIN = "0101" <<
-- >> report "DIN = "& str(DIN)& " expected 0101 " <<
-- >> severity Error; <<
--
--
--
-- -------------------------------------------------------------------
 
-- MODIFIED by ak 22.02.2007, support for numeric std unsigned
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
 
 
package txt_util is
 
-- prints a message to the screen
procedure print(text: string);
 
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
 
-- converts std_logic into a character
function chr(sl: std_logic) return character;
 
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
 
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
 
-- converts std_logic_vector into a string (binary base)
function str(slv: unsigned) return string;
-- converts boolean into a string
function str(b: boolean) return string;
 
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
 
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
 
-- converts integer to string, using base 10
function str(int: integer) return string;
 
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
 
 
-- functions to manipulate strings
-----------------------------------
 
-- convert a character to upper case
function to_upper(c: character) return character;
 
-- convert a character to lower case
function to_lower(c: character) return character;
 
-- convert a string to upper case
function to_upper(s: string) return string;
 
-- convert a string to lower case
function to_lower(s: string) return string;
 
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
 
 
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
 
 
 
 
package body txt_util is
 
 
 
 
-- prints text to the screen
 
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
 
 
 
 
-- prints text to the screen when active
 
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
 
 
-- converts std_logic into a character
 
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
 
 
 
-- converts std_logic into a string (1 to 1)
 
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
 
 
 
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
 
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
 
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
 
function str(slv: unsigned) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
 
function str(b: boolean) return string is
 
begin
if b then
return "true";
else
return "false";
end if;
end str;
 
 
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
 
 
 
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function str(int: integer; base: integer) return string is
 
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
 
begin
 
-- bug fix for negative numbers
abs_int := abs(int);
 
num := abs_int;
 
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
 
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
 
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
 
end str;
 
 
-- convert integer to string, using base 10
function str(int: integer) return string is
 
begin
 
return str(int, 10) ;
 
end str;
 
 
 
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
 
 
 
-- functions to manipulate strings
-----------------------------------
 
 
-- convert a character to upper case
 
function to_upper(c: character) return character is
 
variable u: character;
 
begin
 
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
 
return u;
 
end to_upper;
 
 
-- convert a character to lower case
 
function to_lower(c: character) return character is
 
variable l: character;
 
begin
 
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
 
return l;
 
end to_lower;
 
 
 
-- convert a string to upper case
 
function to_upper(s: string) return string is
 
variable uppercase: string (s'range);
 
begin
 
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
 
end to_upper;
 
 
 
-- convert a string to lower case
 
function to_lower(s: string) return string is
 
variable lowercase: string (s'range);
 
begin
 
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
 
end to_lower;
 
 
 
-- functions to convert strings into other types
 
 
-- converts a character into a std_logic
 
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
 
 
-- converts a string into std_logic_vector
 
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
 
 
 
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
 
 
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
 
 
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
 
 
 
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
 
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
 
 
 
 
end txt_util;
 
 
 
 
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/tb/tb_basic_tester.vhd
0,0 → 1,363
-------------------------------------------------------------------------------
-- Title : Testbench for a hibi network
-- Project :
-------------------------------------------------------------------------------
-- File : tb_basic_tester.vhd
-- Author : ege
-- Created : 2010/03/16
-- Last update: 2011-11-25
-- Description:
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010/03/16 1.0 ES Created
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use ieee.std_logic_misc.all;
use std.textio.all;
 
--use work.txt_util.all;
use work.hibiv2_pkg.all;
 
entity tb_basic_tester is
end tb_basic_tester;
 
 
 
architecture structural of tb_basic_tester is
 
constant x_pels_c : integer := 640;
constant y_pels_c : integer := 320;
 
constant n_ag_c : integer := 3; -- number of agents (=IPs)
 
-- HIBI parameters
constant data_width_c : integer := 32; -- bits
constant addr_width_c : integer := 32; -- bits
constant counter_width_c : integer := 16; -- bits
constant id_width_c : integer := 6; -- bits
constant max_send_c : integer := 40; -- words
constant arb_type_c : integer := 0; -- 0-3
constant tx_fifo_size_c : integer := 4; -- words
constant rx_fifo_size_c : integer := 4; -- words
 
type gen_addr_array_type is array (0 to 3) of integer;
constant addresses_c : gen_addr_array_type :=
(16#00000010#, -- video_gen
16#00000030#, -- pic manipulator
16#00000050#, -- ddr
16#00000070# -- currently unused
);
 
 
-- IPs and wrappers can run on different frequencies
-- (All Ips using one clock and all wrappers unsing the other)
-- Frequencies must be integer multiple of each other.
-- Edit both period and frequencies manually and ensure consistency.
constant PERIOD_IP_C : time := 1*10 ns;
constant PERIOD_HIBI_C : time := 1*10 ns;
constant rel_agent_freq_c : integer := 1;
constant rel_bus_freq_c : integer := 1;
 
 
-- Global signals
signal clk_ip : std_logic := '1';
signal clk_noc : std_logic := '1';
signal rst_n : std_logic := '0';
 
-- Define types for arrays. Transposed versions are needed for or_reduce
-- function in bus resolution.
type data_vec_type is array (n_ag_c-1 downto 0) of std_logic_vector (data_width_c-1 downto 0);
type comm_vec_type is array (n_ag_c-1 downto 0) of std_logic_vector (comm_width_c-1 downto 0);
type trnsp_data_vec is array (data_width_c-1 downto 0) of std_logic_vector (n_ag_c-1 downto 0);
type trnsp_comm_vec is array (comm_width_c-1 downto 0) of std_logic_vector (n_ag_c-1 downto 0);
 
-- Signals going from the IPs to the wrappers.
-- Note that full and one_p actually come from wrapper but they are grouped
-- here due their purpose.
signal av_ip_wra : std_logic_vector ( n_ag_c-1 downto 0);
signal data_ip_wra : data_vec_type;
signal comm_ip_wra : comm_vec_type;
signal we_ip_wra : std_logic_vector ( n_ag_c-1 downto 0);
signal full_wra_ip : std_logic_vector ( n_ag_c-1 downto 0);
signal one_p_wra_ip : std_logic_vector ( n_ag_c-1 downto 0);
 
-- Signals going from the wrappers to the IPs.
signal av_wra_ip : std_logic_vector ( n_ag_c-1 downto 0);
signal data_wra_ip : data_vec_type;
signal comm_wra_ip : comm_vec_type;
signal re_ip_wra : std_logic_vector ( n_ag_c-1 downto 0);
signal empty_wra_ip : std_logic_vector ( n_ag_c-1 downto 0);
signal one_d_wra_ip : std_logic_vector ( n_ag_c-1 downto 0);
-- Signals going from the wrappers to the OR ports.
signal av_wra_bus : std_logic_vector ( n_ag_c-1 downto 0);
signal data_wra_bus : data_vec_type;
signal comm_wra_bus : comm_vec_type;
signal trnsp_data_out : trnsp_data_vec;
signal trnsp_comm_out : trnsp_comm_vec;
signal full_wra_bus : std_logic_vector ( n_ag_c-1 downto 0);
signal lock_wra_bus : std_logic_vector ( n_ag_c-1 downto 0);
 
-- Signals going from the OR ports to the wrappers.
signal av_bus_wra : std_logic;
signal data_bus_wra : std_logic_vector(data_width_c-1 downto 0);
signal comm_bus_wra : std_logic_vector(comm_width_c-1 downto 0);
signal full_bus_wra : std_logic;
signal lock_bus_wra : std_logic;
 
-- 2007/04/16
constant dbg_width_c : integer := 1;
signal debug_tb_wra : std_logic_vector ( dbg_width_c-1 downto 0);
 
 
-- constant arb_type_c : integer := 0;
 
 
 
begin -- structural
 
 
-- Component 0
sender: entity work.basic_test_tx
 
generic map(
conf_file_g => "test_tx.txt",
comm_width_g => 3,
data_width_g => 32
)
port map(
clk => clk_ip,
rst_n => rst_n,
-- done_out => ,
 
agent_av_out => av_ip_wra (0),
agent_data_out => data_ip_wra (0),
agent_comm_out => comm_ip_wra (0),
agent_we_out => we_ip_wra (0),
agent_full_in => full_wra_ip (0),
agent_one_p_in => one_p_wra_ip (0)
);
re_ip_wra (0) <= '0';
 
 
-- Component 1
av_ip_wra (1) <= '0';
data_ip_wra (1) <= (others => 'Z');
comm_ip_wra (1) <= (others => 'Z');
we_ip_wra (1) <= '0';
 
 
receiver: entity work.basic_test_rx
 
generic map(
conf_file_g => "test_rx.txt",
comm_width_g => 3,
data_width_g => 32
)
port map(
clk => clk_ip,
rst_n => rst_n,
-- done_out => ,
 
-- HIBI WRAPPER PORTS
agent_av_in => av_wra_ip (1),
agent_data_in => data_wra_ip (1),
agent_comm_in => comm_wra_ip (1),
agent_re_out => re_ip_wra (1),
agent_empty_in => empty_wra_ip (1),
agent_one_d_in => one_d_wra_ip (1)
);
-- Component 2
av_ip_wra (2) <= '0';
data_ip_wra (2) <= (others => 'Z');
comm_ip_wra (2) <= (others => 'Z');
we_ip_wra (2) <= '0';
 
re_ip_wra (2) <= '1';
 
hibi_net : for ag in 0 to n_ag_c-1 generate
hibi_wrapper_r4_1 : entity work.hibi_wrapper_r4
generic map (
id_g => ag+1,
base_id_g => 2**id_width_c-1,
inv_addr_en_g => 0,
-- first parameter to addresses_c is the segment,
-- second is the agents number within the segment
addr_g => addresses_c (ag),
 
id_width_g => id_width_c,
addr_width_g => addr_width_c,
data_width_g => data_width_c,
comm_width_g => 3,
counter_width_g => counter_width_c,
rx_fifo_depth_g => rx_fifo_size_c,
rx_msg_fifo_depth_g => 0, -- fifo_size_c
tx_fifo_depth_g => tx_fifo_size_c,
tx_msg_fifo_depth_g => 0, -- fifo_size_c
 
rel_agent_freq_g => rel_agent_freq_c,
rel_bus_freq_g => rel_bus_freq_c,
arb_type_g => arb_type_c, --13.4.2007
 
 
prior_g => ag +1,
max_send_g => max_send_c,
n_agents_g => n_ag_c,
 
n_cfg_pages_g => 1,
n_time_slots_g => 0,
n_extra_params_g => 1,
multicast_en_g => 0,
cfg_re_g => 0,
cfg_we_g => 1, --0,
 
debug_width_g => dbg_width_c --2007/04/16
)
port map (
agent_clk => clk_ip,
bus_clk => clk_noc,
bus_sync_clk => clk_noc,
agent_sync_clk => clk_ip,
rst_n => rst_n,
 
bus_av_in => av_bus_wra,
bus_data_in => data_bus_wra,
bus_comm_in => comm_bus_wra,
bus_full_in => full_bus_wra,
bus_lock_in => lock_bus_wra,
bus_av_out => av_wra_bus (ag),
bus_data_out => data_wra_bus (ag),
bus_comm_out => comm_wra_bus (ag),
bus_full_out => full_wra_bus (ag),
bus_lock_out => lock_wra_bus (ag),
 
agent_av_in => av_ip_wra (ag),
agent_data_in => data_ip_wra (ag),
agent_comm_in => comm_ip_wra (ag),
agent_we_in => we_ip_wra (ag),
agent_full_out => full_wra_ip (ag),
agent_one_p_out => one_p_wra_ip (ag),
 
agent_re_in => re_ip_wra (ag),
agent_av_out => av_wra_ip (ag),
agent_data_out => data_wra_ip (ag),
agent_comm_out => comm_wra_ip (ag),
agent_empty_out => empty_wra_ip (ag),
agent_one_d_out => one_d_wra_ip (ag),
 
--debug_out => dummy,
debug_in => debug_tb_wra
 
);
 
end generate hibi_net;
 
 
 
 
-- assign the bus signals. bus signals are first transposed, eg.
-- 3*32b buses -> 32*3b buses
trnsp_bus : for j in 0 to n_ag_c-1 generate
 
i : for i in 0 to data_width_c-1 generate
trnsp_data_out (i)(j) <= data_wra_bus (j)(i);
end generate i;
 
k : for k in 0 to comm_width_c-1 generate
trnsp_comm_out (k)(j) <= comm_wra_bus (j)(k);
end generate k;
end generate trnsp_bus;
 
 
 
-- here we or_reduce the transposed signals, so we get the in-signals
-- for wrappers.
or_reduce_data : for i in 0 to data_width_c-1 generate
data_bus_wra (i) <= or_reduce(trnsp_data_out (i));
end generate or_reduce_data;
 
 
chk_lock: process (lock_wra_bus)
variable n_locks_v : integer := 0;
begin -- process chk_lock
 
n_locks_v := 0;
for i in 0 to n_ag_c -1 loop
if lock_wra_bus (i) = '1' then
n_locks_v := n_locks_v +1;
end if;
end loop; -- i
 
if n_locks_v > 1 then
assert false report "Multiple drivers for lock signal!!!" severity error;
end if;
end process chk_lock;
or_reduce_comm : for i in 0 to comm_width_c-1 generate
comm_bus_wra(i) <= or_reduce(trnsp_comm_out(i));
end generate or_reduce_comm;
 
 
or_reduce_rest : for i in 0 to comm_width_c-1 generate
av_bus_wra <= or_reduce(av_wra_bus);
lock_bus_wra <= or_reduce(lock_wra_bus);
full_bus_wra <= or_reduce(full_wra_bus);
end generate or_reduce_rest;
 
clk_ip <= not clk_ip after PERIOD_IP_C/2;
clk_noc <= not clk_noc after PERIOD_HIBI_C/2;
rst_n <= '0', '1' after 4.6 * PERIOD_HIBI_C;
 
 
end structural;
 
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/sim/cfg_env.sh
0,0 → 1,3
echo 'Initialize VHDL simulator. Assumes bash shell'
 
source /share/tktprog/mentor/modeltech-6.5c/modeltech.sh
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/sim/test_rx.txt
0,0 → 1,29
# This is an input file for basci tester's tx unit
# Comments start with #
# Each line has 3 or 4 integer values:
# delay_in_cycles addr data cmd(optional)
# The values are in hexadecimal format
 
# Unlike in tx side, here one can define
# don't care values. Setting any value to
# 0xF...F (=-1 in decimal) will be interpreted as don't care.
# The receiver checks that something arrives but not its
# contents.
# Moreover, comm (last param) can simply be omitted
# and then no checking is done.
 
0025 00000030 00000100 02
0050 00000031 00000101 02
0012 00000032 00000102 03
# There can be empty lines as shown below
 
# Address 0...0 means that it must not change from previous transfer
0005 00000000 00000103 03
 
# Values can be separated with tabs as shown below.
# Note the omission of the command (same as 0xFF)
0005 00000000 00000104
 
# This is intentional error with data value
# so that you can see how errors are reported in simulation
0005 00000000 0000BABE FF
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/sim/test_tx.txt
0,0 → 1,25
# This is an input file for basci tester's tx unit
# Comments start with #
# Each line has 3 or 4 integer values:
# delay_in_cycles addr data cmd(optional)
# The values are in hexadecimal format
 
000A 00000030 00000100 02
0005 00000031 00000101 02
0008 00000032 00000102 03
 
# There can be empty lines as shown below
 
# addr=0 means that no new addr will be sent
 
0005 00000000 00000103 03 # comment can be at the end of the line
 
# Values can be separated with tabs as shown below
# Moreover, comm (last param) can be omitted and then the default
# write command will be used
 
0001 00000000 00000104
 
# There will be at least 1 cycle delay even if a delay of 0 is specified
 
0000 00000000 00000105
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/sim/create_makefile.sh
0,0 → 1,95
#!/bin/sh
#
# Skripti kaantaa kaikki vhdl-tiedostot ja tekee niista makefilen
# Ymparistomuuttjat
# TMP_DIR kertoo mihin hakemistoon kaannetyt fiilut laitetaan.
#
 
clear
 
if test -z $TMP_DIR
then
echo "Env variable TMP_DIR, which defines the location of Modelsim's work dir, is not set"
echo "->Exit"
exit
fi
 
mkdir $TMP_DIR
 
#Poistetaan vanha codelib ja tehdaan ja mapataan uusi
echo "Removing old vhdl library "
rm -rf $TMP_DIR/codelib
rm -rf $TMP_DIR/st
 
 
echo; echo "Creating a new library at"
echo $TMP_DIR; echo
 
vlib $TMP_DIR/codelib
vmap work $TMP_DIR/codelib
 
# vlib $TMP_DIR/st
# vmap st $TMP_DIR/st
 
 
# ST:n kirjastokomponenttien simulointimallit
# echo 'Compliling ST synthesis libraries'
# vcom -quiet -work st /export/prog/IC/st/hcmos9/HCMOS9SIGE_8.0/CORE9GPLL_SNPS_AVT_4.1_1.1/VHDL_FUNCT/CORE9GPLL_COMPONENTS.vhd
# vcom -quiet -work st /export/prog/IC/st/hcmos9/HCMOS9SIGE_8.0/CORE9GPLL_SNPS_AVT_4.1_1.1/VHDL_FUNCT/CORE9GPLL_VHDL_FUNCT.vhd
 
#vcom -quiet -work st /export/prog/IC/st/hcmos9/HCMOS9SIGE_8.0/CORE9GPLL_SNPS_AVT_4.1_1.1/VHDL_FUNCT/CORE9GPLL_COMPONENTS.vhd
#vcom -quiet -work st /export/prog/IC/st/hcmos9/HCMOS9SIGE_8.0/CORE9GPLL_SNPS_AVT_4.1_1.1/VHDL_FUNCT/CORE9GPLL_VHDL_FUNCT.vhd
 
 
 
echo; echo "Compiling vhdl codes"; echo
 
echo; echo "Compiling HIBI"; echo
 
HIBI_DIR="../../hibi/vhd"
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/hibiv2_pkg.vhd
 
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/addr_decoder.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/addr_data_demuxes.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/addr_data_muxes.vhd
 
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/cfg_init_pkg.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/cfg_mem.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/copy_of_multiclk_fifo.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/dyn_arb.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/lfsr.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/fifo.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/double_fifo_demux_wr.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/double_fifo_mux_rd.vhd
 
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/rx_ctrl.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/tx_ctrl.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/receiver.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/transmitter.vhd
 
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/hibi_wrapper_r1.vhd
vcom -quiet -check_synthesis -pedanticerrors $HIBI_DIR/hibi_wrapper_r4.vhd
 
echo
echo "Compile basic tester component"
TESTER_DIR="../vhd"
vcom -quiet -check_synthesis -pedanticerrors $TESTER_DIR/txt_util.vhd
vcom -quiet -check_synthesis -pedanticerrors $TESTER_DIR/basic_tester_pkg.vhd
vcom -quiet -check_synthesis -pedanticerrors $TESTER_DIR/basic_tester_rx.vhd
vcom -quiet -check_synthesis -pedanticerrors $TESTER_DIR/basic_tester_tx.vhd
 
 
 
# Testipenkki
echo; echo "Compiling vhdl testbenches";echo
vcom -quiet ../tb/tb_basic_tester.vhd
 
 
echo;echo "Creating a new makefile"
rm -f makefile.vhd
vmake $TMP_DIR/codelib > makefile.vhd
 
echo " --------Create_Makefile done------------- "
 
 
 
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/sim/tb_basic_tester.do
0,0 → 1,82
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_basic_tester/clk_ip
add wave -noupdate -format Logic /tb_basic_tester/clk_noc
add wave -noupdate -format Logic /tb_basic_tester/rst_n
add wave -noupdate -format Literal -expand /tb_basic_tester/av_ip_wra
add wave -noupdate -format Literal -radix decimal -expand /tb_basic_tester/data_ip_wra
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/comm_ip_wra
add wave -noupdate -format Literal /tb_basic_tester/we_ip_wra
add wave -noupdate -format Literal /tb_basic_tester/full_wra_ip
add wave -noupdate -format Literal /tb_basic_tester/one_p_wra_ip
add wave -noupdate -format Literal /tb_basic_tester/av_wra_ip
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/data_wra_ip
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/comm_wra_ip
add wave -noupdate -format Literal /tb_basic_tester/re_ip_wra
add wave -noupdate -format Literal /tb_basic_tester/empty_wra_ip
add wave -noupdate -format Literal /tb_basic_tester/one_d_wra_ip
add wave -noupdate -format Literal /tb_basic_tester/av_wra_bus
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/data_wra_bus
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/comm_wra_bus
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/trnsp_data_out
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/trnsp_comm_out
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/full_wra_bus
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/lock_wra_bus
add wave -noupdate -format Logic /tb_basic_tester/av_bus_wra
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/data_bus_wra
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/comm_bus_wra
add wave -noupdate -format Logic /tb_basic_tester/full_bus_wra
add wave -noupdate -format Logic /tb_basic_tester/lock_bus_wra
add wave -noupdate -format Literal /tb_basic_tester/debug_tb_wra
add wave -noupdate -divider sender
add wave -noupdate -format Literal /tb_basic_tester/sender/conf_file_g
add wave -noupdate -format Literal /tb_basic_tester/sender/comm_width_g
add wave -noupdate -format Literal /tb_basic_tester/sender/data_width_g
add wave -noupdate -format Logic /tb_basic_tester/sender/clk
add wave -noupdate -format Logic /tb_basic_tester/sender/done_out
add wave -noupdate -format Literal /tb_basic_tester/sender/curr_state_r
add wave -noupdate -format Literal /tb_basic_tester/sender/delay_r
add wave -noupdate -format Logic /tb_basic_tester/sender/agent_av_out
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/sender/agent_data_out
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/sender/agent_comm_out
add wave -noupdate -format Logic /tb_basic_tester/sender/agent_we_out
add wave -noupdate -format Logic /tb_basic_tester/sender/agent_full_in
add wave -noupdate -format Logic /tb_basic_tester/sender/agent_one_p_in
add wave -noupdate -divider receiver
add wave -noupdate -format Literal /tb_basic_tester/receiver/conf_file_g
add wave -noupdate -format Literal /tb_basic_tester/receiver/comm_width_g
add wave -noupdate -format Literal /tb_basic_tester/receiver/data_width_g
add wave -noupdate -format Logic /tb_basic_tester/receiver/clk
add wave -noupdate -format Logic /tb_basic_tester/receiver/done_out
add wave -noupdate -format Logic /tb_basic_tester/receiver/agent_av_in
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/receiver/agent_data_in
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/receiver/agent_comm_in
add wave -noupdate -format Logic /tb_basic_tester/receiver/agent_empty_in
add wave -noupdate -format Logic /tb_basic_tester/receiver/agent_one_d_in
add wave -noupdate -format Logic /tb_basic_tester/receiver/agent_re_out
add wave -noupdate -format Literal /tb_basic_tester/receiver/curr_state_r
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/receiver/last_addr_r
add wave -noupdate -format Literal /tb_basic_tester/receiver/cycle_counter_r
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/receiver/delay_r
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/receiver/dst_addr_r
add wave -noupdate -format Literal -radix unsigned /tb_basic_tester/receiver/data_val_r
add wave -noupdate -format Literal -radix decimal /tb_basic_tester/receiver/comm_r
add wave -noupdate -format Logic /tb_basic_tester/receiver/addr_correct_r
add wave -noupdate -format Literal /tb_basic_tester/receiver/n_addr_r
add wave -noupdate -format Literal /tb_basic_tester/receiver/n_data_r
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {509 ns} 0}
configure wave -namecolwidth 332
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ns} {578 ns}
/funbase_ip_library/trunk/TUT/ip.hwp.communication/basic_tester/readme.txt
0,0 → 1,109
-----------------------
Basic tester component
-----------------------
 
Purpose: Send and receive simple test data to/from HIBI.
It is easy to create basic tests for new HIBI-compliant IP component,
e.g. writing and reading a couple registers.
 
Structure:
Two components: tx and rx, both using the same
pkg that defines procedure for reading traffic file.
 
Example testbench instantiates tx, rx, and two HIBI (r4) wrappers.
 
 
file --> basic_tester_tx --> hibi2_r4
|
|
v
file --> basic_tester_rx <-- hibi2_r4
|
|
V
"Error msg if something went wrong"
 
 
Usage:
Go to directory sim.
 
Define env variable TMP_DIR
so that it points to some temporary dir where the compiled
stuff will be located, e.g. $PWD or /tmp/<username> or similar.
Create VHDL work lib and compile all files by executing:
./create_makefile
 
Start simulation:
vsim tb_basic_tester -novopt -do tb_basic_tester.do
 
Traffic examples take only about 600 ns to execute.
There will be 3 messagtes after statup
1) tx reaches the end of its config file
2) rx detects the intentional data corruption for the last data word
3) rx reaches the end of its config file
 
In addition to violated assertions, rx unit will have internal
signal "error_r" that will go upon an error condition.
However, this might get optimized away if you don't use
the flag "-novopt".
 
Configuration:
Traffic is configured with ASCII text files that are
located into same directory where ModelSim is launched
("sim" in this case). They look pretty much the same
for both tx and rx.
 
There is one line for each transfer.
 
Files can have comments (#) and empty lines
 
Each transfer has up to 4 parameter:
delay_in_cycles dst_addr data_value command
 
Parameters are separated with space or tab.
Delay is 4 hexadecimal characters, addr and data 8 char each,
and command 2 hex characters. Read procedure will
discard the line if it cannot interpret the line, e.g. if
there is only "5" and not "0005" for the delay.
 
Command can be omitted and then default write will be used.
 
Address 0...0 means that tx does not send a new address,
whereas rx assumes that addr does not change:
a) it receives the same addr as on prev transfers,
b) or it does not receive addr at all but new data.
 
Value F..F on rx side means that rx don't care about
that value. However, it still checks the other parameters.
E.g. any incoming addr will match but the data will be checked.
 
 
Checked cases in rx:
 
Next transfer arrives within "delay" clock cycles" after reading the conf file.
Addr matches the specified value
Addr does not change
Data matches
Command matches
Some combination of addr/data/cmd matches
If more data arrives than expected
 
 
Testing your own IP
For example, send few commands with basic_tester_tx
and configure rx according to expected responses.
file --> basic_tester_tx --> hibi2_r4
file --> basic_tester_rx <-- wrapper
^
|
v
hibi2_r4 --> your IP
wrapper <-- is here |
 
 
---
 
Erno Salminen, TUT
2010-10-08

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