OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 66 to Rev 67
    ↔ Reverse comparison
  •

Rev 66 → Rev 67

/trunk/rtl/verilog/pci_tpram.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.4 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
103,13 → 106,11
`ifdef PCI_BIST
,
// debug chain signals
trst,
SO,
SI,
shift_DR,
capture_DR,
extest,
tck
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_sen // bist scan shift enable
`endif
);
 
141,13 → 142,11
 
`ifdef PCI_BIST
// debug chain signals
input trst ;
output SO ;
input SI ;
input shift_DR ;
input capture_DR ;
input extest ;
input tck ;
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_sen; // bist scan shift enable
`endif
 
//
172,16 → 171,12
.WEN (!we_a)
`ifdef PCI_BIST
,
// reset
.trst (trst),
 
// debug chain signals
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
 
/trunk/rtl/verilog/pci_bridge32.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.4 2002/10/08 17:17:05 mihad
// Added BIST signals for RAMs.
//
166,13 → 169,11
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
capture_DR ,
extest ,
tck
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_sen // bist scan shift enable
`endif
);
 
274,13 → 275,11
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
input capture_DR ;
input extest ;
input tck ;
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_sen; // bist scan shift enable
 
// internal wires for serial chain connection
wire SO_internal ;
800,13 → 799,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO_internal),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
 
984,13 → 981,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI_internal),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
 
/trunk/rtl/verilog/wbw_wbr_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.6 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
100,13 → 103,11
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
capture_DR ,
extest ,
tck
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_sen // bist scan shift enable
`endif
) ;
 
212,13 → 213,11
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
input capture_DR ;
input extest ;
input tck ;
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_sen; // bist scan shift enable
`endif
 
/*-----------------------------------------------------------------------------------------------------------
334,8 → 333,8
wire wbr_read_enable = 1'b1 ;
 
`ifdef PCI_BIST
wire SO_internal ; // wires for connection of debug ports on two rams
wire SI_internal = SO_internal ;
wire scanb_so_internal ; // wires for connection of debug ports on two rams
wire scanb_si_internal = scanb_so_internal ;
`endif
 
// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
362,13 → 361,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO_internal),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so_internal),
.scanb_sen (scanb_sen)
`endif
);
 
395,13 → 392,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI_internal),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si_internal),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
 
460,13 → 455,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
 
/trunk/rtl/verilog/top.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.5 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
121,13 → 124,11
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
capture_DR ,
extest ,
tck
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_sen // bist scan shift enable
`endif
);
 
185,14 → 186,11
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
input capture_DR ;
input extest ;
input tck ;
 
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_sen; // bist scan shift enable
`endif
 
wire [31:0] AD_out ;
347,13 → 345,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
/trunk/rtl/verilog/pciw_pcir_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.7 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
108,13 → 111,11
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
capture_DR ,
extest ,
tck
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_sen // bist scan shift enable
`endif
) ;
 
230,13 → 231,11
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
input capture_DR ;
input extest ;
input tck ;
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_sen; // bist scan shift enable
`endif
 
/*-----------------------------------------------------------------------------------------------------------
360,8 → 359,8
wire pcir_read_enable = 1'b1 ;
 
`ifdef PCI_BIST
wire SO_internal ; // wires for connection of debug ports on two rams
wire SI_internal = SO_internal ;
wire scanb_so_internal ; // wires for connection of debug ports on two rams
wire scanb_si_internal = scanb_so_internal ;
`endif
 
// instantiate and connect two generic rams - one for pci write fifo and one for pci read fifo
388,13 → 387,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO_internal),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so_internal),
.scanb_sen (scanb_sen)
`endif
);
 
421,13 → 418,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI_internal),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si_internal),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
 
486,13 → 481,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
 
/trunk/rtl/verilog/wb_tpram.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.4 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
103,13 → 106,11
`ifdef PCI_BIST
,
// debug chain signals
trst,
SO,
SI,
shift_DR,
capture_DR,
extest,
tck
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_sen // bist scan shift enable
`endif
);
 
141,13 → 142,11
 
`ifdef PCI_BIST
// debug chain signals
input trst ;
output SO ;
input SI ;
input shift_DR ;
input capture_DR ;
input extest ;
input tck ;
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_sen; // bist scan shift enable
`endif
 
//
172,16 → 171,12
.WEN (!we_a)
`ifdef PCI_BIST
,
// reset
.trst (trst),
 
// debug chain signals
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
);
/trunk/rtl/verilog/pci_target_unit.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.7 2002/10/08 17:17:05 mihad
// Added BIST signals for RAMs.
//
163,13 → 166,11
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
capture_DR ,
extest ,
tck
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_sen // bist scan shift enable
`endif
);
 
272,13 → 273,11
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
input capture_DR ;
input extest ;
input tck ;
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_sen; // bist scan shift enable
`endif
 
 
561,13 → 560,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
) ;
 
/trunk/rtl/verilog/wb_slave_unit.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.5 2002/10/08 17:17:06 mihad
// Added BIST signals for RAMs.
//
156,13 → 159,11
`ifdef PCI_BIST
,
// debug chain signals
trst ,
SO ,
SI ,
shift_DR ,
capture_DR ,
extest ,
tck
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_sen // bist scan shift enable
`endif
);
 
269,13 → 270,11
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input trst ;
output SO ;
input SI ;
input shift_DR ;
input capture_DR ;
input extest ;
input tck ;
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_sen; // bist scan shift enable
`endif
 
// pci master interface outputs
579,13 → 578,11
 
`ifdef PCI_BIST
,
.trst (trst),
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR (capture_DR),
.extest (extest),
.tck (tck)
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_sen (scanb_sen)
`endif
) ;
 

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