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URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 67 to Rev 68
    ↔ Reverse comparison
  •

Rev 67 → Rev 68

/trunk/or1ksim/cpu/or32/execute.c
50,6 → 50,9
int nop_period = 0;
int nop_maxperiod = 0;
 
/* freemem 'pointer' */
extern unsigned long freemem;
 
/* Completition queue */
struct icomplet_entry icomplet[20];
 
245,7 → 248,7
char *regstr;
unsigned int memaddr;
disp = atoi(operand); /* operand == "nn(rXX)" */
disp = strtol(operand, NULL, 0); /* operand == "nn(rXX)" */
debug("eval_operand: disp=%u", disp);
regstr = strstr(operand, "(r") + 1; /* regstr == "rXX)" */
*strstr(regstr, ")") = '\0'; /* regstr == "rXX" */
287,7 → 290,7
char *regstr;
unsigned int memaddr;
disp = atoi(operand); /* operand == "nn(rXX)" */
disp = strtol(operand, NULL, 0); /* operand == "nn(rXX)" */
regstr = strstr(operand, "(r") + 1; /* regstr == "rXX)" */
*strstr(regstr, ")") = '\0'; /* regstr == "rXX" */
memaddr = eval_reg(regstr) + disp;
552,8 → 555,8
} else
if (CURINSN("l.rfe")) {
cur->func_unit = exception;
pctemp = eval_operand(cur->op1) & ~0x3;
mtspr(SPR_SR, (mfspr(SPR_SR) & ~0x3) | (eval_operand(cur->op1) & 0x3));
pctemp = mfspr(SPR_EPCR_BASE);
mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
} else
if (CURINSN("l.nop")) {
cur->func_unit = nop;
625,7 → 628,7
cur->dependsrc2 = cur->op1;
cur->dependdst = ccr_flag;
flag = eval_operand(cur->op1) == eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sfne") || CURINSN("l.sfnei")) {
cur->func_unit = compare;
632,7 → 635,7
cur->dependsrc2 = cur->op1;
cur->dependdst = ccr_flag;
flag = eval_operand(cur->op1) != eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sfgts") || CURINSN("l.sfgtsi")) {
cur->func_unit = compare;
640,7 → 643,7
cur->dependdst = ccr_flag;
flag = (signed)eval_operand(cur->op1) >
(signed)eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sfges") || CURINSN("l.sfgesi")) {
cur->func_unit = compare;
648,7 → 651,7
cur->dependdst = ccr_flag;
flag = (signed)eval_operand(cur->op1) >=
(signed)eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sflts") || CURINSN("l.sfltsi")) {
cur->func_unit = compare;
656,7 → 659,7
cur->dependdst = ccr_flag;
flag = (signed)eval_operand(cur->op1) <
(signed)eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sfles") || CURINSN("l.sflesi")) {
cur->func_unit = compare;
664,7 → 667,7
cur->dependdst = ccr_flag;
flag = (signed)eval_operand(cur->op1) <=
(signed)eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sfgtu") || CURINSN("l.sfgtui")) {
cur->func_unit = compare;
672,7 → 675,7
cur->dependdst = ccr_flag;
flag = (unsigned)eval_operand(cur->op1) >
(unsigned)eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sfgeu") || CURINSN("l.sfgeui")) {
cur->func_unit = compare;
680,7 → 683,7
cur->dependdst = ccr_flag;
flag = (unsigned)eval_operand(cur->op1) >=
(unsigned) eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sfltu") || CURINSN("l.sfltui")) {
cur->func_unit = compare;
688,7 → 691,7
cur->dependdst = ccr_flag;
flag = (unsigned)eval_operand(cur->op1) <
(unsigned)eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.sfleu") || CURINSN("l.sfleui")) {
cur->func_unit = compare;
696,19 → 699,26
cur->dependdst = ccr_flag;
flag = (unsigned)eval_operand(cur->op1) <=
(unsigned)eval_operand(cur->op2);
mtspr(SPR_CCR, mfspr(SPR_CCR) & ~SPR_CCR_FLAG | flag);
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag);
} else
if (CURINSN("l.mtsr")) {
cur->func_unit = move;
if (mfspr(SPR_SR) & SPR_SR_SUPV)
mtspr(eval_operand(cur->op1), eval_operand(cur->op2));
else {
printf("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
cont_run = 0;
}
} else
if (CURINSN("l.mfsr")) {
cur->func_unit = move;
if (mfspr(SPR_SR) & SPR_SR_SUPV)
set_operand(cur->op1, mfspr(eval_operand(cur->op2)));
else
else {
set_operand(cur->op1, 0);
printf("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
cont_run = 0;
}
} else
if (CURINSN("simrdtsc")) { /* obsolete */
set_operand(cur->op1, cycles + loadcycles + storecycles);
734,6 → 744,22
case 203:
printf("syscall exit(%d)\n", eval_operand("r3"));
cont_run = 0;
break;
case 204: {
unsigned long startaddr;
unsigned long endaddr;
/* if ((startaddr = eval_mem32(eval_reg("r4"))) == -1)
startaddr = (freemem & ~(PAGE_SIZE)) + PAGE_SIZE; */
startaddr = 0x80000000;
printf("sys 204: startaddr=%x virtphy=%x\n", startaddr, eval_reg("r5"));
fflush(stdout);
endaddr = loadcode(simgetstr(stackaddr, eval_reg("r3")), startaddr, eval_reg("r5"));
set_reg32("r3", endaddr);
/* setsim_mem32(eval_reg("r4"), startaddr);
setsim_mem32(eval_reg("r5"), endaddr);*/
break;
}
default:
}
}

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