URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 67 to Rev 68
- ↔ Reverse comparison
Rev 67 → Rev 68
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
0,0 → 1,65
-- |
-- Title: Testbed for SD-Core |
-- File: TbdSd-Rtl-ea.vhdl |
-- Author: Rainer Kastl |
-- Standard: VHDL'93 |
-- |
-- Description: |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.Ics307Values.all; |
|
entity TbdSd is |
|
port ( |
iClk : std_ulogic; |
inResetAsync : std_ulogic; |
|
-- SD Card |
ioCmd : inout std_logic; -- Cmd line to and from card |
oSclk : out std_ulogic; |
ioData : inout std_logic_vector(3 downto 0); |
|
-- Ics307 |
oIcs307Sclk : out std_ulogic; |
oIcs307Data : out std_ulogic; |
oIcs307Strobe : out std_ulogic |
); |
|
end entity TbdSd; |
|
architecture Rtl of TbdSd is |
begin |
|
SDTop_inst : entity work.SdTop(Rtl) |
port map ( |
iClk => iClk, |
inResetAsync => inResetAsync, |
ioCmd => ioCmd, |
oSclk => oSclk, |
ioData => ioData |
); |
|
-- Configure clock to 25MHz, it could be configured differently! |
Ics307Configurator_inst : entity work.Ics307Configurator(Rtl) |
generic map( |
gCrystalLoadCapacitance_C => cCrystalLoadCapacitance_C_25MHz, |
gReferenceDivider_RDW => cReferenceDivider_RDW_25MHz, |
gVcoDividerWord_VDW => cVcoDividerWord_VDW_25MHz, |
gOutputDivide_S => cOutputDivide_S_25MHz, |
gClkFunctionSelect_R => cClkFunctionSelect_R_25MHz, |
gOutputDutyCycleVoltage_TTL => cOutputDutyCycleVoltage_TTL_25MHz |
) |
port map( |
iClk => iClk, |
inResetAsync => inResetAsync, |
oSclk => oIcs307Sclk, |
oData => oIcs307Data, |
oStrobe => oIcs307Strobe |
); |
|
end architecture Rtl; |
|
/sdhc-sc-core/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl
18,7 → 18,7
|
-- SD Card |
ioCmd : inout std_logic; -- Cmd line to and from card |
oClk : out std_ulogic; |
oSclk : out std_ulogic; |
ioData : inout std_logic_vector(3 downto 0) |
); |
end entity SdTop; |
30,7 → 30,7
|
begin |
ioData <= "ZZZZ"; |
oClk <= iClk; |
oSclk <= iClk; |
|
SdController_inst: entity work.SdController(Rtl) |
port map (iClk => iClk, |
/sdhc-sc-core/trunk/src/grpComponents/pkgIcs307Values/src/Ics307Values-p.vhdl
0,0 → 1,30
-- |
-- Title: Constants for Ics307Configurator |
-- File: Ics307Values-p.vhdl |
-- Author: Rainer Kastl |
-- Standard: VHDL'93 |
-- |
-- Description: |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
package Ics307Values is |
cCrystalLoadCapacitance_C_48MHz : std_ulogic_vector(1 downto 0) := "00"; |
cReferenceDivider_RDW_48MHz : std_ulogic_vector(6 downto 0) := "0000011"; |
cVcoDividerWord_VDW_48MHz : std_ulogic_vector(8 downto 0) := "000010000"; |
cOutputDutyCycleVoltage_TTL_48MHz : std_ulogic := '1'; |
cClkFunctionSelect_R_48MHz : std_ulogic_vector(1 downto 0) := "00"; |
cOutputDivide_S_48MHz : std_ulogic_vector(2 downto 0) := "100"; |
|
cCrystalLoadCapacitance_C_25MHz : std_ulogic_vector(1 downto 0) := "00"; |
cOutputDutyCycleVoltage_TTL_25MHz : std_ulogic := '1'; |
cClkFunctionSelect_R_25MHz : std_ulogic_vector(1 downto 0) := "00"; |
cOutputDivide_S_25MHz : std_ulogic_vector(2 downto 0) := "000"; |
cVcoDividerWord_VDW_25MHz : std_ulogic_vector(8 downto 0) := "000000111"; |
cReferenceDivider_RDW_25MHz : std_ulogic_vector(6 downto 0) := "0000001"; |
end package Ics307Values; |
|
|