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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 671 → Rev 672

/trunk/or1ksim/sim-config.h
24,14 → 24,17
 
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
 
#define MAX_UARTS 4 /* Max. number of UARTs simulated */
#define MAX_DMAS 4 /* Max. number of DMA controllers */
#define MAX_ETHERNETS 4 /* Max. number of Ethernet MACs */
#define MAX_GPIOS 4 /* Max. number of GPIO modules */
#define MAX_MEMORIES 16 /* Max. number of memory devices attached */
#define MAX_VGAS 4 /* Max. number of VGAs */
#define MAX_SBUF_LEN 256 /* Max. length of store buffer */
#define MAX_UARTS 4 /* Max. number of UARTs simulated */
#define MAX_DMAS 4 /* Max. number of DMA controllers */
#define MAX_ETHERNETS 4 /* Max. number of Ethernet MACs */
#define MAX_GPIOS 4 /* Max. number of GPIO modules */
#define MAX_MEMORIES 16 /* Max. number of memory devices attached */
#define MAX_VGAS 4 /* Max. number of VGAs */
#define MAX_SBUF_LEN 256 /* Max. length of store buffer */
 
#define EXE_LOG_HARDWARE 0 /* Print out RTL states */
#define EXE_LOG_SOFTWARE 1 /* Executed log prints out dissasembly */
 
#define STR_SIZE (256)
 
struct config {
168,104 → 171,108
} dc;
struct {
int enabled; /* branch prediction buffer analysis */
int sbp_bnf_fwd; /* Static branch prediction for l.bnf uses forward prediction */
int sbp_bf_fwd; /* Static branch prediction for l.bf uses forward prediction */
int btic; /* branch prediction target insn cache analysis */
int missdelay; /* How much cycles does the miss cost */
int hitdelay; /* How much cycles does the hit cost */
#if 0
int nways; /* Number of BP ways */
int nsets; /* Number of BP sets */
int blocksize; /* BP entry size */
int ustates; /* number of BP usage states */
int pstates; /* number of BP predict states */
#endif
} bpb;
 
struct {
unsigned long upr; /* Unit present register */
unsigned long ver, rev; /* Version register */
int sr; /* Supervision register */
int superscalar; /* superscalara analysis */
int hazards; /* dependency hazards analysis */
int dependstats; /* dependency statistics */
int raw_range; /* raw register usage over time stats; range in cycles, 0 = disabled */
int sbuf_len; /* length of store buffer, zero if disabled */
} cpu;
struct {
int debug; /* Simulator debugging */
int verbose; /* Force verbose output */
 
int profile; /* Is profiler running */
int profile_mode; /* Profiler operating mode */
char prof_fn[STR_SIZE]; /* Profiler filename */
int mprofile; /* Is memory profiler running */
int mprofile_mode; /* Memory profiler operating mode */
int mprofile_group; /* Grouping for memory profiler */
char mprof_fn[STR_SIZE];/* Memory profiler filename */
 
int history; /* instruction stream history analysis */
int exe_log; /* Print out RTL states? */
char exe_log_fn[STR_SIZE]; /* RTL state comparison filename */
int spr_log; /* Print out SPR states */
char spr_log_fn[STR_SIZE]; /* SPR state log filename */
long clkcycle_ps; /* Clock duration in ps */
int enabled; /* branch prediction buffer analysis */
int sbp_bnf_fwd; /* Static branch prediction for l.bnf uses forward prediction */
int sbp_bf_fwd; /* Static branch prediction for l.bf uses forward prediction */
int btic; /* branch prediction target insn cache analysis */
int missdelay; /* How much cycles does the miss cost */
int hitdelay; /* How much cycles does the hit cost */
#if 0
int nways; /* Number of BP ways */
int nsets; /* Number of BP sets */
int blocksize; /* BP entry size */
int ustates; /* number of BP usage states */
int pstates; /* number of BP predict states */
#endif
} bpb;
struct {
unsigned long upr; /* Unit present register */
unsigned long ver, rev; /* Version register */
int sr; /* Supervision register */
int superscalar; /* superscalara analysis */
int hazards; /* dependency hazards analysis */
int dependstats; /* dependency statistics */
int raw_range; /* raw register usage over time stats; range in cycles, 0 = disabled */
int sbuf_len; /* length of store buffer, zero if disabled */
} cpu;
struct {
int debug; /* Simulator debugging */
int verbose; /* Force verbose output */
int profile; /* Is profiler running */
int profile_mode; /* Profiler operating mode */
char prof_fn[STR_SIZE]; /* Profiler filename */
int mprofile; /* Is memory profiler running */
int mprofile_mode; /* Memory profiler operating mode */
int mprofile_group; /* Grouping for memory profiler */
char mprof_fn[STR_SIZE]; /* Memory profiler filename */
int history; /* instruction stream history analysis */
int exe_log; /* Print out RTL states? */
int exe_log_type; /* Type of log */
int exe_log_start; /* First instruction to log */
int exe_log_end; /* Last instruction to log, -1 if continuous */
int exe_log_marker; /* If nonzero, place markers before each exe_log_marker instructions */
char exe_log_fn[STR_SIZE]; /* RTL state comparison filename */
int spr_log; /* Print out SPR states */
char spr_log_fn[STR_SIZE]; /* SPR state log filename */
long clkcycle_ps; /* Clock duration in ps */
} sim;
struct {
int enabled; /* Whether is debug module enabled */
int gdb_enabled; /* Whether is debugging with gdb possible */
int server_port; /* A user specified port number for services */
unsigned long vapi_id; /* "Fake" vapi device id for JTAG proxy */
} debug;
struct { /* Verification API, part of Advanced Core Verification */
int enabled; /* Whether is VAPI module enabled */
int server_port; /* A user specified port number for services */
int log_enabled; /* Whether to log the vapi requests */
int hide_device_id; /* Whether to log device ID for each request */
char vapi_fn[STR_SIZE]; /* vapi log filename */
} vapi;
struct {
int enabled; /* Whether power menagement is operational */
} pm;
};
struct runtime {
struct {
FILE *fprof; /* Profiler file */
FILE *fmprof; /* Memory profiler file */
FILE *fexe_log; /* RTL state comparison file */
FILE *fspr_log; /* SPR state log file */
int init; /* Whether we are still initilizing sim */
int script_file_specified; /* Whether script file was already loaded */
char *filename; /* Original Command Simulator file (CZ) */
int output_cfg; /* Whether sim is to output cfg files */
char script_fn[STR_SIZE]; /* Script file read */
int iprompt; /* Interactive prompt */
} sim;
 
struct {
int enabled; /* Whether is debug module enabled */
int gdb_enabled; /* Whether is debugging with gdb possible */
int server_port; /* A user specified port number for services */
unsigned long vapi_id; /* "Fake" vapi device id for JTAG proxy */
} debug;
 
struct { /* Verification API, part of Advanced Core Verification */
int enabled; /* Whether is VAPI module enabled */
int server_port; /* A user specified port number for services */
int log_enabled; /* Whether to log the vapi requests */
int hide_device_id; /* Whether to log device ID for each request */
char vapi_fn[STR_SIZE]; /* vapi log filename */
} vapi;
struct {
int enabled; /* Whether power menagement is operational */
} pm;
};
 
struct runtime {
struct {
FILE *fprof; /* Profiler file */
FILE *fmprof; /* Memory profiler file */
FILE *fexe_log; /* RTL state comparison file */
FILE *fspr_log; /* SPR state log file */
int init; /* Whether we are still initilizing sim */
int script_file_specified;/* Whether script file was already loaded */
char *filename; /* Original Command Simulator file (CZ) */
int output_cfg; /* Whether sim is to output cfg files */
char script_fn[STR_SIZE];/* Script file read */
int iprompt; /* Interactive prompt */
} sim;
struct {
unsigned long ifea; /* Instruction fetch effective address */
unsigned long lea; /* Load effective address */
unsigned long sea; /* Store effective address */
unsigned long ld; /* Load data */
unsigned long sd; /* Store data */
unsigned long lsea; /* Load/Store effective address */
} cpu;
struct {
unsigned long ifea; /* Instruction fetch effective address */
unsigned long lea; /* Load effective address */
unsigned long sea; /* Store effective address */
unsigned long ld; /* Load data */
unsigned long sd; /* Store data */
unsigned long lsea; /* Load/Store effective address */
} cpu;
struct {
int random_seed; /* Initialize the memory with random values, starting with seed */
} memory;
struct { /* Verification API, part of Advanced Core Verification */
int enabled; /* Whether is VAPI module enabled */
FILE *vapi_file; /* vapi file */
int server_port; /* A user specified port number for services */
} memory;
struct { /* Verification API, part of Advanced Core Verification */
int enabled; /* Whether is VAPI module enabled */
FILE *vapi_file; /* vapi file */
int server_port; /* A user specified port number for services */
} vapi;
};
 
/trunk/or1ksim/sim.cfg
323,6 → 323,19
 
exe_log = 0/1
whether execution log should be generated
exe_log = default/hardware/software
type of executed log, default is used if not specified
exe_log_start = <value>
index of first instruction to start log with, default = 0
exe_log_end = <value>
index of last instruction to end log with; not limited, if omitted
exe_log_marker = <value>
<value> specifies number of instructions before horizontal marker is
printed; if zero, markers are disabled (default)
 
exe_log_fn = "<filename>"
where to put execution log in, used only if 'exe_log'
350,6 → 363,10
history = 1
/* iprompt = 0 */
exe_log = 0
exe_log_type = hardware
exe_log_start = 0
exe_log_end = 0
exe_log_marker = 0
exe_log_fn = "executed.log"
spr_log = 0
spr_log_fn = "spr.log"
/trunk/or1ksim/cpu/or32/execute.c
537,19 → 537,51
unsigned long i = iqueue[0].insn_addr;
 
if (i == 0xffffffff) return;
fprintf(runtime.sim.fexe_log, "\nEXECUTED(): %.8lx: ", i);
fprintf(runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1));
fprintf(runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3));
for(i = 0; i < MAX_GPRS; i++) {
if (i % 4 == 0)
fprintf(runtime.sim.fexe_log, "\n");
fprintf(runtime.sim.fexe_log, "GPR%2u: %.8lx ", i, reg[i]);
if (config.sim.exe_log_marker && instructions % config.sim.exe_log_marker == 0) {
fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n");
}
fprintf(runtime.sim.fexe_log, "\n");
fprintf(runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
fprintf(runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
fprintf(runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
fprintf(runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));
if (config.sim.exe_log_start <= instructions && (config.sim.exe_log_end <= 0 || instructions <= config.sim.exe_log_end)) {
switch (config.sim.exe_log_type) {
case EXE_LOG_HARDWARE:
fprintf (runtime.sim.fexe_log, "\nEXECUTED(): %.8lx: ", i);
fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1));
fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3));
for(i = 0; i < MAX_GPRS; i++) {
if (i % 4 == 0)
fprintf(runtime.sim.fexe_log, "\n");
fprintf (runtime.sim.fexe_log, "GPR%2u: %.8lx ", i, reg[i]);
}
fprintf (runtime.sim.fexe_log, "\n");
fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
fprintf (runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));
break;
case EXE_LOG_SOFTWARE:
{
int labels = 0;
if (verify_memoryarea(i)) {
struct label_entry *entry;
entry = get_label(i);
if (entry) {
printf("%s: ", entry->name);
labels++;
}
} else {
printf("<invalid addr>: ");
labels++;
}
if (labels) fprintf (runtime.sim.fexe_log, "\n");
fprintf (runtime.sim.fexe_log, "%.8lx ", i);
if (index >= 0) {
extern char *disassembled;
disassemble_insn (iqueue[0].insn_index);
printf(" %s", disassembled);
} else
printf("<invalid>");
}
}
}
}
 
#if 0
/trunk/or1ksim/sim-config.c
55,6 → 55,10
memset(&config, 0, sizeof(config));
/* Sim */
config.sim.exe_log = 0;
config.sim.exe_log_type = EXE_LOG_HARDWARE;
config.sim.exe_log_start = 0;
config.sim.exe_log_end = 0;
config.sim.exe_log_marker = 0;
config.sim.spr_log = 0;
strcpy (config.sim.exe_log_fn, "executed.log");
strcpy (config.sim.spr_log_fn, "spr.log");
363,6 → 367,7
/* Forward declarations of functions */
void base_include ();
void sim_clkcycle ();
void sim_exe_log_type ();
void change_device ();
void end_device ();
void uart_nuarts ();
531,6 → 536,10
{6, "mprof_fn", "=\"%s\"", NULL, (void *)(&config.sim.mprof_fn[0]), 0},
{6, "history", "=%i", NULL, (void *)(&config.sim.history), 0},
{6, "exe_log", "=%i", NULL, (void *)(&config.sim.exe_log), 0},
{6, "exe_log_type", "=%s ", sim_exe_log_type, (void *)(&tempS[0]), 0},
{6, "exe_log_start", "=%i", NULL, (void *)(&config.sim.exe_log_start), 0},
{6, "exe_log_end", "=%i", NULL, (void *)(&config.sim.exe_log_end), 0},
{6, "exe_log_marker", "=%i", NULL, (void *)(&config.sim.exe_log_marker), 0},
{6, "exe_log_fn", "=\"%s\"", NULL, (void *)(&config.sim.exe_log_fn[0]), 0},
{6, "spr_log", "=%i", NULL, (void *)(&config.sim.spr_log), 0},
{6, "spr_log_fn", "=\"%s\"", NULL, (void *)(&config.sim.spr_log_fn[0]), 0},
668,6 → 677,20
ERROR("invalid time format.");
}
 
void sim_exe_log_type () {
if (strcmp (tempS, "default") == 0)
config.sim.exe_log_type = EXE_LOG_HARDWARE;
else if (strcmp (tempS, "hardware") == 0)
config.sim.exe_log_type = EXE_LOG_HARDWARE;
else if (strcmp (tempS, "software") == 0) {
config.sim.exe_log_type = EXE_LOG_SOFTWARE;
} else {
char tmp[200];
sprintf (tmp, "invalid execute log type '%s'.\n", tempS);
ERROR(tmp);
}
}
 
void uart_nuarts () {
if (tempL >= 0 && tempL < MAX_UARTS)
config.nuarts = tempL;

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