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/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
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A CM of a buffered Clos for SDM-Clos routers |
*** SystemVerilog is used *** |
|
History: |
08/07/2011 Initial version. <wsong83@gmail.com> |
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*/ |
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// the router structure definitions |
`include "define.v" |
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module cm (/*AUTOARG*/ |
// Outputs |
do0, do1, do2, do3, dia, do4, |
// Inputs |
di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4, |
rst_n |
); |
|
parameter KN = 5; // dummy parameter, the number of IMs |
parameter DW = 8; // the data width of each IP |
parameter SCN = DW/2; // the number of sub-channels in one IP |
|
input [KN-1:0][SCN-1:0] di0, di1, di2, di3; // input data |
input [3:0] sdec, ndec, ldec; // the decoded direction requests |
input [1:0] wdec, edec; // the decoded direction requests |
output [KN-1:0][SCN-1:0] do0, do1, do2, do3; // output data |
|
`ifdef ENABLE_CHANNEL_SLICING |
input [KN-1:0][SCN-1:0] di4; // data input |
output [KN-1:0][SCN-1:0] dia; // input ack |
output [KN-1:0][SCN-1:0] do4; // data output |
input [KN-1:0][SCN-1:0] doa, doa4; // output ack |
`else |
input [KN-1:0] di4; // data input |
output [KN-1:0] dia; // input ack |
output [KN-1:0] do4; // data output |
input [KN-1:0] doa, doa4; // output ack |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
`ifndef ENABLE_CRRD |
output [KN-1:0] cms; // the state feedback to IMs |
`endif |
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input rst_n; // global active low reset |
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wire [KN-1:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3; // the data output of CM |
`ifdef ENABLE_CHANNEL_SLICING |
wire [KN-1:0][SCN-1:0] cmo4, cmoa, cmoa4; // data and ack wires |
`else |
wire [KN-1:0] cmo4, cmoa, cmoa4; // data and ack wires |
`endif |
wire [3:0] wcfg, ecfg, lcfg; // switch configuration |
wire [1:0] scfg, ncfg; // switch configuration |
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genvar i, j; |
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// data switch |
dcb_xy #(.VCN(1), .VCW(DW)) |
CM ( |
.sia ( dia[i][0] ), |
.wia ( dia[i][1] ), |
.nia ( dia[i][2] ), |
.eia ( dia[i][3] ), |
.lia ( dia[i][4] ), |
.so0 ( cmo0[i][0] ), |
.so1 ( cmo1[i][0] ), |
.so2 ( cmo2[i][0] ), |
.so3 ( cmo3[i][0] ), |
.so4 ( cmo4[i][0] ), |
.wo0 ( cmo0[i][1] ), |
.wo1 ( cmo1[i][1] ), |
.wo2 ( cmo2[i][1] ), |
.wo3 ( cmo3[i][1] ), |
.wo4 ( cmo4[i][1] ), |
.no0 ( cmo0[i][2] ), |
.no1 ( cmo1[i][2] ), |
.no2 ( cmo2[i][2] ), |
.no3 ( cmo3[i][2] ), |
.no4 ( cmo4[i][2] ), |
.eo0 ( cmo0[i][3] ), |
.eo1 ( cmo1[i][3] ), |
.eo2 ( cmo2[i][3] ), |
.eo3 ( cmo3[i][3] ), |
.eo4 ( cmo4[i][3] ), |
.lo0 ( cmo0[i][4] ), |
.lo1 ( cmo1[i][4] ), |
.lo2 ( cmo2[i][4] ), |
.lo3 ( cmo3[i][4] ), |
.lo4 ( cmo4[i][4] ), |
.si0 ( di0[i][0] ), |
.si1 ( di1[i][0] ), |
.si2 ( di2[i][0] ), |
.si3 ( di3[i][0] ), |
.si4 ( di4[i][0] ), |
.wi0 ( di0[i][1] ), |
.wi1 ( di1[i][1] ), |
.wi2 ( di2[i][1] ), |
.wi3 ( di3[i][1] ), |
.wi4 ( di4[i][1] ), |
.ni0 ( di0[i][2] ), |
.ni1 ( di1[i][2] ), |
.ni2 ( di2[i][2] ), |
.ni3 ( di3[i][2] ), |
.ni4 ( di4[i][2] ), |
.ei0 ( di0[i][3] ), |
.ei1 ( di1[i][3] ), |
.ei2 ( di2[i][3] ), |
.ei3 ( di3[i][3] ), |
.ei4 ( di4[i][3] ), |
.li0 ( di0[i][4] ), |
.li1 ( di1[i][4] ), |
.li2 ( di2[i][4] ), |
.li3 ( di3[i][4] ), |
.li4 ( di4[i][4] ), |
.soa ( cmoa[i][0] ), |
.woa ( cmoa[i][1] ), |
.noa ( cmoa[i][2] ), |
.eoa ( cmoa[i][3] ), |
.loa ( cmoa[i][4] ), |
.soa4 ( cmoa4[i][0] ), |
.woa4 ( cmoa4[i][1] ), |
.noa4 ( cmoa4[i][2] ), |
.eoa4 ( cmoa4[i][3] ), |
.loa4 ( cmoa4[i][4] ), |
.wcfg ( wcfg[i] ), |
.ecfg ( ecfg[i] ), |
.lcfg ( lcfg[i] ), |
.scfg ( scfg[i] ), |
.ncfg ( ncfg[i] ) |
); |
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// the allocator |
cm_alloc CMD ( |
`ifndef ENABLE_CRRD |
.s ( cms ), |
`endif |
.sra ( ), |
.wra ( ), |
.nra ( ), |
.era ( ), |
.lra ( ), |
.scfg ( scfg ), |
.ncfg ( ncfg ), |
.wcfg ( wcfg ), |
.ecfg ( ecfg ), |
.lcfg ( lcfg ), |
.sr ( sdec ), |
.wr ( wdec ), |
.nr ( ndec ), |
.er ( edec ), |
.lr ( ldec ) |
); |
|
|
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endmodule // cm |
/async_sdm_noc/branches/clos_opt/clos_opt/src/im.v
24,8 → 24,13
// Outputs |
do0, do1, do2, do3, deco, dia, do4, |
// Inputs |
di0, di1, di2, di3, deci, di4, doa, doa4, rst_n |
di0, di1, di2, di3, deci, di4, doa, doa4 |
`ifndef ENABLE_CRRD |
, cms |
`endif |
, rst_n |
); |
|
parameter MN = 2; // the number of CMs |
parameter NN = 2; // the number of IPs in one IM |
parameter DW = 8; // the data width of a single IP |
56,21 → 61,22
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input rst_n; // global active low reset |
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wire cfg; // the configuration for the IM |
wire [MN-1:0][NN-1:0] cfg; // the configuration for the IM |
wire [MN-1:0][SCN-1:0] imo0, imo1, imo2, imo3; // the IM output data |
wire [MN-1:0][SN-1:0] imodec; // the IM output dec |
`ifdef ENABLE_CHANNEL_SLICING |
wire [MN-1:0][SCN-1:0] imo4; // IM output data |
wire [MN-1:0][SCN-1:0] imoa, imoa4; // IM output ack |
wire [MN-1:0][SCN-1:0] eofan, eofan, doan, deca, decan; // stage control acks |
wire [MN-1:0][SCN-1:0] eofan, doan, deca; // stage control acks |
`else |
wire [MN-1:0] imo4; // IM data output |
wire [MN-1:0] imoa, imoa4; // IM output ack |
wire [MN-1:0] eofan, eofan, doan, deca, decan; // stage control acks |
wire [MN-1:0] eofan, doan, deca; // stage control acks |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
wire [MN-1:0] decan; |
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genvar i, j; |
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genvar i; |
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// the data crossbar |
dcb #(.NN(NN), .MN(MN), .DW(DW)) |
IMDCB ( |
134,15 → 140,69
.d_in_a ( ), |
.d_out ( do4[i][j] ), |
.d_in ( imo4[i][j] ), |
.d_out_a ( eofa[i][j] ), |
.d_out_a ( eofan[i][j] ), |
); |
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ppc PCTL ( |
.deca ( deca[i][j] ), |
. |
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pipen #(.DW(SN)) |
PDEC ( |
|
.deca ( deca[i][j] ), |
.dia ( imoa4[i][j] ), |
.eof ( do4[i][j] ), |
.doa ( doa[i][j] ), |
.dec ( |deco[i] ) |
); |
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assign doan[i][j] = (~doa[i][j])&rst_n; |
assign eofan[i][j] = (~deca[i][j])&rst_n; |
end // block: SC |
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assign decan[i] = (~&deca[i])&rst_n; |
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`else // !`ifdef ENABLE_CHANNEL_SLICING |
pipe4 #(.DW(DW)) |
P ( |
.o0 ( do0[i] ), |
.o1 ( do1[i] ), |
.o2 ( do2[i] ), |
.o3 ( do3[i] ), |
.ia ( imoa[i] ), |
.i0 ( imo0[i] ), |
.i1 ( imo1[i] ), |
.i2 ( imo2[i] ), |
.i3 ( imo3[i] ), |
.oa ( doan[i] ) |
); |
|
pipen #(.DW(1)) |
PEoF ( |
.d_in_a ( ), |
.d_out ( do4[i] ), |
.d_in ( imo4[i] ), |
.d_out_a ( eofan[i] ) |
); |
|
ppc PCTL ( |
.deca ( deca[i] ), |
.dia ( imoa4[i] ), |
.eof ( do4[i] ), |
.doa ( doa[i] ), |
.dec ( |deco[i] ) |
); |
|
assign doan[i] = (~doa[i])&rst_n; |
assign eofan[i] = (~deca[i])&rst_n; |
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assign decan[i] = (~deca[i])&rst_n; |
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`endif // !`ifdef ENABLE_CHANNEL_SLICING |
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pipen #(.DW(SN)) |
PDEC ( |
.d_in_a ( ), |
.d_out ( deco[i] ), |
.d_in ( imodec[i] ), |
.d_out_a ( decan[i] ) |
); |
end // block: OPD |
endgenerate |
|
endmodule // im |