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  • This comparison shows the changes necessary to convert path 
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    from Rev 68 to Rev 69
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Rev 68 → Rev 69

/jart/branches/ver0branch/powerGrid.vhd
32,15 → 32,15
package powerGrid is
 
-- R2 for size and width
type SIZE_WIDTH is array (0 to 1) of integer;
type DUPLA is array (0 to 2) of SIZE_WIDTH;
type SIZE_WIDTH is array (integer,integer) of integer;
type DUPLA is array (0 to 2,1 downto 0) of integer;
-- Tuple for widths
type WARRAY is array (0 to 2) of integer;
-- Index
constant SZINDEX: integer :=0;
constant WDINDEX: integer :=1;
constant SZINDEX: integer :=0; -- Size Description Index.
constant WDINDEX: integer :=1; -- Width description Index.
-- Register file for spheres.
-- OP1 : One sphere output per clock.
53,10 → 53,11
constant SZALFA : integer := 1;
constant SZBETA : integer := 2;
constant DBUSW : integer := 64;
constant BUSW : integer := 32;
constant HBUSW : integer := 18;
-- Size and Width.
-- Size and Width depending upon the number of spheres to push out in one clock (OP1= One sphere, OP2 = Two spheres, OP4= Four spheres).
constant REGSZADD : WARRAY := (12,11,10);
constant CIDSZADD : DUPLA := ((1,0),(2,1),(4,2));
300,8 → 301,9
generic (
OPMODE : integer := OP4; -- By default push out 4 spheres at same time.
SZMODE : integer := SZBETA; -- By default the max sphere numbers is 2048, but could be 4096 with SZALFA.
SZMODE : integer := SZBETA -- By default the max sphere numbers is 2048, but could be 4096 with SZALFA.
);
port (
308,7 → 310,7
clk, ena: in std_logic; -- The usual control signals.
wen : in std_logic_vector (CIDSZADD(OPMODE(SZINDEX))*4-1 downto 0); -- Write enable signals
wen : in std_logic_vector (CIDSZADD(OP4,SZINDEX)-1 downto 0); -- Write enable signals
add : in std_logic_vector (REGSZADD(OPMODE)-SZMODE downto 0); -- Address bus
datain : in std_logic_vector (BUSW-1 downto 0); -- incoming data from 32 bits width bus.
320,7 → 322,7
);
end entity;
end component;
-- A scan flip flop, aka selectable input ff.
component scanFF
/jart/branches/ver0branch/sqrt.vhd
18,9 → 18,7
clk,rst,ena : in std_logic;
radical : in std_logic_vector (W2-1 downto 0);
sho : out std_logic;
a,b,x,y : out std_logic_vector ((W2/2)-1 downto 0);
decoder : out integer range 0 to (W2/2)-1
root : out std_logic_vector ((W2/2)-1 downto 0)
);
end entity;
 
36,6 → 34,10
signal sa2,sb2,sx2,sy2 : std_logic_vector (WP-1 downto 0);
signal localenc1 : integer range 0 to WP-1;
signal localenc2 : integer range 0 to WP-1;
signal sho : std_logic;
signal a,b,x,y : std_logic_vector ((W2/2)-1 downto 0);
signal decoder : integer range 0 to (W2/2)-1;
signal ab,xy : std_logic_vector (W2-1 downto 0);
begin
53,7 → 55,13
-- Stage 1 : Function for signal Y.
muxs1(i) <= sy1(i) or (not(sx1(i)) and sb1_1(i));
-- Stage 3 :
ab(i*2) <= b(i);
ab(i*2+1) <= a(i);
xy(i*2) <= y(i);
xy(i*2+1) <= x(i);
end generate signalization;
60,8 → 68,7
stages: process (rst,clk,ena,sx0,sx1,localenc2)
variable localenc0 : integer range 0 to WP-1;
variable localenc0 : integer range 0 to WP-1;
begin
-- Highest signifcant pair enconder : look for the bit pair with the most significant bit.
98,7 → 105,10
a<=(others => '0');
b<=(others => '0');
--Stage 4
root <= (others=>'0');
elsif rising_edge(clk) and ena='1' then
137,11 → 147,21
decoder<=localenc2;
sho<=sa2(localenc2);
stage34
-- stage34
for i in 0 to WP-1 loop
if i>decoder then
root(i)<='0';
elsif decoder-i>2 then
root(i)<=ab(decoder+i+1);
elsif decoder-i=2 then
root(i)<=(ab(decoder+i+1) and not(sho)) or (xy(decoder+i+1) and sho);
else
root(i)<=xy(decoder+i+1);
end if;
end loop;
end if;
 
end process stages;

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