URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 68 to Rev 69
- ↔ Reverse comparison
Rev 68 → Rev 69
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/TbdSdsyn.tcl
0,0 → 1,87
# Copyright (C) 1991-2010 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
|
# Quartus II: Generate Tcl File for Project |
# File: SdCmdsyn.tcl |
# Generated on: Wed Jun 23 17:07:05 2010 |
|
# Load Quartus II Tcl Project package |
package require ::quartus::project |
package require ::quartus::flow |
|
set need_to_close_project 0 |
set make_assignments 1 |
|
# Check that the right project is open |
if {[is_project_open]} { |
if {[string compare $quartus(project) "TbdSdsyn"]} { |
puts "Project TbdSdsyn is not open" |
set make_assignments 0 |
} |
} else { |
# Only open if not already open |
if {[project_exists TbdSdsyn]} { |
project_open -revision TbdSdsyn TbdSdsyn |
} else { |
project_new -revision TbdSdsyn TbdSdsyn |
} |
set need_to_close_project 1 |
} |
|
# Make assignments |
if {$make_assignments} { |
set_global_assignment -name FAMILY "Cyclone II" |
set_global_assignment -name DEVICE EP2C35F484C8 |
set_global_assignment -name TOP_LEVEL_ENTITY TbdSd |
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga |
set_global_assignment -name VHDL_FILE "../../../grpGlobal/pkgGlobal/src/Global-p.vhdl" |
set_global_assignment -name VHDL_FILE "../../../grpSd/pkgSd/src/Sd-p.vhdl" |
set_global_assignment -name VHDL_FILE "../../../grpCrc/pkgCRCs/src/CRCs-p.vhdl" |
set_global_assignment -name VHDL_FILE "../../../grpCrc/unitCrc/src/Crc-Rtl-ea.vhdl" |
set_global_assignment -name VHDL_FILE "../../../grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl" |
set_global_assignment -name VHDL_FILE "../../../grpSd/unitSdController/src/SdController-Rtl-ea.vhdl" |
set_global_assignment -name VHDL_FILE "../../../grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl" |
set_global_assignment -name VHDL_FILE "../../../grpComponents/pkgIcs307Values/src/Ics307Values-p.vhdl"; |
set_global_assignment -name VHDL_FILE "../../../grpComponents/unitIcs307Configurator/src/Ics307Configurator-e.vhd"; |
set_global_assignment -name VHDL_FILE "../../../grpComponents/unitIcs307Configurator/src/Ics307Configurator-Rtl-a.vhd"; |
set_global_assignment -name VHDL_FILE "../../../grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl" |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name SMART_RECOMPILE ON |
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id Clock |
set_global_assignment -name ENABLE_DRC_SETTINGS OFF |
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF |
set_global_assignment -name USE_CONFIGURATION_DEVICE ON |
set_global_assignment -name GENERATE_RBF_FILE ON |
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" |
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" |
set_instance_assignment -name CLOCK_SETTINGS Clock -to iClk |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
|
# Commit assignments |
export_assignments |
|
# Compile project |
if {[catch {execute_flow -compile} result]} { |
puts "\nResult: $result\n" |
puts "ERROR: Compilation failed. See report files.\n" |
} else { |
puts "\nINFO: Compilation was successful.\n" |
} |
|
# Close project |
if {$need_to_close_project} { |
project_close |
} |
} |
sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/TbdSdsyn.tcl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/Makefile
===================================================================
--- sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/Makefile (nonexistent)
+++ sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/Makefile (revision 69)
@@ -0,0 +1,9 @@
+# Makefile for synthesizing crcs
+
+include ../../../../Makefile.rules
+
+all: TbdSdsyn.syn
+
+clean:
+ rm -rf db incremental_db *.rbf *.sof *.pin *.pof
+
Index: sdhc-sc-core/trunk/src/grpComponents/pkgIcs307Values/src/Ics307Values-p.vhdl
===================================================================
--- sdhc-sc-core/trunk/src/grpComponents/pkgIcs307Values/src/Ics307Values-p.vhdl (revision 68)
+++ sdhc-sc-core/trunk/src/grpComponents/pkgIcs307Values/src/Ics307Values-p.vhdl (revision 69)
@@ -12,19 +12,19 @@
use ieee.numeric_std.all;
package Ics307Values is
- cCrystalLoadCapacitance_C_48MHz : std_ulogic_vector(1 downto 0) := "00";
- cReferenceDivider_RDW_48MHz : std_ulogic_vector(6 downto 0) := "0000011";
- cVcoDividerWord_VDW_48MHz : std_ulogic_vector(8 downto 0) := "000010000";
- cOutputDutyCycleVoltage_TTL_48MHz : std_ulogic := '1';
- cClkFunctionSelect_R_48MHz : std_ulogic_vector(1 downto 0) := "00";
- cOutputDivide_S_48MHz : std_ulogic_vector(2 downto 0) := "100";
+ constant cCrystalLoadCapacitance_C_48MHz : std_ulogic_vector(1 downto 0) := "00";
+ constant cReferenceDivider_RDW_48MHz : std_ulogic_vector(6 downto 0) := "0000011";
+ constant cVcoDividerWord_VDW_48MHz : std_ulogic_vector(8 downto 0) := "000010000";
+ constant cOutputDutyCycleVoltage_TTL_48MHz : std_ulogic := '1';
+ constant cClkFunctionSelect_R_48MHz : std_ulogic_vector(1 downto 0) := "00";
+ constant cOutputDivide_S_48MHz : std_ulogic_vector(2 downto 0) := "100";
- cCrystalLoadCapacitance_C_25MHz : std_ulogic_vector(1 downto 0) := "00";
- cOutputDutyCycleVoltage_TTL_25MHz : std_ulogic := '1';
- cClkFunctionSelect_R_25MHz : std_ulogic_vector(1 downto 0) := "00";
- cOutputDivide_S_25MHz : std_ulogic_vector(2 downto 0) := "000";
- cVcoDividerWord_VDW_25MHz : std_ulogic_vector(8 downto 0) := "000000111";
- cReferenceDivider_RDW_25MHz : std_ulogic_vector(6 downto 0) := "0000001";
+ constant cCrystalLoadCapacitance_C_25MHz : std_ulogic_vector(1 downto 0) := "00";
+ constant cOutputDutyCycleVoltage_TTL_25MHz : std_ulogic := '1';
+ constant cClkFunctionSelect_R_25MHz : std_ulogic_vector(1 downto 0) := "00";
+ constant cOutputDivide_S_25MHz : std_ulogic_vector(2 downto 0) := "000";
+ constant cVcoDividerWord_VDW_25MHz : std_ulogic_vector(8 downto 0) := "000000111";
+ constant cReferenceDivider_RDW_25MHz : std_ulogic_vector(6 downto 0) := "0000001";
end package Ics307Values;