URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- This comparison shows the changes necessary to convert path
/
- from Rev 691 to Rev 692
- ↔ Reverse comparison
Rev 691 → Rev 692
/trunk/or1ksim/cpu/common/stats.c
38,15 → 38,15
const char func_unit_str[30][30] = { "unknown", "exception", "arith", "shift", "compare", |
"branch", "jump", "load", "store", "movimm", "move", "extend", "nop", "mac" }; |
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struct dstats_entry dstats[DSTATS_LEN]; /* dependency stats */ |
struct sstats_entry sstats[SSTATS_LEN]; /* single stats */ |
struct fstats_entry fstats[FSTATS_LEN]; /* functional units stats */ |
struct mstats_entry mstats; /* misc units stats */ |
struct cachestats_entry ic_stats; /* instruction cache stats */ |
struct cachestats_entry dc_stats; /* data cache stats */ |
struct immustats_entry immu_stats; /* insn mmu stats */ |
struct dmmustats_entry dmmu_stats; /* data mmu stats */ |
struct raw_stats raw_stats; /* RAW hazard stats */ |
struct dstats_entry dstats[DSTATS_LEN] = {0}; /* dependency stats */ |
struct sstats_entry sstats[SSTATS_LEN] = {0}; /* single stats */ |
struct fstats_entry fstats[FSTATS_LEN] = {0}; /* functional units stats */ |
struct mstats_entry mstats = {0}; /* misc units stats */ |
struct cachestats_entry ic_stats = {0}; /* instruction cache stats */ |
struct cachestats_entry dc_stats = {0}; /* data cache stats */ |
struct immustats_entry immu_stats = {0}; /* insn mmu stats */ |
struct dmmustats_entry dmmu_stats = {0}; /* data mmu stats */ |
struct raw_stats raw_stats = {0}; /* RAW hazard stats */ |
|
/* Dependency */ |
|
176,16 → 176,16
} else |
printf("BTIC simulation disabled. Enabled it to see BTIC analysis\n"); |
|
if (testsprbits(SPR_UPR, SPR_UPR_ICP)) { |
if (config.ic.enabled) { |
printf("IC read: hit %d(%d%%), miss %d\n", ic_stats.readhit, (ic_stats.readhit * 100) / SD(ic_stats.readhit + ic_stats.readmiss), ic_stats.readmiss); |
} else |
printf("No ICache. Set UPR[ICP]\n"); |
printf("No ICache. Enable it to see IC results.\n"); |
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if (testsprbits(SPR_UPR, SPR_UPR_DCP)) { |
if (config.dc.enabled) { |
printf("DC read: hit %d(%d%%), miss %d\n", dc_stats.readhit, (dc_stats.readhit * 100) / SD(dc_stats.readhit + dc_stats.readmiss), dc_stats.readmiss); |
printf("DC write: hit %d(%d%%), miss %d\n", dc_stats.writehit, (dc_stats.writehit * 100) / SD(dc_stats.writehit + dc_stats.writemiss), dc_stats.writemiss); |
} else |
printf("No DCache. Set UPR[DCP]\n"); |
printf("No DCache. Enable it to see DC results.\n"); |
|
if (testsprbits(SPR_UPR, SPR_UPR_IMP)) { |
printf("IMMU read: hit %d(%d%%), miss %d\n", immu_stats.fetch_tlbhit, (immu_stats.fetch_tlbhit * 100) / SD(immu_stats.fetch_tlbhit + immu_stats.fetch_tlbmiss), immu_stats.fetch_tlbmiss); |