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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
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    from Rev 694 to Rev 695
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Rev 694 → Rev 695

/trunk/or1ksim/peripheral/ethernet.h
70,6 → 70,7
#define ETH_MODER_EXDFREN_OFFSET 9
#define ETH_MODER_NOBCKOF_OFFSET 8
#define ETH_MODER_LOOPBCK_OFFSET 7
#define ETH_MODER_IFG_OFFSET 6
#define ETH_MODER_PRO_OFFSET 5
#define ETH_MODER_IAM_OFFSET 4
#define ETH_MODER_BRO_OFFSET 3
97,6 → 98,39
#define ETH_PACKETLEN_MAXFL_OFFSET 0
#define ETH_PACKETLEN_MAXFL_WIDTH 16
 
/* Field definitions for COLLCONF */
#define ETH_COLLCONF_MAXRET_OFFSET 16
#define ETH_COLLCONF_MAXRET_WIDTH 4
#define ETH_COLLCONF_COLLVALID_OFFSET 0
#define ETH_COLLCONF_COLLVALID_WIDTH 6
 
/* Field definitions for CTRLMODER */
#define ETH_CMODER_TXFLOW_OFFSET 2
#define ETH_CMODER_RXFLOW_OFFSET 1
#define ETH_CMODER_PASSALL_OFFSET 0
 
/* Field definitions for MIIMODER */
#define ETH_MIIMODER_MRST_OFFSET 10
#define ETH_MIIMODER_NOPRE_OFFSET 8
#define ETH_MIIMODER_CLKDIV_OFFSET 0
#define ETH_MIIMODER_CLKDIV_WIDTH 8
 
/* Field definitions for MIICOMMAND */
#define ETH_MIICOMM_WCDATA_OFFSET 2
#define ETH_MIICOMM_RSTAT_OFFSET 1
#define ETH_MIICOMM_SCANS_OFFSET 0
 
/* Field definitions for MIIADDRESS */
#define ETH_MIIADDR_RGAD_OFFSET 8
#define ETH_MIIADDR_RGAD_WIDTH 5
#define ETH_MIIADDR_FIAD_OFFSET 0
#define ETH_MIIADDR_FIAD_WIDTH 5
 
/* Field definitions for MIISTATUS */
#define ETH_MIISTAT_NVALID_OFFSET 9
#define ETH_MIISTAT_BUSY_OFFSET 8
#define ETH_MIISTAT_FAIL_OFFSET 0
 
/* Field definitions for TX buffer descriptors */
#define ETH_TX_BD_LENGTH_OFFSET 16
#define ETH_TX_BD_LENGTH_WIDTH 16
107,14 → 141,15
#define ETH_TX_BD_CRC_OFFSET 11
#define ETH_TX_BD_LAST_OFFSET 10
#define ETH_TX_BD_PAUSE_OFFSET 9
#define ETH_TX_BD_DEFER_OFFSET 8
#define ETH_TX_BD_COLLISION_OFFSET 7
#define ETH_TX_BD_RETRANSMIT_OFFSET 6
#define ETH_TX_BD_UNDERRUN_OFFSET 5
#define ETH_TX_BD_NO_CARRIER_OFFSET 4
#define ETH_TX_BD_RETRY_OFFSET 0
#define ETH_TX_BD_UNDERRUN_OFFSET 8
#define ETH_TX_BD_RETRY_OFFSET 4
#define ETH_TX_BD_RETRY_WIDTH 4
#define ETH_TX_BD_RETRANSMIT_OFFSET 3
#define ETH_TX_BD_COLLISION_OFFSET 2
#define ETH_TX_BD_DEFER_OFFSET 1
#define ETH_TX_BD_NO_CARRIER_OFFSET 0
 
 
/* Field definitions for RX buffer descriptors */
#define ETH_RX_BD_LENGTH_OFFSET 16
#define ETH_RX_BD_LENGTH_WIDTH 16
121,17 → 156,13
#define ETH_RX_BD_EMPTY_OFFSET 15
#define ETH_RX_BD_INTERRUPT_OFFSET 14
#define ETH_RX_BD_WRAP_OFFSET 13
#define ETH_RX_BD_LAST_OFFSET 10
#define ETH_RX_BD_PAUSE_OFFSET 9
#define ETH_RX_BD_DEFER_OFFSET 8
#define ETH_RX_BD_COLLISION_OFFSET 7
#define ETH_RX_BD_RETRANSMIT_OFFSET 6
#define ETH_RX_BD_UNDERRUN_OFFSET 5
#define ETH_RX_BD_NO_CARRIER_OFFSET 4
#define ETH_RX_BD_RETRY_OFFSET 0
#define ETH_RX_BD_RETRY_WIDTH 4
#define ETH_RX_BD_MISS_OFFSET 7
#define ETH_RX_BD_UVERRUN_OFFSET 6
#define ETH_RX_BD_INVALID_OFFSET 5
#define ETH_RX_BD_DRIBBLE_OFFSET 4
#define ETH_RX_BD_TOOBIG_OFFSET 3
#define ETH_RX_BD_TOOSHORT_OFFSET 2
#define ETH_RX_BD_CRC_OFFSET 1
#define ETH_RX_BD_LATECOLL_OFFSET 0
 
 
 
 
#endif /* __OR1KSIM_PERIPHERAL_ETHERNET_H */
/trunk/or1ksim/peripheral/ethernet_i.h
81,6 → 81,15
/*
* Implementatino of Ethernet MAC Registers and State
*/
#define ETH_TXSTATE_IDLE 0
#define ETH_TXSTATE_WAIT4BD 10
#define ETH_TXSTATE_READFIFO 20
#define ETH_TXSTATE_TRANSMIT 30
 
#define ETH_RXSTATE_IDLE 0
#define ETH_RXSTATE_WAIT4BD 10
#define ETH_RXSTATE_RECV 20
#define ETH_RXSTATE_WRITEFIFO 30
struct eth_device
{
/* Base address in memory */
106,25 → 115,28
/* Current TX state */
struct
{
unsigned long bd_index;
unsigned long bd;
unsigned working, waiting_for_dma, error;
unsigned packet_length;
unsigned minimum_length, maximum_length;
unsigned add_crc;
unsigned long crc_value;
unsigned bytes_left, bytes_sent;
unsigned long state;
unsigned long bd_index;
unsigned long bd;
unsigned long bd_addr;
unsigned working, waiting_for_dma, error;
unsigned packet_length;
unsigned minimum_length, maximum_length;
unsigned add_crc;
unsigned long crc_value;
unsigned bytes_left, bytes_sent;
} tx;
 
/* Current RX state */
struct
{
unsigned long bd_index;
unsigned long bd;
int fd;
off_t *offset;
unsigned working, error, waiting_for_dma;
unsigned packet_length, bytes_read, bytes_left;
unsigned long state;
unsigned long bd_index;
unsigned long bd;
int fd;
off_t *offset;
unsigned working, error, waiting_for_dma;
unsigned packet_length, bytes_read, bytes_left;
} rx;
 
/* Visible registers */
147,9 → 159,13
unsigned long miirx_data;
unsigned long miistatus;
/* Buffer descriptors */
unsigned long bd_ram[ETH_BD_SPACE / 4];
/* Buffer descriptors */
unsigned long bd_ram[ETH_BD_SPACE / 4];
} regs;
 
unsigned long rx_buff[0x10000];
unsigned long tx_buff[0x10000];
unsigned long lo_buff[0x10000];
};
 
 

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