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https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk
Subversion Repositories 10_100m_ethernet-fifo_convertor
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- This comparison shows the changes necessary to convert path
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- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/RxModule.v
2,8 → 2,9
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
|
////Next task: make the feedback to PC showing need data. |
//Next step, reduce the resource consumed |
|
//version 0.5, defined many parameter to configure the IP core, making it easier to use. |
//vertion 0.4, add the function for TxModule to get start in a configurable ff_clk time after |
// RxModule receiving the first frame. To modify the delay time just to |
// change the value of the macro-variable delay_cnt_config. |
12,12 → 13,19
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`include "common.v" |
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`define eth_buf_len 1416 //1416=8*(8+6+6+2+3+148+4) |
`define nibble_cnt_step 9'h001 |
`define ff_source_cnt_len 8 //(2^ff_source_cnt_len) must be larger than uframelen |
`define nibble_cnt_len 10 //(2^nibble_cnt_len) must be larger than eth_buf_len/4 |
`define delay_cnt_len 4 //(2^delay_cnt_len) must be larger than the number of clocks you want TxModule to wait at the beginning |
`define delay_cnt_config 4'h9 //the initiation value for the delay_cnt |
`define ff_data_buf_index_len 5 //(2^ff_data_buf_index_len) must be larger than or equal to num_uframe*2 |
`define toggle_lsbs 4'h0 //the length of zeros is ff_data_buf_index_len-1 |
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`define delay_cnt_config 4'h0 |
`define delay_cnt_step 4'h1 |
//8 bytes preamble, 12 bytes source address and destination address, 2 bytes length/type, 3bytes frameID |
`define eth_buf_len (8*(8+6+6+2)+`frameidlen+`uframelen*`num_uframe+8*4) //the last 4 bytes CRC |
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`define frameid_offset 176 //index of frameid in eth_buf |
`define data_offset (`frameid_offset+`frameidlen) //index of beginning of data in eth_buf |
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module RxModule(phy_rxd, phy_rxen, phy_rxclk, phy_rxer, |
ff_clk, ff_data, ff_en, |
|
25,7 → 33,7
frameid, |
`endif |
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empty, start); |
start); |
input phy_rxen, phy_rxclk, phy_rxer; //MII interface |
input [3:0] phy_rxd; |
|
33,30 → 41,30
output ff_data, ff_en; |
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`ifdef frameIDfromRx |
output[23:0] frameid; |
output[`frameidlen-1:0] frameid; |
`endif |
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output empty, start; //to tell TxModule that buf in RxModule needs data |
output start; //to tell TxModule that buf in RxModule needs data |
reg ff_data; |
reg ff_en; |
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reg[147:0] ff_data_buf[0:15]; // |
reg[147:0] ff_d; |
wire[3:0] toggle; |
reg[7:0] ff_cnt = 8'h00; |
reg[`uframelen-1:0] ff_data_buf[0:`num_uframe*2-1]; //declare |
reg[`uframelen-1:0] ff_d; |
reg[`ff_source_cnt_len-1:0] ff_cnt; |
reg[`eth_buf_len-1:0] eth_buf; |
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reg[8:0] nibble_cnt=9'h00; |
reg[`nibble_cnt_len-1:0] nibble_cnt=0; |
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`ifdef frameIDfromRx |
reg[23:0] frameidt[0:1]; |
reg[`frameidlen-1:0] frameidt[0:1]; |
`endif |
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reg start=1'b0; |
reg start_intra=1'b0; |
reg[3:0] delay_cnt; |
reg[`delay_cnt_len-1:0] delay_cnt; |
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reg[3:0] ff_data_buf_index = 4'h0; |
reg[`ff_data_buf_index_len-1:0] ff_data_buf_index; |
wire[`ff_data_buf_index_len-1:0] toggle; |
reg ff_state; |
reg[3:0] gap_cnt = 4'h0; |
|
65,43 → 73,58
always@(posedge phy_rxclk)begin //receive data from Ethernet including the preamble, SFD and CRC |
if(phy_rxen & ~phy_rxer) begin //data is valid and no error |
eth_buf <= {phy_rxd, eth_buf[`eth_buf_len-1:4]}; |
nibble_cnt <= nibble_cnt + `nibble_cnt_step; |
nibble_cnt <= nibble_cnt + 1; |
end |
else if ((nibble_cnt == 9'd354 ) & ((eth_buf[111:64] ^ `MAC_ADD)==48'h0)) begin |
else if ((nibble_cnt == (`eth_buf_len>>2) ) & (eth_buf[111:64] == `MAC_ADD)) begin |
//one frame has been transfered over, the destinate address is right and then been put into the buffer |
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`ifdef frameIDfromRx |
frameidt[toggle[3]] <= eth_buf[199:176]; |
frameidt[~ff_data_buf_index[`ff_data_buf_index_len-1]] <= eth_buf[`data_offset-1:`frameid_offset]; |
`endif |
|
ff_data_buf[toggle ] <= eth_buf[347:200]; |
ff_data_buf[toggle+4'h1] <= eth_buf[495:348]; |
ff_data_buf[toggle+4'h2] <= eth_buf[643:496]; |
ff_data_buf[toggle+4'h3] <= eth_buf[791:644]; |
ff_data_buf[toggle+4'h4] <= eth_buf[939:792]; |
ff_data_buf[toggle+4'h5] <= eth_buf[1087:940]; |
ff_data_buf[toggle+4'h6] <= eth_buf[1235:1088]; |
ff_data_buf[toggle+4'h7] <= eth_buf[1383:1236]; |
`ifdef num_cover_4 |
ff_data_buf[toggle ] <= eth_buf[`data_offset+ 1*`uframelen-1: `data_offset+ 0*`uframelen]; |
ff_data_buf[toggle + 1] <= eth_buf[`data_offset+ 2*`uframelen-1: `data_offset+ 1*`uframelen]; |
ff_data_buf[toggle + 2] <= eth_buf[`data_offset+ 3*`uframelen-1: `data_offset+ 2*`uframelen]; |
ff_data_buf[toggle + 3] <= eth_buf[`data_offset+ 4*`uframelen-1: `data_offset+ 3*`uframelen]; |
`ifdef num_cover_8 |
ff_data_buf[toggle + 4] <= eth_buf[`data_offset+ 5*`uframelen-1: `data_offset+ 4*`uframelen]; |
ff_data_buf[toggle + 5] <= eth_buf[`data_offset+ 6*`uframelen-1: `data_offset+ 5*`uframelen]; |
ff_data_buf[toggle + 6] <= eth_buf[`data_offset+ 7*`uframelen-1: `data_offset+ 6*`uframelen]; |
ff_data_buf[toggle + 7] <= eth_buf[`data_offset+ 8*`uframelen-1: `data_offset+ 7*`uframelen]; |
`ifdef num_cover_16 |
ff_data_buf[toggle + 8] <= eth_buf[`data_offset+ 9*`uframelen-1: `data_offset+ 8*`uframelen]; |
ff_data_buf[toggle + 9] <= eth_buf[`data_offset+10*`uframelen-1: `data_offset+ 9*`uframelen]; |
ff_data_buf[toggle + 10] <= eth_buf[`data_offset+11*`uframelen-1: `data_offset+10*`uframelen]; |
ff_data_buf[toggle + 11] <= eth_buf[`data_offset+12*`uframelen-1: `data_offset+11*`uframelen]; |
ff_data_buf[toggle + 12] <= eth_buf[`data_offset+13*`uframelen-1: `data_offset+12*`uframelen]; |
ff_data_buf[toggle + 13] <= eth_buf[`data_offset+14*`uframelen-1: `data_offset+13*`uframelen]; |
ff_data_buf[toggle + 14] <= eth_buf[`data_offset+15*`uframelen-1: `data_offset+14*`uframelen]; |
ff_data_buf[toggle + 15] <= eth_buf[`data_offset+16*`uframelen-1: `data_offset+15*`uframelen]; |
`endif |
`endif |
`endif |
|
start_intra <= 1'b1; |
nibble_cnt <= 9'h000; |
nibble_cnt <= 0; |
end |
else |
nibble_cnt <= 9'h000; |
nibble_cnt <= 0; |
end |
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assign empty = ((ff_data_buf_index[2:0]==3'b011)|(ff_data_buf_index[2:0]==3'b100)); |
//assign empty = ((ff_data_buf_index[2:0]==3'b011)|(ff_data_buf_index[2:0]==3'b100)); |
//every four 148bit, generate an empty signal to the TxModule |
assign toggle = {~ff_data_buf_index[3],3'h0}; //indicate which half buffer is available |
assign toggle = {~ff_data_buf_index[`ff_data_buf_index_len-1],`toggle_lsbs}; //indicate which half buffer is available |
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`ifdef frameIDfromRx |
assign frameid = frameidt[ff_data_buf_index[3]];// |
assign frameid = frameidt[ff_data_buf_index[`ff_data_buf_index_len-1]];// |
`endif |
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always@(negedge ff_clk) //flow the data out of the buffer |
if(start_intra==1'b0) begin //wait the first frame to come |
ff_state <= transfer; |
ff_cnt <= 8'h00; |
ff_data_buf_index <= 4'hf; |
ff_cnt <= 0; |
ff_data_buf_index <= -1; // to fill every bit in ff_data_buf_index with 1s |
ff_en <= 1'b0; |
|
delay_cnt <= `delay_cnt_config; |
109,24 → 132,24
else |
case(ff_state) |
transfer: begin |
delay_cnt <= delay_cnt - `delay_cnt_step; |
delay_cnt <= delay_cnt - 1; |
if(delay_cnt == 0) start <=1'b1; |
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if(ff_cnt==8'h00) begin //load new 148 bits |
{ff_d[146:0],ff_data} <= ff_data_buf[ff_data_buf_index+4'h1]; |
ff_data_buf_index <= ff_data_buf_index + 4'h1; |
ff_cnt <= ff_cnt + 8'h01; |
if(ff_cnt==0) begin //load new 148 bits |
{ff_d[`uframelen-2:0],ff_data} <= ff_data_buf[ff_data_buf_index + 1]; |
ff_data_buf_index <= ff_data_buf_index + 1; |
ff_cnt <= ff_cnt + 1; |
ff_en <= 1'b1; |
end |
else if(ff_cnt == 8'd148) begin //every 148 bit need a gap |
else if(ff_cnt == `uframelen) begin //every 148 bit need a gap |
ff_en <= 1'b0; |
ff_cnt <= 8'h0; |
ff_cnt <= 0; |
ff_state <= gap; |
ff_data <= 1'b0; |
end |
else begin |
{ff_d[146:0],ff_data} <= ff_d; |
ff_cnt <= ff_cnt + 8'h01; |
{ff_d[`uframelen-2:0],ff_data} <= ff_d; |
ff_cnt <= ff_cnt + 1; |
end |
end |
gap: begin //the 8.25 bit gap is implement by (3*8+9)/4 |
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/TxModule.v
2,10 → 2,9
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
|
//Next step, reduce the resource consumed |
|
|
//Next step, add ff_data control to show the IP is busy |
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//version 0.5, defined many parameter to configure the IP core, making it easier to use. |
//version 0.3, declared a new variable data_av, and use it to start sending frame. |
//version 0.3, delete the usage of pre_buf, and rename the pre to preaddlt |
//version 0.3, add the option of frameID mode, by include common.v and judge the macro-varible frameIDfromRx |
12,12 → 11,16
//This module is used to receive data from the demodulate module and send the data to the Ethernet PHY chip |
`include "common.v" |
|
`define tx_data_buf_len 649 //3*8+156.25*4 |
`define tx_data_len 656 //make the length of tx_data_buf be conformed to IEEE802.3 |
`define tx_data_buf_len (`frameidlen+`uframelen*`num_uframe+132) |
//132=8.25*`num_uframe is the space between the uframes |
`define tx_data_madeup 4 //add to tx_data_buf_len to make 132 is dividible by 8 |
`define append_zero 4'h0 |
`define tx_data_len (`tx_data_buf_len+`tx_data_madeup) |
//make the length of tx_data_buf be conformed to IEEE802.3 |
`define ff_sink_cnt_len 12 //make sure 2^ff_sink_cnt_len is larger than or equal to tx_data_buf_len |
`define ff_cnt_init (1+`frameidlen) |
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`define ff_cnt_wide 11 |
`define ff_cnt_init 11'd25 |
`define ff_cnt_step 11'h1 |
`define tx_cnt_len 10 //make sure 2^tx_cnt_len is larger than [(`tx_data_len >> 2) + 51] |
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module TxModule(reset, phy_txd, phy_txen, phy_txclk, phy_txer, |
ff_clk, ff_en, ff_data, |
26,16 → 29,16
frameid, |
`endif |
|
empty, start, |
start, |
test1, test2, test3, test4); |
input phy_txclk, reset; |
input ff_clk, ff_en, ff_data; //ff_clk should be 207.83333KHz |
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`ifdef frameIDfromRx |
input[23:0] frameid; //get the frameid information from RxModule |
input[`frameidlen-1:0] frameid; //get the frameid information from RxModule |
`endif |
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input empty, start; //decide whether should give out the "need-data" ethernet package |
input start; //decide whether should give out the "need-data" ethernet package |
output [3:0] phy_txd; //MII |
output phy_txen, phy_txer; |
|
43,7 → 46,7
reg test1;//, test2, test3, test4; |
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`ifdef frameIDcount |
reg[23:0] frameid=24'h00_00_00; |
reg[`frameidlen-1:0] frameid=0; |
`endif |
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reg[3:0] phy_txd; |
56,9 → 59,9
reg pre_toggle, toggle=1'b0; //helps to decide when to give PC a MAC frame |
reg[`tx_data_len-1:0] tx_data; //used as FIFO |
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reg[`ff_cnt_wide-1:0] ff_cnt=0; |
reg[`ff_sink_cnt_len-1:0] ff_cnt=0; |
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reg[8:0] tx_cnt; |
reg[`tx_cnt_len-1:0] tx_cnt; |
reg data_av; |
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reg Enable_Crc, Initialize_Crc; //declare the variables for the CRC module |
79,8 → 82,8
always @ (posedge ff_clk) begin //receive data from demodulate module every bit one by one |
if(ff_en & start) begin |
if (ff_cnt==0) begin |
tx_data_buf[toggle][`tx_data_buf_len-1:`tx_data_buf_len-25] <= {ff_data, frameid}; |
ff_cnt <= `ff_cnt_init; //11'd25 |
tx_data_buf[toggle][`tx_data_buf_len-1:`tx_data_buf_len-`frameidlen-1] <= {ff_data, frameid}; |
ff_cnt <= `ff_cnt_init; //`frameidlen+1 |
//tosend <= 1'b0; |
end |
else if (ff_cnt == `tx_data_buf_len-1) begin |
90,12 → 93,12
toggle <= ~toggle; |
//every time a frame being sent, frameID increases one |
`ifdef frameIDcount |
frameid <= frameid + 24'h00_00_01; |
frameid <= frameid + 1; |
`endif |
end |
else begin |
tx_data_buf[toggle] <= {ff_data, tx_data_buf[toggle][`tx_data_buf_len-1:1]}; |
ff_cnt <= ff_cnt + `ff_cnt_step; |
ff_cnt <= ff_cnt + 1; |
end |
end |
end |
119,13 → 122,13
end |
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s_pre: //send the preambles |
if(tx_cnt ==9'h00f) |
if(tx_cnt == 15) |
state <= s_add; |
else |
state <= s_pre; |
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s_add: begin //send the destination address, source address and type |
if(tx_cnt==9'h02b) |
if(tx_cnt== 43) |
state <= s_data; |
else |
state <= s_add; |
132,15 → 135,14
end |
s_data: //send data to PHY, every time four bits, lower bits go first |
//test2 <= ~test2; |
if (tx_cnt == (`tx_data_len >> 2)+9'h02b) |
if (tx_cnt == (`tx_data_len >> 2) + 43) |
state <= s_crc; |
else state <= s_data; |
|
s_crc: |
if (tx_cnt == (`tx_data_len >> 2)+9'h033) |
if (tx_cnt == (`tx_data_len >> 2) + 51) |
state <= s_idle; |
else |
state <= s_crc; |
else state <= s_crc; |
|
default: |
state <= s_idle; |
154,11 → 156,11
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always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame |
if (reset) |
tx_cnt <= 9'h000; |
tx_cnt <= 0; |
else if(state==s_idle) |
tx_cnt <= 9'h000; |
tx_cnt <= 0; |
else |
tx_cnt <= tx_cnt + 9'h01; |
tx_cnt <= tx_cnt + 1; |
end |
|
always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame |
167,11 → 169,12
else |
case (state) |
s_idle: begin |
tx_data <= {7'h0,tx_data_buf[~toggle]}; |
tx_data <= {`append_zero, tx_data_buf[~toggle]}; |
//already stored MAC preamble, dest address and source address from right to left. |
//decide whether should ask PC for new frame |
if(empty) preaddlt <= {16'h0008, `MAC_ADD, `PC_MAC_ADD, `Preamble}; |
else preaddlt <= {16'h0000, `MAC_ADD, `PC_MAC_ADD, `Preamble}; |
/*if(empty) preaddlt <= {16'h0008, `MAC_ADD, `PC_MAC_ADD, `Preamble}; |
else*/ |
preaddlt <= {16'h0000, `MAC_ADD, `PC_MAC_ADD, `Preamble}; |
end |
s_pre: |
{preaddlt[171:0], phy_txd} <= preaddlt; |
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/EthernetModule.v
55,7 → 55,7
`ifdef frameIDfromRx |
.frameid(frameid), |
`endif |
.empty(empty), .start(start), |
.start(start), |
.test1(test1), .test2(test2), .test3(test3), .test4(test4)); |
|
RxModule RxModule_inst(.phy_rxd(phy_rxd), .phy_rxen(rxen_in), .phy_rxclk(phy_rxclk), .phy_rxer(phy_rxer), |
63,7 → 63,7
`ifdef frameIDfromRx |
.frameid(frameid), |
`endif |
.empty(empty), .start(start)); |
.start(start)); |
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//assign test1 = ff_en; |
//assign test2 = ff_data; |
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/common.v
2,6 → 2,9
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
|
//Next step, reduce the resource consumed |
|
//version 0.5, defined many parameter to configure the IP core, making it easier to use. |
//version 0.3, create this file to be a common included one for future use to config the IP core |
//This file used to define some macro-varibles which can be used by all other files |
|
13,4 → 16,14
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//The MAC address of this MAC IP core and the other terminal on the Ethernet, can be changed! |
`define MAC_ADD 48'h0100_0000_0000 //mac address: 0x00-00-00-00-00-01 |
`define PC_MAC_ADD 48'hffff_ffff_ffff //mac address of the other terminal |
`define PC_MAC_ADD 48'hffff_ffff_ffff //mac address of the other terminal |
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`define uframelen 148 //148-bit |
`define num_uframe 16 //the number of uframes received once |
//`define num_cover_32 |
`define num_cover_16 |
`define num_cover_8 |
`define num_cover_4 |
|
|
`define frameidlen 24 //the id of the MAC frame |