OpenCores
URL https://opencores.org/ocsvn/RISCMCU/RISCMCU/trunk

Subversion Repositories RISCMCU

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/trunk/vhdl/v_ir.vhd
0,0 → 1,74
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity v_ir is
port( instruction : in std_logic_vector(15 downto 0);
en, clk, clrn : in std_logic;
ir : buffer std_logic_vector(15 downto 0);
imm_value : out std_logic_vector(7 downto 0);
rd, rr : out integer range 0 to 15
);
end v_ir;
 
architecture ir of v_ir is
begin
 
process(clk,clrn)
begin
if clrn = '0' then
ir <= "0000000000000000";
elsif clk'event and clk = '1' then
if en = '1' then
ir <= instruction;
end if;
end if;
end process;
 
imm_value <= ir(11 downto 8) & ir(3 downto 0);
rd <= conv_integer(ir(7 downto 4));
rr <= conv_integer(ir(3 downto 0));
 
end ir;
/trunk/vhdl/v_extint.vhd
0,0 → 1,104
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity v_extint is
port( clk, clrn, extpin, clr_intf : in std_logic;
rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic;
extirq : out std_logic;
c : inout std_logic_vector(7 downto 0));
end v_extint;
 
architecture extint of v_extint is
 
signal int0, flag, currentstate, laststate : std_logic;
signal isc0 : integer range 0 to 3;
 
begin
 
c <= "000000" & conv_std_logic_vector(isc0,2) when rd_mcucr = '1' else
'0' & int0 & "000000" when rd_gimsk = '1' else
"ZZZZZZZZ";
 
extirq <= int0 and not extpin when isc0 = 0 else
int0 and flag;
 
process(clk, clrn)
begin
if clrn = '0' then
int0 <= '0';
isc0 <= 0;
currentstate <= '0';
laststate <= '0';
elsif clk'event and clk = '1' then
if wr_gimsk = '1' then
int0 <= c(6);
end if;
if wr_mcucr = '1' then
isc0 <= conv_integer(c(1 downto 0));
end if;
currentstate <= extpin;
laststate <= currentstate;
end if;
end process;
 
process(clrn, clr_intf, clk, isc0, currentstate)
begin
if clrn = '0' or clr_intf = '1' then
flag <= '0';
elsif clk'event and clk = '1' then
if isc0 = 2 then
if currentstate = '0' and laststate = '1' then
flag <= '1';
end if;
elsif isc0 = 3 then
if currentstate = '1' and laststate = '0' then
flag <= '1';
end if;
end if;
end if;
end process;
 
end extint;
/trunk/vhdl/program.mif
0,0 → 1,165
width = 16;
depth = 512;
 
address_radix = hex;
data_radix = hex;
 
content begin
[0..1ff]: 0;
 
000000:c002;
000001:9518;
000002:9518;
000003:e045;
000004:ef0f;
000005:bb07;
000006:bb01;
000007:bb05;
000008:bb02;
000009:e001;
00000a:bf03;
00000b:e00f;
00000c:bb04;
00000d:e063;
00000e:e071;
00000f:94e8;
000010:d04f;
000011:d015;
000012:bb78;
000013:d047;
000014:d070;
000015:d02c;
000016:d037;
000017:f026;
000018:d01a;
000019:9573;
00001a:bb78;
00001b:cff8;
00001c:d010;
00001d:d067;
00001e:956a;
00001f:d007;
000020:bb78;
000021:d063;
000022:3060;
000023:f349;
000024:d012;
000025:94e8;
000026:cfef;
000027:2f06;
000028:6f00;
000029:bb08;
00002a:d05a;
00002b:d059;
00002c:9508;
00002d:2700;
00002e:bb05;
00002f:d055;
000030:ef0f;
000031:bb05;
000032:9508;
000033:9897;
000034:d050;
000035:9a97;
000036:9508;
000037:d033;
000038:9101;
000039:bb05;
00003a:d04a;
00003b:ef0f;
00003c:bb05;
00003d:e041;
00003e:d046;
00003f:951a;
000040:f7b9;
000041:9508;
000042:d028;
000043:d02a;
000044:9321;
000045:bb25;
000046:d03e;
000047:ef0f;
000048:bb05;
000049:e041;
00004a:d03a;
00004b:951a;
00004c:f7b1;
00004d:9508;
00004e:d01c;
00004f:d00b;
000050:9478;
000051:d00e;
000052:94f8;
000053:9101;
000054:1320;
000055:9468;
000056:d004;
000057:d03d;
000058:951a;
000059:f7a9;
00005a:9508;
00005b:b303;
00005c:7f00;
00005d:3f00;
00005e:f7e1;
00005f:9508;
000060:b323;
000061:7f20;
000062:3f20;
000063:f3e1;
000064:d030;
000065:b303;
000066:7f00;
000067:1702;
000068:f7b9;
000069:9522;
00006a:9508;
00006b:2f17;
00006c:e6e2;
00006d:9508;
00006e:b722;
00006f:3024;
000070:f010;
000071:5024;
000072:cffc;
000073:3020;
000074:f411;
000075:e02e;
000076:c009;
000077:3021;
000078:f411;
000079:e02d;
00007a:c005;
00007b:3022;
00007c:f411;
00007d:e02b;
00007e:c001;
00007f:e027;
000080:b702;
000081:9507;
000082:9507;
000083:bf02;
000084:9508;
000085:2f3e;
000086:e6e0;
000087:8100;
000088:950a;
000089:8300;
00008a:f7d9;
00008b:e6e1;
00008c:8100;
00008d:950a;
00008e:8300;
00008f:f7b1;
000090:954a;
000091:f7a1;
000092:e045;
000093:2fe3;
000094:9508;
000095:2700;
000096:950a;
000097:f7f1;
000098:9508;
 
 
end;
/trunk/vhdl/v_ram.vhd
0,0 → 1,99
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity v_ram is
port( addrbus : in std_logic_vector(7 downto 0);
rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic;
clk, clrn : in std_logic;
c : inout std_logic_vector(7 downto 0)
);
end entity;
architecture ram of v_ram is
 
component lpm_ram_dq
generic( lpm_width: positive := 8;
lpm_widthad: positive := 8;
lpm_numwords: natural := 256;
lpm_file: string := "ram.mif";
lpm_indata: string := "unregistered";
lpm_address_control: string := "unregistered";
lpm_outdata: string := "unregistered"
);
port( data: in std_logic_vector(lpm_width-1 downto 0);
address: in std_logic_vector(lpm_widthad-1 downto 0);
we: in std_logic;
inclock: in std_logic := '0';
outclock: in std_logic := '0';
q: out std_logic_vector(lpm_width-1 downto 0)
);
end component;
 
signal mar, mbr, ram_out : std_logic_vector(7 downto 0);
 
begin
 
sram: lpm_ram_dq
port map(data => mbr, address => mar, we => wr_ram, q => ram_out);
 
c <= ram_out when rd_ram = '1' else
"ZZZZZZZZ";
 
process(clk,clrn)
begin
if clrn = '0' then
mar <= "00000000";
mbr <= "00000000";
elsif clk'event and clk = '1' then
if ld_mbr = '1' then
mbr <= c;
end if;
if ld_mar = '1' then
mar <= addrbus;
end if;
end if;
end process;
 
end ram;
/trunk/vhdl/v_timer.vhd
0,0 → 1,177
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity v_timer is
port( extpin, clr_tov0 : in std_logic;
rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic;
rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic;
clk, clrn : in std_logic;
c : inout std_logic_vector(7 downto 0);
timerirq : out std_logic
);
end v_timer;
 
architecture timer of v_timer is
 
signal toie0, tov0 : std_logic;
signal cs : integer range 0 to 7;
signal tcnt0 : std_logic_vector(7 downto 0);
signal div1, div2, div4, div8, div16, div32, div64, div128, div256, div512, div1024 : std_logic;
signal timerclk, inc_tcnt0, currentstate, laststate : std_logic;
 
begin
 
-- Timer Interrupt Request
timerirq <= toie0 and tov0;
 
-- Read 4 Registers
c <= "000000" & toie0 & "0" when rd_timsk = '1' else
"000000" & tov0 & "0" when rd_tifr = '1' else
conv_std_logic_vector(cs,8) when rd_tccr0 = '1' else
tcnt0 when rd_tcnt0 = '1' else
"ZZZZZZZZ";
 
-- Select Clock Source
with cs select
timerclk <= '0' when 0,
clk when 1,
div8 when 2,
div64 when 3,
div256 when 4,
div1024 when 5,
not extpin when 6,
extpin when 7;
 
-- Timer : clear/write 4 registers, increment timer, set overflow flag, sample clock source
process(clrn, clr_tov0, wr_tifr, c, clk)
begin
if clrn = '0' then
toie0 <= '0';
cs <= 0;
tcnt0 <= "00000000";
tov0 <= '0';
currentstate <= '0';
laststate <= '0';
 
elsif clr_tov0 = '1' or (wr_tifr = '1' and c(1) = '1') then
tov0 <= '0';
 
elsif clk'event and clk = '1' then
 
if wr_tcnt0 = '1' then
tcnt0 <= c;
elsif inc_tcnt0 = '1' then
tcnt0 <= tcnt0 + 1;
if tcnt0 = "11111111" then
tov0 <= '1';
end if;
end if;
 
if wr_timsk = '1' then
toie0 <= c(1);
end if;
if wr_tccr0 = '1' then
cs <= conv_integer(c(2 downto 0));
end if;
 
currentstate <= timerclk;
laststate <= currentstate;
 
end if;
end process;
 
-- Detect rising edge
inc_tcnt0 <= '1' when (laststate ='0' and currentstate = '1') or cs = 1 else
'0';
 
-- 10 bit prescaler
process(clk, clrn)
begin
if clrn = '0' then
div2 <= '0';
div4 <= '0';
div8 <= '0';
div16 <= '0';
div32 <= '0';
div64 <= '0';
div128 <= '0';
div256 <= '0';
div512 <= '0';
div1024 <= '0';
 
elsif clk'event and clk = '1' then
div2 <= not div2;
if div2 = '1' then
div4 <= not div4;
if div4 = '1' then
div8 <= not div8;
if div8 = '1' then
div16 <= not div16;
if div16 = '1' then
div32 <= not div32;
if div32 = '1' then
div64 <= not div64;
if div64 = '1' then
div128 <= not div128;
if div128 = '1' then
div256 <= not div256;
if div256 = '1' then
div512 <= not div512;
if div512 = '1' then
div1024 <= not div1024;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
 
end timer;
/trunk/vhdl/v_controlunit.vhd
0,0 → 1,533
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
entity v_controlunit is
port( ir : in std_logic_vector(15 downto 0);
sr : in std_logic_vector(7 downto 0);
clk, clrn : in std_logic;
skip, extirq, timerirq : in std_logic;
 
en : buffer std_logic;
wr_reg : buffer std_logic;
rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp : out std_logic;
sren : out std_logic_vector (6 downto 0);
 
c2a,c2b : out std_logic;
asel : out integer range 0 to 1;
bsel : out integer range 0 to 3;
bitsel : out integer range 0 to 7;
set : out std_logic;
 
add, subcp, logic, right, dir, pass_a : out std_logic;
 
wcarry : out std_logic;
logicsel : out integer range 0 to 3;
rightsel : out integer range 0 to 2;
dirsel : out integer range 0 to 1;
 
addoffset : out std_logic;
push, pull : out std_logic;
 
cpse, skiptest : out std_logic;
 
bclr,bset : out std_logic;
bld : out std_logic;
cbisbi : out std_logic;
 
vec2, vec4 : buffer std_logic;
 
dest : out integer range 0 to 15;
srsel : out integer range 0 to 7;
offset : out std_logic_vector(8 downto 0);
clr_i, set_i, clr_intf, clr_tov0 : out std_logic;
 
rd_sreg, wr_sreg : out std_logic;
rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic;
rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic;
rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic;
rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic;
rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic
 
);
end v_controlunit;
 
architecture controlunit of v_controlunit is
 
type statetype is (exes, nop2s, nop1s, lds, sts, cbisbis, sbicss, sleeps);
 
signal ibr : std_logic_vector(11 downto 0);
signal state : statetype;
signal one, neg, imm : std_logic;
 
signal
cpcm, sbcm, addm, cpsem, cpm, subm, adcm, andm, eorm, orm, movm,
cpim, sbcim, subim, orim, andim, ldm, stm, comm, negm, swapm, incm,
asrm, lsrm, rorm, decm, bsetm, bclrm, retm, retim, sleepm,
cbisbim, sbicsm, inm, outm, rjmpm, rcallm, ldim,
brbcsm, bldm, bstm, sbrcsm,
ld_incm, ld_decm, st_incm, st_decm : std_logic;
 
signal ioaddr : integer range 0 to 16#3f#;
signal rd_io, wr_io, break, irq, get_io, wr_ram_fast, branchtest, branch, jmp : std_logic;
 
component v_iodecoder
port( ioaddr : in integer range 0 to 16#3f#;
rd_io, wr_io : in std_logic;
rd_sreg, wr_sreg : out std_logic;
rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic;
rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic;
rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic;
rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic;
rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic
);
end component;
 
begin
 
-- Instruction Decoder
-- Decode 51 instructions generate 46 'm signals
-- Combine brbcs+brbs (brbcs) cbi+sbi (cbisbi) sbrc+sbrs (sbrcs) sbic+sbis (sbics)
 
process(ir, wr_reg, get_io, ibr)
begin
 
cpcm <= '0'; sbcm <= '0'; addm <= '0';
cpsem <= '0'; cpm <= '0'; subm <= '0'; adcm <= '0';
andm <= '0'; eorm <= '0'; orm <= '0'; movm <= '0';
cpim <= '0'; sbcim <= '0'; subim <= '0'; orim <= '0'; andim <= '0';
ldm <= '0'; stm <= '0'; comm <= '0'; negm <= '0'; swapm <= '0'; incm <= '0';
asrm <= '0'; lsrm <= '0'; rorm <= '0'; decm <= '0';
bsetm <= '0'; bclrm <= '0'; retm <= '0'; retim <= '0'; sleepm <= '0';
cbisbim <= '0'; sbicsm <= '0';
inm <= '0'; outm <= '0'; rjmpm <= '0'; rcallm <= '0'; ldim <= '0';
brbcsm <= '0'; bldm <= '0'; bstm <= '0'; sbrcsm <= '0';
ld_incm <= '0'; ld_decm <= '0'; st_incm <= '0'; st_decm <= '0';
 
case ir(15 downto 12) is
when "0000" =>
if ir(11 downto 10) = "01" then cpcm <= '1'; end if;
if ir(11 downto 10) = "10" then sbcm <= '1'; end if;
if ir(11 downto 10) = "11" then addm <= '1'; end if;
when "0001" =>
if ir(11 downto 10) = "00" then cpsem<= '1'; end if;
if ir(11 downto 10) = "01" then cpm <= '1'; end if;
if ir(11 downto 10) = "10" then subm <= '1'; end if;
if ir(11 downto 10) = "11" then adcm <= '1'; end if;
when "0010" =>
if ir(11 downto 10) = "00" then andm <= '1'; end if;
if ir(11 downto 10) = "01" then eorm <= '1'; end if;
if ir(11 downto 10) = "10" then orm <= '1'; end if;
if ir(11 downto 10) = "11" then movm <= '1'; end if;
when "0011" =>
cpim <= '1';
when "0100" =>
sbcim <= '1';
when "0101" =>
subim <= '1';
when "0110" =>
orim <= '1';
when "0111" =>
andim <= '1';
when "1000" =>
if ir(11 downto 9) = "000" then ldm <= '1'; end if;
if ir(11 downto 9) = "001" then stm <= '1'; end if;
when "1001" =>
if ir(11 downto 9) = "000" then
if ir(1 downto 0) = "01" then ld_incm <= '1'; end if;
if ir(1 downto 0) = "10" then ld_decm <= '1'; end if;
end if;
if ir(11 downto 9) = "001" then
if ir(1 downto 0) = "01" then st_incm <= '1'; end if;
if ir(1 downto 0) = "10" then st_decm <= '1'; end if;
end if;
if ir(11 downto 9) = "010" then
case ir(3 downto 0) is
when "0000" => comm <= '1';
when "0001" => negm <= '1';
when "0010" => swapm <= '1';
when "0011" => incm <= '1';
when "0101" => asrm <= '1';
when "0110" => lsrm <= '1';
when "0111" => rorm <= '1';
when "1010" => decm <= '1';
when "1000" =>
if ir(8 downto 7) = "00" then bsetm <= '1'; end if;
if ir(8 downto 7) = "01" then bclrm <= '1'; end if;
if ir(8 downto 7) & ir(4) = "100" then retm <= '1'; end if;
if ir(8 downto 7) & ir(4) = "101" then retim <= '1'; end if;
if ir(8 downto 7) = "11" then sleepm <= '1'; end if;
when others =>
end case;
elsif ir(11 downto 10) = "10" then
if ir(8) = '0' then cbisbim <= '1'; -- cbi, sbi
else sbicsm <= '1'; end if; -- sbic, sbis
end if;
when "1011" =>
if ir(11) = '0' then inm <= '1';
else outm <= '1';
end if;
when "1100" =>
rjmpm <= '1';
when "1101" =>
rcallm <= '1';
when "1110" =>
ldim <= '1';
when "1111" =>
if ir(11) = '0' then brbcsm <= '1'; end if;
if ir(11 downto 9) = "100" then bldm <= '1'; end if;
if ir(11 downto 9) = "101" then bstm <= '1'; end if;
if ir(11 downto 10) = "11" then sbrcsm <= '1'; end if;-- sbrc, sbrs
when others =>
end case;
 
 
-- Generate Fetch Stage Signals : C2A and C2B (C2A active also when fetch I/O)
if ((ibr(7 downto 4) = ir(7 downto 4)) and wr_reg = '1') or get_io = '1' then
c2a <= '1';
else
c2a <= '0';
end if;
 
if (ibr(7 downto 4) = ir(3 downto 0)) and wr_reg = '1' then
c2b <= '1';
else
c2b <= '0';
end if;
 
end process;
 
-- Generate wcarry, logicsel, rightsel and dirsel
-- Load IBR with IR when EN active
process(clk,clrn)
begin
if clrn = '0' then
ibr <= "000000000000";
 
wcarry <= '0';
logicsel <= 0;
rightsel <= 0;
dirsel <= 0;
 
elsif clk'event and clk = '1' then
if en = '1' then
ibr <= ir(11 downto 0);
end if;
 
wcarry <= adcm or sbcm or sbcim or cpcm;
 
if orm = '1' or orim = '1' then logicsel <= 1;
elsif eorm = '1' then logicsel <= 2;
elsif comm = '1' then logicsel <= 3;
else logicsel <= 0;
end if;
if rorm = '1' then rightsel <= 1;
elsif asrm = '1' then rightsel <= 2;
else rightsel <= 0;
end if;
if swapm = '1' then dirsel <= 1;
else dirsel <= 0;
end if;
end if;
end process;
 
 
-- Finite State Machine
 
irq <= (timerirq or extirq) and sr(7);
break <= branch or skip or irq;
 
process(clk, clrn)
begin
 
if clrn = '0' then
 
state <= exes;
 
en <= '1'; get_io <= '0';
pass_a <= '0'; wr_reg <= '0'; sren <= "0000000";
rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0';
ld_mar <= '0'; ld_mbr <= '0'; inc_zp <= '0'; dec_zp <= '0';
add <= '0'; subcp <= '0'; logic <= '0'; right <= '0'; dir <= '0';
jmp <= '0'; push <= '0'; pull <= '0'; branchtest <= '0';
bclr <= '0'; bset <= '0'; bld <= '0';
cpse <= '0'; skiptest <= '0';
cbisbi <= '0';
vec2 <= '0'; vec4 <= '0'; set_i <= '0';
 
elsif clk'event and clk = '1' then
 
en <= '1'; get_io <= '0';
pass_a <= '0'; wr_reg <= '0'; sren <= "0000000";
rd_io <= '0'; wr_io <= '0'; rd_ram <= '0'; wr_ram_fast <= '0';
ld_mar <= '0'; ld_mbr <= '0'; inc_zp <= '0'; dec_zp <= '0';
add <= '0'; subcp <= '0'; logic <= '0'; right <= '0'; dir <= '0';
jmp <= '0'; push <= '0'; pull <= '0'; branchtest <= '0';
bclr <= '0'; bset <= '0'; bld <= '0';
cpse <= '0'; skiptest <= '0';
cbisbi <= '0';
vec2 <= '0'; vec4 <= '0'; set_i <= '0';
 
case state is
 
when exes =>
if break = '1' then
 
if branch = '1' then
state <= nop1s;
 
elsif skip = '1' then
 
elsif irq = '1' then
state <= nop2s;
push <= '1';
if extirq = '1' then
vec2 <= '1';
else
vec4 <= '1';
end if;
end if;
 
else
 
if rjmpm = '1' or rcallm = '1' or retm = '1' or retim = '1' then
state <= nop2s;
elsif cbisbim = '1' then
state <= cbisbis;
elsif sbicsm = '1' then
state <= sbicss;
elsif ldm = '1' or ld_incm = '1' or ld_decm = '1' then
state <= lds;
elsif stm = '1' or st_incm = '1' or st_decm = '1' then
state <= sts;
elsif sleepm = '1' then
state <= sleeps;
end if;
 
-- PC signals
jmp <= rjmpm or rcallm; -- encoded
push <= rcallm;
pull <= retm or retim;
 
-- PC and IR signals
en <= not (cbisbim or sbicsm
or stm or st_incm or st_decm or
ldm or ld_incm or ld_decm);
 
-- General Purpose Register File signals
wr_reg <= addm or adcm or incm
or subm or subim or sbcm or sbcim or decm or negm
or andm or andim or orm or orim or eorm or comm
or lsrm or rorm or asrm
or ldim or movm or swapm
or inm;
inc_zp <= ld_incm or st_incm;
dec_zp <= ld_decm or st_decm;
 
-- ALU signals
add <= addm or adcm or incm;
subcp <= subm or subim or sbcm or sbcim or decm or negm
or cpm or cpim or cpcm;
logic <= andm or andim or orm or orim or eorm or comm;
right <= lsrm or rorm or asrm;
dir <= ldim or movm or swapm;
bld <= bldm;
pass_a <= outm or stm or st_incm or st_decm;
cpse <= cpsem;
skiptest <= sbrcsm;
 
 
-- SR signals
bclr <= bclrm;
bset <= bsetm;
set_i <= retim;
 
sren(0) <= addm or adcm
or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm
or comm
or lsrm or rorm or asrm;
 
for i in 1 to 4 loop
sren(i) <= addm or adcm or incm
or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or decm or negm
or andm or andim or orm or orim or eorm or comm
or lsrm or rorm or asrm;
end loop;
 
sren(5) <= addm or adcm
or subm or subim or sbcm or sbcim or cpm or cpcm or cpim or negm;
sren(6) <= bstm;
 
-- Data RAM signals
ld_mar <= ldm or ld_incm or ld_decm or stm or st_incm or st_decm;
ld_mbr <= stm or st_incm or st_decm;
-- I/O decoder signals
wr_io <= outm;
rd_io <= inm or sbicsm or cbisbim;
if inm = '1' or outm = '1' then
ioaddr <= conv_integer(ir(10 downto 9) & ir(3 downto 0));
else
ioaddr <= conv_integer('0' & ir(7 downto 3));
end if;
 
 
-- Branch Evaluation Unit signal
branchtest <= brbcsm;
 
 
-- Fetch I/O, generate C2A
get_io <= cbisbim or sbicsm;
 
end if;
 
when nop2s =>
state <= nop1s;
 
when nop1s =>
state <= exes;
 
when cbisbis =>
state <= exes;
cbisbi <= '1';
wr_io <= '1';
when sbicss =>
state <= exes;
skiptest <= '1';
 
when lds =>
state <= exes;
wr_reg <= '1';
rd_ram <= '1';
 
when sts =>
state <= exes;
wr_ram_fast <= '1';
 
when sleeps =>
en <= '0';
if irq = '1' then
en <= '1';
state <= nop2s;
push <= '1';
if extirq = '1' then
vec2 <= '1';
else
vec4 <= '1';
end if;
end if;
 
end case;
end if;
end process;
 
-- Generate Delayed WR_RAM signal to avoid writing to wrong address
process(state, wr_ram_fast)
begin
if state = exes then
wr_ram <= wr_ram_fast;
else
wr_ram <= '0';
end if;
end process;
 
 
-- Branch Evaluation Unit
process(branchtest, sr, ibr)
begin
if branchtest = '1' and (sr(conv_integer(ibr(2 downto 0))) = not ibr(10)) then
branch <= '1';
else
branch <= '0';
end if;
end process;
 
 
-- IO address decoder
iodec : v_iodecoder
port map (ioaddr, rd_io, wr_io, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind);
 
 
-- Intruction Buffer Register (IBR) to signals ------------------
dest <= conv_integer(ibr(7 downto 4));
srsel <= conv_integer(ibr(6 downto 4));
set <= ibr(9);
bitsel <= conv_integer(ibr(2 downto 0));
offset <= ibr(8 downto 0) when jmp = '1' else
ibr(9) & ibr(9) & ibr(9 downto 3);
 
 
-- Generate Fetch Stage Signals : ASEL and SEL
imm <= subim or sbcim or cpim or andim or orim or ldim;
one <= incm or decm;
neg <= negm;
 
asel <= 1 when neg = '1' and get_io = '0' else
0;
bsel <= 1 when neg = '1' else
2 when imm = '1' else
3 when one = '1' else
0;
 
 
-- Decode Control Signal
addoffset <= branch or jmp; -- PC
clr_i <= vec2 or vec4; -- PC
clr_intf <= vec2; -- External Interrupt
clr_tov0 <= vec4; -- Timer
 
end controlunit;
 
 
/trunk/vhdl/v_alu.vhd
0,0 → 1,295
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.lpm_components.all;
 
entity v_alu is
port( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);
c2a, c2b : in std_logic;
asel : in integer range 0 to 1;
bsel : in integer range 0 to 3;
 
bitsel : in integer range 0 to 7;
set : in std_logic;
c_flag, t_flag : in std_logic;
add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic;
cpse, skiptest : in std_logic;
 
wcarry : in std_logic;
logicsel : in integer range 0 to 3;
rightsel : in integer range 0 to 2;
dirsel : in integer range 0 to 1;
 
clk, clrn : in std_logic;
 
c : buffer std_logic_vector(7 downto 0);
tosr : buffer std_logic_vector (6 downto 0);
skip : out std_logic
);
 
end v_alu;
 
architecture alu of v_alu is
 
signal a, b : std_logic_vector(7 downto 0);
 
signal sr : std_logic_vector(6 downto 0);
 
signal cin, overflow, cout : std_logic;
 
signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0);
 
begin
 
-- Operand Fetch Unit --
 
process(clrn, clk)
begin
if clrn = '0' then
a <= "00000000";
b <= "00000000";
elsif clk'event and clk = '1' then
case asel is
when 0 =>
if c2a = '1' then
a <= c;
else
a <= reg_rd;
end if;
when 1 =>
a <= "00000000";
end case;
 
case bsel is
when 0 =>
if c2b = '1' then
b <= c;
else
b <= reg_rr;
end if;
when 1 =>
b <= reg_rd;
when 2 =>
b <= imm_value;
when 3 =>
b <= "00000001";
end case;
end if;
end process;
 
 
-- Execution Unit --
 
cin <= c_flag when add = '1' and wcarry = '1' else
'0' when add = '1' and wcarry = '0' else
not c_flag when wcarry = '1' else
'1';
 
 
-- Adder-Subtracter
adder1 : lpm_add_sub
generic map(lpm_width => 8)
port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow);
 
-- Logic Unit
with logicsel select
logic_out <= a and b when 0, -- and, andi
a or b when 1, -- or, ori
a xor b when 2, -- eor
not a when 3; -- com
 
-- Shifter
right_out(6 downto 0) <= a(7 downto 1);
with rightsel select
right_out(7) <= '0' when 0, -- lsr
c_flag when 1, -- ror
a(7) when 2; -- asr
 
-- Direct Unit
with dirsel select
dir_out <= b when 0, -- ldi, mov
(a(3 downto 0) & a(7 downto 4)) when 1; -- swap
 
-- Bit Loader
process(bld, bitsel, a, t_flag, set)
begin
for i in 0 to 7 loop
if i /= bitsel then
bldcbi_out(i) <= a(i);
elsif bld = '1' then
bldcbi_out(i) <= t_flag;
else
bldcbi_out(i) <= set;
end if;
end loop;
end process;
 
-- Results to Data Bus
process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a)
begin
 
c <= "ZZZZZZZZ";
 
-- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg
if add = '1' or subcp = '1' then
c <= sum;
end if;
 
-- and, andi, or, ori, eor, com
if logic = '1' then
c <= logic_out;
end if;
 
-- lsr, lsr, asr
if right = '1' then
c <= right_out;
end if;
 
-- ldi, mov, swap
if dir = '1' then
c <= dir_out;
end if;
 
-- bld, cbisbi
if bld = '1' or cbisbi = '1' then
c <= bldcbi_out;
end if;
 
-- out, st z, st z+, st -z
if pass_a = '1' then
c <= a;
end if;
 
end process;
 
 
-- Skip Evaluation Unit --
process(cpse, skiptest, a, b, set, bitsel, c)
begin
 
skip <= '0';
-- cpse
if cpse = '1' then
if a = b then
skip <= '1';
end if;
 
-- sbrc, sbrs
elsif skiptest = '1' then
if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then
skip <= '1';
end if;
 
end if;
end process;
 
-- Flags Evaluation Unit --
process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel)
begin
 
-- C sr(0)
if add = '1' then
sr(0) <= cout;
elsif right = '1' then
sr(0) <= a(0);
elsif logic = '1' then -- com
sr(0) <= '1';
else -- subcp
sr(0) <= not cout;
--sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7));
end if;
 
-- Z sr(1)
if (add = '1' or subcp = '1') and sum = "00000000" then
sr(1) <= '1';
elsif logic = '1' and logic_out = "00000000" then
sr(1) <= '1';
elsif right = '1' and right_out = "00000000" then
sr(1) <= '1';
else
sr(1) <= '0';
end if;
 
-- N sr(2)
if (add = '1' or subcp = '1') and sum(7) = '1' then
sr(2) <= '1';
elsif logic = '1' and logic_out(7) = '1' then
sr(2) <= '1';
elsif right = '1' and right_out(7) = '1' then
sr(2) <= '1';
else
sr(2) <= '0';
end if;
 
-- V sr(3)
if right = '1' then
sr(3) <= right_out(7) xor a(0);
elsif logic = '1' then
sr(3) <= '0';
else
sr(3) <= overflow;
end if;
 
-- S sr(4)
sr(4) <= sr(2) xor sr(3);
 
-- H sr(5)
if add = '1' then
sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3));
else -- subcp
sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3));
end if;
 
-- T sr(6)
sr(6) <= a(bitsel);
 
end process;
 
tosr <= sr;
 
end alu;
/trunk/vhdl/v_port_bit.vhd
0,0 → 1,83
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity v_port_bit is
port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic;
clk,clrn : in std_logic;
c : inout std_logic;
pin : inout std_logic
);
end v_port_bit;
 
architecture port_bit of v_port_bit is
 
signal datareg, ddr : std_logic;
 
begin
 
c <= datareg when rd_port = '1' else
ddr when rd_ddr = '1' else
pin when rd_pin = '1' else
'Z';
 
pin <= datareg when ddr = '1' else
'Z';
 
process(clrn, clk)
begin
if clrn = '0' then
datareg <= '0';
ddr <= '0';
elsif clk'event and clk = '1' then
if wr_port = '1' then
datareg <= c;
end if;
if wr_ddr = '1' then
ddr <= c;
end if;
end if;
end process;
 
end port_bit;
 
/trunk/vhdl/v_sr.vhd
0,0 → 1,86
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity v_sr is
port( clk,clrn: in std_logic;
sren,tosr : in std_logic_vector(6 downto 0);
srsel : in integer range 0 to 7;
clr_i,set_i,bset,bclr : in std_logic;
rd_sreg, wr_sreg : in std_logic;
c : inout std_logic_vector(7 downto 0);
sr : inout std_logic_vector(7 downto 0)
);
end v_sr;
 
architecture sr of v_sr is
begin
 
c <= sr when rd_sreg = '1' else
"ZZZZZZZZ";
 
process(clk,clrn,rd_sreg,sr)
begin
if clrn = '0' then
sr <= "00000000";
elsif clk'event and clk = '1' then
if wr_sreg = '1' then
sr <= c;
elsif bset = '1' or bclr = '1' then
sr(srsel) <= bset;
elsif clr_i = '1' or set_i = '1' then
sr(7) <= set_i;
else
for i in 0 to 6 loop
if sren(i) = '1' then
sr(i) <= tosr(i);
end if;
end loop;
end if;
end if;
 
end process;
 
end sr;
 
 
/trunk/vhdl/ram.mif
0,0 → 1,10
width = 8;
depth = 256;
 
address_radix = hex;
data_radix = hex;
 
content begin
[0..ff]: 0;
 
end;
/trunk/vhdl/v_port.vhd
0,0 → 1,71
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity v_port is
port( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic;
clk, clrn : in std_logic;
c : inout std_logic_vector(7 downto 0);
pin : inout std_logic_vector(7 downto 0)
);
end v_port;
 
architecture ioport of v_port is
 
component v_port_bit
port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic;
clk,clrn : in std_logic;
c : inout std_logic;
pin : inout std_logic
);
end component;
 
begin
 
g1:
for i in 0 to 7 generate
u1 : v_port_bit
port map (rd_port, wr_port, rd_ddr, wr_ddr, rd_pin, clk, clrn, c(i), pin(i));
end generate;
 
end ioport;
/trunk/vhdl/v_gpr.vhd
0,0 → 1,87
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity v_gpr is
port( c : in std_logic_vector(7 downto 0);
wr_reg, inc_zp, dec_zp : in std_logic;
rd, rr, dest : in integer range 0 to 15;
clk, clrn : in std_logic;
reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0)
);
end v_gpr;
 
architecture gpr of v_gpr is
 
type regfiletype is array (0 to 15) of std_logic_vector(7 downto 0);
 
signal reg : regfiletype;
 
begin
 
addrbus <= reg(14) - 16#61# when dec_zp = '1' else
reg(14) - 16#60#;
 
reg_rd <= reg(rd);
reg_rr <= reg(rr);
 
process(clk, clrn)
begin
if clrn = '0' then
for i in 0 to 15 loop
reg(i) <= "00000000";
end loop;
elsif clk'event and clk = '1' then
if wr_reg = '1' then
reg(dest) <= c;
end if;
if inc_zp = '1' then
reg(14) <= reg(14) + 1;
elsif dec_zp = '1' then
reg(14) <= reg(14) - 1;
end if;
end if;
end process;
 
end gpr;
/trunk/vhdl/license.txt
0,0 → 1,144
GNU LESSER GENERAL PUBLIC LICENSE
Version 2.1, February 1999
 
 
Copyright (C) 1991, 1999 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
 
[This is the first released version of the Lesser GPL. It also counts
as the successor of the GNU Library Public License, version 2, hence
the version number 2.1.]
 
Preamble
The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public Licenses are intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users.
 
This license, the Lesser General Public License, applies to some specially designated software packages--typically libraries--of the Free Software Foundation and other authors who decide to use it. You can use it too, but we suggest you first think carefully about whether this license or the ordinary General Public License is the better strategy to use in any particular case, based on the explanations below.
 
When we speak of free software, we are referring to freedom of use, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish); that you receive source code or can get it if you want it; that you can change the software and use pieces of it in new free programs; and that you are informed that you can do these things.
 
To protect your rights, we need to make restrictions that forbid distributors to deny you these rights or to ask you to surrender these rights. These restrictions translate to certain responsibilities for you if you distribute copies of the library or if you modify it.
 
For example, if you distribute copies of the library, whether gratis or for a fee, you must give the recipients all the rights that we gave you. You must make sure that they, too, receive or can get the source code. If you link other code with the library, you must provide complete object files to the recipients, so that they can relink them with the library after making changes to the library and recompiling it. And you must show them these terms so they know their rights.
 
We protect your rights with a two-step method: (1) we copyright the library, and (2) we offer you this license, which gives you legal permission to copy, distribute and/or modify the library.
 
To protect each distributor, we want to make it very clear that there is no warranty for the free library. Also, if the library is modified by someone else and passed on, the recipients should know that what they have is not the original version, so that the original author's reputation will not be affected by problems that might be introduced by others.
 
Finally, software patents pose a constant threat to the existence of any free program. We wish to make sure that a company cannot effectively restrict the users of a free program by obtaining a restrictive license from a patent holder. Therefore, we insist that any patent license obtained for a version of the library must be consistent with the full freedom of use specified in this license.
 
Most GNU software, including some libraries, is covered by the ordinary GNU General Public License. This license, the GNU Lesser General Public License, applies to certain designated libraries, and is quite different from the ordinary General Public License. We use this license for certain libraries in order to permit linking those libraries into non-free programs.
 
When a program is linked with a library, whether statically or using a shared library, the combination of the two is legally speaking a combined work, a derivative of the original library. The ordinary General Public License therefore permits such linking only if the entire combination fits its criteria of freedom. The Lesser General Public License permits more lax criteria for linking other code with the library.
 
We call this license the "Lesser" General Public License because it does Less to protect the user's freedom than the ordinary General Public License. It also provides other free software developers Less of an advantage over competing non-free programs. These disadvantages are the reason we use the ordinary General Public License for many libraries. However, the Lesser license provides advantages in certain special circumstances.
 
For example, on rare occasions, there may be a special need to encourage the widest possible use of a certain library, so that it becomes a de-facto standard. To achieve this, non-free programs must be allowed to use the library. A more frequent case is that a free library does the same job as widely used non-free libraries. In this case, there is little to gain by limiting the free library to free software only, so we use the Lesser General Public License.
 
In other cases, permission to use a particular library in non-free programs enables a greater number of people to use a large body of free software. For example, permission to use the GNU C Library in non-free programs enables many more people to use the whole GNU operating system, as well as its variant, the GNU/Linux operating system.
 
Although the Lesser General Public License is Less protective of the users' freedom, it does ensure that the user of a program that is linked with the Library has the freedom and the wherewithal to run that program using a modified version of the Library.
 
The precise terms and conditions for copying, distribution and modification follow. Pay close attention to the difference between a "work based on the library" and a "work that uses the library". The former contains code derived from the library, whereas the latter must be combined with the library in order to run.
 
 
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License Agreement applies to any software library or other program which contains a notice placed by the copyright holder or other authorized party saying it may be distributed under the terms of this Lesser General Public License (also called "this License"). Each licensee is addressed as "you".
 
A "library" means a collection of software functions and/or data prepared so as to be conveniently linked with application programs (which use some of those functions and data) to form executables.
 
The "Library", below, refers to any such software library or work which has been distributed under these terms. A "work based on the Library" means either the Library or any derivative work under copyright law: that is to say, a work containing the Library or a portion of it, either verbatim or with modifications and/or translated straightforwardly into another language. (Hereinafter, translation is included without limitation in the term "modification".)
 
"Source code" for a work means the preferred form of the work for making modifications to it. For a library, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the library.
 
Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running a program using the Library is not restricted, and output from such a program is covered only if its contents constitute a work based on the Library (independent of the use of the Library in a tool for writing it). Whether that is true depends on what the Library does and what the program that uses the Library does.
 
1. You may copy and distribute verbatim copies of the Library's complete source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and distribute a copy of this License along with the Library.
 
You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee.
 
2. You may modify your copy or copies of the Library or any portion of it, thus forming a work based on the Library, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions:
 
 
a) The modified work must itself be a software library.
b) You must cause the files modified to carry prominent notices stating that you changed the files and the date of any change.
c) You must cause the whole of the work to be licensed at no charge to all third parties under the terms of this License.
d) If a facility in the modified Library refers to a function or a table of data to be supplied by an application program that uses the facility, other than as an argument passed when the facility is invoked, then you must make a good faith effort to ensure that, in the event an application does not supply such function or table, the facility still operates, and performs whatever part of its purpose remains meaningful.
(For example, a function in a library to compute square roots has a purpose that is entirely well-defined independent of the application. Therefore, Subsection 2d requires that any application-supplied function or table used by this function must be optional: if the application does not supply it, the square root function must still compute square roots.)
 
These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Library, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Library, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it.
 
Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Library.
 
In addition, mere aggregation of another work not based on the Library with the Library (or with a work based on the Library) on a volume of a storage or distribution medium does not bring the other work under the scope of this License.
 
3. You may opt to apply the terms of the ordinary GNU General Public License instead of this License to a given copy of the Library. To do this, you must alter all the notices that refer to this License, so that they refer to the ordinary GNU General Public License, version 2, instead of to this License. (If a newer version than version 2 of the ordinary GNU General Public License has appeared, then you can specify that version instead if you wish.) Do not make any other change in these notices.
 
Once this change is made in a given copy, it is irreversible for that copy, so the ordinary GNU General Public License applies to all subsequent copies and derivative works made from that copy.
 
This option is useful when you wish to copy part of the code of the Library into a program that is not a library.
 
4. You may copy and distribute the Library (or a portion or derivative of it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange.
 
If distribution of object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place satisfies the requirement to distribute the source code, even though third parties are not compelled to copy the source along with the object code.
 
5. A program that contains no derivative of any portion of the Library, but is designed to work with the Library by being compiled or linked with it, is called a "work that uses the Library". Such a work, in isolation, is not a derivative work of the Library, and therefore falls outside the scope of this License.
 
However, linking a "work that uses the Library" with the Library creates an executable that is a derivative of the Library (because it contains portions of the Library), rather than a "work that uses the library". The executable is therefore covered by this License. Section 6 states terms for distribution of such executables.
 
When a "work that uses the Library" uses material from a header file that is part of the Library, the object code for the work may be a derivative work of the Library even though the source code is not. Whether this is true is especially significant if the work can be linked without the Library, or if the work is itself a library. The threshold for this to be true is not precisely defined by law.
 
If such an object file uses only numerical parameters, data structure layouts and accessors, and small macros and small inline functions (ten lines or less in length), then the use of the object file is unrestricted, regardless of whether it is legally a derivative work. (Executables containing this object code plus portions of the Library will still fall under Section 6.)
 
Otherwise, if the work is a derivative of the Library, you may distribute the object code for the work under the terms of Section 6. Any executables containing that work also fall under Section 6, whether or not they are linked directly with the Library itself.
 
6. As an exception to the Sections above, you may also combine or link a "work that uses the Library" with the Library to produce a work containing portions of the Library, and distribute that work under terms of your choice, provided that the terms permit modification of the work for the customer's own use and reverse engineering for debugging such modifications.
 
You must give prominent notice with each copy of the work that the Library is used in it and that the Library and its use are covered by this License. You must supply a copy of this License. If the work during execution displays copyright notices, you must include the copyright notice for the Library among them, as well as a reference directing the user to the copy of this License. Also, you must do one of these things:
 
 
a) Accompany the work with the complete corresponding machine-readable source code for the Library including whatever changes were used in the work (which must be distributed under Sections 1 and 2 above); and, if the work is an executable linked with the Library, with the complete machine-readable "work that uses the Library", as object code and/or source code, so that the user can modify the Library and then relink to produce a modified executable containing the modified Library. (It is understood that the user who changes the contents of definitions files in the Library will not necessarily be able to recompile the application to use the modified definitions.)
b) Use a suitable shared library mechanism for linking with the Library. A suitable mechanism is one that (1) uses at run time a copy of the library already present on the user's computer system, rather than copying library functions into the executable, and (2) will operate properly with a modified version of the library, if the user installs one, as long as the modified version is interface-compatible with the version that the work was made with.
c) Accompany the work with a written offer, valid for at least three years, to give the same user the materials specified in Subsection 6a, above, for a charge no more than the cost of performing this distribution.
d) If distribution of the work is made by offering access to copy from a designated place, offer equivalent access to copy the above specified materials from the same place.
e) Verify that the user has already received a copy of these materials or that you have already sent this user a copy.
For an executable, the required form of the "work that uses the Library" must include any data and utility programs needed for reproducing the executable from it. However, as a special exception, the materials to be distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable.
 
It may happen that this requirement contradicts the license restrictions of other proprietary libraries that do not normally accompany the operating system. Such a contradiction means you cannot use both them and the Library together in an executable that you distribute.
 
7. You may place library facilities that are a work based on the Library side-by-side in a single library together with other library facilities not covered by this License, and distribute such a combined library, provided that the separate distribution of the work based on the Library and of the other library facilities is otherwise permitted, and provided that you do these two things:
 
 
a) Accompany the combined library with a copy of the same work based on the Library, uncombined with any other library facilities. This must be distributed under the terms of the Sections above.
b) Give prominent notice with the combined library of the fact that part of it is a work based on the Library, and explaining where to find the accompanying uncombined form of the same work.
8. You may not copy, modify, sublicense, link with, or distribute the Library except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense, link with, or distribute the Library is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance.
 
9. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Library or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Library (or any work based on the Library), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Library or works based on it.
 
10. Each time you redistribute the Library (or any work based on the Library), the recipient automatically receives a license from the original licensor to copy, distribute, link with or modify the Library subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties with this License.
 
11. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Library at all. For example, if a patent license would not permit royalty-free redistribution of the Library by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Library.
 
If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply, and the section as a whole is intended to apply in other circumstances.
 
It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice.
 
This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License.
 
12. If the distribution and/or use of the Library is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Library under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License.
 
13. The Free Software Foundation may publish revised and/or new versions of the Lesser General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.
 
Each version is given a distinguishing version number. If the Library specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Library does not specify a license version number, you may choose any version ever published by the Free Software Foundation.
 
14. If you wish to incorporate parts of the Library into other free programs whose distribution conditions are incompatible with these, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally.
 
NO WARRANTY
 
15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
 
16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
 
 
END OF TERMS AND CONDITIONS
/trunk/vhdl/v_iodecoder.vhd
0,0 → 1,144
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity v_iodecoder is
port( ioaddr : in integer range 0 to 16#3f#;
rd_io, wr_io : in std_logic;
rd_sreg, wr_sreg : out std_logic;
rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic;
rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic;
rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic;
rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic;
rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic
);
end v_iodecoder;
 
architecture iodecoder of v_iodecoder is
begin
 
process(rd_io, ioaddr)
begin
 
rd_sreg <= '0';
rd_gimsk <= '0';
rd_timsk <= '0';
rd_tifr <= '0';
rd_mcucr <= '0';
rd_tccr0 <= '0';
rd_tcnt0 <= '0';
 
rd_portb <= '0';
rd_ddrb <= '0';
rd_pinb <= '0';
rd_portc <= '0';
rd_ddrc <= '0';
rd_pinc <= '0';
rd_portd <= '0';
rd_ddrd <= '0';
rd_pind <= '0';
 
if rd_io = '1' then
case ioaddr is
when 16#3f# => rd_sreg <= '1';
when 16#3b# => rd_gimsk <= '1';
when 16#39# => rd_timsk <= '1';
when 16#38# => rd_tifr <= '1';
when 16#35# => rd_mcucr <= '1';
when 16#33# => rd_tccr0 <= '1';
when 16#32# => rd_tcnt0 <= '1';
 
when 16#18# => rd_portb <= '1';
when 16#17# => rd_ddrb <= '1';
when 16#16# => rd_pinb <= '1';
when 16#15# => rd_portc <= '1';
when 16#14# => rd_ddrc <= '1';
when 16#13# => rd_pinc <= '1';
when 16#12# => rd_portd <= '1';
when 16#11# => rd_ddrd <= '1';
when 16#10# => rd_pind <= '1';
when others =>
end case;
end if;
end process;
 
process(wr_io, ioaddr)
begin
 
wr_sreg <= '0';
wr_gimsk <= '0';
wr_timsk <= '0';
wr_tifr <= '0';
wr_mcucr <= '0';
wr_tccr0 <= '0';
wr_tcnt0 <= '0';
wr_portb <= '0';
wr_ddrb <= '0';
wr_portc <= '0';
wr_ddrc <= '0';
wr_portd <= '0';
wr_ddrd <= '0';
 
if wr_io = '1' then
case ioaddr is
when 16#3f# => wr_sreg <= '1';
when 16#3b# => wr_gimsk <= '1';
when 16#39# => wr_timsk <= '1';
when 16#38# => wr_tifr <= '1';
when 16#35# => wr_mcucr <= '1';
when 16#33# => wr_tccr0 <= '1';
when 16#32# => wr_tcnt0 <= '1';
 
when 16#18# => wr_portb <= '1';
when 16#17# => wr_ddrb <= '1';
when 16#15# => wr_portc <= '1';
when 16#14# => wr_ddrc <= '1';
when 16#12# => wr_portd <= '1';
when 16#11# => wr_ddrd <= '1';
when others =>
end case;
end if;
end process;
 
end iodecoder;
/trunk/vhdl/v_rom.vhd
0,0 → 1,80
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity v_rom is
port( pc : in std_logic_vector(8 downto 0);
instruction : out std_logic_vector(15 downto 0));
end v_rom;
 
architecture rom of v_rom is
 
component LPM_ROM
generic (
LPM_WIDTH: integer := 16;
LPM_WIDTHAD: integer := 9;
LPM_NUMWORDS: integer := 512;
LPM_FILE: string := "program.mif";
LPM_ADDRESS_CONTROL: string := "UNREGISTERED";
LPM_OUTDATA: string := "UNREGISTERED"
);
port (
ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
inclock: IN STD_LOGIC := '0';
outclock: IN STD_LOGIC := '0';
memenab: IN STD_LOGIC := '1';
Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
);
end component;
 
signal gnd, vcc : std_logic;
 
begin
 
vcc <= '1';
gnd <= '0';
 
v1 : LPM_ROM
port map (address => pc, memenab => vcc, q => instruction);
 
end rom;
/trunk/vhdl/v_freqdiv.vhd
0,0 → 1,67
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity v_freqdiv is
port( clock : in std_logic;
div2, div4, div8, div16 : buffer std_logic);
end v_freqdiv;
 
architecture myfreqdiv of v_freqdiv is
begin
process(clock)
begin
if clock'event and clock = '1' then
div2 <= not div2;
if div2 = '1' then
div4 <= not div4;
if div4 = '1' then
div8 <= not div8;
if div8 = '1' then
div16 <= not div16;
end if;
end if;
end if;
end if;
end process;
end myfreqdiv;
/trunk/vhdl/v_pc.vhd
0,0 → 1,101
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity v_pc is
port( offset : in std_logic_vector(8 downto 0);
en, addoffset, push, pull, vec2, vec4 : in std_logic;
clk, clrn : in std_logic;
pc : buffer std_logic_vector(8 downto 0)
);
end v_pc;
 
architecture pc of v_pc is
constant vector2 : std_logic_vector(8 downto 0) := "000000001";
constant vector4 : std_logic_vector(8 downto 0) := "000000010";
signal pcb, stack0, stack1, stack2, stack3 : std_logic_vector(8 downto 0);
begin
 
process(clk, clrn)
begin
if clrn = '0' then
pc <= "000000000";
pcb <= "000000000";
stack0 <= "000000000";
stack1 <= "000000000";
stack2 <= "000000000";
stack3 <= "000000000";
elsif clk'event and clk = '1' then
if en = '1' then
pcb <= pc;
if addoffset = '1' then
pc <= pcb + offset;
elsif pull = '1' then
pc <= stack0;
elsif vec2 = '1' then
pc <= vector2;
elsif vec4 = '1' then
pc <= vector4;
else
pc <= pc + 1;
end if;
 
if push = '1' then
if addoffset = '1' then
stack0 <= pcb;
else
stack0 <= pcb - 1;
end if;
stack1 <= stack0;
stack2 <= stack1;
stack3 <= stack2;
elsif pull = '1' then
stack0 <= stack1;
stack1 <= stack2;
stack2 <= stack3;
end if;
end if;
end if;
end process;
end pc;
/trunk/vhdl/v_riscmcu.vhd
0,0 → 1,315
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU project ----
---- http://www.opencores.org/projects/riscmcu/ ----
---- ----
---- Description ----
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
---- ----
---- Author(s): ----
---- - Yap Zi He, yapzihe@hotmail.com ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity v_riscmcu is
port (
clock : in STD_LOGIC;
reset : in STD_LOGIC;
pinb : inout STD_LOGIC_VECTOR(7 downto 0);
pinc : inout STD_LOGIC_VECTOR(7 downto 0);
pind : inout STD_LOGIC_VECTOR(7 downto 0)
);
end v_riscmcu;
 
architecture riscmcu of v_riscmcu is
 
signal extpin : std_logic;
 
signal clk, clrn, div2, div4, div8, div16 : std_logic;
signal sr, reg_rd, reg_rr, c, addrbus: std_logic_vector(7 downto 0);
 
signal pc, offset : std_logic_vector(8 downto 0);
signal instruction, ir : std_logic_vector(15 downto 0);
 
signal skip, en, wr_reg : std_logic;
signal sren : std_logic_vector (6 downto 0);
signal c2a, c2b, add, subcp, logic, right, dir, pass_a : std_logic;
signal wcarry : std_logic;
signal logicsel : integer range 0 to 3;
signal rightsel : integer range 0 to 2;
signal dirsel : integer range 0 to 1;
signal addoffset, push, pull, cpse, skiptest : std_logic;
signal bclr,bset, bld, cbisbi : std_logic;
signal dest, rr, rd : integer range 0 to 15;
signal srsel : integer range 0 to 7;
signal imm_value : std_logic_vector(7 downto 0);
 
signal tosr : std_logic_vector (6 downto 0);
 
signal vec2, vec4, clr_i, set_i, clr_tov0, clr_intf, timerirq, extirq : std_logic;
 
signal rd_sreg,wr_sreg,rd_gimsk,wr_gimsk,rd_timsk, wr_timsk, rd_tifr,wr_tifr : std_logic;
signal rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : std_logic;
signal rd_portb,wr_portb,rd_ddrb,wr_ddrb,rd_pinb : std_logic;
signal rd_portc,wr_portc,rd_ddrc,wr_ddrc,rd_pinc : std_logic;
signal rd_portd,wr_portd,rd_ddrd,wr_ddrd,rd_pind : std_logic;
 
signal t_flag, c_flag : std_logic;
 
signal vcc, gnd : std_logic;
 
signal rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp :std_logic;
 
signal bitsel : integer range 0 to 7;
signal set : std_logic;
 
signal asel : integer range 0 to 1;
signal bsel : integer range 0 to 3;
 
component v_freqdiv
port ( clock : in std_logic;
div2, div4, div8, div16 : buffer std_logic
);
end component;
 
component v_pc
port ( offset : in std_logic_vector(8 downto 0);
en, addoffset, push, pull, vec2, vec4 : in std_logic;
clk, clrn : in std_logic;
pc : buffer std_logic_vector(8 downto 0)
);
end component;
 
component v_rom
port ( pc : in std_logic_vector(8 downto 0);
instruction : out std_logic_vector(15 downto 0)
);
end component;
 
component v_ir
port ( instruction : in std_logic_vector(15 downto 0);
en, clk, clrn : in std_logic;
ir : buffer std_logic_vector(15 downto 0);
imm_value : out std_logic_vector(7 downto 0);
rd, rr : out integer range 0 to 15
);
end component;
 
component v_controlunit
port ( ir : in std_logic_vector(15 downto 0);
sr : in std_logic_vector(7 downto 0);
clk, clrn : in std_logic;
skip, extirq, timerirq : in std_logic;
 
en : buffer std_logic;
wr_reg : buffer std_logic;
rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp : out std_logic;
sren : out std_logic_vector (6 downto 0);
 
c2a,c2b : out std_logic;
asel : out integer range 0 to 1;
bsel : out integer range 0 to 3;
bitsel : out integer range 0 to 7;
set : out std_logic;
 
add, subcp, logic, right, dir, pass_a : out std_logic;
 
wcarry : out std_logic;
logicsel : out integer range 0 to 3;
rightsel : out integer range 0 to 2;
dirsel : out integer range 0 to 1;
 
addoffset : out std_logic;
push, pull : out std_logic;
 
cpse, skiptest : out std_logic;
 
bclr,bset : out std_logic;
bld : out std_logic;
cbisbi : out std_logic;
 
vec2, vec4 : buffer std_logic;
 
dest : out integer range 0 to 15;
srsel : out integer range 0 to 7;
offset : out std_logic_vector(8 downto 0);
clr_i, set_i, clr_intf, clr_tov0 : out std_logic;
 
rd_sreg, wr_sreg : out std_logic;
rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic;
rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic;
rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic;
rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic;
rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic
);
end component;
 
component v_gpr
port ( c : in std_logic_vector(7 downto 0);
wr_reg, inc_zp, dec_zp : in std_logic;
rd, rr, dest : in integer range 0 to 15;
clk, clrn : in std_logic;
reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0)
);
end component;
 
component v_alu
port ( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);
c2a, c2b : in std_logic;
asel : in integer range 0 to 1;
bsel : in integer range 0 to 3;
 
bitsel : in integer range 0 to 7;
set : in std_logic;
c_flag, t_flag : in std_logic;
add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic;
cpse, skiptest : in std_logic;
 
wcarry : in std_logic;
logicsel : in integer range 0 to 3;
rightsel : in integer range 0 to 2;
dirsel : in integer range 0 to 1;
 
clk, clrn : in std_logic;
 
c : buffer std_logic_vector(7 downto 0);
tosr : buffer std_logic_vector (6 downto 0);
skip : out std_logic
);
end component;
 
component v_sr
port ( clk,clrn: in std_logic;
sren,tosr : in std_logic_vector(6 downto 0);
srsel : in integer range 0 to 7;
clr_i,set_i,bset,bclr : in std_logic;
rd_sreg, wr_sreg : in std_logic;
c : inout std_logic_vector(7 downto 0);
sr : inout std_logic_vector(7 downto 0)
);
end component;
 
component v_ram
port ( addrbus : in std_logic_vector(7 downto 0);
rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic;
clk, clrn : in std_logic;
c : inout std_logic_vector(7 downto 0)
);
end component;
 
component v_port
port ( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic;
clk, clrn : in std_logic;
c : inout std_logic_vector(7 downto 0);
pin : inout std_logic_vector(7 downto 0)
);
end component;
 
component v_timer
port ( extpin, clr_tov0 : in std_logic;
rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic;
rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic;
clk, clrn : in std_logic;
c : inout std_logic_vector(7 downto 0);
timerirq : out std_logic
);
end component;
 
component v_extint
port ( clk, clrn, extpin, clr_intf : in std_logic;
rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic;
extirq : out std_logic;
c : inout std_logic_vector(7 downto 0)
);
end component;
 
begin
U_v_freqdiv: v_freqdiv
port map (clock, div2, div4, div8, div16);
 
U_v_pc: v_pc
port map (offset, en, addoffset, push, pull, vec2, vec4, clk, clrn, pc);
 
U_v_rom: v_rom
port map (pc, instruction);
 
U_v_ir: v_ir
port map (instruction, en, clk, clrn, ir, imm_value, rd, rr);
 
U_v_controlunit: v_controlunit
port map (ir, sr, clk, clrn, skip, extirq, timerirq, en, wr_reg, rd_ram, wr_ram, ld_mar, ld_mbr, inc_zp, dec_zp, sren, c2a, c2b, asel, bsel, bitsel, set, add, subcp, logic, right, dir, pass_a, wcarry, logicsel, rightsel, dirsel, addoffset, push, pull, cpse, skiptest, bclr, bset, bld, cbisbi, vec2, vec4, dest, srsel, offset, clr_i, set_i, clr_intf, clr_tov0, rd_sreg, wr_sreg, rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_mcucr, wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind);
 
U_v_gpr: v_gpr
port map (c, wr_reg, inc_zp, dec_zp, rd, rr, dest, clk, clrn, reg_rd, reg_rr, addrbus);
 
U_v_alu: v_alu
port map (reg_rd, reg_rr, imm_value, c2a, c2b, asel, bsel, bitsel, set, c_flag, t_flag, add, subcp, logic, right, dir, bld, cbisbi, pass_a, cpse, skiptest, wcarry, logicsel, rightsel, dirsel, clk, clrn, c, tosr, skip);
 
U_v_sr: v_sr
port map (clk, clrn, sren, tosr, srsel, clr_i, set_i, bset, bclr, rd_sreg, wr_sreg, c, sr);
 
U_v_ram: v_ram
port map (addrbus, rd_ram, wr_ram, ld_mar, ld_mbr, clk, clrn, c);
 
U_v_timer: v_timer
port map (extpin, clr_tov0, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, clk, clrn, c, timerirq);
 
U_v_extint: v_extint
port map (clk, clrn, extpin, clr_intf, rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk, extirq, c);
 
 
U_v_portB: v_port
port map (rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, clk, clrn, c, pinb);
 
U_v_portC: v_port
port map (rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, clk, clrn, c, pinc);
 
U_v_portD: v_port
port map (rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind, clk, clrn, c, pind);
 
extpin <= pind(7);
clrn <= reset;
clk <= div4;
vcc <= '1';
gnd <= '0';
t_flag <= sr(6);
c_flag <= sr(0);
end riscmcu;
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.