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/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/Am9080/prom/microcode_original.mif
0,0 → 1,1069
;EMULATOR ASSEMBLY (MARCH 1977)
;07/06/77
;
;PC SOURCE AND/OR OBJECT CODE. x = DONT CARE
0000 ;INITIALIZATION:
 
0000 RESET: ALU DOUBLE, PC,PC.FTOB.F & AND & ZA :\, ALUC s, BASW & /lOC,, TO. INTE a IF.INY, & NUM DBUS, Hc:3&& NOC
0000 1000000011100000 0011110111110001 1011011111111110 11100100
 
0001 ALU,H#D,FTOB.F & DR & D2 & ALUC & BASW & 10C & /NOC & IF,INV & NUM
0001 1100000000000000 0011110111110000 0011010101011010 11011111
 
0002 ALU,H#C,FTOB.F & ANII *' 2Ft a, ALUC s, BASW & IOC & /NOC & IF,INV & NUM
0002 1100000000000000 0011110111110000 0011010101011000 11100100
 
0003 ALU,,,FTOB.F & AND :\, ZA & st.uc & BASLJ & IOC,,TO.A & /NOC & IF R.PUSH & NUM
0003 1100000000000011 0111110111110001 0011010101010100 11100100
 
0004 FETCH: ALU DOUELE,PC,PC,FTDB.F & DR & 2A :\, ALUC & BASI,,, s, /IOC IN.,TO.A :\, MEMR & IF .INV,READY & NUM, $
0004 0100000000010000 0010010111010001 0011011111111110 11011100
 
0005 INCPC & IF D.R. ,HOLD & NUM,HLDD & NOC
0005 1100000000110000 1110100111110001 0011011111111110 11000100
 
0000
0000 ;HOLD AND MEMORY REFERENCE SUBROUTINES AND HANDLERS:
0000
 
0000 ORG 10
 
000A HLDSB: NALU & IOC a, HLDA & IF R.RTN, INV, HOLD & ttUM. s
000A 1100000000101001 1010100111111000 0011010101010100 01XXXXXX
 
000B HLDF: HALU g, IDC & HLDA & IF R.F, INY,HOLD & l'tUM, s
000B 1100000000101111 1010100111111000 0011010101010100 01XXXXXX
 
000C HLDD: ttALU *' IDe & HLDA & IF D.R. ,HOLD & NUM. :I;
000C 1100000000110000 1110100111111000 0011010101010100 01XXXXXX
 
000D ~!MRSB: ALU DOUBLE,PC,PC.FTOB.F & DR & 2A & IOC,,TO.A :\, /ALUC & MEMR & IF R.RTN. ,READY & HUM. $ & BASW
000D 1100000000110101 1110010111010001 0011011111111110 11011100
 
 
000E 1100000000111001 1110010111100101 0011011111111110 11011100
 
000F MMWF: ALU DOUBLE.PC.PC.FTOB.F & DR & ZA & ALue & BASW & /MEMW & IF R.F,,READY *' IOC. DH.TO.A & NUM, $
000F 1100000000111111 1110010111100101 0011011111111110 11011100
 
0010 MMRF: ALU DOUELE.PC,PC,FTOB.F & DR & ZA & ALUC & BASW :\, MEMR & /IOC,,TO.A ~ IF R.F ,,READY ~ NUM , $
0010 1100000001000011 1110010111010001 0011011111111110 11011100
 
0011 MMRSP: ALU DOUBLE,SP,SP,FTOB.F ~ OR ~ 2A & IOC,,TO.A & BASW & /ALUC & MEMR & IF R.RTN.,READY & NUM, $
0011 1100000001000101 1110010111010001 0011011100010000 11011100
 
0012 MMWSPH: ALU DOUBLE,SP,SP',FTOB.F s, DR & 2A & ALUC 3. BASbJ & /IOC,DH,TO.A & MEMW 3. IF R.RTN, ,READY 3. NUM, $
0012 1100000001001001 1110010111100101 0011011100010000 11011100
 
0013 MMWSPL: ALU DOUBLE, Sp, Sp, F TOB. F 3. DR & ZA & ALUC & BASW & /IOC,DL,TO.A & MEMW & IF R.RTN,,READY & NUM, $
0013 1100000001001101 1110010111100011 0011011100010000 11011100
 
0000
0000 ;MACROCODES:
0000
 
0014 MOVRR: ftLU, ,,FTOB.F & ALUC & BASW SW,SW & OR & 2A & IOC & /IF R.F, INV,HOLD 3. NUM, HLDF & NOC
0014 1100000000101111 1010101111110000 0111010101010100 11011100
 
0015 MOVMR: ALU DOUBLE, H 3. ftLUC & DR & 2ft 3. BASW 3. IDC,,TO.A & HLD
0015 1100000000101001 0110100111110001 0011011010010100 01011100
 
0016 ALU.& OR & 2A & BASW, SW ~< ftLUC & IOC,,TD.D 3. HLD
0016 1100000000101001 0110100111110000 1111010101010100 01011100
 
0017 ALU DOUBLE,PC.PC,FTOB.F & ALUC & OR & ZA & BASW & /MEMW & IF R.F,,READY & NUM, s & . IOC, DH, TO.A
0017 1100000001011111 1110010111100101 0011011111111110 11011100
 
0018 MOVRM: ALU DOUBLE, H & ALUC & OR & 2A & BASW & IOC,,TO.A & HLD
0018 1100000000101001 0110100111110001 0011011010010100 01011100
 
0019 ALU DOUBLE,PC,PC,FTOB.F 3. DR & ZA & ALUC & BASW & MMR & /lOC, , TO.A
0019 1100000000110101 0010010111010001 0011011111111110 11011100
 
001A ALU,.,FTOB.F & OR & DZ & BASW SW & ALUC & IOC 3. /NOC & IF R.F, INV, HOLD & NUM. HLDF
001A 1100000000101111 1010101111110000 0011010101010100 11011111
 
001B MVIR: INCPC & MMR
001B 1100000000110101 0010010111010001 0011011111111110 11000100
 
001C ALIJ, , ,FTOB. F & OR & DZ & ALUC & BASI.o.I SW & IDC / 3. NOC & IF R.F, INV, HOLD & NUM. HLDF
001C 1100000000101111 1010101111110000 0011010101010100 11011111
 
001D NAlU
001D XXXXXXXXXXXXXXXX XXXXXXOXXXXXXXXX X011010101010100 01XXXXXX
 
001E MVIM: NALU & MMR & IDe
001E 1100000000110101 0010010111010000 0011010101010100 01XXXXXX
 
001F ALU,,,FTOB.F &. BASW & OR &. DZ & ALUC & IOC ,,TO.D s, HLD
001F 1100000000101001 0110100111110000 1011010101010100 11011111
 
0020 ALU DOUBLE,H & DR & ZA & ALUC & BASW & IOC,,TO.A & HLD
0020 1100000000101001 0110100111110001 0011011010010100 01011100
 
0021 ALU DOUBLE,PC,PC,FTOB.F & PLUS & ZA & ALUC & BASW & /MEMW & IF R.F,,READY & NUM, MMWF & IOC,DH,TO.A
0021 1100000000111111 1110010111100101 0011011111111110 11000100
 
0022 LXIB: INCPC & MMR
0022 1100000000110101 0010010111010001 0011011111111110 11000100
 
0023 ALU,,C,FTOB.F & OR & DZ & ALUC & BASW & HLD & IOC
0023 1100000000101001 0110100111110000 0011010101000010 11011111
 
0024 INCPC & MMR
0024 1100000000110101 0010010111010001 0011011111111110 11000100
 
0025 ALU,,B,FTOB.F, & OR & D2 & ALUC &. BASW &. NOC & /IF R.F,INY,HOLD & NUM,HLDF & IOC
0025 1100000000101111 1010100111110000 0011010101000000 11011111
 
0026 LDA: INCPC & MMR
0026 1100000000110101 0010010111010001 0011011111111110 11000100
 
0027 ALU DOUBLE,,jFTOB.F & OR & DZ & ALUC & BASW & HLD & lOC
0027 1100000000101001 0110100111110000 0011011101010100 11011111
 
0028 INCPC & MMR
0028 1100000000110101 0010010111010001 0011011111111110 11000100
 
0029 ALU,,,FTOB.F &. DR &. DZ &. ALUC 3, BASI.<l & HLD & IOC
0029 1100000000101001 0110100111110000 0011010101010100 11011111
 
 
002A 1100000000101001 0110100111110001 0011011101010100 01011100
 
002B ALU DOUBLE,PC,PC,~TOB.F &. OR & 2A & ALUC & BASW & /10C,,TO.A & MMR
002B 1100000000110101 0010010111010001 0011011111111110 11011100
 
002C ALU.A,A,FTOB.F & OR & I1Z & ALIJC & BASW &. IOC &0 /NOC & IF R.F,INY,HOLD & NUM, HLDF
002C 1100000000101111 1010100111110000 0011010011101110 11011111
 
002D STA' INCPC & MMR
002D 1100000000110101 0010010111010001 0011011111111110 11000100
 
002E ALU DOUBLE,,, FTOB. F & DR & DZ & ALIJC & BASW & roc a, HLD
002E 1100000000101001 0110100111110000 0011011101010100 11011111
 
002F INCPC & MMR
002F 1100000000110101 0010010111010001 0011011111111110 11000100
 
0030 ALU,,,FTDB.F & OR & DZ & ALUC & BASW Ii- roc & HLD
0030 1100000000101001 0110100111110000 0011010101010100 11011111
 
0031 ALU DOUBLE,,,FTOB.F & DR & 2A & ALUC & BASW & IOC.,TO.A '1 /HLD
0031 1100000000101001 0110100111110001 0011011101010100 11011100
 
0032 ALU,A,A,FTOB.F ~ OR ~ 2A ~ ALUC ~ BASW & IDC,,TD.D & HLD
0032 1100000000101001 0110100111110000 1011010011101110 11011100
 
0033 ALU DDUBLE,PC,PC,FTOB.F ~ OR ~ 2A & ALUC & BASW & ,,IOC,DH,TD.A & MEMI,, & IF R.F,,READY & NUM, MMWF
0033 1100000000111111 1110010111100101 0011011111111110 11011100
 
 
0034 1100000000101111 1010100111110000 0100000101001110 11000001
 
0035 ADDN: All) DDUBLE,H & DR & 2A & ALUC s, BASW & IDC, ,TO.A & HLD
0035 1100000000101001 0110100111110001 0011011010010100 01011100
 
0036 ADDM1: ALU DDUBLE.PC,PC,FTOB.F ~DR ~ 2A & ALUC ~ BASW ~ /IOC ,,TO.A ~ MMR
0036 1100000000110101 0010010111010001 0011011111111110 11011100
 
 
0037 1100000000101111 1010100111110000 0000000011101110 11000101
 
0038 ADI: INCPC ~ MMR
0038 1100000000110101 0010010111010001 0011011111111110 11000100
 
0039 ALU.A,A,FTDB.F & PLUS & DA & ALUC UPDTALL,,CNL , /BASW & IDC & NOC & IF R.F,INV,HOLD & NUM,HLDF
0039 1100000000101111 1010100111110000 0000000011101110 11000101
 
003A ADCR: NALU & IOC & NOC s, IF, INY, CY 3. NUM, AIIDR
003A 1100000011010000 0000010111110000 0011010101010100 01XXXXXX
 
003B ALU,,A.FTOB.F 3. PLUS 3. AB & BASW,SW 3. ALue UPDTALL 3. /IDC & NOC & IF R. F, INV, HOLD & NUN, HLDF
003B 1100000000101111 1010100111110000 0100010101001110 11000001
 
003C ADCN: ALU IlDlIBLE,H & OR e, 2A 3. ALUC & BASW 3. IDC,,TD.A & ...-NDe & IF,INV,CY 3. NUM,ADDNI
003C 1100000011011000 0000010111110001 0011011010010100 01011100
 
003D ALU DOUBLE ,PC,PC,FTDB.F 3. DR 3. 2A 3. ALUC 3. BASI,, 3. /IDC,,TD.A 3. MMR
003D 1100000000110101 0010010111010001 0011011111111110 11011100
 
 
003E 1100000000101111 1010100111110000 0000010011101110 11000101
 
003F ACI: NALI) & IDC & NOC & IF,zNV,CY & NUM,ADI
003F 1100000011100000 0000010111110000 0011010101010100 01XXXXXX
 
0040 INCPC 3. MMR
0040 1100000000110101 0010010111010001 0011011111111110 11000100
 
0041 ALU,A.A,FTOB.F & PLUS & DA & ALUC UPDTALL & B'ASW & /IOC & NOC & IF R.F,INY,HOLD & NUM,HLDF
0041 1100000000101111 1010100111110000 0000010011101110 11000101
 
0042 JMP: INCPC & MMR
0042 1100000000110101 0010010111010001 0011011111111110 11000100
 
0043 ALU DOUB'LE, , ,FTDB.F & OR s, D2 & ALUC & BAS~J & /IOC & HLD
0043 1100000000101001 0110100111110000 0011011101010100 11011111
 
0044 I NCPC & MMR ,,
0044 1100000000110101 0010010111010001 0011011111111110 11000100
 
0045 ALIJ,, ,FTDB. F & OR & DZ & ALUC & BASW s, IDC s, HLD
0045 1100000000101001 0110100111110000 0011010101010100 11011111
 
0046 ALU DOUBLE, ,PC,FTDB.A s, DR s, ZFt & ALUC & BASW & roc, ,TO.A & /' NOC & IF R.F,IN\,I,HDLD & NUM,HLDF
0046 1100000000101111 1010100111110001 0011011101011110 10011100
 
0047 CALL: INCPC s MMR
0047 1100000000110101 0010010111010001 0011011111111110 11000100
 
0048 ALU DDUB'LE,,,FTDB'.F & DR & DZ & ALUC & BASW & IOC & /HLD
0048 1100000000101001 0110100111110000 0011011101010100 11011111
 
0049 INCPC e, MMR
0049 1100000000110101 0010010111010001 0011011111111110 11000100
 
004A ALU,,,FTOB.F & OR & DZ & ALUC & BASW & IOC & HLD
004A 1100000000101001 0110100111110000 0011010101010100 11011111
 
004B FtLU DDUB'LE,SP,SP,FTOB.F & SUNIM & ZA & ALUC,,CNL & /BASW & IDC,,TD.A & HLD
004B 1100000000101001 0110100111110001 0011001100010000 11001100
 
 
004C 1100000000101001 0110100111110000 1011011111110100 01011100
 
004D ALU DDUBLE,SP,SP,FTDB'.F & SUNIM & 2A & ALUC,,CNL & /IDC,DH.TD.A & BASW & MEMW & IF C.SB'R,INY,READY & --NUM, MM~ISPH
004D 1100000001001001 0010010111100101 0011001100010000 11001100
 
004E ALU DOUB'LE,,PC,FTDB'.F & DR & ZA & ALUC & B'ASW & /IDC,DL,TO.A & MEMW & IF R.F,,READY & NUM, $
004E 1100000100111011 1110010111100011 0011011101011110 11011100
 
004F NFtLU
004F XXXXXXXXXXXXXXXX XXXXXXOXXXXXXXXX XOI1010101010100 01XXXXXX
 
0050 RET: ALU DDUBLE.SP,SP,FTOB.A & PLUS & ZA & BASW & ALUC & /IDC,,TD.A & NOC & IF C.SB'R & NUM,MMRSP
0050 1100000001000101 0111110111110001 0011011100010000 10000100
 
0051 ALU DOUBLE,PC,PC,FTOB.F ~ OR & DZ & BASW ~ ALUC & /lOC & HLD
0051 1100000000101001 0110100111110000 0011011111111110 11011111
 
0052 ALU DOUBLE, SP, sp, FTOB. A e, PLUS s, ZA ~ BASI,,! s, ALUC s, /IOC,,TO.A & MEMR $, IF C.SBR,INV,READY & NUM,MMRSP
0052 1100000001000101 0010010111010001 0011011100010000 10000100
 
0053 ALLI,PC,PC,FTDB.F & OR & 112 & ALLIC & BASW & roc & HLD
0053 1100000000101001 0110100111110000 0011010111111110 11011111
 
0054 ALU DOUBLE,PC.PC, & OR ~ 2A &. ALLIe & BASW & IOC, ,TO.A & /NOC & IF R.F,INV,HOLD & NUM, HLDF
0054 1100000000101111 1010100111110001 0011 01111111111 0 01011100
0055 RST: ALU DOUBLE,H::C,,FTOB.F & AND Il. DA & ALUC & BASW & /lOC e, HLD
0055 1100000000101001 0110100111110000 0011011110010100 11100101
 
0056 RSTlI ALU DOUBLE,PC Il. OR &. ZA 2. ALUC 2. BASI~ & roc,, TO. D & HLD
0056 1100000000101001 0110100111110000 1011011111110100 01011100
 
0057 ALU DOUBLE,SP,SP,FTOB.F & SUNIM & ZA &. ALLlC,,CNL 2. /BASI,,! & IOC,, TO. A & NOC & IF C. SBR & NUM, MMWSPH
0057 1100000001001001 0111110111110001 0011001100010000 11001100
 
0058 ALU DOUBLE, SP,SP,FTOB.F & SLiNIM & ZA & ALUC,,CNL & /BASW & IOC,,TO.A & HLD
0058 1100000000101001 0110100111110001 0011001100010000 11001100
 
 
0059 1100000101100111 1110010111100011 0011011101011110 11011100
 
005A RLC: ALU,A.A.UROT.F &. OR &. ZA & BASW &. IOC & /ALUC UPDTCY & HLD
005A 1100000000101001 0110100111110000 0001010011101111 11011100
 
 
005B 1100001001110011 1011000111110000 0011010101010100 01XXXXXX
 
005C ALLI , OR & ALUC L1PDTCY s, BASI,,! & IDC , /NOC &. IF R.F,INV.HOLD *' NUM,HL1IF
005C 1100000000101111 1010100111110000 0001010101010100 01011XXX
 
005D RRC: ALU.A.A.DROT.F &. OR & ZA & BASW & IOC &. ALUC UPDTCY & /HLD
005D 1100000000101001 0110100111110000 0001010011101111 01011100
 
005E ALU,A &. DR & ZA 3, BASW & IOC & ALue $. NOC & IF & NUM,RL
005E 1100000101101100 0111110111110000 0011010011110100 01011100
 
005F RAL: & ALU,A.A.UROT.F $. OR & ZA &. BASW & IOC & ALUC UPDTCY.SWAP
005F 1100000101101100 0111110111110000 0001110011101111 11011100
 
0060 RAR: ALU,A,A,DROT.F :l. DR :l. ZA :l. BASW :l. IOC ~ ALUC ~ HLD
0060 1100000000101001 0110100111110000 0011010011101111 01011100
 
0061 ALU,A,A,UROT.F ~ DR :l. ZA & BASW ~ IDC ~ ALUC & HLD
0061 1100000000101001 0110100111110000 0011010011101111 11011100
 
0062 ALU,A,A,DROT.F' & DR $. ZA & BASW :l. IOC & ALUC UPDTCY, /SWAP & NOC & IF R.F,INV,F3 & NUM,STC
0062 1100001001110011 1011000111110000 0001110011101111 01011100
 
0063 ALU & OR & ALUC UPDTCY ,I\. BASW & 10C & NOC & /IF R.F,INV,HOLD & NUM,HLDF
0063 1100000000101111 1010100111110000 0001010101010100 01011XXX
 
 
0064 1100000000101001 0110101111110000 1011011101010100 01011011
 
0065 ALU DOUBLE.SP,SP,FTOB.F :l. SUNIM & ZA & ALUC.,CNL $. /IOC,,TO.A $. BASW $. HLD
0065 1100000000101001 0110100111110001 0011001100010000 11001100
 
0066 ALU DOUBLE,SP,SP.FTOB.F & SUNIM & ZA & ALUC.,CNL & /SASW :l. IOC,DH,TO.A & MEMW & IF C.S~R,INV,READY Il. /NUM,MMWSPH
0066 1100000001001001 0010010111100101 0011001100010000 11001100
 
0067 ALU DDUBLE,PC,PC,FTOB.F & OR & ZA & ALUC & BASW & /IOC,DL,TO.A & MEMW & IF R.F.,READY & NUM, $
0067 1100000110011111 1110010111100011 0011011111111110 11011100
 
 
0068 1100000000101001 0110100111110000 1011010011110100 01011100
 
 
0069 1100000001001001 0111110111110001 0011001100010000 11001100
 
006A NALU & IOC,FLAGS & MEMW & IF,INV,READY $. NUM,$
006A 1100000110101000 0010010111100110 0011010101010100 01XXXXXX
 
006B ALU DOUBLE,SP,SP,FTOB.F Il. SUNIM & ZA & ALUC.,CNL & BASW ll./lOC & HLD
006B 1100000000101001 0110100111110000 0011001100010000 11001100
 
006C ALU DOUBLE,PC,PC,FTOB.F ~, OR & ZA I), ALUC & BASW & IOC,,T O.A &/NOC & IF R.F, INV,HOLD & NUM,HLDF
006C 1100000000101111 1010100111110001 0011011111111110 11011100
 
 
006D 1100000000101001 0110100111110000 0011011101000000 11000011
 
006E ALU DOUBLE.B,C,FTOB.A & OR & DZ & ALUC,SWAP & BASW & /IOC & NOC & IF R.F.INV,HOLD & NUM,HLDF
006E 1100000000101111 1010100111110000 0011111000000010 10011111
 
 
006F 1100000000101001 0110100111110000 0011001101000000 11001011
 
0070 ALU DOUBLE,B,C.FTDB.A & OR :l, DZ :l, ALUC.S~IAP & IDC & /NOC & IF R.F,INV,HOLD & NUM,HLDF
0070 1100000000101111 101010X111110000 0X11111000000010 10011111
 
0071 DAD. B: ALU DOUBLE,B,H,FTOB.F & PLUS & AB & ALLIC UPDTCY,,CNL & I DC a, /BASW & HLD
0071 1100000000101001 0110100111110000 0001001000001000 11000001
 
0072 DADll ALU DOUBLE,H,L,FTOB.A & OR 3. DZ & ALUC,SWAP & BASW :l, /IOC & NOC & IF R.F,INV,HOLD & NUM.HLDF
0072 1100000000101111 1010100111110000 0011111010001010 10011111
 
0073 DAD.D: ALU DOUBLE,D,H,FTOB.F & PLUS & AB & ALUC UPDTCY,,CNL & I DC Il./BASI,J & NOC & IF & NUM,DADI
0073 1100000111001000 0111110111110000 0001001001001000 11000001
 
0074 DAD.H: ALU DOUBLE,H,H,FTOB.F & PUIS & AB & ALlJC UPDTCY,,CNL :l, I DC 3. /BASW 3. NOC :l, IF & NUM, DADI
0074 1100000111001000 0111110111110000 0001001010001000 11000001
 
0075 DAD.SP: ALU DOUBLE,SP,H,FTOB.F & PLUS & AB & ALUC UPDTCY,,CNL & IDe 3. ,'BASW & NOC 3. IF & NUM,DADI
0075 1100000111001000 0111110111110000 0001001100001000 11000001
 
0076 CMPR: ALlI,,A, & BASW,SW 3. AB & SUNIM & ALUC UPDTALL & IOC & /NDC & IF R.F.INV,HDLD S. NIJM,HLDF
0076 1100000000101111 1010100111110000 0100010101001110 01001001
 
0077 CPI I INCPC S. MMR
0077 1100000000110101 0010010111010001 0011011111111110 11000100
 
0078 ALU,A S. :&S~) S. DA 3. SUNIM S. ALue UPDTALL a. IOC 3- ,NOC a. IF R.F,INV,HOLD & NUM,HLDF
0078 1100000000101111 1010100111110000 0000010011110100 01001101
 
0079 CMPM: ALU DOUBLE.H & DR & 2A & IOC.,TO.A 3. BASW & ALUC & HLD
0079 1100000000101001 0110100111110001 0011011010010100 01011100
 
007A ALU DDUBLE,PC & OR & ZA & IOC,,TO.A & BASW 3. ALUC 3. MMR
007A 1100000000110101 0010010111010001 0011011111110100 01011100
 
007B ALU,A I!o BASW & DA & SLlNII1 & ALIJC UPDTALL S. IOC.& /NOC & IF R.F,INV,HOLD & NUM,HLDF
007B 1100000000101111 1010100111110000 0000010011110100 01001101
 
007C POP.B: ALU DOUBLE,SP,SP,FTOB.A & DR & ZA :I. ALUC & BASW a. /IOC,,TO.A a. NOC & IF C.SBR, ,HOLD a. NUM.HLDSB
007C 1100000000101001 0110100111110001 0011011100010000 10011100
 
007D ALU DOUBLE,SP,SP,FTOB.F & PLUS :I. ZA & ALUC & BASW & / IOC,,TO.A a. MEMR & IF C.SBR.INV,READY & NUM.MMRSP
007D 1100000001000101 0010010111010001 0011011100010000 11000100
 
007E ALU,,C,FTOB.F & DR & DZ & ALUC & IOC & BASW & HLD
007E 1100000000101001 0110100111110000 0011010101000010 11011111
 
007F ALU DOUBLE,SP,SP,FTOB.F & PLUS& ZA & ALUC & BASW & /IOC,,TO.A & MEMR & IF C.SBR.INV,READY & NUM,MMRSP
007F 1100000001000101 0010010111010001 0011011100010000 11000100
 
0080 ALU.,B,FTOB.F & DR & DZ & ALUC & IOC & BASW & HLD
0080 1100000000101001 0110100111110000 0011010101000000 11011111
 
0081 ALU DOUBLE,PC & DR & ZA & ALUC & IOC.,TO.A & BASW & /NOC & IF R.F.INV.HOLD & NUM.HLDF
0081 1100000000101111 1010100111110001 0011011111110100 01011100
 
0082 HLT: NALU & IOC'& HLD
0082 1100000000101001 0110100111110000 0011010101010100 01XXXXXX
 
0083 NALU & IOC & NOC & IF ,INV,INT & NUM.HLT
0083 1100001000001000 0010000111110000 0011010101010100 01XXXXXX
 
0084 INTHNDL: NALU & IOC & INTA & IF,INV & NUM
0084 1100000000000000 0011110011110000 0011010101010100 01XXXXXX
 
0085 NALU & lOC & INTA & IF & NUM.RSTI
0085 1100000101011000 0111110011110000 0011010101010100 01XXXXXX
 
0086 NOP: NALU & IDC & IF R.F, INV, HOLD ~, NUM,HLDF & NOC
0086 1100000000101111 1010100111110000 0011010101010100 01XXXXXX
 
0087 IN. : INCPC & MMR
0087 1100000000110101 0010010111010001 0011011111111110 11000100
 
 
0088 1100000000101001 0110100111110001 0011010101010100 01011111
 
0089 ALU DOUBLE. PC & DR & ZA & BASW & ALUC & IDC., TO. A & /IOR & IF,INV,READY & NUM.$
0089 1100001000100100 0010010101110001 0011011111110100 01011100
 
008A ALU, ,A.FTDB.F ~ OR Il. DZ Il. at.uc & IDC & BASW e, NOC e, /IF R.F,INV.HOLD & NUM.HLDF
008A 1100000000101111 1010100111110000 0011010101001110 11011111
 
008B OUT.' ALlI,A & DR & ZA & IDC,,TO.D & BAS~J & ALLIC & HLD
008B 1100000000101001 0110100111110000 1011010011110100 01011100
 
008C INCPC ~ MMR
008C 1100000000110101 0010010111010001 0011011111111110 11000100
 
008D ALU & OR & DZ & ALUC & 10C,,TO.A & BASW & HLD
008D 1100000000101001 0110100111110001 0011010101010100 01011111
 
008E AlU DOUBlE,PC & OR & ZA & BASW & AlUC & IDC,DH,TO.A & /!OW & IF R.F,,READY & NUM,$
008E 1100001000111011 1110010110110101 0011011111110100 01011100
 
008F EI: AlU,H::C & NXOR is. 2A & lDC,,TO.INTE & BASW & ALUC & /NOC & IF R.F.INV.HOlD & NUM,HlDF
008F 1100000000101111 1010100111110001 1011010110010100 01111100
 
0090 DI: ALU & AND & 2A & 10C,, TO. INTE & BASW & ALUC & NOC & /IF R.F,INV,HOlD & NUM,HLDF
0090 1100000000101111 1010100111110001 1011010101010100 01100100
 
0091 SPHL: ALU DOUBlE,H.SP.FTOB.F & OR & ZA & AlUC & BASW & IOC & /NOC & IF R.F,INV.HOLD is. NUM,HlDF
0091 1100000000101111 1010100111110000 0011011010010000 11011100
 
0092 ;XTHU AlU DOUBLE,H & OR & ZA & AlUC & BASW & IOC,,TO.D & HLD
0092 1100000000101001 0110100111110000 1011011010010100 01011100
 
0093 ALU DOUBLE.SP & DR & ZA & AlUC & BASW & 10C,.TO.A & HLD
0093 1100000000101001 0110100111110001 0011011100010100 01011100
 
0094 NAlU & IOC & MEMR & IF.INV,READY & NUM,$
0094 1100001001010000 0010010111010000 0011010101010100 01XXXXXX
 
0095 AlU,,l.FTOB.F & OR & DZ & AlUC & IOC & BASW & HLD
0095 1100000000101001 0110100111110000 0011010101001010 11011111
 
0096 ALU DOUBlE,SP,SP.FTOB.F & PLUS & ZA & ALUC & BASW & /IDC,DL,TO.A & MEMW & IF C.SBR.JNV,READY is. NUM,MMbJSPL
0096 1100000001001101 0010010111100011 0011011100010000 11000100
 
0097 NALU & 10C & MEMR is. IF. INV, READY & NUM,$
0097 1100001001011100 0010010111010000 0011010101010100 01XXXXXX
 
0098 ALU,,H,FTOB.F ~ DR & DZ ~ ALUC & IOC ~ BASW & HLD
0098 1100000000101001 0110100111110000 0011010101001000 11011111
 
0099 ALU DOUBLE. PC & OR & ZA & ALLIC ~ BASW & IOC,DH,TO.A & /MEMW & IF,INV,READY & NUM.i
0099 1100001001100100 0010010111100101 0011011111110100 01011100
 
009A ALU DOUBlE,SP.SP,FTOB.F & ZA & SUNIM & ALUC.,CNL & /BASt..' is. IDC & NOC S. IF R.F. INV,HOLD & NUM.HLDF
009A 1100000000101111 1010100111110000 0011001100010000 11001100
 
 
009B 1100000000101111 1010100111110001 0011011010011110 11011100
 
 
009C 1100000000101111 1010100111110000 0001000110010100 01001100
 
009D CMC: ALU & AND & ZA & ALUC UPDTCY & BA~~I ~< IDC & NOC & /IF R.F,,CY & NUM, STC
009D 1100001001110011 1100010111110000 0001010101010100 01100100
 
009E ALU & AND & ZA & ALUC UPDTCY,,CNL & BASW & IDC & /NOC & IF R.F,INY,HOLD & NUM,HLDF
009E 1100000000101111 1010100111110000 0001000101010100 01100100
 
009F ANAR: ALU,,A,FTOB.F & AND & AB & ALUC UPDTALL & BASW ,~W & /IDC & NOC & IF R.F.INY,HDLD &NUM,HLDF
009F 1100000000101111 1010100111110000 0100010101001110 11100001
 
 
00A0 1100000000101111 1010100111110000 0100010101001110 11110001
 
00A1 ORAR: ALU,,A,FTOB.F & DR & AB & ALUC UPDTALL & BA~W ,SW & /IOC & NOC & IF R.F,INY,HOLD & NUM,HLDF
00A1 1100000000101111 1010100111110000 0100010101001110 11011001
 
00A2 DCRM: ALU IIOUBLE.H & DR & ZA & ALUC & IOC. ,TO.A & BASW & HLD
00A2 1100000000101001 0110100111110001 0011011010010100 01011100
 
00A3 NALU & IOC & MEMR & IF,INY.READY & NUM,$
00A3 1100001010001100 0010010111010000 0011010101010100 01XXXXXX
 
00A4 ALU & DZ & MINUS & ALUC UPDTFL,,CNL & BASW & /IOC,,TO.D & HLD
00A4 1100000000101001 0110100111110000 1010000101010100 01010111
 
00A5 ALU DOUBLE,PC & OR & ZA & ALUC & BA~W ~. IOC,DH,TO.A & /MEMW & IF R.F,,READY & NUM,$
00A5 1100001010010111 1110010111100101 0011011111110100 01011100
 
00A6 INRM: ALU DDUBLE,H & DR & ZA & ALUC & IOC,,TO.A & BASW & HLD
00A6 1100000000101001 0110100111110001 0011011010010100 01011100
 
00A7 NALU & IOC & MEMR & IF,INV,READY & NUM,$
00A7 1100001010011100 0010010111010000 0011010101010100 01XXXXXX
 
00A8 ALl! & DZ & PLU~ & ai.uc UPIITFL & BASW & IOC,, TO. D & HLD
00A8 1100000000101001 0110100111110000 1010010101010100 01000111
 
00A9 ALU DOUBLE,PC & DR & ZA & ALue & BASW & IOC,DH,TD.A & /MEMW & IF R.F,.READY & NUM.$
00A9 1100001010100111 1110010111100101 0011011111110100 01011100
 
00AA DCRR: ALU.,,FTOB.F & ZB & SUNIM & ALUC UPDTFL,.CNL & /BASI,o,I SW & IDC & IF R.F,INV,HOLD & NUM.HLDF s NOC
00AA 1100000000101111 1010101111110000 0010000101010100 11001011
 
00AB INRR: ALU,,,FTOB.F & ZB & PLUS & ALUe UPDTFL & BA~W ~W & IOC & /NOC & IF R.F,INV,HOLD & NUM,HLDF
00AB 1100000000101111 1010101111110000 0010010101010100 11000011
 
00AC SUBR: ALU,,A,FTOB.F & AB & SUNIM & ALUC UPDTALL & BASW , ~W & /IOC:I. NOC :I. IF R.F,INV,HOLD :I. NUM,HLDF
00AC 1100000000101111 1010100111110000 0100010101001110 11001001
 
00AD SUBM: ALU DOUBLE,H & DR & 2A :I. ALUC & BASil) & IDC,,TO.A & HLD
00AD 1100000000101001 0110100111110001 0011011010010100 01011100
 
00AE ALU DOUBLE, PC & OR 2., ZA & BASW :I. ALLIC :I. IOC,,TO.A & MMR
00AE 1100000000110101 0010010111010001 0011011111110100 01011100
 
00AF ALU,A,A,FTDB.F & DA & SUNIM & ALUC UPDTALL & /BASW & IOC & NOC & IF R.F,INV,HOLD & NUM,HLDF
00AF 1100000000101111 1010100111110000 0000010011101110 11001101
 
00B0 SUI: INCPC & MMR
00B0 1100000000110101 0010010111010001 0011011111111110 11000100
 
00B1 ALU,A,A,FTOB.F & DA 2., SUNIM :I. ALUC UPDTALL & /BAS~J & IDC & NOC 2., IF R.F,INV,HOLD:I. NUM,HLDF
00B1 1100000000101111 1010100111110000 0000010011101110 11001101
 
00B2 SBBR: NALU & IDC :I. NOC :I. IF,INV,CY :I. NUM,SUBR
00B2 1100001010110000 0000010111110000 0011010101010100 01XXXXXX
 
00B3 ALU,.A,FTOB.F:I. AB e, SUNIM & BASld,SW & ALUC UPDTALL.,CN L &/IDC %< NOC :I. IF R.F,INV,HOLD & NUM,HLDF
00B3 1100000000101111 1010100111110000 0100000101001110 11001001
 
00B4 SBBM: ALU DOUBLE,H & OR & 2A & IOC,,TO.A & BASil) 2., ALUC & /NOC %< IF ,INV,CY & NUM,$UBM+l
00B4 1100001010111000 0000010111110001 0011011010010100 01011100
 
00B5 ALU DOUBLE, PC & OR %. 2A s, lOC,, TO. A :I. BASW :I. ALUC 2., MMR
00B5 1100000000110101 0010010111010001 0011011111110100 01011100
 
00B6 ALU,A,A,FTDB.F 2., DA :I. SUNIM & ALUC UPDTALL,,CHL :I. /BASW:I. IOC :I. NOC :I. IF R.F,INV,HOLD :I. NUM,HLDF
00B6 1100000000101111 1010100111110000 0000000011101110 11001101
 
00B7 SBt: NALU :I. lOC & NOC & IF,INV,CY :I. HUM,SUI
00B7 1100001011000000 0000010111110000 0011010101010100 01XXXXXX
 
00B8 NRLU & IOC :I. NOC & IF & NUM,SBll
00B8 1100010101110100 0111110111110000 0011010101010100 01XXXXXX
 
00B9 ANAM: ALU DDUBLE,H & DR & 2A :I. IOC,,TO.A & ALUC & BASW :I. HLD
00B9 1100000000101001 0110100111110001 0011011010010100 01011100
 
00BA ALU DOUBLE,PC :I. OR :I. ZA :I. IOC,,TO.A & ALUC & BASW & MMR
00BA 1100000000110101 0010010111010001 0011011111110100 01011100
 
00BB ALU,A,A,FTOB.F & AND & DR & ALUC UPDTALL & BASW & /IOC & NOC & IF R.F,INV,HOLD & NUM,HLDF
00BB 1100000000101111 1010100111110000 0000010011101110 11100101
 
 
00BC 1100000000101001 0110100111110001 0011011010010100 01011100
 
00BD ALU DOUBLE.PC & OR a, 2A & IOC,, TO. A & FtLUC & IoAS~J & MMR
00BD 1100000000110101 0010010111010001 0011011111110100 01011100
 
00BE FtLU,A,A,FTOB.F & XOR & DA & FtLUC UPDTALL & BASW & /IOC & NOC & IF R.F,INV,HOLD & NUM,HLDF
00BE 1100000000101111 1010100111110000 0000010011101110 11110101
 
00BF DRAM: ALU DOUBLE,H & OR & 2A & IOC,,TO.A & FtLUC & BASW & HLD
00BF 1100000000101001 0110100111110001 0011011010010100 01011100
 
00C0 ALU DOUBLE,PC & OR & 2A & rOC,,TO.A :l. FtLUC & BASW & MMR
00C0 1100000000110101 0010010111010001 0011011111110100 01011100
 
00C1 ALU, fit A, FToB. F & DR & DA & ALUC IJPDTALL & BASW & -,IDC & NOC & IF R.F, INV, HOLD & NUM;HLDF
00C1 1100000000101111 1010100111110000 0000010011101110 11011101
 
00C2 FtNII INCPC & MMR
00C2 1100000000110101 0010010111010001 0011011111111110 11000100
 
00C3 ALU,A,A,FTOB.F & AND & DA & ALUC UPDTALL & BASW & IDC & ?NOC & IF R.FoINV.HOLD & NUM,HLDF
00C3 1100000000101111 1010100111110000 0000010011101110 11100101
 
00C4 ;XRI: INCPC & MMR
00C4 1100000000110101 0010010111010001 0011011111111110 11000100
 
00C5 ALU,A,A,FTOB.F & XCR & DA & ALUC UPDTALL & BASW & IOC & -'NOC & IF R.F,INV,HOLD & NUM,HLDF
00C5 1100000000101111 1010100111110000 0000010011101110 11110101
 
00C6 ORI: INCPC & MMR
00C6 1100000000110101 0010010111010001 0011011111111110 11000100
 
00C7 ALU,A,A,FTOB.F & OR & DA & ALUC UPDTALL & BAS~I :& IOC & ,,NOC & IF R.F,INV,HOLD & NUM,HLDF
00C7 1100000000101111 1010100111110000 0000010011101110 11011101
 
00C8 CMA: ALU,A,A,FTDB.F & NXCR & ZA & IDC :& ALUC & llASW & ,,NOC & IF R.F.INV.HOLD & NUM,HLDF
00C8 1100000000101111 1010100111110000 0011010011101110 11111100
 
00C9 LHLD: INepc & MMR
00C9 1100000000110101 0010010111010001 0011011111111110 11000100
 
00CA ALU'DDUBLE, ,,FTDB.F 11 OR 11 D2 11 ALUC 11 BASW 11 IDC 11 HLD
00CA 1100000000101001 0110100111110000 0011011101010100 11011111
 
00CB INCPC 11 MMR
00CB 1100000000110101 0010010111010001 0011011111111110 11000100
 
00CC ALU,,,FTDB.F 11 DR 11 DZ 11 ALUC & BASW & IDC & HLD
00CC 1100000000101001 0110100111110000 0011010101010100 11011111
 
00CD ALU DDUBLE, ,,FTDB.F 11 OR & 2A 11 ALUC 11 IDC,,TD.A 11 /BASW 11 HLD
00CD 1100000000101001 0110100111110001 0011011101010100 11011100
 
00CE tlALU & IDC & MEMR 11 IF, INV,READY 11 HUM, s
00CE 1100001100111000 0010010111010000 0011010101010100 01XXXXXX
 
00CF ALU,,L,FTDB.F & DR & DZ 11 IDC 11 BASW 11 ALUC & HLD
00CF 1100000000101001 0110100111110000 0011010101001010 11011111
 
00D0 ALU DDUBLE,,,FTOB.F 11 PLUS 11 ALUC 11 BASW 11 IDC,,TO.A & H LD/ 11 ZA
00D0 1100000000101001 0110100111110001 0011011101010100 11000100
 
 
00D1 1100001101000100 0010010111010001 0011011111110100 01011100
 
00D2 ALU,,H,FTOB.F 11 DR & D2 11 IOC 11 BASW 11 ALUC 11 ,,'NDC 11 IF R.F, INV,HOLD & tlUM,HLDF
00D2 1100000000101111 1010100111110000 0011010101001000 11011111
 
00D3 SHLD: INCPC 11 MMR
00D3 1100000000110101 0010010111010001 0011011111111110 11000100
 
00D4 ALU DOUBLE,,,FTOB.F :& DR 11 D2 11 ALUC 11 BASW 11 IOC 11 HLD
00D4 1100000000101001 0110100111110000 0011011101010100 11011111
 
00D5 INCPC 11 MMR
00D5 1100000000110101 0010010111010001 0011011111111110 11000100
 
00D6 ALU,,,FTOB.F' DR & DZ 11 ALUC & BASW :& IOC & HLD
00D6 1100000000101001 0110100111110000 0011010101010100 11011111
 
00D7 ALU DOUBLE,,,FTDB.F & DR & ZA 11 ALUC & IOC,,TD.A 11/BAS(d & HLD
00D7 1100000000101001 0110100111110001 0011011101010100 11011100
 
00D8 ALU DOUBLE,H & DR & ZA 11 IOC,,TO.D & BASW & ALue & HLD
00D8 1100000000101001 0110100111110000 1011011010010100 01011100
 
00D9 NALU 11 IDC,DL & MEM~I & IF, INV,READY & NUM, s
00D9 1100001101100100 0010010111100010 0011010101010100 01XXXXXX
 
00DA ALU DOUBLE,,,FTOB.F I\. PLUS & 2A & ALUC & BASW I\. /IOC,,TO.A I\. HLD
00DA 1100000000101001 0110100111110001 0011011101010100 11000100
 
00DB ALU DOUBLE ,PC I\. OR I\. 2A I\. ALUC & IOC,DH,TO.A I\. BASW I\. /MEMW & IF R.F,,READY I\. NUM, $
00DB 1100001101101111 1110010111100101 0011011111110100 01011100
 
00DC LDAX.B: ALU DOUBLE,B I\. BASW I\. 2A I\. OR & IOC,,TO.A & ALUC I\. HLD
00DC 1100000000101001 0110100111110001 0011011000010100 01011100
 
00DD ALU DOUBLE,PC & OR & 2A I\. IOC,,TO.A & ALUC I\. BASW I\. /MEMR & IF,INV,READY & NUM, $
00DD 1100001101110100 0010010111010001 0011011111110100 01011100
 
00DE ALU,,A,FTOB.F & OR & D2 & ALue I\. BASW & IDC & /NOC I\. IF R.F,INV,HOLD & NUM,HLDF
00DE 1100000000101111 1010100111110000 0011010101001110 11011111
 
 
00DF 1100000000101001 0110101111110001 0011011101010100 01011011
 
00E0 ALU,A & OR & 2A & IOC.,TO.D & BASW I\. ALue & HLD
00E0 1100000000101001 0110100111110000 1011010011110100 01011100
 
00E1 ALU DOUBLE,PC & OR & 2A & IOC,DH.TO.A & BASW I\. ALUC & /MEMW & IF R.F,INV,HOLD & NUM, HLDF
00E1 1100000000101111 1010100111100101 0011011111110100 01011100
 
00E2 WXCHG: ALU DOLlBLE,D,,FTOB.F & OR & 2A & ALLIe & BASh! & IDe & HLD
00E2 1100000000101001 0110100111110000 0011011001010100 11011100
 
00E3 ALU DOLlBLE,H,D,FTOB.F I\. OR I\. 2A & ALue & BASW & IDe I\. HLD
00E3 1100000000101001 0110100111110000 0011011010000100 11011100
 
00E4 ALU DOUBLE,,H,FTOB.F & OR & 2A & ALue & BASh! I\. IOC I\. /NOC & IF R.F,INV,HOLD & NLlM,HLDF
00E4 1100000000101111 1010100111110000 0011011101001000 11011100
 
00E5 U<ID: INCPC & t1MR
00E5 1100000000110101 0010010111010001 0011011111111110 11000100
 
00E6 ALLI,.E.FTOB.F & OR & D2 & ALLIe ~ BASW & HLD & IDe
00E6 1100000000101001 0110100111110000 0011010101000110 11011111
 
00E7 INCPC s, MMR
00E7 1100000000110101 0010010111010001 0011011111111110 11000100
 
00E8 ALU,,D.FTOB.F. & OR & D2 & ALUC & BASW & NOC & /IF R.F,INV,HOLD & NUM,HLDF & IOC
00E8 1100000000101111 1010100111110000 0011010101000100 11011111
 
00E9 LXIH: INCPC ~ MMR
00E9 1100000000110101 0010010111010001 0011011111111110 11000100
 
00EA ALU,,L,FTOB.F ~ OR ~ DZ ~ ALUC ~ BASW & HLD ~ IOC
00EA 1100000000101001 0110100111110000 0011010101001010 11011111
 
00EB INCPC & MMR
00EB 1100000000110101 0010010111010001 0011011111111110 11000100
 
00EC ALU,,H,FTOB.F, & OR 3. DZ 3. ALUC 3. BASW 3. NOC & /IF R.FdNY,HOLD 3. NUM.HLDF & IOC
00EC 1100000000101111 1010100111110000 0011010101001000 11011111
 
00ED LXISP: INCPC & MMR
00ED 1100000000110101 0010010111010001 0011011111111110 11000100
 
00EE ALU DOUBLE,,SP,FTDB.F & DR & D2 & ALUC & BASW 3. HLD & ID C
00EE 1100000000101001 0110100111110000 0011011101010000 11011111
 
00EF INCPC & MMR
00EF 1100000001110101 0010010111010001 0011011111111110 11000100
 
00F0 ALU,,$P.FTOB.F. & OR & DZ & ALUC & BASW & NOC & /IF R. F. INY, HOLD & NUM, HLDF & IDC
00F0 1100000000101111 1010100111110000 0011010101010000 11011111
 
00F1 INXDI ALU DOUBLE,,D.FTDB.F & PLUS & ZB & ALUC & BASW & IDC & HLD
00F1 1100000000101001 0110100111110000 0011011101000100 11000011
 
00F2 ALU DDUBLE,D,E,FTDB.A & OR :$, DZ & ALUC,SWAP & BASW & /IDC <I. tiDC 3. IF R.F,INY,HOLD & NUM,HLDF
00F2 1100000000101111 1010100111110000 0011111001000110 10011111
 
00F3 INXH: ALU DDUBLE,,H,FTOB.F & PLUS & ZB & ALUC & BASW & IOC & HLD
00F3 1100000000101001 0110100111110000 0011011101001000 11000011
 
00F4 ALU DDUBLE,H,L,FTOB.A & OR & DZ & ALUC,SWAP & BASW & /IDC & NDC & IF R.F.INY,HDLD & NUM,HLDF
00F4 1100000000101111 1010100111110000 0011111010001010 10011111
 
00F5 INXSPI ALU DOUBLE,,SP,FTDB.F , PLUS & ZB & ALUC & BASW , IDC & /NDC' IF R.F,INY,HDLD & NUM,HLDF
00F5 1100000000101111 1010100111110000 0011011101010000 11000011
 
00F6 DCXD: ALU DDUBLE,,D,FTDB.F & SUNIM , ZB & ALUC,,CNL & /BASW & IDC & HLD
00F6 1100000000101001 0110100111110000 0011001101000100 11001011
 
00F7 ALU DOU~lE,D,E,FTDB.A & OR & DZ , ALUC,$WAP & IDC & /NOC & IF R.F,INV,HOLD & NUM,HLDF
00F7 1100000000101111 101010Xl11110000 OXII111001000110 10011111
 
00F8 DCXH: ALU DOUBLE,,H,FTOB.F & SUNIM & ZB & ALUC,,CNL & /BASW & IOC & HLD
00F8 1100000000101001 0110100111110000 0011001101001000 11001011
 
00F9 ALU DDUBLE,H,L,FTOB.A & DR & DZ & ALUC,SWAP a, IDC &-'NOC 3. IF R.F,INV,HOLD & NUM,HLDF
00F9 1100000000101111 101010X111110000 0X11111010001010 10011111
 
00FA DCXSP: ALU DOUBLE,,SP,FTOB.F & SUNIM 3. ZB 3. ALUC,,CNL & /BASW & IOC & NDC & IF R.F,INY,HOLD , NUM,HLDF
00FA 1100000000101111 1010100111110000 0011001101010000 11001011
 
00FB POP.D: ALLI DOUBLE,SP,SP,FTOB.A & DR & ZA & ALUC & BASI~ & dOC,,TO.A' NOC 3. IF.,C.SBR,,HOLD & NUM,HLDSB
00FB 1100000000101001 0110100111110001 0011011100010000 10011100
 
00FC ALU DOUBLE,SP,SP,FTOB.F & PLUS' ZA & ALUC 3. BASW 3. / IOC,,TO.A 3. MEMR & IF C.SBR,INV,READY 3. NUM,MI'1RSP
00FC 1100000001000101 0010010111010001 0011011100010000 11000100
 
00FD ALU, ,E,FTDB.F 3. DR 3. DZ 3. ALUC 3. roc & BASI~ , HLD
00FD 1100000000101001 0110100111110000 0011010101000110 11011111
 
00FE ALU DDUBLE,SP,SP,FTDB.F , PLlIS' ZA , ALLIC & BASW , dOC,,TO.A & MEMR 3. IF C.SBRolNY,READY & NUM,MMRSP
00FE 1100000001000101 0010010111010001 0011011100010000 11000100
 
 
00FF 1100000000101001 0110100111110000 0011010101000100 11011111
 
0100 ALU DOUBLE,PC a, DR & ZA & ALLIC & IOC,,TD.A 3. BAS'I~ , /NOC & IF R.F,INY,HOLD & NUM.HLDF
0100 1100000000101111 1010100111110001 0011011111110100 01011100
 
0101 PDP.H: ALLI DOUBLE,SP,SP,FTDB.A & DR & ZA & AlUC & BASW & -'IOC,,TD.A & NOC & IF C.S'BR.,HOLD & NUM,HlDSB
0101 1100000000101001 0110100111110001 0011011100010000 10011100
 
0102 Alll DlJlIBLE,SP,SP,FTIJII.F & PL1JS & ZA s, ALLIC , BASI~ ~, ./ IOC,,TIJ.A & MEMR , IF C.SBR,INV,READY , NUM,MMRSP
0102 1100000001000101 0010010111010001 0011011100010000 11000100
 
0103 ALU,,L,FTOB.F & DR , DZ & ALLIC & IOC & I1ASW & HLD
0103 1100000000101001 0110100111110000 0011010101001010 11011111
 
 
0104 1100000001000101 0010010111010001 0011011100010000 11000100
 
0105 ALU,,H,FTOB.F & DR & DZ 3. ALLIe & IOC & BASW & HLD
0105 1100000000101001 0110100111110000 0011010101001000 11011111
 
0106 ALU DOUBLE, PC & DR & ZA & ALUC , IOC,,TO.A 3. BASW , /NDC & IF R.F,INY,HOLD & NUM.HlDF
0106 1100000000101111 1010100111110001 0011011111110100 01011100
 
0107 JNZ: NALLI & IDC 3. NOC 3. IF .INV,Z , NlIM,JMP
0107 1100000100001000 0000000111110000 0011010101010100 01XXXXXX
 
0108 INCPC & HLD
0108 1100000000101001 0110100111110001 0011011111111110 11000100
 
0109 INCPC & IF R.F,INV,HOlD & NUM,HlDF & Noe
0109 1100000000101111 1010100111110001 0011011111111110 11000100
 
010A CNZ: NAlU s, IDC s, NOC & IF dNV,Z & NUM,CAll
010A 1100000100011100 0000000111110000 0011010101010100 01XXXXXX
 
010B INCPC & HlD
010B 1100000000101001 0110100111110001 0011011111111110 11000100
 
010C INcpe & NOC & IF R.F,INV,HOlD & NUM,HlDF
010C 1100000000101111 1010100111110001 0011011111111110 11000100
 
010D RN2: NAlU & IOC & NOC & IF R.F,,Z & NUM,RET
010D 1100000101000011 1100000111110000 0011010101010100 01XXXXXX
 
 
010E 1100000100001000 0100000111110000 0011010101010100 01XXXXXX
 
010F INCPC & HlD
010F 1100000000101001 0110100111110001 0011011111111110 11000100
 
0110 INCPC & NOC & IF R.FoINV,HOlD & NUM,HLDF
 
0110 1100000000101111 1010100111110001 0011011111111110 11000100
 
0111 CZ: NAlU & IOC & NOC & IF , ,2 & NUM,CAlL
0111 1100000100011100 0100000111110000 0011010101010100 01XXXXXX
 
0112 INCPC & HLD
0112 1100000000101001 0110100111110001 0011011111111110 11000100
 
0113 INCPC & NOC & IF R.F,INV,HOLD & NUM,HLDF
0113 1100000000101111 1010100111110001 0011011111111110 11000100
 
0114 RZ: NAlU & IOC & HOC & IF R.F,INV,Z & NUM,RET
0114 1100000101000011 1000000111110000 0011010101010100 01XXXXXX
 
0115 .JNC: NALU & IOC & NOC & IF ,INV,CY & NUM,.JMP
0115 1100000100001000 0000010111110000 0011010101010100 01XXXXXX
 
0116 INCPC &HlD
0116 1100000000101001 0110100111110001 0011011111111110 11000100
 
0117 INCPC & NOC & IF R.F,INV,HOLD & NUM,HlDF
0117 1100000000101111 1010100111110001 0011011111111110 11000100
 
0118 CNC: NAlU & IOC & Noe & IF ,INV,CY'& NUM,CALL
0118 1100000100011100 0000010111110000 0011010101010100 01XXXXXX
 
0119 INCPC & HLD
0119 1100000000101001 0110100111110001 0011011111111110 11000100
 
011A INCPC & NOC & IF R.F ,INV,HOLD & NUM,HLDF
011A 1100000000101111 1010100111110001 0011011111111110 11000100
 
011B RNC: NALU & IDC & NOC & IF R.F,,CY & NOM,RET
011B 1100000101000011 1100010111110000 0011010101010100 01XXXXXX
 
 
011C 1100000100001000 0100010111110000 0011010101010100 01XXXXXX
 
011D INCPC & HLD
011D 1100000000101001 0110100111110001 0011011111111110 11000100
 
011E INCPC s, NDC e, IF R.FoINy.HDLD & NUM,HLDF
011E 1100000000101111 1010100111110001 0011011111111110 11000100
 
011F CC: NALU & IOC a NDC & IF ,,CY & NUM, CALL
011F 1100000100011100 0100010111110000 0011010101010100 01XXXXXX
 
0120 INCPC & HLD
0120 1100000000101001 0110100111110001 0011011111111110 11000100
 
0121 INCPC & NOC & IF R.F,INY,HOLD & NUM,HLDF
0121 1100000000101111 1010100111110001 0011011111111110 11000100
 
0122 RC: NALU & IDC & NOC & IF R.F,INY,CY & NUM,RET
0122 1100000101000011 1000010111110000 0011010101010100 01XXXXXX
 
0123 JPO: NALU & IDC & NOC & IF',INY,P & NUM,JMP
0123 1100000100001000 0000100111110000 0011010101010100 01XXXXXX
 
0124 INCPC & HLD
0124 1100000000101001 0110100111110001 0011011111111110 11000100
 
0125 INCPC & NOC & IF R.F,INY,HDLD & NUM,HLDF
0125 1100000000101111 1010100111110001 0011011111111110 11000100
 
0126 CPO: tlALU & IOC & NOC & IF ,INY,P & NUM,CALL
0126 1100000100011100 0000100111110000 0011010101010100 01XXXXXX
 
0127 INCPC & HLD
0127 1100000000101001 0110100111110001 0011011111111110 11000100
 
0128 INCPC & NOC & IF R.F,INV,HOLD& NUM,HLDF
0128 1100000000101111 1010100111110001 0011011111111110 11000100
 
0129 RPO: NALU & IOC & NOC & IF R.F,,P & NUM,RET
0129 1100000101000011 1100100111110000 0011010101010100 01XXXXXX
 
012A JPE: NALU & IOC & NOC & IF ,,p 3. NUM,~MP
012A 1100000100001000 0100100111110000 0011010101010100 01XXXXXX
 
0l2B INCPC 3. HLD
012B 1100000000101001 0110100111110001 0011011111111110 11000100
 
012C INCPC I), NOC &IF R.FdNY,HOLD :I, NUM,HLDF
012C 1100000000101111 1010100111110001 0011011111111110 11000100
 
012D CPE: NALU :I, IOC & NOC & IF ,,p & NUM,CALL
012D 1100000100011100 0100100111110000 0011010101010100 01XXXXXX
 
012E INCPC $. HLD
012E 1100000000101001 0110100111110001 0011011111111110 11000100
 
012F INCPC & NOC & IF R.F,INY,HOLD & NUM,HLDF
012F 1100000000101111 1010100111110001 0011011111111110 11000100
 
0130 RPE: NALU & IOC & NOC & IF R.F.INY,P & NUM,RET
0130 1100000101000011 1000100111110000 0011010101010100 01XXXXXX
 
0131 JP: NALU S. IOC S. NOC S. IF .INY.$ & NUM.JMP
0131 1100000100001000 0000110111110000 0011010101010100 01XXXXXX
 
0132 INCPC & HLD
0132 1100000000101001 0110100111110001 0011011111111110 11000100
 
0133 INCPC & NOC s. IF R.F,INV,HOLD S. NUM,HLDF
0133 1100000000101111 1010100111110001 0011011111111110 11000100
 
0134 CP: NALU S. IOC S. NOC ~ IF R.F,,$ & NUM,CALL
0134 1100000100011111 1100110111110000 0011010101010100 01XXXXXX
 
0135 INCPC & HLD
0135 1100000000101001 0110100111110001 0011011111111110 11000100
 
0136 INCPC S. NOC S. IF R.F,INV.HOLD S. NUM.HLDF
0136 1100000000101111 1010100111110001 0011011111111110 11000100
 
0137 RP: NALU S. IOC & NOC S. IF .INY,S & NUM,RET
0137 1100000101000000 0000110111110000 0011010101010100 01XXXXXX
 
0138 JM: NALU a, IOC & NOC & IF ,,S S. NUM,JMP
0138 1100000100001000 0100110111110000 0011010101010100 01XXXXXX
 
0139 ItKPC S. HLD
0139 1100000000101001 0110100111110001 0011011111111110 11000100
 
013A INCPC & NOC & IF R.F,INY,HOLD S. NUM,HLDF
013A 1100000000101111 1010100111110001 0011011111111110 11000100
 
013E CM: NALU & IOC & NOC :I. IF ,,s & NUM,CALL
013B 1100000100011100 0100110111110000 0011010101010100 01XXXXXX
 
013C INCPC & HLD
013C 1100000000101001 0110100111110001 0011011111111110 11000100
 
013D INepc 'NOC:I. IF R.F,INV,HOLD :I. NUM,HLDF
013D 1100000000101111 1010100111110001 0011011111111110 11000100
 
013E RM: NALU' IOC & NOC & IF R.F,INV,S :I. NUM,RET
013E 1100000101000011 1000110111110000 0011010101010100 01XXXXXX
 
013F DAA: tiRLU & IOC :I. HLII
013F 1100000000101001 0110100111110000 0011010101010100 01XXXXXX
 
0140 NALU & IDC & IF.INV & NUM DBUS,006 & NOC
0140 1000000000011000 0011110111110000 0011010101010100 01XXXXXX
 
0141 ALU,,,FTOB.F & OR :I. DZ & ALUC :I. BASW & IOC & /NOC & IF,.Ae & NUM,DAAI
0141 1100010100011000 0101000111110000 0011010101010100 11011111
 
0142 NALU , IDC ll. IF,INV :l. NUM D.BUS,OOF S. NOC
0142 1000000000111100 0011110111110000 0011010101010100 01XXXXXX
 
 
0143 1000000000101000 0011110111110000 0011010011110100 00100101
 
0144 ALU a. DQ & SUIHM a. fiLUC a. BASW & IDC & HLD
0144 1100000000101001 0110100111110000 0011010101010100 01001110
 
0145 tiALU II< IDC & NOC & IFdNY,CN.4 & NUM.$+2
0145 1100010100011100 0011100111110000 0011010101010100 01XXXXXX
 
 
0146 1100010101111101 0100010111110000 0000000101001110 11000001
 
0147 NALU & IOC & IF,INY & NUM DBUS, 060 2. NOC
0147 1000000110000000 0011110111110000 0011010101010100 01XXXXXX
 
 
014&1100010100111100 0100010111110000 0011010101010100 11011111
 
0149 NALU 2. IDC i!, IF,INV & NUN DEUS,OFO & NOC
0149 1000001111000000 0011110111110000 0011010101010100 DIXXXXXX
 
014A ALU,A,,FTOQ & AND & DA & ALUC & BASW 2. IOC & /NOC & IF,INY & NUM DBIJS,OAO
014A 1000001010000000 0011110111110000 0011010011110100 00100101
 
014B ALU & DQ & SUNIM & ALUC & BASW & IOC il. HLD
014B 1100000000101001 0110100111110000 0011010101010100 01001110
 
014C ~jALU & IOC & NOC il. IF.INY,CN.4 & NlIM,$+2
014C 1100010100111000 0011100111110000 0011010101010100 01XXXXXX
 
014D DAA2: ALU,,A,FTOB.F il. PLUS & AB & ALUC UPDTALL ,,CNL il. /BASI.oJ & IDC & HLD
014D 1100000000101001 0110100111110000 000000010100111a 11000001
 
014E NALU & IOC & NOC & IF R.F,ltlV,HOLD & NUM,HLDF
014E 1100000000101111 1010100111110000 0011010101010100 01XXXXXX
 
014F DAA3: ALU.,A,FTOB.F ~ PLUS ~ AB & ALUC UPDTFL,,CNL & /BASW & IOC & NOC & IF R.F,INV,HOLD & NUM,HLDF
014F 1100000000101111 1010100111110000 0010000101001110 11000001
 
0150 POP.PSWI ALU DOUBLE,SP,SP,FTOB.A :l. DR s, Zti & ALUC & BASW e, IOC,,T O.A &/NOC & IF C.SBR,,HOLD & NUM,HLDSB
0150 1100000000101001 0110100111110001 0011011100010000 10011100
 
0151 ALU DOUBLE.SP,SP,FTDB.F =I< PLUS & ZA & ALLIe & BASW & MEMR & /IDC,,TO.A & IF C.SBRdNY,READY e, NUM,MMRSP
0151 1100000001000101 0010010111010001 0011011100010000 11000100
 
0152 ALlJ & NAND & ALUC & I DC & BASI,) & HLD
0152 1100000000101001 0110100111110000 0011010101010100 01101XXX
 
0153 ALU DOUBLE,$P,SP,FTOB.F ~ PLUS & ZA & ALUC & BASW & dOC,,TO.A ~ MEMR ~ IF-C.SBR.JNV,READY & NUM.MMRSP
0153 1100000001000101 0010010111010001 0011011100010000 11000100
 
0154 ALU,,A,FTDB.F ~ DR & D2 & ALUC & BASW & IOC & HLD
0154 1100000000101001 0110100111110000 0011010101001110 11011111
 
0155 ALU DOUBLE,PC & DR & ZA & ALUC ~ IOC,,TO.A ~ BASW ~ NOC & /IF R.F,INV,HOLD & NUM,HLDF
0155 1100000000101111 1010100111110001 0011011111110100 01011100
 
0156 LDAX.D: ALU DOUBLE,D & BASW ~ ZA & DR & IOC,,TO.A & ALUC & HLD
0156 1100000000101001 0110100111110001 0011011001010100 01011100
 
0157 ALU DOUBLE,PC & DR & ZA ~ IOC,,TO.A ~ ALUC & BASW & /MEMR ~ IF,INY,READY & NUM, $
0157 1100010101011100 0010010111010001 0011011111110100 01011100
 
0158 ALU,,A,FTOB.F & DR & DZ & ALUC ~ BASW & IOC & /NOC & IF R.F,INY,HOLD & NUM,HLDF
0159 1100000000101111 1010100111110000 0011010101001110 11011111
 
0159 XCHG: ~ HLD
0159 1100000000101001 0110100111110000 0011111001001110 10011111
 
015A ALU DOUBLE,H,D,FTOB.A & DR & ZA & ALUC & BASW & IOC & HLD
015A 1100000000101001 0110100111110000 0011011010000100 10011100
 
015B ALU DOUBLE,L,H,FTOB.A & DR & DZ & ALUC,SWAP & BASW & IOC & HLD
015B 1100000000101001 0110100111110000 0011111010101000 10011111
 
015C ALU DOUBLE,D,E,FTOB.A & ALUC,SWAP & BASW & IOC , /NOC & IF R.F,INV,HOLD & NUM,HLDF & DR & DZ
015C 1100000000101111 1010100111110000 0011111001000110 10011111
 
015D SBI1: INepc & MMR
015D 1100000000110101 0010010111010001 0011011111111110 11000100
 
015E /BASW & NOC & IF R.F,INV,HOLD & NUM,HLDF
015E 1100000000101111 1010100111110000 0000000011101110 11001111
 
015F DAA4: ALU,Hec & SUNIM & ZA , ALUC UPDTCY,,CNL & BASW & /IDC & NOC & IF R.RTN , NUM
015F 1100000000000001 1111110111110000 0001000110010100 01001100
 
0000 ORG H#1FF
 
01FF INTRPT: NALU & IDC & NOC & IF & NUM,INTHNDL
01FF 1100001000010000 0111110111110000 0011010101010100 01XXXXXX
 
0200 END
 
 
/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/clocksinglestepper.vhd
0,0 → 1,71
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/13/2017 10:55:47 PM
-- Design Name:
-- Module Name: clocksinglestepper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity clocksinglestepper is
Port ( reset : in STD_LOGIC;
clock0_in : in STD_LOGIC;
clock1_in : in STD_LOGIC;
clock2_in : in STD_LOGIC;
clock3_in : in STD_LOGIC;
clocksel : in STD_LOGIC_VECTOR(1 downto 0);
modesel : in STD_LOGIC;
singlestep : in STD_LOGIC;
clock_out : out STD_LOGIC);
end clocksinglestepper;
 
architecture Behavioral of clocksinglestepper is
 
signal clock_in, clock_disable, clock_ss: std_logic;
 
begin
 
clock_in <= clock0_in when (clocksel = "00") else
clock1_in when (clocksel = "01") else
clock2_in when (clocksel = "10") else
clock3_in when (clocksel = "11") else
'0';
clock_out <= clock_in or clock_disable;
clock_ss <= clock_in when (clock_disable = '0') else singlestep;
 
ss: process(reset, clock_ss, modesel)
begin
if (reset = '1') then
clock_disable <= modesel;
else
if (rising_edge(clock_ss)) then
clock_disable <= (not clock_disable and modesel);
end if;
end if;
end process;
 
end Behavioral;
/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/interrupt_controller.vhd
0,0 → 1,123
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:12:03 12/12/2017
-- Design Name:
-- Module Name: interrupt_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity interrupt_controller is
Port ( CLK : in STD_LOGIC;
nRESET : in STD_LOGIC;
INT : out STD_LOGIC;
nINTA : in STD_LOGIC;
INTE : in STD_LOGIC;
D : out STD_LOGIC_VECTOR (7 downto 0);
DEVICEREQ : in STD_LOGIC_VECTOR (7 downto 0);
DEVICEACK : out STD_LOGIC_VECTOR (7 downto 0));
end interrupt_controller;
 
architecture Behavioral of interrupt_controller is
 
--constant opcode_rst0: std_logic_vector(7 downto 0) := X"C7";
--constant opcode_rst1: std_logic_vector(7 downto 0) := X"CF";
--constant opcode_rst2: std_logic_vector(7 downto 0) := X"D7";
--constant opcode_rst3: std_logic_vector(7 downto 0) := X"DF";
--constant opcode_rst4: std_logic_vector(7 downto 0) := X"E7";
--constant opcode_rst5: std_logic_vector(7 downto 0) := X"EF";
--constant opcode_rst6: std_logic_vector(7 downto 0) := X"F7";
--constant opcode_rst7: std_logic_vector(7 downto 0) := X"FF";
constant opcode_noop: std_logic_vector(7 downto 0) := X"00";
 
signal vector: std_logic_vector(7 downto 0);
signal level: std_logic_vector(3 downto 0);
signal intreq, intclk: std_logic;
 
begin
 
D <= vector when (nINTA = '0') else "ZZZZZZZZ";
--intclk <= CLK when (intreq = '0') else nINTA;
INT <= intreq;
 
level <= "1111" when DEVICEREQ(7) = '1' else -- highest level 7 == RST 7
"1110" when DEVICEREQ(6) = '1' else
"1101" when DEVICEREQ(5) = '1' else
"1100" when DEVICEREQ(4) = '1' else
"1011" when DEVICEREQ(3) = '1' else
"1010" when DEVICEREQ(2) = '1' else
"1001" when DEVICEREQ(1) = '1' else
"1000" when DEVICEREQ(0) = '1' else -- lowest level 0 == RST 0
"0000"; -- no interrupt
 
generate_ack: process(nINTA, vector)
begin
if (nINTA = '0') then
case vector(5 downto 3) is
when "000" =>
DEVICEACK <= "00000001";
when "001" =>
DEVICEACK <= "00000010";
when "010" =>
DEVICEACK <= "00000100";
when "011" =>
DEVICEACK <= "00001000";
when "100" =>
DEVICEACK <= "00010000";
when "101" =>
DEVICEACK <= "00100000";
when "110" =>
DEVICEACK <= "01000000";
when "111" =>
DEVICEACK <= "10000000";
when others =>
null;
end case;
else
DEVICEACK <= "00000000";
end if;
end process;
 
loadvector: process(nRESET, CLK, level, INTE, nINTA)
begin
if (nRESET = '0') then
intreq <= '0';
vector <= opcode_noop; --- not really used
else
if (rising_edge(CLK)) then
if (intreq = '0') then
if (level(3) = '1' and INTE = '1') then
intreq <= '1';
vector <= "11" & level(2 downto 0) & "111";
end if;
else
intreq <= nINTA;
end if;
end if;
end if;
end process;
 
end Behavioral;
 
/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/simpleram.vhd
0,0 → 1,112
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:56:00 11/12/2017
-- Design Name:
-- Module Name: simpleram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity simpleram is
generic (
address_size: positive := 16;
default_value: STD_LOGIC_VECTOR(7 downto 0) := X"FF");
Port (
clk: in STD_LOGIC;
D : inout STD_LOGIC_VECTOR (7 downto 0);
A : in STD_LOGIC_VECTOR ((address_size - 1) downto 0);
nRead : in STD_LOGIC;
nWrite : in STD_LOGIC;
nSelect : in STD_LOGIC);
end simpleram;
 
-- Using RAM from Xilinx IPCore library
--architecture structural of simpleram is
--
--component ram4kx8 IS
-- PORT (
-- clka : IN STD_LOGIC;
-- ena : IN STD_LOGIC;
-- wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-- );
--end component;
--
--signal d_out: std_logic_vector(7 downto 0);
--signal ena: std_logic;
--signal wr: std_logic_vector(0 downto 0);
--
--begin
--
--ena <= not nSelect;
--wr <= "" & not nWrite;
--D <= d_out when (nRead = '0' and nSelect = '0') else "ZZZZZZZZ";
--
--inner_ram: ram4kx8 port map
-- (
-- clka => clk,
-- ena => ena,
-- wea => wr,
-- addra => A,
-- dina => D,
-- douta => d_out
-- );
--
--end structural;
-- Using standard abstract VHDL
architecture Behavioral of simpleram is
 
type bytememory is array(0 to (2 ** address_size) - 1) of std_logic_vector(7 downto 0);
signal d_out: std_logic_vector(7 downto 0);
signal control: std_logic_vector(2 downto 0);
 
signal ram: bytememory := (others => default_value);
attribute ram_style: string;
attribute ram_style of ram: signal is "block";
 
begin
 
control <= nSelect & nRead & nWrite;
D <= d_out when (nRead = '0' and nSelect = '0') else "ZZZZZZZZ";
 
readwrite: process(clk, control, A, D, ram)
begin
case control is
when "010" => -- write
if (rising_edge(clk)) then
ram(to_integer(unsigned(A))) <= D;
end if;
when "001" => -- read
d_out <= ram(to_integer(unsigned(A)));
when others =>
null;
end case;
end process;
 
end Behavioral;
 
/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk/sys9080.vhd
0,0 → 1,536
----------------------------------------------------------------------------------
-- Company: @Home
-- Engineer: zpekic@hotmail.com
--
-- Create Date: 08/24/2017 11:13:02 PM
-- Design Name:
-- Module Name: sys9080 - Behavioral
-- Project Name: Simple 8-bit system around microcode implemented Am9080 CPU
-- Target Devices: https://www.micro-nova.com/mercury/ + Baseboard
-- Tool Versions: ISE 14.7 (nt)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.99 - Kinda works...
-- Additional Comments:
-- https://en.wikichip.org/w/images/7/76/An_Emulation_of_the_Am9080A.pdf
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity sys9080 is
Port (
-- 50MHz on the Mercury board
CLK: in std_logic;
-- Master reset button on Mercury board
USR_BTN: in std_logic;
-- Switches on baseboard
-- SW(1 downto 0) -- LED display selection
-- 0 0 Sys9080 - A(7:0) & D(7:0) & io and memory r/w on dots
-- 0 1 Sys9080 - OUT port 1 & port 0
-- 1 0 Am9080 - microinstruction counter & instruction register
-- 1 1 Am9080 - content of register as defined by SW5:2
-- SW(5 downto 2) -- 4 bit Am9080 register selector when inspecting register states in SS mode
-- SW(6 downto 5) -- system clock speed
-- 0 0 1Hz (can be used with SS mode)
-- 0 1 1024Hz (can be used with SS mode)
-- 1 0 6.125MHz
-- 1 1 25MHz
-- SW7
-- 0 single step mode off (BTN3 should be pressed once to start the system)
-- 1 single step mode on (use with BTN3)
SW: in std_logic_vector(7 downto 0);
-- Push buttons on baseboard
-- BTN0 - generate RST 7 interrupt which will dump processor regs and memory they are pointing to over ACIA0
-- BTN1 - bypass ACIA Rx char input processing and dump received bytes and status to ACIA0
-- BTN2 - put processor into HOLD mode
-- BTN3 - single step clock cycle forward if in SS mode (NOTE: single press on this button is needed after reset to unlock SS circuit)
BTN: in std_logic_vector(3 downto 0);
-- Stereo audio output on baseboard
--AUDIO_OUT_L, AUDIO_OUT_R: out std_logic;
-- 7seg LED on baseboard
A_TO_G: out std_logic_vector(6 downto 0);
AN: out std_logic_vector(3 downto 0);
DOT: out std_logic;
-- 4 LEDs on Mercury board
LED: out std_logic_vector(3 downto 0);
-- ADC interface
--ADC_MISO: in std_logic;
--ADC_MOSI: out std_logic;
--ADC_SCK: out std_logic;
--ADC_CSN: out std_logic;
--PMOD interface (for hex keypad)
PMOD: inout std_logic_vector(7 downto 0)
 
);
end sys9080;
 
architecture Structural of sys9080 is
 
component clock_divider is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
slow : out STD_LOGIC_VECTOR (11 downto 0);
fast : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
 
component clocksinglestepper is
Port ( reset : in STD_LOGIC;
clock0_in : in STD_LOGIC;
clock1_in : in STD_LOGIC;
clock2_in : in STD_LOGIC;
clock3_in : in STD_LOGIC;
clocksel : in STD_LOGIC_VECTOR(1 downto 0);
modesel : in STD_LOGIC;
singlestep : in STD_LOGIC;
clock_out : out STD_LOGIC);
end component;
 
component counter16bit is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
mode : in STD_LOGIC_VECTOR (1 downto 0);
d : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end component;
 
component debouncer8channel is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
signal_raw : in STD_LOGIC_VECTOR(7 downto 0);
signal_debounced : out STD_LOGIC_VECTOR(7 downto 0));
end component;
 
component fourdigitsevensegled is
Port ( -- inputs
data : in STD_LOGIC_VECTOR (15 downto 0);
digsel : in STD_LOGIC_VECTOR (1 downto 0);
showdigit : in STD_LOGIC_VECTOR (3 downto 0);
showdot : in STD_LOGIC_VECTOR (3 downto 0);
showsegments : in STD_LOGIC;
-- outputs
anode : out STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
 
component simpledevice is
Port(
clk : in STD_LOGIC;
reset: in STD_LOGIC;
D: inout STD_LOGIC_VECTOR(7 downto 0);
A: in STD_LOGIC_VECTOR(3 downto 0);
nRead: in STD_LOGIC;
nWrite: in STD_LOGIC;
IntReq: out STD_LOGIC;
IntAck: in STD_LOGIC;
nSelect: in STD_LOGIC;
direct_in: in STD_LOGIC_VECTOR(15 downto 0);
direct_out: out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
 
component ACIA is
Port(
clk : in STD_LOGIC;
reset: in STD_LOGIC;
D: inout STD_LOGIC_VECTOR(7 downto 0);
A: in STD_LOGIC;
nRead: in STD_LOGIC;
nWrite: in STD_LOGIC;
nSelect: in STD_LOGIC;
IntReq: out STD_LOGIC;
IntAck: in STD_LOGIC;
txd: out STD_LOGIC;
rxd: in STD_LOGIC
);
end component;
 
component simpleram is
generic (
address_size: integer;
default_value: STD_LOGIC_VECTOR(7 downto 0)
);
Port (
clk: in STD_LOGIC;
D : inout STD_LOGIC_VECTOR (7 downto 0);
A : in STD_LOGIC_VECTOR ((address_size - 1) downto 0);
nRead : in STD_LOGIC;
nWrite : in STD_LOGIC;
nSelect : in STD_LOGIC);
end component;
 
component hexfilerom is
Generic (
filename: string;
address_size: integer;
default_value: STD_LOGIC_VECTOR(7 downto 0)
);
Port (
D : out STD_LOGIC_VECTOR (7 downto 0);
A : in STD_LOGIC_VECTOR ((address_size - 1) downto 0);
nRead : in STD_LOGIC;
nSelect : in STD_LOGIC
);
end component;
 
component interrupt_controller is
Port ( CLK : in STD_LOGIC;
nRESET : in STD_LOGIC;
INT : out STD_LOGIC;
nINTA : in STD_LOGIC;
INTE : in STD_LOGIC;
D : out STD_LOGIC_VECTOR (7 downto 0);
DEVICEREQ : in STD_LOGIC_VECTOR (7 downto 0);
DEVICEACK : out STD_LOGIC_VECTOR (7 downto 0));
end component;
 
component Am9080a is
Port ( DBUS : inout STD_LOGIC_VECTOR (7 downto 0);
ABUS : out STD_LOGIC_VECTOR (15 downto 0);
WAITOUT : out STD_LOGIC;
nINTA : out STD_LOGIC;
nIOR : out STD_LOGIC;
nIOW : out STD_LOGIC;
nMEMR : out STD_LOGIC;
nMEMW : out STD_LOGIC;
HLDA : out STD_LOGIC;
INTE : out STD_LOGIC;
CLK : in STD_LOGIC;
nRESET : in STD_LOGIC;
INT: in STD_LOGIC;
READY: in STD_LOGIC;
HOLD: in STD_LOGIC;
-- debug port, not part of actual processor
debug_ena : in STD_LOGIC;
debug_sel : in STD_LOGIC;
debug_out : out STD_LOGIC_VECTOR (19 downto 0);
debug_reg : in STD_LOGIC_VECTOR(3 downto 0)
);
end component;
 
--component ila_0 IS
-- PORT (
-- clk : IN STD_LOGIC;
-- probe0 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
-- probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0));
--end component;
 
component vio_0 IS
PORT (
clk : IN STD_LOGIC;
probe_in0 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe_in1 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe_in2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe_in3 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe_out0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
probe_out1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
probe_out2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
probe_out3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END component;
 
-- CPU buses
signal data_bus: std_logic_vector(7 downto 0);
signal address_bus: std_logic_vector(15 downto 0);
signal Reset, nReset: std_logic;
signal clock_main: std_logic;
signal nIORead, nIOWrite, nMemRead, nMemWrite: std_logic;
signal IntReq, nIntAck, Hold, HoldAck, IntE: std_logic;
 
-- other signals
signal reset_delay: std_logic_vector(3 downto 0);
signal DeviceReq: std_logic_vector(7 downto 0);
signal DeviceAck: std_logic_vector(7 downto 0);
signal switch: std_logic_vector(7 downto 0);
signal button: std_logic_vector(7 downto 0);
--signal cnt: std_logic_vector(31 downto 0);
signal io_output: std_logic_vector(15 downto 0);
signal led_bus: std_logic_vector(19 downto 0);
signal cpu_debug_bus, sys_debug_bus: std_logic_vector(19 downto 0);
signal nIoEnable, nACIA0Enable, nACIA1Enable, nBootRomEnable, nMonRomEnable, nRamEnable: std_logic;
signal readwritesignals: std_logic_vector(4 downto 0);
signal showsegments: std_logic;
signal flash: std_logic;
signal freq2k, freq1k, freq512, freq256, freq128, freq64, freq32, freq16, freq8, freq4, freq2, freq1: std_logic;
signal freq25M, freq12M5, freq6M25, freq3M125: std_logic;
 
begin
Reset <= USR_BTN;
nReset <= '0' when (Reset = '1') or (reset_delay /= "0000") else '1';
led_bus <= cpu_debug_bus when (switch(1) = '1') else sys_debug_bus;
sys_debug_bus <= readwritesignals(4 downto 1) & address_bus(7 downto 0) & data_bus when (switch(0) = '0') else "0000" & io_output;
readwritesignals <= (not nIORead) & (not nIOWrite) & (not nMemRead) & (not nMemWrite) & (not nIntAck);
showsegments <= '0' when (switch(1 downto 0) = "00" and readwritesignals = "00000") else '1';
 
Hold <= button(2);
flash <= HoldAck or freq2; -- blink in hold bus mode!
-- DISPLAY
LED(3) <= nIntAck;
LED(2) <= IntReq;
LED(1) <= HoldAck;
LED(0) <= clock_main;
led4x7: fourdigitsevensegled port map (
-- inputs
data => led_bus(15 downto 0),
digsel(1) => freq1k,
digsel(0) => freq2k,
showdigit(3) => flash,
showdigit(2) => flash,
showdigit(1) => flash,
showdigit(0) => flash,
showdot => led_bus(19 downto 16),
showsegments => showsegments,
-- outputs
anode => AN,
segment(6 downto 0) => A_TO_G(6 downto 0),
segment(7) => DOT
);
 
-- FREQUENCY GENERATOR
one_sec: clock_divider port map
(
clock => CLK,
reset => Reset,
slow(11) => freq1, -- 1Hz
slow(10) => freq2, -- 2Hz
slow(9) => freq4, -- 4Hz
slow(8) => freq8, -- 8Hz
slow(7) => freq16, -- 16Hz
slow(6) => freq32, -- 32Hz
slow(5) => freq64, -- 64Hz
slow(4) => freq128, -- 128Hz
slow(3) => freq256, -- 256Hz
slow(2) => freq512, -- 512Hz
slow(1) => freq1k, -- 1024Hz
slow(0) => freq2k, -- 2048Hz
fast(3) => freq3M125,
fast(2) => freq6M25,
fast(1) => freq12M5,
fast(0) => freq25M
);
 
-- DEBOUNCE the 8 switches and 4 buttons
debouncer_sw: debouncer8channel port map (
clock => freq128,
reset => Reset,
signal_raw => SW,
signal_debounced => switch
);
 
debouncer_btn: debouncer8channel port map (
clock => freq128,
reset => Reset,
signal_raw(7 downto 4) => "1111",
signal_raw(3 downto 0) => BTN(3 downto 0),
signal_debounced => button
);
-- Hook up buttons to generate interrupts
irq7: process(nReset, button(0), deviceack(7))
begin
if (nReset = '0' or deviceack(7) = '1') then
devicereq(7) <= '0';
else
if (rising_edge(button(0))) then
devicereq(7) <= '1';
end if;
end if;
end process;
 
irq6: process(nReset, button(1), deviceack(6))
begin
if (nReset = '0' or deviceack(6) = '1') then
devicereq(6) <= '0';
else
if (rising_edge(button(1))) then
devicereq(6) <= '1';
end if;
end if;
end process;
-- delay to generate nReset 4 cycles after reset
generate_nReset: process (clock_main, Reset)
begin
if (Reset = '1') then
reset_delay <= "1111";
else
if (rising_edge(clock_main)) then
reset_delay <= reset_delay(2 downto 0) & Reset;
end if;
end if;
end process;
-- Single step by each clock cycle, slow or fast
ss: clocksinglestepper port map (
reset => Reset,
clock0_in => freq2,
clock1_in => freq2k,
clock2_in => freq3M125,
clock3_in => freq25M,
clocksel => switch(6 downto 5),
modesel => switch(7),
singlestep => button(3),
clock_out => clock_main
);
-- ila_ss: ila_0 port map (
-- clk => CLK,
-- probe0(5) => RESET,
-- probe0(4) => button(3),
-- probe0(3) => switch(3),
-- probe0(2) => switch(2),
-- probe0(1) => freq2k,
-- probe0(0) => freq1,
-- probe1(0) => clock_main
-- );
nIoEnable <= (nIoRead and nIoWrite) when address_bus(7 downto 4) = "0000" else '1'; -- 0x00 - 0x0F
nACIA0Enable <= (nIoRead and nIoWrite) when address_bus(7 downto 1) = "0001000" else '1'; -- 0x10 - 0x11
nACIA1Enable <= (nIoRead and nIoWrite) when address_bus(7 downto 1) = "0001001" else '1'; -- 0x12 - 0x13
nBootRomEnable <= nMemRead when address_bus(15 downto 10) = "000000" else '1'; -- 1k ROM (0000 - 03FF)
nMonRomEnable <= nMemRead when address_bus(15 downto 10) = "000001" else '1'; -- 1k ROM (0400 - 07FF)
nRamEnable <= (nMemRead and nMemWrite) when address_bus(15 downto 8) = "11111111" else '1'; -- 256b RAM (FF00 - FFFF)
iodevice: simpledevice port map(
clk => CLK, -- this is the full 50MHz clock!
reset => Reset,
D => data_bus,
A => address_bus(3 downto 0),
nRead => nIORead,
nWrite => nIOWrite,
nSelect => nIoEnable,
IntReq => open,
IntAck => '1',
direct_in(7 downto 0) => switch,
direct_in(15 downto 8) => button,
direct_out => io_output
);
 
acia0: ACIA port map(
clk => CLK, -- this is the full 50MHz clock!
reset => Reset,
D => data_bus,
A => address_bus(0),
nRead => nIORead,
nWrite => nIOWrite,
nSelect => nAcia0Enable,
IntReq => DeviceReq(5),
IntAck => DeviceAck(5),
txd => PMOD(0),
rxd => PMOD(1)
);
 
acia1: ACIA port map(
clk => CLK, -- this is the full 50MHz clock!
reset => Reset,
D => data_bus,
A => address_bus(0),
nRead => nIORead,
nWrite => nIOWrite,
nSelect => nAcia1Enable,
IntReq => DeviceReq(4),
IntAck => DeviceAck(4),
txd => PMOD(2),
rxd => PMOD(3)
);
bootrom: hexfilerom
generic map(
filename => "./prog/zout/boot.hex",
address_size => 10,
default_value => X"FF" -- if executed, will be RST 7
)
port map(
D => data_bus,
A => address_bus(9 downto 0),
nRead => nMemRead,
nSelect => nBootRomEnable
);
 
monrom: hexfilerom
generic map(
filename => "./prog/zout/altmon.hex",
address_size => 10,
default_value => X"FF" -- if executed, will be RST 7
)
port map(
D => data_bus,
A => address_bus(9 downto 0),
nRead => nMemRead,
nSelect => nMonRomEnable
);
 
ram: simpleram
generic map(
address_size => 8,
default_value => X"FF" -- if executed, will be RST 7
)
port map(
clk => clock_main,
D => data_bus,
A => address_bus(7 downto 0),
nRead => nMemRead,
nWrite => nMemWrite,
nSelect => nRamEnable
);
ic: interrupt_controller Port map (
CLK => CLK, -- this is the full 50MHz clock!
nRESET => nReset,
INT => IntReq,
nINTA => nIntAck,
INTE => IntE,
D => data_bus,
DEVICEREQ(7) => devicereq(7), -- button 0
DEVICEREQ(6) => devicereq(6), -- button 1
DEVICEREQ(5) => devicereq(5), -- ACIA 0
DEVICEREQ(4) => '0', --devicereq(4), -- ACIA 1 $BUGBUG - interrupt req stuck for ACIA1?
DEVICEREQ(3) => '0',
DEVICEREQ(2) => '0',
DEVICEREQ(1) => '0',
DEVICEREQ(0) => '0',
DEVICEACK => DeviceAck
);
cpu: Am9080a port map (
DBUS => data_bus,
ABUS => address_bus,
WAITOUT => open,
nINTA => nIntAck,
nIOR => nIORead,
nIOW => nIOWrite,
nMEMR => nMemRead,
nMEMW => nMemWrite,
HLDA => HoldAck,
INTE => IntE,
CLK => clock_main,
nRESET => nReset,
INT => IntReq,
READY => '1', -- TODO - use to implement single stepping per instruction, not cycle
HOLD => Hold,
-- debug port, not part of actual processor
debug_ena => switch(1),
debug_sel => switch(0),
debug_out => cpu_debug_bus,
debug_reg => switch(5 downto 2)
);
end;

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