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/async_sdm_noc/branches/common/src/cell_lib.v
1,140 → 1,163
// A synthesizable cell library for asynchronous logic
// author Wei Song, songw@cs.man.ac.uk
// the Advanced Processor Technology Group
// the School of Computer Science
// the Uniersity of Manchester
// 5th May, 2009
// a latch is added, 11/08/2010 songw@cs.man.ac.uk
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
A synthesizable cell library for asynchronous circuis.
Some cell are directly initialized to one of the Nangate 45nm cell lib.
History:
05/05/2009 Initial version. <wsong83@gmail.com>
20/05/2011 Change to general verilog description for opensource.
The Nangate cell library is used. <wsong83@gmail.com>
*/
 
// General 2-input C-element
module c2 (a0, a1, q);
 
module c2 (
a0
,a1
,q
);
input a0, a1; // two inputs
output q; // output
 
input a0;
input a1;
output q;
wire [2:0] m; // internal wires
 
AO222EHD U1 ( .A1(q), .A2(a0), .B1(q), .B2(a1), .C1(a0), .C2(a1), .O(q) );
 
nand U1 (m[0], a0, a1);
nand U2 (m[1], a0, q);
nand U3 (m[2], a1, q);
assign q = &m;
endmodule
 
// the dc2 cell for Faraday 130nm Tech
module dc2 (
d
,a
,q
);
// the 2-input C-element on data paths, different name for easy synthesis scription
module dc2 (d, a, q);
 
input d;
input a;
output q;
input d; // data input
input a; // ack input
output q; // data output
 
AO222HHD U1 ( .A1(q), .A2(d), .B1(q), .B2(a), .C1(d), .C2(a), .O(q) );
wire [2:0] m; // internal wires
 
endmodule // dc2
nand U1 (m[0], a, d);
nand U2 (m[1], d, q);
nand U3 (m[2], a, q);
assign q = &m;
 
module c2n (
a0
,a1
,q
);
endmodule
 
input a0;
input a1;
output q;
// 2-input C-element with a minus input
module c2n (a, b, q);
 
AO12EHD U1 (.B1(a1), .B2(q), .A1(a0), .O(q));
input a; // the normal input
input b; // the minus input
output q; // output
 
wire m; // internal wire
and U1 (m, b, q);
or U2 (q, m, a);
endmodule
 
// 2-input C-element with a plus input
module c2p (a, b, q);
 
module c2p (
a0
,a1
,q
);
input a; // the normal input
input b; // the plus input
output q; // output
 
input a0;
input a1;
output q;
wire m; // internal wire
 
or U1 (m, b, q);
and U2 (q, m, a);
endmodule
 
OA12EHD U1 ( .B1(a1), .B2(q), .A1(a0), .O(q) );
// 2-input MUTEX cell, Nangate
module mutex ( a, b, qa, qb ); // !!! dont touch !!!
 
endmodule
input a, b; // request inputs
output qa, qb; // grant outputs
 
// for Faraday
module mutex ( a, b, qa, qb );
input a, b;
output qa, qb;
wire qan, qbn;
wire qan, qbn; // internal wires
 
ND2HHD U1 ( .I1(a), .I2(qbn), .O(qan) );
NR3HHD U2 ( .I1(qbn), .I2(qbn), .I3(qbn), .O(qb) );
NR3HHD U3 ( .I1(qan), .I2(qan), .I3(qan), .O(qa) );
ND2KHD U4 ( .I1(b), .I2(qan), .O(qbn) );
NAND2_X2 U1 ( .A1(a), .A2(qbn), .ZN(qan) ); // different driving strength for fast convergence
NOR3_X2 U2 ( .A1(qbn), .A2(qbn), .A3(qbn), .ZN(qb) ); // pulse filter
NOR3_X2 U3 ( .A1(qan), .A2(qan), .A3(qan), .ZN(qa) ); // pulse filter
NAND2_X1 U4 ( .A1(b), .A2(qan), .ZN(qbn) );
 
endmodule
 
 
module c2p1 (
a0,
a1,
b,
q
);
input a0, a1, b;
output q;
// 3-input C-element with a plus input
module c2p1 (a0, a1, b, q);
input a0, a1; // normal inputs
input b; // plus input
output q; // output
wire n1;
OA12EHD U2 ( .B1(a1), .B2(a0), .A1(q), .O(n1) );
AO13EHD U1 ( .B1(a1), .B2(a0), .B3(b), .A1(n1), .O(q) );
//assign q = (a0&a1&b)|(a0&q)|(b0&q);
endmodule // c2p1
wire [2:0] m; // internal wires
 
nand U1 (m[0], a0, a1, b);
nand U2 (m[1], a0, q);
nand U3 (m[2], a1, q);
assign q = &m;
 
endmodule
 
// the basic element of a tree arbiter
module tarb ( ngnt, ntgnt, req, treq );
output [1:0] ngnt;
input [1:0] req;
input ntgnt;
output treq;
wire n1, n2;
wire [1:0] mgnt;
 
mutex ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) );
c2n C0 ( .a0(ntgnt), .a1(n2), .q(ngnt[0]) );
c2n C1 ( .a0(ntgnt), .a1(n1), .q(ngnt[1]) );
ND2HHD U1 ( .I1(n1), .I2(n2), .O(treq) );
ND2DHD U2 ( .I1(ngnt[0]), .I2(mgnt[1]), .O(n1) );
ND2DHD U3 ( .I1(ngnt[1]), .I2(mgnt[0]), .O(n2) );
input [1:0] req; // request input
output [1:0] ngnt; // the negative grant output
output treq; // combined request output
input ntgnt; // the negative combined grant input
wire n1, n2; // internal wires
wire [1:0] mgnt; // outputs of the MUTEX
 
mutex ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) );
c2n C0 ( .a(ntgnt), .b(n2), .q(ngnt[0]) );
c2n C1 ( .a(ntgnt), .b(n1), .q(ngnt[1]) );
nand U1 (treq, n1, n2);
nand U2 (n1, ngnt[0], mgnt[1]);
nand U3 (n2, ngnt[1], mgnt[0]);
endmodule
 
// the tile in a multi-resource arbiter
module cr_blk ( bo, hs, cbi, rbi, rg, cg );
input cbi, rbi, rg, cg;
output bo, hs;
wire blk;
 
c2p1 XG ( .a0(rg), .a1(cg), .b(blk), .q(bo) );
c2p1 HG ( .a0(cbi), .a1(rbi), .b(bo), .q(hs) );
NR2EHD U1 ( .I1(rbi), .I2(cbi), .O(blk) );
input rg, cg; // input requests
input cbi, rbi; // input blockage
output bo; // output blockage
output hs; // match result
wire blk; // internal wire
 
c2p1 XG ( .a0(rg), .a1(cg), .b(blk), .q(bo) );
c2p1 HG ( .a0(cbi), .a1(rbi), .b(bo), .q(hs) );
nor U1 (blk, rbi, cbi);
 
endmodule
 
// a data latch template, Nangate
module dlatch ( q, qb, d, g);
output q, qb;
input d, g;
 
DLAHEHD U1 (.Q(q), .QB(qb), .D(d), .G(g));
endmodule // dlatch
DLH_X1 U1 (.Q(q), .D(d), .G(g));
endmodule
 
// a delay line, Nangate
module delay (q, a);
input a;
output q;
BUFKHD U (.O(q), .I(a));
endmodule // delay
BUF_X2 U (.Z(q), .A(a));
endmodule
 

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