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/trunk/rtl/vhdl/fsm_core_v2_1.vhd File deleted
trunk/rtl/vhdl/fsm_core_v2_1.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/vhdl/add_sub.vhd =================================================================== --- trunk/rtl/vhdl/add_sub.vhd (revision 7) +++ trunk/rtl/vhdl/add_sub.vhd (nonexistent) @@ -1,135 +0,0 @@ --- VHDL Entity R65C02_TC.ADD_SUB.symbol --- --- Created: --- by - eda.UNKNOWN (ENTWICKL4-XP-PR) --- at - 16:40:32 09.08.2008 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity ADD_SUB is - port( - d_in : in std_logic_vector ( 7 downto 0 ) := X"00"; - reg_0F_in : in std_logic := '0'; - reg_7F_in : in std_logic := '0'; - reg_a_in : in std_logic_vector ( 7 downto 0 ) := X"00"; - sel : in std_logic_vector ( 1 downto 0 ) := "00"; - reg_0F : out std_logic := '0'; - reg_6F : out std_logic := '0'; - reg_a : out std_logic_vector ( 7 downto 0 ) := X"00"; - zw_alu : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; - zw_alu1 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; - zw_alu2 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; - zw_alu3 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; - zw_alu4 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00" - ); - --- Declarations - -end ADD_SUB ; - --- Jens-D. Gutschmidt Project: R65C02_TC --- scantara2003@yahoo.de --- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- CVS Revisins History --- --- $Log: not supported by cvs2svn $ --- --- Title: Adder and Substractor --- Path: R65C02_TC/ADD_SUB/flow --- Edited: by eda on 05 Aug 2008 --- --- VHDL Architecture R65C02_TC.ADD_SUB.flow --- --- Created: --- by - eda.UNKNOWN (ENTWICKL4-XP-PR) --- at - 16:40:32 09.08.2008 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; -architecture flow of ADD_SUB is - -begin - - ----------------------------------------------------------------- - process0_proc : process (d_in, reg_0F_in, reg_7F_in, reg_a_in, sel, zw_alu, zw_alu1, zw_alu2, zw_alu3, zw_alu4) - ----------------------------------------------------------------- - begin - case sel(1 downto 0) is - when "01" => - reg_6F <= reg_7F_in XOR zw_ALU(7); - reg_0F <= zw_ALU4(4); - reg_A <= zw_ALU(7 downto 0); - zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + - unsigned (zw_ALU4(7 downto 5)); - zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + - unsigned (zw_ALU3(7 downto 5)); - - zw_ALU4(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & - (zw_ALU2(4) OR zw_ALU4(4)) & '0'; - zw_ALU3(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & - (zw_ALU1(4) OR zw_ALU3(4)) & '0'; - - zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; - zw_ALU2(4 downto 0) <= unsigned ('0' & reg_A_in(7 downto 4)) + unsigned - ('0' & D_IN(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); - - zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; - zw_ALU1(4 downto 0) <= unsigned ('0' & reg_A_in(3 downto 0)) + unsigned - ('0' & D_IN(3 downto 0)) + reg_0F_in; - when "00" => - reg_6F <= reg_7F_in XOR zw_ALU(7); - reg_0F <= zw_ALU(8); - reg_A <= zw_ALU(7 downto 0); - zw_ALU <= unsigned ('0' & reg_A_in) + unsigned ('0' & D_IN) + reg_0F_in; - when "10" => - reg_6F <= reg_7F_in XOR zw_ALU(7); - reg_0F <= zw_ALU(8); - reg_A <= zw_ALU(7 downto 0); - zw_ALU <= unsigned ('0' & reg_A_in) + unsigned ('0' & NOT (D_IN)) + reg_0F_in; - when "11" => - reg_6F <= reg_7F_in XOR zw_ALU(7); - reg_0F <= zw_ALU2(4); - reg_A <= zw_ALU(7 downto 0); - zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + - unsigned ((zw_ALU4(8 downto 5))); - zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + - unsigned ((zw_ALU3(8 downto 5))); - - zw_ALU4(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & - (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; - zw_ALU3(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & - (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; - - zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; - zw_ALU2(4 downto 0) <= unsigned ('0' & reg_A_in(7 downto 4)) + unsigned - ('0' & NOT (D_IN(7 downto 4))) + zw_ALU1(4); - - zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; - zw_ALU1(4 downto 0) <= unsigned ('0' & reg_A_in(3 downto 0)) + unsigned - ('0' & NOT (D_IN(3 downto 0))) + reg_0F_in; - when others => - reg_6F <= reg_7F_in XOR zw_ALU(7); - reg_0F <= zw_ALU(8); - reg_A <= zw_ALU(7 downto 0); - zw_ALU <= unsigned ('0' & reg_A_in) + unsigned ('0' & D_IN) + reg_0F_in; - end case; - end process process0_proc; - - -end flow;
trunk/rtl/vhdl/add_sub.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/vhdl/alu.vhd =================================================================== --- trunk/rtl/vhdl/alu.vhd (revision 7) +++ trunk/rtl/vhdl/alu.vhd (nonexistent) @@ -1,222 +0,0 @@ --- VHDL Entity R65C02_TC.ALU.symbol --- --- Created: --- by - eda.UNKNOWN (ENTWICKL4-XP-PR) --- at - 20:01:56 12.08.2008 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity ALU is - port( - ch_a_i : in std_logic_vector (7 downto 0); - ch_b_i : in std_logic_vector (7 downto 0); - reg_0flag_core_i : in std_logic; - reg_3flag_core_i : in std_logic; - reg_7flag_core_i : in std_logic; - sel_alu_as_i : in std_logic; - sel_alu_out_i : in std_logic_vector (2 downto 0); - d_alu_o : out std_logic_vector (7 downto 0); - reg_0flag_o : out std_logic; - reg_1flag_o : out std_logic; - reg_6flag_o : out std_logic; - reg_7flag_o : out std_logic - ); - --- Declarations - -end ALU ; - --- Jens-D. Gutschmidt Project: R65C02_TC --- scantara2003@yahoo.de --- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- CVS Revisins History --- --- $Log: not supported by cvs2svn $ --- --- Title: ALU --- Path: R65C02_TC/ALU/struct --- Edited: by eda on 11 Aug 2008 --- --- VHDL Architecture R65C02_TC.ALU.struct --- --- Created: --- by - eda.UNKNOWN (ENTWICKL4-XP-PR) --- at - 20:01:57 12.08.2008 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -library R65C02_TC; - -architecture struct of ALU is - - -- Architecture declarations - - -- Internal signal declarations - signal decode_neg_o_i : std_logic_vector(7 downto 0); - signal decode_o_i : std_logic_vector(7 downto 0); - signal din0_o_i : std_logic; - signal din1_o_i : std_logic; - signal din2_o_i : std_logic; - signal din3_o_i : std_logic; - signal din_o_i : std_logic; - signal dout_o_i : std_logic; - signal q_a_o_i : std_logic_vector(7 downto 0); - signal q_and_o_i : std_logic_vector(7 downto 0); - signal q_or_o_i : std_logic_vector(7 downto 0); - signal q_xor_o_i : std_logic_vector(7 downto 0); - signal sel_o_i : std_logic_vector(1 downto 0); - signal val_one : std_logic_vector(7 downto 0); - signal val_two : std_logic_vector(7 downto 0); - signal val_zero : std_logic_vector(7 downto 0); - - -- Implicit buffer signal declarations - signal d_alu_o_internal : std_logic_vector (7 downto 0); - - - -- Component Declarations - component ADD_SUB - port ( - d_in : in std_logic_vector ( 7 downto 0 ) := X"00"; - reg_0F_in : in std_logic := '0'; - reg_7F_in : in std_logic := '0'; - reg_a_in : in std_logic_vector ( 7 downto 0 ) := X"00"; - sel : in std_logic_vector ( 1 downto 0 ) := "00"; - reg_0F : out std_logic := '0'; - reg_6F : out std_logic := '0'; - reg_a : out std_logic_vector ( 7 downto 0 ) := X"00"; - zw_alu : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; - zw_alu1 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; - zw_alu2 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; - zw_alu3 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; - zw_alu4 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00" - ); - end component; - - -- Optional embedded configurations - -- pragma synthesis_off - for all : ADD_SUB use entity R65C02_TC.ADD_SUB; - -- pragma synthesis_on - - -begin - -- Architecture concurrent statements - -- HDL Embedded Text Block 3 eb3 - -- eb1 1 - val_zero (7 downto 0) <= X"00"; - val_one (7 downto 0) <= X"01"; - val_two (7 downto 0) <= X"02"; - sel_o_i(0) <= reg_3flag_core_i AND sel_alu_out_i(0); - sel_o_i(1) <= sel_alu_as_i; - - - - -- ModuleWare code(v1.9) for instance 'U_15' of 'decoder1' - u_15combo_proc: process (ch_a_i(2 DOWNTO 0)) - begin - decode_o_i <= (others => '0'); - case ch_a_i(2 DOWNTO 0) is - when "000" => decode_o_i(0) <= '1'; - when "001" => decode_o_i(1) <= '1'; - when "010" => decode_o_i(2) <= '1'; - when "011" => decode_o_i(3) <= '1'; - when "100" => decode_o_i(4) <= '1'; - when "101" => decode_o_i(5) <= '1'; - when "110" => decode_o_i(6) <= '1'; - when "111" => decode_o_i(7) <= '1'; - when others => decode_o_i <= (others => '0'); - end case; - end process u_15combo_proc; - - -- ModuleWare code(v1.9) for instance 'U_4' of 'inv' - decode_neg_o_i <= not(decode_o_i); - - -- ModuleWare code(v1.9) for instance 'U_8' of 'inv' - reg_1flag_o <= not(din_o_i); - - -- ModuleWare code(v1.9) for instance 'U_9' of 'inv' - reg_7flag_o <= not(din1_o_i); - - -- ModuleWare code(v1.9) for instance 'U_10' of 'inv' - din1_o_i <= not(d_alu_o_internal(7)); - - -- ModuleWare code(v1.9) for instance 'U_14' of 'inv' - din3_o_i <= not(sel_alu_out_i(0)); - - -- ModuleWare code(v1.9) for instance 'U_5' of 'mux' - u_5combo_proc: process(q_and_o_i, q_or_o_i, q_xor_o_i, decode_o_i, - decode_neg_o_i, q_a_o_i, val_zero, - sel_alu_out_i) - begin - case sel_alu_out_i is - when "000" => d_alu_o_internal <= q_and_o_i; - when "001" => d_alu_o_internal <= q_or_o_i; - when "010" => d_alu_o_internal <= q_xor_o_i; - when "011" => d_alu_o_internal <= decode_o_i; - when "100" => d_alu_o_internal <= decode_neg_o_i; - when "101" => d_alu_o_internal <= q_a_o_i; - when "110" => d_alu_o_internal <= q_a_o_i; - when "111" => d_alu_o_internal <= val_zero; - when others => d_alu_o_internal <= (others => 'X'); - end case; - end process u_5combo_proc; - - -- ModuleWare code(v1.9) for instance 'U_7' of 'por' - din_o_i <= d_alu_o_internal(0) or d_alu_o_internal(1) or d_alu_o_internal(2) or d_alu_o_internal(3) or d_alu_o_internal(4) or d_alu_o_internal(5) or d_alu_o_internal(6) or d_alu_o_internal(7); - - -- ModuleWare code(v1.9) for instance 'U_0' of 'sand' - q_and_o_i <= ch_a_i and ch_b_i; - - -- ModuleWare code(v1.9) for instance 'U_11' of 'sand' - din0_o_i <= sel_alu_out_i(0) and reg_0flag_core_i; - - -- ModuleWare code(v1.9) for instance 'U_13' of 'sand' - din2_o_i <= din3_o_i and sel_alu_as_i; - - -- ModuleWare code(v1.9) for instance 'U_1' of 'sor' - q_or_o_i <= ch_a_i or ch_b_i; - - -- ModuleWare code(v1.9) for instance 'U_12' of 'sor' - dout_o_i <= din0_o_i or din2_o_i; - - -- ModuleWare code(v1.9) for instance 'U_2' of 'sxor' - q_xor_o_i <= ch_a_i xor ch_b_i; - - -- Instance port mappings. - U_6 : ADD_SUB - port map ( - d_in => ch_b_i, - reg_0F_in => dout_o_i, - reg_7F_in => reg_7flag_core_i, - reg_a_in => ch_a_i, - sel => sel_o_i, - reg_0F => reg_0flag_o, - reg_6F => reg_6flag_o, - reg_a => q_a_o_i, - zw_alu => open, - zw_alu1 => open, - zw_alu2 => open, - zw_alu3 => open, - zw_alu4 => open - ); - - -- Implicit buffered output assignments - d_alu_o <= d_alu_o_internal; - -end struct;
trunk/rtl/vhdl/alu.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/vhdl/fsm_core_v2_0.vhd =================================================================== --- trunk/rtl/vhdl/fsm_core_v2_0.vhd (revision 7) +++ trunk/rtl/vhdl/fsm_core_v2_0.vhd (nonexistent) @@ -1,6066 +0,0 @@ --- VHDL Entity R65C02_TC.fsm_core_V2_0.symbol --- --- Created: --- by - eda.UNKNOWN (ENTWICKL4-XP-PR) --- at - 19:53:12 05.08.2008 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity fsm_core_V2_0 is - port( - CLK : in std_logic; - D_IN : in std_logic_vector ( 7 downto 0 ); - IRQn : in std_logic; - NMI : in std_logic; - RDY : in std_logic; - RSTn : in std_logic; - S_O : in std_logic; - adr_PC : in std_logic_vector (15 downto 0); - adr_SP : in std_logic_vector (15 downto 0); - adr_nxt_PC : in std_logic_vector (15 downto 0); - adr_nxt_SP : in std_logic_vector (15 downto 0); - cout_PC : in std_logic; - d_ALU : in std_logic_vector ( 7 downto 0 ); - d_REGS : in std_logic_vector ( 7 downto 0 ); - q_a : in std_logic_vector ( 7 downto 0 ); - q_x : in std_logic_vector ( 7 downto 0 ); - q_y : in std_logic_vector ( 7 downto 0 ); - reg_0F : in std_logic; - reg_1F : in std_logic; - reg_6F : in std_logic; - reg_7F : in std_logic; - A : out std_logic_vector (15 downto 0); - D_OUT : out std_logic_vector ( 7 downto 0 ); - RD : out std_logic; - RWn : out std_logic; - SYNC : out std_logic; - WR : out std_logic; - a_ALU : out std_logic_vector ( 7 downto 0 ); - adr_out : out std_logic_vector (15 downto 0); - b_ALU : out std_logic_vector ( 7 downto 0 ); - d_REGS_out : out std_logic_vector ( 7 downto 0 ); - ld : out std_logic_vector ( 1 downto 0 ); - ld_PC : out std_logic; - ld_SP : out std_logic; - load_REGS : out std_logic; - offset : out std_logic_vector ( 15 downto 0 ); - reg_0F_out : out std_logic; - reg_1F_out : out std_logic; - reg_3F_out : out std_logic; - reg_7F_out : out std_logic; - sel_ALU_as : inout std_logic; - sel_ALU_out : inout std_logic_vector ( 2 downto 0 ); - sel_PC_as : inout std_logic; - sel_PC_in : inout std_logic_vector ( 1 downto 0 ); - sel_PC_val : inout std_logic_vector ( 1 downto 0 ); - sel_RB_in : inout std_logic_vector ( 2 downto 0 ); - sel_RB_out : inout std_logic_vector ( 2 downto 0 ); - sel_SP_as : inout std_logic; - sel_SP_in : inout std_logic_vector ( 1 downto 0 ); - sel_SP_val : inout std_logic_vector ( 1 downto 0 ); - sel_reg : inout std_logic_vector ( 1 downto 0 ) - ); - --- Declarations - -end fsm_core_V2_0 ; - --- Jens-D. Gutschmidt Project: R65C02_TC - --- scantara2003@yahoo.de - --- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG - --- - --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - --- the Free Software Foundation, either version 3 of the License, or any later version. - --- - --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - --- - --- You should have received a copy of the GNU General Public License along with this program. If not, see . - --- - --- CVS Revisins History - --- - --- $Log: not supported by cvs2svn $ - --- - --- Title: FSM for all op codes - --- Path: R65C02_TC/fsm_core_V2_0/fsm - --- Edited: by eda on 05 Aug 2008 - --- --- VHDL Architecture R65C02_TC.fsm_core_V2_0.fsm --- --- Created: --- by - eda.UNKNOWN (ENTWICKL4-XP-PR) --- at - 19:53:18 05.08.2008 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -architecture fsm of fsm_core_V2_0 is - - -- Architecture Declarations - signal reg_F : std_logic_vector( 7 DOWNTO 0 ); - signal reg_PC : std_logic_vector(15 DOWNTO 0); - signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 ); - signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); - signal sig_PC : std_logic_vector(15 DOWNTO 0); - signal sig_RD : std_logic; - signal sig_RWn : std_logic; - signal sig_SYNC : std_logic; - signal sig_WR : std_logic; - signal zw_ALU : std_logic_vector( 8 DOWNTO 0 ); - signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 ); - signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 ); - signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 ); - signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 ); - signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); - signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); - signal zw_REG_NMI : std_logic; - signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); - signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); - signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_w1 : std_logic_vector( 15 DOWNTO 0 ); - signal zw_w2 : std_logic_vector( 15 DOWNTO 0 ); - signal zw_w3 : std_logic_vector( 15 DOWNTO 0 ); - - subtype state_type is - std_logic_vector(7 downto 0); - - -- State vector declaration - attribute state_vector : string; - attribute state_vector of fsm : architecture is "current_state"; - - -- Hard encoding - constant FETCH : state_type := "00000000"; - constant s1 : state_type := "00000001"; - constant s2 : state_type := "00000011"; - constant s5 : state_type := "00000010"; - constant s3 : state_type := "00000110"; - constant s4 : state_type := "00000111"; - constant s12 : state_type := "00000101"; - constant s16 : state_type := "00000100"; - constant s17 : state_type := "00001100"; - constant s24 : state_type := "00001101"; - constant s271 : state_type := "00001111"; - constant s273 : state_type := "00001110"; - constant s304 : state_type := "00001010"; - constant s307 : state_type := "00001011"; - constant s177 : state_type := "00001001"; - constant s180 : state_type := "00001000"; - constant s181 : state_type := "00011000"; - constant s183 : state_type := "00011001"; - constant s184 : state_type := "00011011"; - constant s185 : state_type := "00011010"; - constant s186 : state_type := "00011110"; - constant s187 : state_type := "00011111"; - constant s188 : state_type := "00011101"; - constant s189 : state_type := "00011100"; - constant s190 : state_type := "00010100"; - constant s191 : state_type := "00010101"; - constant s192 : state_type := "00010111"; - constant s193 : state_type := "00010110"; - constant s377 : state_type := "00010010"; - constant s381 : state_type := "00010011"; - constant s378 : state_type := "00010001"; - constant s382 : state_type := "00010000"; - constant s379 : state_type := "00110000"; - constant s383 : state_type := "00110001"; - constant s384 : state_type := "00110011"; - constant s380 : state_type := "00110010"; - constant s385 : state_type := "00110110"; - constant s386 : state_type := "00110111"; - constant s387 : state_type := "00110101"; - constant s388 : state_type := "00110100"; - constant s389 : state_type := "00111100"; - constant s391 : state_type := "00111101"; - constant s392 : state_type := "00111111"; - constant s390 : state_type := "00111110"; - constant s393 : state_type := "00111010"; - constant s394 : state_type := "00111011"; - constant s395 : state_type := "00111001"; - constant s396 : state_type := "00111000"; - constant s397 : state_type := "00101000"; - constant s398 : state_type := "00101001"; - constant s399 : state_type := "00101011"; - constant s400 : state_type := "00101010"; - constant s401 : state_type := "00101110"; - constant s526 : state_type := "00101111"; - constant s527 : state_type := "00101101"; - constant s528 : state_type := "00101100"; - constant s529 : state_type := "00100100"; - constant s530 : state_type := "00100101"; - constant s531 : state_type := "00100111"; - constant s544 : state_type := "00100110"; - constant s545 : state_type := "00100010"; - constant s546 : state_type := "00100011"; - constant s547 : state_type := "00100001"; - constant s549 : state_type := "00100000"; - constant s550 : state_type := "01100000"; - constant s404 : state_type := "01100001"; - constant s556 : state_type := "01100011"; - constant s557 : state_type := "01100010"; - constant s579 : state_type := "01100110"; - constant s201 : state_type := "01100111"; - constant s202 : state_type := "01100101"; - constant s211 : state_type := "01100100"; - constant s215 : state_type := "01101100"; - constant s217 : state_type := "01101101"; - constant s218 : state_type := "01101111"; - constant s222 : state_type := "01101110"; - constant s223 : state_type := "01101010"; - constant s224 : state_type := "01101011"; - constant s225 : state_type := "01101001"; - constant s226 : state_type := "01101000"; - constant s243 : state_type := "01111000"; - constant s244 : state_type := "01111001"; - constant s247 : state_type := "01111011"; - constant s344 : state_type := "01111010"; - constant s343 : state_type := "01111110"; - constant s250 : state_type := "01111111"; - constant s251 : state_type := "01111101"; - constant s360 : state_type := "01111100"; - constant s403 : state_type := "01110100"; - constant s406 : state_type := "01110101"; - constant s407 : state_type := "01110111"; - constant s409 : state_type := "01110110"; - constant s412 : state_type := "01110010"; - constant s413 : state_type := "01110011"; - constant s416 : state_type := "01110001"; - constant s418 : state_type := "01110000"; - constant s510 : state_type := "01010000"; - constant s553 : state_type := "01010001"; - constant s555 : state_type := "01010011"; - constant s558 : state_type := "01010010"; - constant s560 : state_type := "01010110"; - constant s561 : state_type := "01010111"; - constant s563 : state_type := "01010101"; - constant s564 : state_type := "01010100"; - constant s565 : state_type := "01011100"; - constant s566 : state_type := "01011101"; - constant s266 : state_type := "01011111"; - constant s301 : state_type := "01011110"; - constant s302 : state_type := "01011010"; - constant RES : state_type := "01011011"; - constant s511 : state_type := "01011001"; - constant s559 : state_type := "01011000"; - constant s567 : state_type := "01001000"; - constant s568 : state_type := "01001001"; - constant s569 : state_type := "01001011"; - constant s570 : state_type := "01001010"; - constant s571 : state_type := "01001110"; - constant s572 : state_type := "01001111"; - constant s573 : state_type := "01001101"; - constant s574 : state_type := "01001100"; - constant s548 : state_type := "01000100"; - constant s551 : state_type := "01000101"; - constant s552 : state_type := "01000111"; - constant s575 : state_type := "01000110"; - constant s576 : state_type := "01000010"; - constant s577 : state_type := "01000011"; - constant s532 : state_type := "01000001"; - constant s533 : state_type := "01000000"; - constant s534 : state_type := "11000000"; - constant s535 : state_type := "11000001"; - constant s536 : state_type := "11000011"; - constant s537 : state_type := "11000010"; - constant s274 : state_type := "11000110"; - constant s305 : state_type := "11000111"; - constant s203 : state_type := "11000101"; - constant s212 : state_type := "11000100"; - constant s219 : state_type := "11001100"; - constant s227 : state_type := "11001101"; - constant s228 : state_type := "11001111"; - constant s267 : state_type := "11001110"; - constant s268 : state_type := "11001010"; - constant s269 : state_type := "11001011"; - constant s578 : state_type := "11001001"; - constant s580 : state_type := "11001000"; - constant s25 : state_type := "11011000"; - - -- Declare current and next state signals - signal current_state : state_type; - signal next_state : state_type; - - -- Declare any pre-registered internal signals - signal D_OUT_cld : std_logic_vector ( 7 downto 0 ); - signal RD_cld : std_logic ; - signal RWn_cld : std_logic ; - signal SYNC_cld : std_logic ; - signal WR_cld : std_logic ; - signal sel_ALU_as_cld : std_logic ; - signal sel_ALU_out_cld : std_logic_vector ( 2 downto 0 ); - signal sel_PC_as_cld : std_logic ; - signal sel_PC_in_cld : std_logic_vector ( 1 downto 0 ); - signal sel_PC_val_cld : std_logic_vector ( 1 downto 0 ); - signal sel_RB_in_cld : std_logic_vector ( 2 downto 0 ); - signal sel_RB_out_cld : std_logic_vector ( 2 downto 0 ); - signal sel_SP_as_cld : std_logic ; - signal sel_SP_in_cld : std_logic_vector ( 1 downto 0 ); - signal sel_SP_val_cld : std_logic_vector ( 1 downto 0 ); - signal sel_reg_cld : std_logic_vector ( 1 downto 0 ); - -begin - - ----------------------------------------------------------------- - clocked_proc : process ( - CLK, - RSTn - ) - ----------------------------------------------------------------- - begin - if (RSTn = '0') then - current_state <= RES; - -- Default Reset Values - D_OUT_cld <= X"00"; - RD_cld <= '0'; - RWn_cld <= '1'; - SYNC_cld <= '0'; - WR_cld <= '0'; - sel_ALU_as_cld <= '0'; - sel_ALU_out_cld <= "000"; - sel_PC_as_cld <= '0'; - sel_PC_in_cld <= "00"; - sel_PC_val_cld <= "00"; - sel_RB_in_cld <= "000"; - sel_RB_out_cld <= "000"; - sel_SP_as_cld <= '0'; - sel_SP_in_cld <= "00"; - sel_SP_val_cld <= "00"; - sel_reg_cld <= "00"; - reg_F <= "00000100"; - reg_PC <= X"0000"; - reg_PC1 <= X"0000"; - sig_PC <= X"0000"; - zw_PC <= X"0000"; - zw_REG_ALU <= '0' & X"00"; - zw_REG_NMI <= '0'; - zw_REG_OP <= X"00"; - zw_REG_sig_PC <= X"0000"; - zw_b1 <= X"00"; - zw_b2 <= X"00"; - zw_b3 <= X"00"; - zw_b4 <= X"00"; - zw_w1 <= X"0000"; - zw_w2 <= X"0000"; - zw_w3 <= X"0000"; - elsif (CLK'event and CLK = '1') then - current_state <= next_state; - -- Default Assignment To Internals - reg_F <= reg_F; - reg_PC <= reg_PC; - reg_PC1 <= reg_PC1; - sig_PC <= sig_PC; - zw_PC <= zw_PC; - zw_REG_ALU <= zw_REG_ALU; - zw_REG_NMI <= zw_REG_NMI or NMI; - zw_REG_OP <= zw_REG_OP; - zw_REG_sig_PC <= zw_REG_sig_PC; - zw_b1 <= zw_b1; - zw_b2 <= zw_b2; - zw_b3 <= zw_b3; - zw_b4 <= zw_b4; - zw_w1 <= zw_w1; - zw_w2 <= zw_w2; - zw_w3 <= zw_w3; - D_OUT_cld <= sig_D_OUT; - RD_cld <= sig_RD; - RWn_cld <= sig_RWn; - SYNC_cld <= sig_SYNC; - WR_cld <= sig_WR; - sel_ALU_as_cld <= sel_ALU_as; - sel_ALU_out_cld <= sel_ALU_out; - sel_PC_as_cld <= sel_PC_as; - sel_PC_in_cld <= sel_PC_in; - sel_PC_val_cld <= sel_PC_val; - sel_RB_in_cld <= sel_RB_in; - sel_RB_out_cld <= sel_RB_out; - sel_SP_as_cld <= sel_SP_as; - sel_SP_in_cld <= sel_SP_in; - sel_SP_val_cld <= sel_SP_val; - sel_reg_cld <= sel_reg; - - -- Combined Actions - case current_state is - when FETCH => - zw_REG_OP <= D_IN; - if ((zw_REG_NMI = '1') and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - zw_REG_NMI <= '0'; - elsif ((IRQn = '0' and - reg_F(2) = '0') and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"69" or - D_IN = X"65" or - D_IN = X"75" or - D_IN = X"6D" or - D_IN = X"7D" or - D_IN = X"79" or - D_IN = X"61" or - D_IN = X"71" or - D_IN = X"72") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - zw_b1(0) <= reg_F(7); - elsif ((D_IN = X"06" or - D_IN = X"16" or - D_IN = X"0E" or - D_IN = X"1E" or - D_IN (3 downto 0) = X"7" or - D_IN = X"14" or - D_IN = X"04" or - D_IN = X"0C" or - D_IN = X"1C") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"90" or - D_IN = X"B0" or - D_IN = X"F0" or - D_IN = X"30" or - D_IN = X"D0" or - D_IN = X"10" or - D_IN = X"50" or - D_IN = X"70" or - D_IN = X"80" or - D_IN (3 downto 0) = X"F") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - zw_b3 <= adr_nxt_PC (15 downto 8); - elsif ((D_IN = X"24" or - D_IN = X"2C" or - D_IN = X"3C" or - D_IN = X"34" or - D_IN = X"89") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"00") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"18") and (RDY = '1')) then - elsif ((D_IN = X"D8") and (RDY = '1')) then - elsif ((D_IN = X"58") and (RDY = '1')) then - elsif ((D_IN = X"B8") and (RDY = '1')) then - elsif ((D_IN = X"E0" or - D_IN = X"E4" or - D_IN = X"EC") and (RDY = '1')) then - sel_RB_out_cld <= "001"; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"C0" or - D_IN = X"C4" or - D_IN = X"CC") and (RDY = '1')) then - sel_RB_out_cld <= "010"; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"C6" or - D_IN = X"D6" or - D_IN = X"CE" or - D_IN = X"DE") and (RDY = '1')) then - zw_b4 <= X"FF"; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"CA") and (RDY = '1')) then - sel_RB_out_cld <= "001"; - sel_reg_cld <= "01"; - sel_RB_in_cld <= "011"; - zw_b4 <= X"FF"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"88") and (RDY = '1')) then - sel_RB_out_cld <= "010"; - sel_reg_cld <= "10"; - sel_RB_in_cld <= "011"; - zw_b4 <= X"FF"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"49" or - D_IN = X"45" or - D_IN = X"55" or - D_IN = X"4D" or - D_IN = X"5D" or - D_IN = X"59" or - D_IN = X"41" or - D_IN = X"51" or - D_IN = X"09" or - D_IN = X"05" or - D_IN = X"15" or - D_IN = X"0D" or - D_IN = X"1D" or - D_IN = X"19" or - D_IN = X"01" or - D_IN = X"11" or - D_IN = X"29" or - D_IN = X"25" or - D_IN = X"35" or - D_IN = X"2D" or - D_IN = X"3D" or - D_IN = X"39" or - D_IN = X"21" or - D_IN = X"31" or - D_IN = X"C9" or - D_IN = X"C5" or - D_IN = X"D5" or - D_IN = X"CD" or - D_IN = X"DD" or - D_IN = X"D9" or - D_IN = X"C1" or - D_IN = X"D1" or - D_IN = X"32" or - D_IN = X"D2" or - D_IN = X"52" or - D_IN = X"12") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"E6" or - D_IN = X"F6" or - D_IN = X"EE" or - D_IN = X"FE") and (RDY = '1')) then - zw_b4 <= X"01"; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"E8") and (RDY = '1')) then - sel_RB_out_cld <= "001"; - sel_reg_cld <= "01"; - sel_RB_in_cld <= "011"; - zw_b4 <= X"01"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"C8") and (RDY = '1')) then - sel_RB_out_cld <= "010"; - sel_reg_cld <= "10"; - sel_RB_in_cld <= "011"; - zw_b4 <= X"01"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"4C" or - D_IN = X"6C" or - D_IN = X"7C") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - elsif ((D_IN = X"20") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - elsif ((D_IN = X"A9" or - D_IN = X"A5" or - D_IN = X"B5" or - D_IN = X"AD" or - D_IN = X"BD" or - D_IN = X"B9" or - D_IN = X"A1" or - D_IN = X"B1" or - D_IN = X"B2") and (RDY = '1')) then - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"A2" or - D_IN = X"A6" or - D_IN = X"B6" or - D_IN = X"AE" or - D_IN = X"BE") and (RDY = '1')) then - sel_reg_cld <= "01"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"A0" or - D_IN = X"A4" or - D_IN = X"B4" or - D_IN = X"AC" or - D_IN = X"BC") and (RDY = '1')) then - sel_reg_cld <= "10"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"46" or - D_IN = X"56" or - D_IN = X"4E" or - D_IN = X"5E") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"EA") and (RDY = '1')) then - elsif ((D_IN = X"48") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sig_PC <= adr_nxt_PC; - elsif ((D_IN = X"08") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - elsif ((D_IN = X"7A") and (RDY = '1')) then - sel_reg_cld <= "10"; - sel_RB_in_cld <= "011"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"28") and (RDY = '1')) then - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"26" or - D_IN = X"36" or - D_IN = X"2E" or - D_IN = X"3E") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"66" or - D_IN = X"76" or - D_IN = X"6E" or - D_IN = X"7E") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"40") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - elsif ((D_IN = X"60") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"E9" or - D_IN = X"E5" or - D_IN = X"F5" or - D_IN = X"ED" or - D_IN = X"FD" or - D_IN = X"F9" or - D_IN = X"E1" or - D_IN = X"F1" or - D_IN = X"F2") and (RDY = '1')) then - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - zw_b1(0) <= reg_F(7); - elsif ((D_IN = X"38") and (RDY = '1')) then - elsif ((D_IN = X"F8") and (RDY = '1')) then - elsif ((D_IN = X"78") and (RDY = '1')) then - elsif ((D_IN = X"85" or - D_IN = X"95" or - D_IN = X"8D" or - D_IN = X"9D" or - D_IN = X"99" or - D_IN = X"81" or - D_IN = X"91" or - D_IN = X"11") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"86" or - D_IN = X"96" or - D_IN = X"8E") and (RDY = '1')) then - sel_RB_out_cld <= "001"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"84" or - D_IN = X"94" or - D_IN = X"8C") and (RDY = '1')) then - sel_RB_out_cld <= "010"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"AA") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "01"; - sel_RB_in_cld <= "000"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sel_SP_in_cld <= "01"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"0A") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"4A") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"2A") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"6A") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"A8") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "10"; - sel_RB_in_cld <= "000"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sel_SP_in_cld <= "01"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"98") and (RDY = '1')) then - sel_RB_out_cld <= "010"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "001"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sel_SP_in_cld <= "01"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"BA") and (RDY = '1')) then - sel_RB_out_cld <= "001"; - sel_reg_cld <= "01"; - sel_RB_in_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sel_SP_in_cld <= "01"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"8A") and (RDY = '1')) then - sel_RB_out_cld <= "001"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "010"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sel_SP_in_cld <= "01"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"9A") and (RDY = '1')) then - sel_RB_out_cld <= "001"; - sel_reg_cld <= "11"; - sel_RB_in_cld <= "111"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sel_SP_in_cld <= "01"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - elsif ((D_IN = X"DA") and (RDY = '1')) then - sel_RB_out_cld <= "001"; - sig_PC <= adr_nxt_PC; - elsif ((D_IN = X"5A") and (RDY = '1')) then - sel_RB_out_cld <= "010"; - sig_PC <= adr_nxt_PC; - elsif ((D_IN = X"68") and (RDY = '1')) then - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"FA") and (RDY = '1')) then - sel_reg_cld <= "01"; - sel_RB_in_cld <= "011"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '0'; - sel_SP_val_cld <= "00"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"9C" or - D_IN = X"9E" or - D_IN = X"64" or - D_IN = X"74") and (RDY = '1')) then - sel_RB_out_cld <= "011"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"3A") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - zw_b4 <= X"FF"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - elsif ((D_IN = X"1A") and (RDY = '1')) then - sel_RB_out_cld <= "000"; - sel_reg_cld <= "00"; - sel_RB_in_cld <= "011"; - zw_b4 <= X"01"; - sel_ALU_out_cld <= "110"; - sel_ALU_as_cld <= '0'; - end if; - when s1 => - if (RDY = '1') then - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s2 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(0) <= '1'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s5 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(3) <= '1'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s3 => - sig_PC <= adr_PC; - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(2) <= '1'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s4 => - if (RDY = '1' and - zw_REG_OP = X"9A") then - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - zw_REG_OP = X"BA") then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1') then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s12 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(0) <= '0'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s16 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(3) <= '0'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s17 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(2) <= '0'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s24 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(6) <= '0'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s271 => - if (RDY = '1' and - zw_REG_OP = X"4C") then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "11"; - zw_b1 <= D_IN; - elsif (RDY = '1' and - zw_REG_OP = X"6C") then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - zw_b1 <= D_IN; - elsif (RDY = '1' and - zw_REG_OP = X"7C") then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "10"; - zw_b1 <= D_IN; - end if; - when s273 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - end if; - when s304 => - if (RDY = '1') then - sig_PC <= adr_PC; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "11"; - zw_b1 <= D_IN; - end if; - when s307 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s177 => - if (RDY = '1' and - (zw_REG_OP = X"85" OR - zw_REG_OP = X"86" OR - zw_REG_OP = X"64" OR - zw_REG_OP = X"84")) then - sig_PC <= X"00" & D_IN; - elsif (RDY = '1' and - (zw_REG_OP = X"95" OR - zw_REG_OP = X"74" OR - zw_REG_OP = X"94")) then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - (zw_REG_OP = X"8D" OR - zw_REG_OP = X"8E" OR - zw_REG_OP = X"9C" OR - zw_REG_OP = X"8C")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= D_IN; - elsif (RDY = '1' and - (zw_REG_OP = X"9D" OR - zw_REG_OP = X"9E")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - zw_REG_OP = X"99") then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - zw_REG_OP = X"91") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_ALU; - elsif (RDY = '1' and - zw_REG_OP = X"81") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - zw_REG_OP = X"96") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - zw_REG_OP = X"92") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_ALU; - end if; - when s180 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s181 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - end if; - when s183 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - end if; - when s184 => - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - when s185 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s186 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s187 => - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - when s188 => - if (RDY = '1') then - sig_PC <= X"00" & d_ALU; - zw_b1 <= D_IN; - end if; - when s189 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s190 => - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - when s191 => - sig_PC <= zw_b3 & zw_b1; - when s192 => - sig_PC <= D_IN & zw_b1; - when s193 => - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - when s377 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s381 => - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - when s378 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s382 => - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - when s383 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s384 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s385 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s386 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F <= D_IN; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s387 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s388 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s389 => - if (RDY = '1') then - sig_PC <= adr_SP; - reg_F <= D_IN; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "11"; - end if; - when s391 => - if (RDY = '1') then - sig_PC <= adr_SP; - zw_b1 <= D_IN; - end if; - when s392 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s390 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s393 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s394 => - if (RDY = '1') then - sig_PC <= adr_SP; - zw_b1 <= D_IN; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - end if; - when s395 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - end if; - when s396 => - if (RDY = '1') then - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s397 => - if (RDY = '1') then - sig_PC <= adr_SP; - zw_b1 <= D_IN; - end if; - when s399 => - sig_PC <= adr_SP; - when s400 => - sig_PC <= adr_PC; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "11"; - when s401 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1 (7 downto 0); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s526 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s527 => - sig_PC <= adr_SP; - when s528 => - sig_PC <= adr_SP; - when s529 => - sig_PC <= X"FFFE"; - when s530 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - reg_F(4) <= '1'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s531 => - if (RDY = '1') then - sig_PC <= X"FFFF"; - zw_b1 <= D_IN; - end if; - when s544 => - sig_PC <= adr_SP; - when s545 => - sig_PC <= adr_SP; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - when s546 => - sig_PC <= adr_PC; - when s547 => - if (RDY = '1') then - sig_PC <= adr_PC; - zw_w1 (7 downto 0) <= D_IN; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "11"; - end if; - when s549 => - if (RDY = '1') then - sig_PC <= D_IN & zw_w1 (7 downto 0); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s550 => - sig_PC <= adr_SP; - sel_PC_in_cld <= "01"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - when s404 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(0) <= q_a(7); - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s556 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(0) <= q_a(0); - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s557 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(0) <= q_a(7); - reg_F(0) <= q_a(7); - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s579 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(0) <= q_a(0); - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s201 => - if (RDY = '1' and - (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR - zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR - zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR - zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then - sig_PC <= X"00" & D_IN; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - sig_PC <= adr_nxt_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - sig_PC <= adr_nxt_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - sig_PC <= adr_nxt_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - sig_PC <= adr_nxt_PC; - reg_F(7) <= zw_ALU(7); - reg_F(0) <= zw_ALU(8); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then - sig_PC <= adr_nxt_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - (zw_REG_OP = X"B5" OR - zw_REG_OP = X"B4" OR - zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR - zw_REG_OP = X"35" OR - zw_REG_OP = X"D5")) then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - (zw_REG_OP = X"AD" OR - zw_REG_OP = X"AE" OR - zw_REG_OP = X"AC" OR - zw_REG_OP = X"4D" OR - zw_REG_OP = X"0D" OR - zw_REG_OP = X"2D" OR - zw_REG_OP = X"CD" OR - zw_REG_OP = X"EC" OR - zw_REG_OP = X"CC")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= D_IN; - elsif (RDY = '1' and - (zw_REG_OP = X"BD" OR - zw_REG_OP = X"BC" OR - zw_REG_OP = X"5D" OR - zw_REG_OP = X"1D" OR - zw_REG_OP = X"3D" OR - zw_REG_OP = X"DD")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - (zw_REG_OP = X"B9" OR - zw_REG_OP = X"BE" OR - zw_REG_OP = X"59" OR - zw_REG_OP = X"19" OR - zw_REG_OP = X"39" OR - zw_REG_OP = X"D9")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - (zw_REG_OP = X"B1" OR - zw_REG_OP = X"51" OR - zw_REG_OP = X"11" OR - zw_REG_OP = X"31" OR - zw_REG_OP = X"D1")) then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_ALU; - elsif (RDY = '1' and - (zw_REG_OP = X"A1" OR - zw_REG_OP = X"41" OR - zw_REG_OP = X"01" OR - zw_REG_OP = X"21" OR - zw_REG_OP = X"C1")) then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - zw_REG_OP = X"B6") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - (zw_REG_OP = X"32" OR - zw_REG_OP = X"D2" OR - zw_REG_OP = X"52" OR - zw_REG_OP = X"B2" OR - zw_REG_OP = X"12")) then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_ALU; - end if; - when s202 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - end if; - when s211 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s215 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - end if; - when s217 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s218 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s222 => - if (RDY = '1') then - sig_PC <= X"00" & d_ALU; - zw_b1 <= D_IN; - end if; - when s223 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s224 => - if ((RDY = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - sig_PC <= adr_PC; - reg_F(7) <= zw_ALU(7); - reg_F(0) <= zw_ALU(8); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1') then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s225 => - if ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - sig_PC <= adr_PC; - reg_F(7) <= zw_ALU(7); - reg_F(0) <= zw_ALU(8); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' AND - zw_b2(0) = '0') then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1') then - sig_PC <= zw_b3 & zw_b1; - end if; - when s226 => - if (RDY = '1' and - (zw_REG_OP = X"C6" OR - zw_REG_OP = X"E6")) then - sig_PC <= X"00" & D_IN; - elsif (RDY = '1' and - (zw_REG_OP = X"D6" OR - zw_REG_OP = X"F6")) then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - (zw_REG_OP = X"CE" OR - zw_REG_OP = X"EE")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= D_IN; - elsif (RDY = '1' and - (zw_REG_OP = X"DE" OR - zw_REG_OP = X"FE")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - end if; - when s243 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - end if; - when s244 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s247 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s344 => - if (RDY = '1') then - sig_PC <= zw_b3 & zw_b1; - end if; - when s343 => - if (RDY = '1') then - zw_b1 <= d_ALU; - end if; - when s251 => - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - when s360 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - end if; - when s403 => - if (RDY = '1' and - (zw_REG_OP = X"1E" or - zw_REG_OP = X"7E" or - zw_REG_OP = X"3E" or - zw_REG_OP = X"5E")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - (zw_REG_OP = X"06" or zw_REG_OP = X"66" or - zw_REG_OP = X"26" or zw_REG_OP = X"46" or - zw_REG_OP = X"04" or zw_REG_OP = X"14")) then - sig_PC <= X"00" & D_IN; - elsif (RDY = '1' and - (zw_REG_OP = X"16" or - zw_REG_OP = X"76" or - zw_REG_OP = X"36" or - zw_REG_OP = X"56")) then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - (zw_REG_OP = X"0E" or - zw_REG_OP = X"6E" or - zw_REG_OP = X"2E" or - zw_REG_OP = X"4E"or - zw_REG_OP = X"0C" or - zw_REG_OP = X"1C")) then - sig_PC <= adr_nxt_PC; - zw_b1 <= D_IN; - elsif (RDY = '1' and - zw_REG_OP (3 downto 0) = X"7") then - sig_PC <= X"00" & D_IN; - sel_ALU_out_cld <= "011"; - sel_ALU_as_cld <= '0'; - end if; - when s406 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - end if; - when s407 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s409 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s412 => - if (RDY = '1') then - sig_PC <= zw_b3 & zw_b1; - end if; - when s416 => - if (RDY = '1' and - (zw_REG_OP = X"06" or - zw_REG_OP = X"16" or - zw_REG_OP = X"0E" or - zw_REG_OP = X"1E")) then - zw_b1 <= D_IN(6 downto 0) & '0'; - zw_b2(0) <= D_IN(7); - elsif (RDY = '1' and - (zw_REG_OP = X"46" or - zw_REG_OP = X"56" or - zw_REG_OP = X"4E" or - zw_REG_OP = X"5E")) then - zw_b1 <= '0' & D_IN(7 downto 1); - zw_b2(0) <= D_IN(0); - elsif (RDY = '1' and - (zw_REG_OP = X"26" or - zw_REG_OP = X"36" or - zw_REG_OP = X"2E" or - zw_REG_OP = X"3E")) then - zw_b1 <= D_IN(6 downto 0) & reg_F(0); - zw_b2(0) <= D_IN(7); - elsif (RDY = '1' and - (zw_REG_OP = X"66" or - zw_REG_OP = X"76" or - zw_REG_OP = X"6E" or - zw_REG_OP = X"7E")) then - zw_b1 <= reg_F(0) & D_IN(7 downto 1); - zw_b2(0) <= D_IN(0); - elsif (RDY = '1' and - zw_REG_OP (7) = '0' and - zw_REG_OP (3 downto 0) = X"7") then - elsif (RDY = '1' and - zw_REG_OP (7) = '1' and - zw_REG_OP (3 downto 0) = X"7") then - elsif (RDY = '1' and - (zw_REG_OP = X"14" or - zw_REG_OP = X"1C")) then - zw_b1 <= D_IN and q_a; - elsif (RDY = '1' and - (zw_REG_OP = X"04" or - zw_REG_OP = X"0C")) then - zw_b1 <= D_IN and q_a; - end if; - when s418 => - if (zw_REG_OP (3 downto 0) = X"7") then - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif ((zw_REG_OP = X"14" or - zw_REG_OP = X"04" or - zw_REG_OP = X"0C" or - zw_REG_OP = X"1C")) then - reg_F(1) <= reg_1F; - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - else - reg_F(0) <= zw_b2(0); - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s510 => - if (RDY = '1' and - zw_REG_OP = X"65") then - sig_PC <= X"00" & D_IN; - elsif (RDY = '1' and - zw_REG_OP = X"69" and - reg_F(3) = '0') then - sig_PC <= adr_nxt_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU(8); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - zw_REG_OP = X"75") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - zw_REG_OP = X"6D") then - sig_PC <= adr_nxt_PC; - zw_b1 <= D_IN; - elsif (RDY = '1' and - zw_REG_OP = X"7D") then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - zw_REG_OP = X"79") then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - zw_REG_OP = X"71") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_ALU; - elsif (RDY = '1' and - zw_REG_OP = X"61") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - zw_REG_OP = X"69" and - reg_F(3) = '1') then - sig_PC <= adr_nxt_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU4(4); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - zw_REG_OP = X"72") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_ALU; - end if; - when s553 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - end if; - when s555 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s558 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - end if; - when s560 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s561 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s563 => - if (RDY = '1') then - sig_PC <= X"00" & d_ALU; - zw_b1 <= D_IN; - end if; - when s564 => - if (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '0') then - sig_PC <= adr_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU(8); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '1') then - sig_PC <= adr_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU4(4); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1') then - sig_PC <= zw_b3 & zw_b1; - end if; - when s565 => - if (RDY = '1' and - reg_F(3) = '0') then - sig_PC <= adr_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU(8); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - reg_F(3) = '1') then - sig_PC <= adr_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU4(4); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s566 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s266 => - if (RDY = '1' and ( - (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or - (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or - (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or - (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and ( - zw_REG_OP = X"8F" or - zw_REG_OP = X"9F" or - zw_REG_OP = X"AF" or - zw_REG_OP = X"BF" or - zw_REG_OP = X"CF" or - zw_REG_OP = X"DF" or - zw_REG_OP = X"EF" or - zw_REG_OP = X"FF" or - zw_REG_OP = X"0F" or - zw_REG_OP = X"1F" or - zw_REG_OP = X"2F" or - zw_REG_OP = X"3F" or - zw_REG_OP = X"4F" or - zw_REG_OP = X"5F" or - zw_REG_OP = X"6F" or - zw_REG_OP = X"7F")) then - sig_PC <= adr_nxt_PC; - zw_b2 <= D_IN; - elsif (RDY = '1') then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "10"; - zw_b2 <= D_IN; - end if; - when s301 => - if (RDY = '1' and - zw_b3 = adr_nxt_PC (15 downto 8)) then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1') then - sig_PC <= zw_b3 & adr_nxt_PC (7 downto 0); - end if; - when s302 => - if (RDY = '1') then - sig_PC <= adr_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when RES => - sel_PC_in_cld <= "00"; - sel_PC_val_cld <= "00"; - sel_PC_as_cld <= '0'; - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - when s511 => - if (RDY = '1' and - zw_REG_OP = X"E5") then - sig_PC <= X"00" & D_IN; - elsif (RDY = '1' and - zw_REG_OP = X"E9" and - reg_F(3) = '0') then - sig_PC <= adr_nxt_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU(8); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - zw_REG_OP = X"F5") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - zw_REG_OP = X"ED") then - sig_PC <= adr_nxt_PC; - zw_b1 <= D_IN; - elsif (RDY = '1' and - zw_REG_OP = X"FD") then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - zw_REG_OP = X"F9") then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - zw_REG_OP = X"F1") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_ALU; - elsif (RDY = '1' and - zw_REG_OP = X"E1") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - zw_REG_OP = X"E9" and - reg_F(3) = '1') then - sig_PC <= adr_nxt_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU2(4); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - zw_REG_OP = X"F2") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_ALU; - end if; - when s559 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - end if; - when s567 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s568 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - end if; - when s569 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s570 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s571 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s572 => - if (RDY = '1') then - sig_PC <= X"00" & d_ALU; - zw_b1 <= D_IN; - end if; - when s573 => - if (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '0') then - sig_PC <= adr_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU(8); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '1') then - sig_PC <= adr_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU2(4); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1') then - sig_PC <= zw_b3 & zw_b1; - end if; - when s574 => - if (RDY = '1' and - reg_F(3) = '0') then - sig_PC <= adr_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU(8); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1' and - reg_F(3) = '1') then - sig_PC <= adr_PC; - - reg_F(7) <= zw_ALU(7); - reg_F(6) <= zw_b1(0) XOR zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU2(4); - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s548 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s551 => - sig_PC <= adr_SP; - when s552 => - sig_PC <= adr_SP; - when s575 => - if (RDY = '1') then - sig_PC <= X"FFFF"; - zw_b1 <= D_IN; - end if; - when s576 => - sig_PC <= X"FFFE"; - when s577 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - reg_F(2) <= '1'; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s532 => - if (RDY = '1') then - sig_PC <= adr_SP; - end if; - when s533 => - sig_PC <= adr_SP; - when s534 => - sig_PC <= adr_SP; - when s535 => - if (RDY = '1') then - sig_PC <= X"FFFB"; - zw_b1 <= D_IN; - end if; - when s536 => - sig_PC <= X"FFFA"; - when s537 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s274 => - if (RDY = '1') then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - end if; - when s203 => - if (RDY = '1' and - zw_REG_OP = X"34") then - sig_PC <= X"00" & D_IN; - zw_b1 <= d_alu; - elsif (RDY = '1' and - zw_REG_OP = X"3C") then - sig_PC <= adr_nxt_PC; - zw_b1 <= d_ALU; - zw_b2(0) <= reg_0F; - elsif (RDY = '1' and - zw_REG_OP = X"24") then - sig_PC <= X"00" & D_IN; - elsif (RDY = '1' and - zw_REG_OP = X"2C") then - sig_PC <= adr_nxt_PC; - zw_b1 <= D_IN; - elsif (RDY = '1' and - zw_REG_OP = X"89") then - sig_PC <= adr_PC; - reg_F(7) <= D_IN(7); - reg_F(6) <= D_IN(6); - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s212 => - if (RDY = '1') then - sig_PC <= D_IN & zw_b1; - zw_b3 <= d_ALU; - end if; - when s219 => - if (RDY = '1') then - sig_PC <= X"00" & zw_b1; - end if; - when s227 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(7) <= D_IN(7); - reg_F(6) <= D_IN(6); - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s228 => - if (RDY = '1' AND - zw_b2(0) = '0') then - sig_PC <= adr_PC; - reg_F(7) <= D_IN(7); - reg_F(6) <= D_IN(6); - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - elsif (RDY = '1') then - sig_PC <= zw_b3 & zw_b1; - end if; - when s268 => - if (RDY = '1' and ( - (zw_b2(0) = '1' and zw_REG_OP = X"8F") or - (zw_b2(1) = '1' and zw_REG_OP = X"9F") or - (zw_b2(2) = '1' and zw_REG_OP = X"AF") or - (zw_b2(3) = '1' and zw_REG_OP = X"BF") or - (zw_b2(4) = '1' and zw_REG_OP = X"CF") or - (zw_b2(5) = '1' and zw_REG_OP = X"DF") or - (zw_b2(6) = '1' and zw_REG_OP = X"EF") or - (zw_b2(7) = '1' and zw_REG_OP = X"FF") or - (zw_b2(0) = '0' and zw_REG_OP = X"0F") or - (zw_b2(1) = '0' and zw_REG_OP = X"1F") or - (zw_b2(2) = '0' and zw_REG_OP = X"2F") or - (zw_b2(3) = '0' and zw_REG_OP = X"3F") or - (zw_b2(4) = '0' and zw_REG_OP = X"4F") or - (zw_b2(5) = '0' and zw_REG_OP = X"5F") or - (zw_b2(6) = '0' and zw_REG_OP = X"6F") or - (zw_b2(7) = '0' and zw_REG_OP = X"7F"))) then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "10"; - zw_b2 <= D_IN; - elsif (RDY = '1') then - sig_PC <= adr_nxt_PC; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when s25 => - if (RDY = '1') then - sig_PC <= adr_PC; - reg_F(7) <= reg_7F; - reg_F(1) <= reg_1F; - sel_PC_in_cld <= "00"; - sel_PC_as_cld <= '0'; - sel_PC_val_cld <= "00"; - sel_SP_in_cld <= "00"; - sel_SP_as_cld <= '1'; - sel_SP_val_cld <= "00"; - end if; - when others => - null; - end case; - end if; - end process clocked_proc; - - ----------------------------------------------------------------- - nextstate_proc : process ( - D_IN, - IRQn, - RDY, - adr_nxt_PC, - current_state, - reg_F, - zw_REG_NMI, - zw_REG_OP, - zw_b2, - zw_b3 - ) - ----------------------------------------------------------------- - begin - case current_state is - when FETCH => - if ((zw_REG_NMI = '1') and (RDY = '1')) then - next_state <= s532; - elsif ((IRQn = '0' and - reg_F(2) = '0') and (RDY = '1')) then - next_state <= s548; - elsif ((D_IN = X"69" or - D_IN = X"65" or - D_IN = X"75" or - D_IN = X"6D" or - D_IN = X"7D" or - D_IN = X"79" or - D_IN = X"61" or - D_IN = X"71" or - D_IN = X"72") and (RDY = '1')) then - next_state <= s510; - elsif ((D_IN = X"06" or - D_IN = X"16" or - D_IN = X"0E" or - D_IN = X"1E" or - D_IN (3 downto 0) = X"7" or - D_IN = X"14" or - D_IN = X"04" or - D_IN = X"0C" or - D_IN = X"1C") and (RDY = '1')) then - next_state <= s403; - elsif ((D_IN = X"90" or - D_IN = X"B0" or - D_IN = X"F0" or - D_IN = X"30" or - D_IN = X"D0" or - D_IN = X"10" or - D_IN = X"50" or - D_IN = X"70" or - D_IN = X"80" or - D_IN (3 downto 0) = X"F") and (RDY = '1')) then - next_state <= s266; - elsif ((D_IN = X"24" or - D_IN = X"2C" or - D_IN = X"3C" or - D_IN = X"34" or - D_IN = X"89") and (RDY = '1')) then - next_state <= s203; - elsif ((D_IN = X"00") and (RDY = '1')) then - next_state <= s526; - elsif ((D_IN = X"18") and (RDY = '1')) then - next_state <= s12; - elsif ((D_IN = X"D8") and (RDY = '1')) then - next_state <= s16; - elsif ((D_IN = X"58") and (RDY = '1')) then - next_state <= s17; - elsif ((D_IN = X"B8") and (RDY = '1')) then - next_state <= s24; - elsif ((D_IN = X"E0" or - D_IN = X"E4" or - D_IN = X"EC") and (RDY = '1')) then - next_state <= s201; - elsif ((D_IN = X"C0" or - D_IN = X"C4" or - D_IN = X"CC") and (RDY = '1')) then - next_state <= s201; - elsif ((D_IN = X"C6" or - D_IN = X"D6" or - D_IN = X"CE" or - D_IN = X"DE") and (RDY = '1')) then - next_state <= s226; - elsif ((D_IN = X"CA") and (RDY = '1')) then - next_state <= s25; - elsif ((D_IN = X"88") and (RDY = '1')) then - next_state <= s25; - elsif ((D_IN = X"49" or - D_IN = X"45" or - D_IN = X"55" or - D_IN = X"4D" or - D_IN = X"5D" or - D_IN = X"59" or - D_IN = X"41" or - D_IN = X"51" or - D_IN = X"09" or - D_IN = X"05" or - D_IN = X"15" or - D_IN = X"0D" or - D_IN = X"1D" or - D_IN = X"19" or - D_IN = X"01" or - D_IN = X"11" or - D_IN = X"29" or - D_IN = X"25" or - D_IN = X"35" or - D_IN = X"2D" or - D_IN = X"3D" or - D_IN = X"39" or - D_IN = X"21" or - D_IN = X"31" or - D_IN = X"C9" or - D_IN = X"C5" or - D_IN = X"D5" or - D_IN = X"CD" or - D_IN = X"DD" or - D_IN = X"D9" or - D_IN = X"C1" or - D_IN = X"D1" or - D_IN = X"32" or - D_IN = X"D2" or - D_IN = X"52" or - D_IN = X"12") and (RDY = '1')) then - next_state <= s201; - elsif ((D_IN = X"E6" or - D_IN = X"F6" or - D_IN = X"EE" or - D_IN = X"FE") and (RDY = '1')) then - next_state <= s226; - elsif ((D_IN = X"E8") and (RDY = '1')) then - next_state <= s25; - elsif ((D_IN = X"C8") and (RDY = '1')) then - next_state <= s25; - elsif ((D_IN = X"4C" or - D_IN = X"6C" or - D_IN = X"7C") and (RDY = '1')) then - next_state <= s271; - elsif ((D_IN = X"20") and (RDY = '1')) then - next_state <= s397; - elsif ((D_IN = X"A9" or - D_IN = X"A5" or - D_IN = X"B5" or - D_IN = X"AD" or - D_IN = X"BD" or - D_IN = X"B9" or - D_IN = X"A1" or - D_IN = X"B1" or - D_IN = X"B2") and (RDY = '1')) then - next_state <= s201; - elsif ((D_IN = X"A2" or - D_IN = X"A6" or - D_IN = X"B6" or - D_IN = X"AE" or - D_IN = X"BE") and (RDY = '1')) then - next_state <= s201; - elsif ((D_IN = X"A0" or - D_IN = X"A4" or - D_IN = X"B4" or - D_IN = X"AC" or - D_IN = X"BC") and (RDY = '1')) then - next_state <= s201; - elsif ((D_IN = X"46" or - D_IN = X"56" or - D_IN = X"4E" or - D_IN = X"5E") and (RDY = '1')) then - next_state <= s403; - elsif ((D_IN = X"EA") and (RDY = '1')) then - next_state <= s1; - elsif ((D_IN = X"48") and (RDY = '1')) then - next_state <= s377; - elsif ((D_IN = X"08") and (RDY = '1')) then - next_state <= s378; - elsif ((D_IN = X"7A") and (RDY = '1')) then - next_state <= s379; - elsif ((D_IN = X"28") and (RDY = '1')) then - next_state <= s380; - elsif ((D_IN = X"26" or - D_IN = X"36" or - D_IN = X"2E" or - D_IN = X"3E") and (RDY = '1')) then - next_state <= s403; - elsif ((D_IN = X"66" or - D_IN = X"76" or - D_IN = X"6E" or - D_IN = X"7E") and (RDY = '1')) then - next_state <= s403; - elsif ((D_IN = X"40") and (RDY = '1')) then - next_state <= s387; - elsif ((D_IN = X"60") and (RDY = '1')) then - next_state <= s390; - elsif ((D_IN = X"E9" or - D_IN = X"E5" or - D_IN = X"F5" or - D_IN = X"ED" or - D_IN = X"FD" or - D_IN = X"F9" or - D_IN = X"E1" or - D_IN = X"F1" or - D_IN = X"F2") and (RDY = '1')) then - next_state <= s511; - elsif ((D_IN = X"38") and (RDY = '1')) then - next_state <= s2; - elsif ((D_IN = X"F8") and (RDY = '1')) then - next_state <= s5; - elsif ((D_IN = X"78") and (RDY = '1')) then - next_state <= s3; - elsif ((D_IN = X"85" or - D_IN = X"95" or - D_IN = X"8D" or - D_IN = X"9D" or - D_IN = X"99" or - D_IN = X"81" or - D_IN = X"91" or - D_IN = X"11") and (RDY = '1')) then - next_state <= s177; - elsif ((D_IN = X"86" or - D_IN = X"96" or - D_IN = X"8E") and (RDY = '1')) then - next_state <= s177; - elsif ((D_IN = X"84" or - D_IN = X"94" or - D_IN = X"8C") and (RDY = '1')) then - next_state <= s177; - elsif ((D_IN = X"AA") and (RDY = '1')) then - next_state <= s4; - elsif ((D_IN = X"0A") and (RDY = '1')) then - next_state <= s404; - elsif ((D_IN = X"4A") and (RDY = '1')) then - next_state <= s556; - elsif ((D_IN = X"2A") and (RDY = '1')) then - next_state <= s557; - elsif ((D_IN = X"6A") and (RDY = '1')) then - next_state <= s579; - elsif ((D_IN = X"A8") and (RDY = '1')) then - next_state <= s4; - elsif ((D_IN = X"98") and (RDY = '1')) then - next_state <= s4; - elsif ((D_IN = X"BA") and (RDY = '1')) then - next_state <= s4; - elsif ((D_IN = X"8A") and (RDY = '1')) then - next_state <= s4; - elsif ((D_IN = X"9A") and (RDY = '1')) then - next_state <= s4; - elsif ((D_IN = X"DA") and (RDY = '1')) then - next_state <= s377; - elsif ((D_IN = X"5A") and (RDY = '1')) then - next_state <= s377; - elsif ((D_IN = X"68") and (RDY = '1')) then - next_state <= s379; - elsif ((D_IN = X"FA") and (RDY = '1')) then - next_state <= s379; - elsif ((D_IN = X"9C" or - D_IN = X"9E" or - D_IN = X"64" or - D_IN = X"74") and (RDY = '1')) then - next_state <= s177; - elsif ((D_IN = X"3A") and (RDY = '1')) then - next_state <= s25; - elsif ((D_IN = X"1A") and (RDY = '1')) then - next_state <= s25; - elsif (RDY = '1') then - next_state <= s1; - else - next_state <= FETCH; - end if; - when s1 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s1; - end if; - when s2 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s2; - end if; - when s5 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s5; - end if; - when s3 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s3; - end if; - when s4 => - if (RDY = '1' and - zw_REG_OP = X"9A") then - next_state <= FETCH; - elsif (RDY = '1' and - zw_REG_OP = X"BA") then - next_state <= FETCH; - elsif (RDY = '1') then - next_state <= FETCH; - else - next_state <= s4; - end if; - when s12 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s12; - end if; - when s16 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s16; - end if; - when s17 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s17; - end if; - when s24 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s24; - end if; - when s271 => - if (RDY = '1' and - zw_REG_OP = X"4C") then - next_state <= s307; - elsif (RDY = '1' and - zw_REG_OP = X"6C") then - next_state <= s273; - elsif (RDY = '1' and - zw_REG_OP = X"7C") then - next_state <= s274; - else - next_state <= s271; - end if; - when s273 => - if (RDY = '1') then - next_state <= s305; - else - next_state <= s273; - end if; - when s304 => - if (RDY = '1') then - next_state <= s307; - else - next_state <= s304; - end if; - when s307 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s307; - end if; - when s177 => - if (RDY = '1' and - (zw_REG_OP = X"85" OR - zw_REG_OP = X"86" OR - zw_REG_OP = X"64" OR - zw_REG_OP = X"84")) then - next_state <= s184; - elsif (RDY = '1' and - (zw_REG_OP = X"95" OR - zw_REG_OP = X"74" OR - zw_REG_OP = X"94")) then - next_state <= s185; - elsif (RDY = '1' and - (zw_REG_OP = X"8D" OR - zw_REG_OP = X"8E" OR - zw_REG_OP = X"9C" OR - zw_REG_OP = X"8C")) then - next_state <= s183; - elsif (RDY = '1' and - (zw_REG_OP = X"9D" OR - zw_REG_OP = X"9E")) then - next_state <= s180; - elsif (RDY = '1' and - zw_REG_OP = X"99") then - next_state <= s180; - elsif (RDY = '1' and - zw_REG_OP = X"91") then - next_state <= s181; - elsif (RDY = '1' and - zw_REG_OP = X"81") then - next_state <= s186; - elsif (RDY = '1' and - zw_REG_OP = X"96") then - next_state <= s185; - elsif (RDY = '1' and - zw_REG_OP = X"92") then - next_state <= s180; - else - next_state <= s177; - end if; - when s180 => - if (RDY = '1') then - next_state <= s191; - else - next_state <= s180; - end if; - when s181 => - if (RDY = '1') then - next_state <= s189; - else - next_state <= s181; - end if; - when s183 => - if (RDY = '1') then - next_state <= s187; - else - next_state <= s183; - end if; - when s184 => - next_state <= FETCH; - when s185 => - if (RDY = '1') then - next_state <= s190; - else - next_state <= s185; - end if; - when s186 => - if (RDY = '1') then - next_state <= s188; - else - next_state <= s186; - end if; - when s187 => - next_state <= FETCH; - when s188 => - if (RDY = '1') then - next_state <= s192; - else - next_state <= s188; - end if; - when s189 => - if (RDY = '1') then - next_state <= s191; - else - next_state <= s189; - end if; - when s190 => - next_state <= FETCH; - when s191 => - next_state <= s193; - when s192 => - next_state <= s193; - when s193 => - next_state <= FETCH; - when s377 => - if (RDY = '1') then - next_state <= s381; - else - next_state <= s377; - end if; - when s381 => - next_state <= FETCH; - when s378 => - if (RDY = '1') then - next_state <= s382; - else - next_state <= s378; - end if; - when s382 => - next_state <= FETCH; - when s379 => - if (RDY = '1') then - next_state <= s383; - else - next_state <= s379; - end if; - when s383 => - if (RDY = '1') then - next_state <= s384; - else - next_state <= s383; - end if; - when s384 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s384; - end if; - when s380 => - if (RDY = '1') then - next_state <= s385; - else - next_state <= s380; - end if; - when s385 => - if (RDY = '1') then - next_state <= s386; - else - next_state <= s385; - end if; - when s386 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s386; - end if; - when s387 => - if (RDY = '1') then - next_state <= s388; - else - next_state <= s387; - end if; - when s388 => - if (RDY = '1') then - next_state <= s389; - else - next_state <= s388; - end if; - when s389 => - if (RDY = '1') then - next_state <= s391; - else - next_state <= s389; - end if; - when s391 => - if (RDY = '1') then - next_state <= s392; - else - next_state <= s391; - end if; - when s392 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s392; - end if; - when s390 => - if (RDY = '1') then - next_state <= s393; - else - next_state <= s390; - end if; - when s393 => - if (RDY = '1') then - next_state <= s394; - else - next_state <= s393; - end if; - when s394 => - if (RDY = '1') then - next_state <= s395; - else - next_state <= s394; - end if; - when s395 => - if (RDY = '1') then - next_state <= s396; - else - next_state <= s395; - end if; - when s396 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s396; - end if; - when s397 => - if (RDY = '1') then - next_state <= s398; - else - next_state <= s397; - end if; - when s398 => - if (RDY = '1') then - next_state <= s399; - else - next_state <= s398; - end if; - when s399 => - next_state <= s400; - when s400 => - next_state <= s401; - when s401 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s401; - end if; - when s526 => - if (RDY = '1') then - next_state <= s527; - else - next_state <= s526; - end if; - when s527 => - next_state <= s528; - when s528 => - next_state <= s529; - when s529 => - next_state <= s531; - when s530 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s530; - end if; - when s531 => - if (RDY = '1') then - next_state <= s530; - else - next_state <= s531; - end if; - when s544 => - next_state <= s550; - when s545 => - next_state <= s546; - when s546 => - next_state <= s547; - when s547 => - if (RDY = '1') then - next_state <= s549; - else - next_state <= s547; - end if; - when s549 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s549; - end if; - when s550 => - next_state <= s545; - when s404 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s404; - end if; - when s556 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s556; - end if; - when s557 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s557; - end if; - when s579 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s579; - end if; - when s201 => - if (RDY = '1' and - (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR - zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR - zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR - zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then - next_state <= s224; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - next_state <= FETCH; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - next_state <= FETCH; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - next_state <= FETCH; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - next_state <= FETCH; - elsif (RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then - next_state <= FETCH; - elsif (RDY = '1' and - (zw_REG_OP = X"B5" OR - zw_REG_OP = X"B4" OR - zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR - zw_REG_OP = X"35" OR - zw_REG_OP = X"D5")) then - next_state <= s217; - elsif (RDY = '1' and - (zw_REG_OP = X"AD" OR - zw_REG_OP = X"AE" OR - zw_REG_OP = X"AC" OR - zw_REG_OP = X"4D" OR - zw_REG_OP = X"0D" OR - zw_REG_OP = X"2D" OR - zw_REG_OP = X"CD" OR - zw_REG_OP = X"EC" OR - zw_REG_OP = X"CC")) then - next_state <= s202; - elsif (RDY = '1' and - (zw_REG_OP = X"BD" OR - zw_REG_OP = X"BC" OR - zw_REG_OP = X"5D" OR - zw_REG_OP = X"1D" OR - zw_REG_OP = X"3D" OR - zw_REG_OP = X"DD")) then - next_state <= s211; - elsif (RDY = '1' and - (zw_REG_OP = X"B9" OR - zw_REG_OP = X"BE" OR - zw_REG_OP = X"59" OR - zw_REG_OP = X"19" OR - zw_REG_OP = X"39" OR - zw_REG_OP = X"D9")) then - next_state <= s211; - elsif (RDY = '1' and - (zw_REG_OP = X"B1" OR - zw_REG_OP = X"51" OR - zw_REG_OP = X"11" OR - zw_REG_OP = X"31" OR - zw_REG_OP = X"D1")) then - next_state <= s215; - elsif (RDY = '1' and - (zw_REG_OP = X"A1" OR - zw_REG_OP = X"41" OR - zw_REG_OP = X"01" OR - zw_REG_OP = X"21" OR - zw_REG_OP = X"C1")) then - next_state <= s218; - elsif (RDY = '1' and - zw_REG_OP = X"B6") then - next_state <= s217; - elsif (RDY = '1' and - (zw_REG_OP = X"32" OR - zw_REG_OP = X"D2" OR - zw_REG_OP = X"52" OR - zw_REG_OP = X"B2" OR - zw_REG_OP = X"12")) then - next_state <= s211; - else - next_state <= s201; - end if; - when s202 => - if (RDY = '1') then - next_state <= s224; - else - next_state <= s202; - end if; - when s211 => - if (RDY = '1') then - next_state <= s225; - else - next_state <= s211; - end if; - when s215 => - if (RDY = '1') then - next_state <= s223; - else - next_state <= s215; - end if; - when s217 => - if (RDY = '1') then - next_state <= s224; - else - next_state <= s217; - end if; - when s218 => - if (RDY = '1') then - next_state <= s222; - else - next_state <= s218; - end if; - when s222 => - if (RDY = '1') then - next_state <= s202; - else - next_state <= s222; - end if; - when s223 => - if (RDY = '1') then - next_state <= s225; - else - next_state <= s223; - end if; - when s224 => - if ((RDY = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - next_state <= FETCH; - elsif ((RDY = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - next_state <= FETCH; - elsif ((RDY = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - next_state <= FETCH; - elsif ((RDY = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - next_state <= FETCH; - elsif (RDY = '1') then - next_state <= FETCH; - else - next_state <= s224; - end if; - when s225 => - if ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - next_state <= FETCH; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - next_state <= FETCH; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - next_state <= FETCH; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - next_state <= FETCH; - elsif (RDY = '1' AND - zw_b2(0) = '0') then - next_state <= FETCH; - elsif (RDY = '1') then - next_state <= s224; - else - next_state <= s225; - end if; - when s226 => - if (RDY = '1' and - (zw_REG_OP = X"C6" OR - zw_REG_OP = X"E6")) then - next_state <= s343; - elsif (RDY = '1' and - (zw_REG_OP = X"D6" OR - zw_REG_OP = X"F6")) then - next_state <= s247; - elsif (RDY = '1' and - (zw_REG_OP = X"CE" OR - zw_REG_OP = X"EE")) then - next_state <= s243; - elsif (RDY = '1' and - (zw_REG_OP = X"DE" OR - zw_REG_OP = X"FE")) then - next_state <= s244; - else - next_state <= s226; - end if; - when s243 => - if (RDY = '1') then - next_state <= s343; - else - next_state <= s243; - end if; - when s244 => - if (RDY = '1') then - next_state <= s344; - else - next_state <= s244; - end if; - when s247 => - if (RDY = '1') then - next_state <= s343; - else - next_state <= s247; - end if; - when s344 => - if (RDY = '1') then - next_state <= s343; - else - next_state <= s344; - end if; - when s343 => - if (RDY = '1') then - next_state <= s250; - else - next_state <= s343; - end if; - when s250 => - if (RDY = '1') then - next_state <= s251; - else - next_state <= s250; - end if; - when s251 => - next_state <= FETCH; - when s360 => - if (RDY = '1') then - next_state <= s227; - else - next_state <= s360; - end if; - when s403 => - if (RDY = '1' and - (zw_REG_OP = X"1E" or - zw_REG_OP = X"7E" or - zw_REG_OP = X"3E" or - zw_REG_OP = X"5E")) then - next_state <= s407; - elsif (RDY = '1' and - (zw_REG_OP = X"06" or zw_REG_OP = X"66" or - zw_REG_OP = X"26" or zw_REG_OP = X"46" or - zw_REG_OP = X"04" or zw_REG_OP = X"14")) then - next_state <= s413; - elsif (RDY = '1' and - (zw_REG_OP = X"16" or - zw_REG_OP = X"76" or - zw_REG_OP = X"36" or - zw_REG_OP = X"56")) then - next_state <= s409; - elsif (RDY = '1' and - (zw_REG_OP = X"0E" or - zw_REG_OP = X"6E" or - zw_REG_OP = X"2E" or - zw_REG_OP = X"4E"or - zw_REG_OP = X"0C" or - zw_REG_OP = X"1C")) then - next_state <= s406; - elsif (RDY = '1' and - zw_REG_OP (3 downto 0) = X"7") then - next_state <= s413; - else - next_state <= s403; - end if; - when s406 => - if (RDY = '1') then - next_state <= s413; - else - next_state <= s406; - end if; - when s407 => - if (RDY = '1') then - next_state <= s412; - else - next_state <= s407; - end if; - when s409 => - if (RDY = '1') then - next_state <= s413; - else - next_state <= s409; - end if; - when s412 => - if (RDY = '1') then - next_state <= s413; - else - next_state <= s412; - end if; - when s413 => - if (RDY = '1') then - next_state <= s416; - else - next_state <= s413; - end if; - when s416 => - if (RDY = '1' and - (zw_REG_OP = X"06" or - zw_REG_OP = X"16" or - zw_REG_OP = X"0E" or - zw_REG_OP = X"1E")) then - next_state <= s418; - elsif (RDY = '1' and - (zw_REG_OP = X"46" or - zw_REG_OP = X"56" or - zw_REG_OP = X"4E" or - zw_REG_OP = X"5E")) then - next_state <= s418; - elsif (RDY = '1' and - (zw_REG_OP = X"26" or - zw_REG_OP = X"36" or - zw_REG_OP = X"2E" or - zw_REG_OP = X"3E")) then - next_state <= s418; - elsif (RDY = '1' and - (zw_REG_OP = X"66" or - zw_REG_OP = X"76" or - zw_REG_OP = X"6E" or - zw_REG_OP = X"7E")) then - next_state <= s418; - elsif (RDY = '1' and - zw_REG_OP (7) = '0' and - zw_REG_OP (3 downto 0) = X"7") then - next_state <= s418; - elsif (RDY = '1' and - zw_REG_OP (7) = '1' and - zw_REG_OP (3 downto 0) = X"7") then - next_state <= s418; - elsif (RDY = '1' and - (zw_REG_OP = X"14" or - zw_REG_OP = X"1C")) then - next_state <= s418; - elsif (RDY = '1' and - (zw_REG_OP = X"04" or - zw_REG_OP = X"0C")) then - next_state <= s418; - else - next_state <= s416; - end if; - when s418 => - if (zw_REG_OP (3 downto 0) = X"7") then - next_state <= FETCH; - elsif ((zw_REG_OP = X"14" or - zw_REG_OP = X"04" or - zw_REG_OP = X"0C" or - zw_REG_OP = X"1C")) then - next_state <= FETCH; - else - next_state <= FETCH; - end if; - when s510 => - if (RDY = '1' and - zw_REG_OP = X"65") then - next_state <= s565; - elsif (RDY = '1' and - zw_REG_OP = X"69" and - reg_F(3) = '0') then - next_state <= FETCH; - elsif (RDY = '1' and - zw_REG_OP = X"75") then - next_state <= s560; - elsif (RDY = '1' and - zw_REG_OP = X"6D") then - next_state <= s553; - elsif (RDY = '1' and - zw_REG_OP = X"7D") then - next_state <= s555; - elsif (RDY = '1' and - zw_REG_OP = X"79") then - next_state <= s555; - elsif (RDY = '1' and - zw_REG_OP = X"71") then - next_state <= s558; - elsif (RDY = '1' and - zw_REG_OP = X"61") then - next_state <= s561; - elsif (RDY = '1' and - zw_REG_OP = X"69" and - reg_F(3) = '1') then - next_state <= FETCH; - elsif (RDY = '1' and - zw_REG_OP = X"72") then - next_state <= s580; - else - next_state <= s510; - end if; - when s553 => - if (RDY = '1') then - next_state <= s565; - else - next_state <= s553; - end if; - when s555 => - if (RDY = '1') then - next_state <= s564; - else - next_state <= s555; - end if; - when s558 => - if (RDY = '1') then - next_state <= s566; - else - next_state <= s558; - end if; - when s560 => - if (RDY = '1') then - next_state <= s565; - else - next_state <= s560; - end if; - when s561 => - if (RDY = '1') then - next_state <= s563; - else - next_state <= s561; - end if; - when s563 => - if (RDY = '1') then - next_state <= s553; - else - next_state <= s563; - end if; - when s564 => - if (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '0') then - next_state <= FETCH; - elsif (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '1') then - next_state <= FETCH; - elsif (RDY = '1') then - next_state <= s565; - else - next_state <= s564; - end if; - when s565 => - if (RDY = '1' and - reg_F(3) = '0') then - next_state <= FETCH; - elsif (RDY = '1' and - reg_F(3) = '1') then - next_state <= FETCH; - else - next_state <= s565; - end if; - when s566 => - if (RDY = '1') then - next_state <= s564; - else - next_state <= s566; - end if; - when s266 => - if (RDY = '1' and ( - (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or - (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or - (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or - (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then - next_state <= FETCH; - elsif (RDY = '1' and ( - zw_REG_OP = X"8F" or - zw_REG_OP = X"9F" or - zw_REG_OP = X"AF" or - zw_REG_OP = X"BF" or - zw_REG_OP = X"CF" or - zw_REG_OP = X"DF" or - zw_REG_OP = X"EF" or - zw_REG_OP = X"FF" or - zw_REG_OP = X"0F" or - zw_REG_OP = X"1F" or - zw_REG_OP = X"2F" or - zw_REG_OP = X"3F" or - zw_REG_OP = X"4F" or - zw_REG_OP = X"5F" or - zw_REG_OP = X"6F" or - zw_REG_OP = X"7F")) then - next_state <= s267; - elsif (RDY = '1') then - next_state <= s301; - else - next_state <= s266; - end if; - when s301 => - if (RDY = '1' and - zw_b3 = adr_nxt_PC (15 downto 8)) then - next_state <= FETCH; - elsif (RDY = '1') then - next_state <= s302; - else - next_state <= s301; - end if; - when s302 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s302; - end if; - when RES => - next_state <= s544; - when s511 => - if (RDY = '1' and - zw_REG_OP = X"E5") then - next_state <= s574; - elsif (RDY = '1' and - zw_REG_OP = X"E9" and - reg_F(3) = '0') then - next_state <= FETCH; - elsif (RDY = '1' and - zw_REG_OP = X"F5") then - next_state <= s569; - elsif (RDY = '1' and - zw_REG_OP = X"ED") then - next_state <= s559; - elsif (RDY = '1' and - zw_REG_OP = X"FD") then - next_state <= s567; - elsif (RDY = '1' and - zw_REG_OP = X"F9") then - next_state <= s567; - elsif (RDY = '1' and - zw_REG_OP = X"F1") then - next_state <= s568; - elsif (RDY = '1' and - zw_REG_OP = X"E1") then - next_state <= s570; - elsif (RDY = '1' and - zw_REG_OP = X"E9" and - reg_F(3) = '1') then - next_state <= FETCH; - elsif (RDY = '1' and - zw_REG_OP = X"F2") then - next_state <= s578; - else - next_state <= s511; - end if; - when s559 => - if (RDY = '1') then - next_state <= s574; - else - next_state <= s559; - end if; - when s567 => - if (RDY = '1') then - next_state <= s573; - else - next_state <= s567; - end if; - when s568 => - if (RDY = '1') then - next_state <= s571; - else - next_state <= s568; - end if; - when s569 => - if (RDY = '1') then - next_state <= s574; - else - next_state <= s569; - end if; - when s570 => - if (RDY = '1') then - next_state <= s572; - else - next_state <= s570; - end if; - when s571 => - if (RDY = '1') then - next_state <= s573; - else - next_state <= s571; - end if; - when s572 => - if (RDY = '1') then - next_state <= s559; - else - next_state <= s572; - end if; - when s573 => - if (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '0') then - next_state <= FETCH; - elsif (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '1') then - next_state <= FETCH; - elsif (RDY = '1') then - next_state <= s574; - else - next_state <= s573; - end if; - when s574 => - if (RDY = '1' and - reg_F(3) = '0') then - next_state <= FETCH; - elsif (RDY = '1' and - reg_F(3) = '1') then - next_state <= FETCH; - else - next_state <= s574; - end if; - when s548 => - if (RDY = '1') then - next_state <= s551; - else - next_state <= s548; - end if; - when s551 => - next_state <= s552; - when s552 => - next_state <= s576; - when s575 => - if (RDY = '1') then - next_state <= s577; - else - next_state <= s575; - end if; - when s576 => - next_state <= s575; - when s577 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s577; - end if; - when s532 => - if (RDY = '1') then - next_state <= s533; - else - next_state <= s532; - end if; - when s533 => - next_state <= s534; - when s534 => - next_state <= s536; - when s535 => - if (RDY = '1') then - next_state <= s537; - else - next_state <= s535; - end if; - when s536 => - next_state <= s535; - when s537 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s537; - end if; - when s274 => - if (RDY = '1') then - next_state <= s305; - else - next_state <= s274; - end if; - when s305 => - if (RDY = '1') then - next_state <= s304; - else - next_state <= s305; - end if; - when s203 => - if (RDY = '1' and - zw_REG_OP = X"34") then - next_state <= s219; - elsif (RDY = '1' and - zw_REG_OP = X"3C") then - next_state <= s212; - elsif (RDY = '1' and - zw_REG_OP = X"24") then - next_state <= s227; - elsif (RDY = '1' and - zw_REG_OP = X"2C") then - next_state <= s360; - elsif (RDY = '1' and - zw_REG_OP = X"89") then - next_state <= FETCH; - else - next_state <= s203; - end if; - when s212 => - if (RDY = '1') then - next_state <= s228; - else - next_state <= s212; - end if; - when s219 => - if (RDY = '1') then - next_state <= s227; - else - next_state <= s219; - end if; - when s227 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s227; - end if; - when s228 => - if (RDY = '1' AND - zw_b2(0) = '0') then - next_state <= FETCH; - elsif (RDY = '1') then - next_state <= s227; - else - next_state <= s228; - end if; - when s267 => - if (RDY = '1') then - next_state <= s269; - else - next_state <= s267; - end if; - when s268 => - if (RDY = '1' and ( - (zw_b2(0) = '1' and zw_REG_OP = X"8F") or - (zw_b2(1) = '1' and zw_REG_OP = X"9F") or - (zw_b2(2) = '1' and zw_REG_OP = X"AF") or - (zw_b2(3) = '1' and zw_REG_OP = X"BF") or - (zw_b2(4) = '1' and zw_REG_OP = X"CF") or - (zw_b2(5) = '1' and zw_REG_OP = X"DF") or - (zw_b2(6) = '1' and zw_REG_OP = X"EF") or - (zw_b2(7) = '1' and zw_REG_OP = X"FF") or - (zw_b2(0) = '0' and zw_REG_OP = X"0F") or - (zw_b2(1) = '0' and zw_REG_OP = X"1F") or - (zw_b2(2) = '0' and zw_REG_OP = X"2F") or - (zw_b2(3) = '0' and zw_REG_OP = X"3F") or - (zw_b2(4) = '0' and zw_REG_OP = X"4F") or - (zw_b2(5) = '0' and zw_REG_OP = X"5F") or - (zw_b2(6) = '0' and zw_REG_OP = X"6F") or - (zw_b2(7) = '0' and zw_REG_OP = X"7F"))) then - next_state <= s301; - elsif (RDY = '1') then - next_state <= FETCH; - else - next_state <= s268; - end if; - when s269 => - if (RDY = '1') then - next_state <= s268; - else - next_state <= s269; - end if; - when s578 => - if (RDY = '1') then - next_state <= s567; - else - next_state <= s578; - end if; - when s580 => - if (RDY = '1') then - next_state <= s555; - else - next_state <= s580; - end if; - when s25 => - if (RDY = '1') then - next_state <= FETCH; - else - next_state <= s25; - end if; - when others => - next_state <= RES; - end case; - end process nextstate_proc; - - ----------------------------------------------------------------- - output_proc : process ( - D_IN, - IRQn, - RDY, - adr_PC, - adr_SP, - adr_nxt_PC, - current_state, - d_ALU, - d_REGS, - q_a, - q_x, - q_y, - reg_F, - sig_PC, - zw_ALU, - zw_ALU1, - zw_ALU2, - zw_ALU3, - zw_ALU4, - zw_REG_NMI, - zw_REG_OP, - zw_b1, - zw_b2, - zw_b3, - zw_b4, - zw_w1 - ) - ----------------------------------------------------------------- - begin - -- Default Assignment - A <= sig_PC; - a_ALU <= X"00"; - adr_out <= X"0000"; - b_ALU <= X"00"; - d_REGS_out <= X"00"; - ld <= "00"; - ld_PC <= '0'; - ld_SP <= '0'; - load_REGS <= '0'; - offset <= X"0000"; - reg_0F_out <= reg_F(0); - reg_1F_out <= reg_F(1); - reg_3F_out <= reg_F(3); - reg_7F_out <= reg_F(7); - -- Default Assignment To Internals - sig_D_OUT <= X"00"; - sig_RD <= '0'; - sig_RWn <= '1'; - sig_SYNC <= '0'; - sig_WR <= '0'; - zw_ALU <= '0' & X"00"; - zw_ALU1 <= '0' & X"00"; - zw_ALU2 <= '0' & X"00"; - zw_ALU3 <= '0' & X"00"; - zw_ALU4 <= '0' & X"00"; - - -- Combined Actions - case current_state is - when FETCH => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_SYNC <= NOT (RDY); - if ((zw_REG_NMI = '1') and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((IRQn = '0' and - reg_F(2) = '0') and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"69" or - D_IN = X"65" or - D_IN = X"75" or - D_IN = X"6D" or - D_IN = X"7D" or - D_IN = X"79" or - D_IN = X"61" or - D_IN = X"71" or - D_IN = X"72") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"06" or - D_IN = X"16" or - D_IN = X"0E" or - D_IN = X"1E" or - D_IN (3 downto 0) = X"7" or - D_IN = X"14" or - D_IN = X"04" or - D_IN = X"0C" or - D_IN = X"1C") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"90" or - D_IN = X"B0" or - D_IN = X"F0" or - D_IN = X"30" or - D_IN = X"D0" or - D_IN = X"10" or - D_IN = X"50" or - D_IN = X"70" or - D_IN = X"80" or - D_IN (3 downto 0) = X"F") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"24" or - D_IN = X"2C" or - D_IN = X"3C" or - D_IN = X"34" or - D_IN = X"89") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"00") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"18") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"D8") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"58") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"B8") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"E0" or - D_IN = X"E4" or - D_IN = X"EC") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"C0" or - D_IN = X"C4" or - D_IN = X"CC") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"C6" or - D_IN = X"D6" or - D_IN = X"CE" or - D_IN = X"DE") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"CA") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"88") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"49" or - D_IN = X"45" or - D_IN = X"55" or - D_IN = X"4D" or - D_IN = X"5D" or - D_IN = X"59" or - D_IN = X"41" or - D_IN = X"51" or - D_IN = X"09" or - D_IN = X"05" or - D_IN = X"15" or - D_IN = X"0D" or - D_IN = X"1D" or - D_IN = X"19" or - D_IN = X"01" or - D_IN = X"11" or - D_IN = X"29" or - D_IN = X"25" or - D_IN = X"35" or - D_IN = X"2D" or - D_IN = X"3D" or - D_IN = X"39" or - D_IN = X"21" or - D_IN = X"31" or - D_IN = X"C9" or - D_IN = X"C5" or - D_IN = X"D5" or - D_IN = X"CD" or - D_IN = X"DD" or - D_IN = X"D9" or - D_IN = X"C1" or - D_IN = X"D1" or - D_IN = X"32" or - D_IN = X"D2" or - D_IN = X"52" or - D_IN = X"12") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"E6" or - D_IN = X"F6" or - D_IN = X"EE" or - D_IN = X"FE") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"E8") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"C8") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"4C" or - D_IN = X"6C" or - D_IN = X"7C") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"20") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"A9" or - D_IN = X"A5" or - D_IN = X"B5" or - D_IN = X"AD" or - D_IN = X"BD" or - D_IN = X"B9" or - D_IN = X"A1" or - D_IN = X"B1" or - D_IN = X"B2") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"A2" or - D_IN = X"A6" or - D_IN = X"B6" or - D_IN = X"AE" or - D_IN = X"BE") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"A0" or - D_IN = X"A4" or - D_IN = X"B4" or - D_IN = X"AC" or - D_IN = X"BC") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"46" or - D_IN = X"56" or - D_IN = X"4E" or - D_IN = X"5E") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"EA") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"48") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"08") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"7A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"28") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"26" or - D_IN = X"36" or - D_IN = X"2E" or - D_IN = X"3E") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"66" or - D_IN = X"76" or - D_IN = X"6E" or - D_IN = X"7E") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"40") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"60") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"E9" or - D_IN = X"E5" or - D_IN = X"F5" or - D_IN = X"ED" or - D_IN = X"FD" or - D_IN = X"F9" or - D_IN = X"E1" or - D_IN = X"F1" or - D_IN = X"F2") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"38") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"F8") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"78") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"85" or - D_IN = X"95" or - D_IN = X"8D" or - D_IN = X"9D" or - D_IN = X"99" or - D_IN = X"81" or - D_IN = X"91" or - D_IN = X"11") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"86" or - D_IN = X"96" or - D_IN = X"8E") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"84" or - D_IN = X"94" or - D_IN = X"8C") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"AA") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"0A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"4A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"2A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"6A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"A8") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"98") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"BA") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"8A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"9A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"DA") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"5A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"68") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"FA") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"9C" or - D_IN = X"9E" or - D_IN = X"64" or - D_IN = X"74") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"3A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif ((D_IN = X"1A") and (RDY = '1')) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s1 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s2 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s5 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s3 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s4 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - zw_REG_OP = X"9A") then - adr_out <= X"01" & d_REGS; - ld <= "11"; - ld_SP <= '1'; - sig_SYNC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"BA") then - d_REGS_out <= adr_SP (7 downto 0); - a_ALU <= adr_SP (7 downto 0); - b_ALU <= X"00"; - load_REGS <= '1'; - sig_SYNC <= '1'; - elsif (RDY = '1') then - a_ALU <= d_REGS; - b_ALU <= X"00"; - load_REGS <= '1'; - sig_SYNC <= '1'; - end if; - when s12 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s16 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s17 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s24 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s271 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s273 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - adr_out <= D_IN & zw_b1; - ld <= "11"; - ld_PC <= '1'; - end if; - when s304 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s307 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - adr_out <= D_IN & zw_b1; - ld <= "11"; - ld_PC <= '1'; - sig_SYNC <= '1'; - end if; - when s177 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - (zw_REG_OP = X"85" OR - zw_REG_OP = X"86" OR - zw_REG_OP = X"64" OR - zw_REG_OP = X"84")) then - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= d_REGS; - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"95" OR - zw_REG_OP = X"74" OR - zw_REG_OP = X"94")) then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - (zw_REG_OP = X"8D" OR - zw_REG_OP = X"8E" OR - zw_REG_OP = X"9C" OR - zw_REG_OP = X"8C")) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"9D" OR - zw_REG_OP = X"9E")) then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"99") then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_y; - elsif (RDY = '1' and - zw_REG_OP = X"91") then - a_ALU <= D_IN; - b_ALU <= X"01"; - elsif (RDY = '1' and - zw_REG_OP = X"81") then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"96") then - a_ALU <= D_IN; - b_ALU <= q_y; - elsif (RDY = '1' and - zw_REG_OP = X"92") then - a_ALU <= D_IN; - b_ALU <= X"01"; - end if; - when s180 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= "0000000" & zw_b2(0); - ld <= "11"; - ld_PC <= '1'; - end if; - when s181 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= q_y; - end if; - when s183 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= d_REGS; - ld <= "11"; - ld_PC <= '1'; - end if; - when s184 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_SYNC <= '1'; - when s185 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= d_REGS; - ld <= "11"; - ld_PC <= '1'; - end if; - when s186 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s187 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_SYNC <= '1'; - when s188 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= zw_b1; - b_ALU <= X"01"; - end if; - when s189 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= "0000000" & zw_b2(0); - ld <= "11"; - ld_PC <= '1'; - end if; - when s190 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_SYNC <= '1'; - when s191 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= d_REGS; - when s192 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= d_REGS; - ld <= "11"; - ld_PC <= '1'; - when s193 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_SYNC <= '1'; - when s377 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= d_REGS; - ld <= "11"; - ld_SP <= '1'; - end if; - when s381 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_SYNC <= '1'; - when s378 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= reg_F; - ld <= "11"; - ld_SP <= '1'; - end if; - when s382 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_SYNC <= '1'; - when s379 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - end if; - when s383 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s384 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - d_REGS_out <= D_IN; - load_REGS <= '1'; - a_ALU <= D_IN; - b_ALU <= X"00"; - sig_SYNC <= '1'; - end if; - when s380 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - end if; - when s385 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s386 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s387 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - end if; - when s388 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - end if; - when s389 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - end if; - when s391 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s392 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - adr_out <= D_IN & zw_b1; - ld <= "11"; - ld_PC <= '1'; - sig_SYNC <= '1'; - end if; - when s390 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - end if; - when s393 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - end if; - when s394 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s395 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - adr_out <= D_IN & zw_b1; - ld <= "11"; - ld_PC <= '1'; - end if; - when s396 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s397 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - ld_PC <= '1'; - end if; - when s398 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= adr_PC (15 downto 8); - end if; - when s399 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= adr_PC (7 downto 0); - when s400 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s401 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - adr_out <= D_IN & zw_b1; - ld <= "11"; - ld_PC <= '1'; - sig_SYNC <= '1'; - end if; - when s526 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - ld_PC <= '1'; - end if; - when s527 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= adr_PC (15 downto 8); - when s528 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= adr_PC (7 downto 0); - when s529 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= reg_F; - when s530 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s531 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s544 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - when s545 => - sig_RWn <= '1'; - sig_RD <= '1'; - adr_out <= X"FFFB"; - ld <= "11"; - ld_PC <= '1'; - when s546 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_PC <= '1'; - when s547 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s549 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - adr_out <= D_IN & zw_w1 (7 downto 0); - ld <= "11"; - ld_PC <= '1'; - sig_SYNC <= '1'; - end if; - when s550 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - when s404 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= q_a (6 downto 0) & '0'; - b_ALU <= X"00"; - d_REGS_out <= q_a (6 downto 0) & '0'; - load_REGS <= '1'; - sig_SYNC <= '1'; - end if; - when s556 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= '0' & q_a (7 downto 1); - b_ALU <= X"00"; - d_REGS_out <= '0' & q_a (7 downto 1); - load_REGS <= '1'; - sig_SYNC <= '1'; - end if; - when s557 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= q_a (6 downto 0) & reg_F(0); - b_ALU <= X"00"; - d_REGS_out <= q_a (6 downto 0) & reg_F(0); - load_REGS <= '1'; - sig_SYNC <= '1'; - end if; - when s579 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= reg_F(0) & q_a (7 downto 1); - b_ALU <= X"00"; - d_REGS_out <= reg_F(0) & q_a (7 downto 1); - load_REGS <= '1'; - sig_SYNC <= '1'; - end if; - when s201 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR - zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR - zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR - zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then - ld <= "11"; - ld_PC <= '1'; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - ld <= "11"; - ld_PC <= '1'; - d_REGS_out <= D_IN OR q_a; - load_REGS <= '1'; - a_ALU <= D_IN OR q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - ld <= "11"; - ld_PC <= '1'; - d_REGS_out <= D_IN XOR q_a; - load_REGS <= '1'; - a_ALU <= D_IN XOR q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - ld <= "11"; - ld_PC <= '1'; - d_REGS_out <= D_IN AND q_a; - load_REGS <= '1'; - a_ALU <= D_IN AND q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - ld <= "11"; - ld_PC <= '1'; - zw_ALU <= unsigned ('0' & d_REGS) + unsigned ('0' & NOT (D_IN)) + 1; - sig_SYNC <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR - zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then - ld <= "11"; - ld_PC <= '1'; - d_REGS_out <= D_IN; - load_REGS <= '1'; - a_ALU <= D_IN; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"B5" OR - zw_REG_OP = X"B4" OR - zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR - zw_REG_OP = X"35" OR - zw_REG_OP = X"D5")) then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - (zw_REG_OP = X"AD" OR - zw_REG_OP = X"AE" OR - zw_REG_OP = X"AC" OR - zw_REG_OP = X"4D" OR - zw_REG_OP = X"0D" OR - zw_REG_OP = X"2D" OR - zw_REG_OP = X"CD" OR - zw_REG_OP = X"EC" OR - zw_REG_OP = X"CC")) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"BD" OR - zw_REG_OP = X"BC" OR - zw_REG_OP = X"5D" OR - zw_REG_OP = X"1D" OR - zw_REG_OP = X"3D" OR - zw_REG_OP = X"DD")) then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - (zw_REG_OP = X"B9" OR - zw_REG_OP = X"BE" OR - zw_REG_OP = X"59" OR - zw_REG_OP = X"19" OR - zw_REG_OP = X"39" OR - zw_REG_OP = X"D9")) then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_y; - elsif (RDY = '1' and - (zw_REG_OP = X"B1" OR - zw_REG_OP = X"51" OR - zw_REG_OP = X"11" OR - zw_REG_OP = X"31" OR - zw_REG_OP = X"D1")) then - a_ALU <= D_IN; - b_ALU <= X"01"; - elsif (RDY = '1' and - (zw_REG_OP = X"A1" OR - zw_REG_OP = X"41" OR - zw_REG_OP = X"01" OR - zw_REG_OP = X"21" OR - zw_REG_OP = X"C1")) then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"B6") then - a_ALU <= D_IN; - b_ALU <= q_y; - elsif (RDY = '1' and - (zw_REG_OP = X"32" OR - zw_REG_OP = X"D2" OR - zw_REG_OP = X"52" OR - zw_REG_OP = X"B2" OR - zw_REG_OP = X"12")) then - a_ALU <= D_IN; - b_ALU <= X"01"; - end if; - when s202 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s211 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= "0000000" & zw_b2(0); - ld <= "11"; - ld_PC <= '1'; - end if; - when s215 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= q_y; - end if; - when s217 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s218 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s222 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= zw_b1; - b_ALU <= X"01"; - end if; - when s223 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= "0000000" & zw_b2(0); - ld <= "11"; - ld_PC <= '1'; - end if; - when s224 => - sig_RWn <= '1'; - sig_RD <= '1'; - if ((RDY = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - d_REGS_out <= D_IN OR q_a; - load_REGS <= '1'; - a_ALU <= D_IN OR q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - d_REGS_out <= D_IN XOR q_a; - load_REGS <= '1'; - a_ALU <= D_IN XOR q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - d_REGS_out <= D_IN AND q_a; - load_REGS <= '1'; - a_ALU <= D_IN AND q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - zw_ALU <= unsigned ('0' & d_REGS) + unsigned ('0' & NOT (D_IN)) + 1; - sig_SYNC <= '1'; - elsif (RDY = '1') then - d_REGS_out <= D_IN; - load_REGS <= '1'; - a_ALU <= D_IN; - b_ALU <= X"00"; - sig_SYNC <= '1'; - end if; - when s225 => - sig_RWn <= '1'; - sig_RD <= '1'; - if ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or - zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or - zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - d_REGS_out <= D_IN OR q_a; - load_REGS <= '1'; - a_ALU <= D_IN OR q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or - zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or - zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - d_REGS_out <= D_IN XOR q_a; - load_REGS <= '1'; - a_ALU <= D_IN XOR q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32" or zw_REG_OP = X"D2")) then - d_REGS_out <= D_IN AND q_a; - load_REGS <= '1'; - a_ALU <= D_IN AND q_a; - b_ALU <= X"00"; - sig_SYNC <= '1'; - elsif ((RDY = '1' AND - zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or - zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or - zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or - zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then - zw_ALU <= unsigned ('0' & d_REGS) + unsigned ('0' & NOT (D_IN)) + 1; - sig_SYNC <= '1'; - elsif (RDY = '1' AND - zw_b2(0) = '0') then - d_REGS_out <= D_IN; - load_REGS <= '1'; - a_ALU <= D_IN; - b_ALU <= X"00"; - sig_SYNC <= '1'; - end if; - when s226 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - (zw_REG_OP = X"C6" OR - zw_REG_OP = X"E6")) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"D6" OR - zw_REG_OP = X"F6")) then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - (zw_REG_OP = X"CE" OR - zw_REG_OP = X"EE")) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"DE" OR - zw_REG_OP = X"FE")) then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_x; - end if; - when s243 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s244 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= "0000000" & zw_b2(0); - ld <= "11"; - ld_PC <= '1'; - end if; - when s247 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s344 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s343 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= zw_b4; - end if; - when s250 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b1; - end if; - when s251 => - sig_RWn <= '1'; - sig_RD <= '1'; - a_ALU <= zw_b1; - b_ALU <= X"00"; - sig_SYNC <= '1'; - when s360 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s403 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - (zw_REG_OP = X"1E" or - zw_REG_OP = X"7E" or - zw_REG_OP = X"3E" or - zw_REG_OP = X"5E")) then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - (zw_REG_OP = X"06" or zw_REG_OP = X"66" or - zw_REG_OP = X"26" or zw_REG_OP = X"46" or - zw_REG_OP = X"04" or zw_REG_OP = X"14")) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"16" or - zw_REG_OP = X"76" or - zw_REG_OP = X"36" or - zw_REG_OP = X"56")) then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - (zw_REG_OP = X"0E" or - zw_REG_OP = X"6E" or - zw_REG_OP = X"2E" or - zw_REG_OP = X"4E"or - zw_REG_OP = X"0C" or - zw_REG_OP = X"1C")) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - zw_REG_OP (3 downto 0) = X"7") then - ld <= "11"; - ld_PC <= '1'; - end if; - when s406 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s407 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= "0000000" & zw_b2(0); - ld <= "11"; - ld_PC <= '1'; - end if; - when s409 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s412 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s413 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s416 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - (zw_REG_OP = X"06" or - zw_REG_OP = X"16" or - zw_REG_OP = X"0E" or - zw_REG_OP = X"1E")) then - sig_D_OUT <= D_IN(6 downto 0) & '0'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"46" or - zw_REG_OP = X"56" or - zw_REG_OP = X"4E" or - zw_REG_OP = X"5E")) then - sig_D_OUT <= '0' & D_IN(7 downto 1); - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"26" or - zw_REG_OP = X"36" or - zw_REG_OP = X"2E" or - zw_REG_OP = X"3E")) then - sig_D_OUT <= D_IN(6 downto 0) & reg_F(0); - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"66" or - zw_REG_OP = X"76" or - zw_REG_OP = X"6E" or - zw_REG_OP = X"7E")) then - sig_D_OUT <= reg_F(0) & D_IN(7 downto 1); - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - elsif (RDY = '1' and - zw_REG_OP (7) = '0' and - zw_REG_OP (3 downto 0) = X"7") then - sig_D_OUT <= D_IN and NOT (d_ALU); - a_ALU <= "00000" & zw_REG_OP (6 downto 4) ; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - elsif (RDY = '1' and - zw_REG_OP (7) = '1' and - zw_REG_OP (3 downto 0) = X"7") then - sig_D_OUT <= D_IN or d_ALU; - a_ALU <= "00000" & zw_REG_OP (6 downto 4) ; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"14" or - zw_REG_OP = X"1C")) then - sig_D_OUT <= D_IN and NOT (q_a); - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - elsif (RDY = '1' and - (zw_REG_OP = X"04" or - zw_REG_OP = X"0C")) then - sig_D_OUT <= D_IN or q_a; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - end if; - when s418 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (zw_REG_OP (3 downto 0) = X"7") then - sig_SYNC <= '1'; - elsif ((zw_REG_OP = X"14" or - zw_REG_OP = X"04" or - zw_REG_OP = X"0C" or - zw_REG_OP = X"1C")) then - a_ALU <= zw_b1; - b_ALU <= X"00"; - sig_SYNC <= '1'; - else - a_ALU <= zw_b1; - b_ALU <= X"00"; - sig_SYNC <= '1'; - end if; - when s510 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - zw_REG_OP = X"65") then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"69" and - reg_F(3) = '0') then - ld <= "11"; - ld_PC <= '1'; - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU <= unsigned ('0' & q_a) + unsigned ('0' & D_IN) + reg_F(0); - sig_SYNC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"75") then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"6D") then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"7D") then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"79") then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_y; - elsif (RDY = '1' and - zw_REG_OP = X"71") then - a_ALU <= D_IN; - b_ALU <= X"01"; - elsif (RDY = '1' and - zw_REG_OP = X"61") then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"69" and - reg_F(3) = '1') then - ld <= "11"; - ld_PC <= '1'; - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU4(7 downto 5)); - zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(7 downto 5)); - - zw_ALU4(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; - zw_ALU3(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; - - zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; - zw_ALU2(4 downto 0) <= unsigned ('0' & q_a(7 downto 4)) + unsigned - ('0' & D_IN(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); - - zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; - zw_ALU1(4 downto 0) <= unsigned ('0' & q_a(3 downto 0)) + unsigned - ('0' & D_IN(3 downto 0)) + reg_F(0); - sig_SYNC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"72") then - a_ALU <= D_IN; - b_ALU <= X"01"; - end if; - when s553 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s555 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= X"01"; - ld <= "11"; - ld_PC <= '1'; - end if; - when s558 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= q_y; - end if; - when s560 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s561 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s563 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= zw_b1; - b_ALU <= X"01"; - end if; - when s564 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '0') then - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU <= unsigned ('0' & q_a) + unsigned ('0' & D_IN) + reg_F(0); - sig_SYNC <= '1'; - elsif (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '1') then - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU4(7 downto 5)); - zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(7 downto 5)); - - zw_ALU4(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; - zw_ALU3(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; - - zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; - zw_ALU2(4 downto 0) <= unsigned ('0' & q_a(7 downto 4)) + unsigned - ('0' & D_IN(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); - - zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; - zw_ALU1(4 downto 0) <= unsigned ('0' & q_a(3 downto 0)) + unsigned - ('0' & D_IN(3 downto 0)) + reg_F(0); - sig_SYNC <= '1'; - end if; - when s565 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - reg_F(3) = '0') then - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU <= unsigned ('0' & q_a) + unsigned ('0' & D_IN) + reg_F(0); - sig_SYNC <= '1'; - elsif (RDY = '1' and - reg_F(3) = '1') then - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU4(7 downto 5)); - zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(7 downto 5)); - - zw_ALU4(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; - zw_ALU3(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; - - zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; - zw_ALU2(4 downto 0) <= unsigned ('0' & q_a(7 downto 4)) + unsigned - ('0' & D_IN(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); - - zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; - zw_ALU1(4 downto 0) <= unsigned ('0' & q_a(3 downto 0)) + unsigned - ('0' & D_IN(3 downto 0)) + reg_F(0); - sig_SYNC <= '1'; - end if; - when s566 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= X"01"; - ld <= "11"; - ld_PC <= '1'; - end if; - when s266 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and ( - (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or - (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or - (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or - (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then - ld <= "11"; - ld_PC <= '1'; - sig_SYNC <= '1'; - elsif (RDY = '1' and ( - zw_REG_OP = X"8F" or - zw_REG_OP = X"9F" or - zw_REG_OP = X"AF" or - zw_REG_OP = X"BF" or - zw_REG_OP = X"CF" or - zw_REG_OP = X"DF" or - zw_REG_OP = X"EF" or - zw_REG_OP = X"FF" or - zw_REG_OP = X"0F" or - zw_REG_OP = X"1F" or - zw_REG_OP = X"2F" or - zw_REG_OP = X"3F" or - zw_REG_OP = X"4F" or - zw_REG_OP = X"5F" or - zw_REG_OP = X"6F" or - zw_REG_OP = X"7F")) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s301 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - zw_b3 = adr_nxt_PC (15 downto 8)) then - offset <= (zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(6 downto 0)); - ld <= "11"; - ld_PC <= '1'; - sig_SYNC <= '1'; - elsif (RDY = '1') then - offset <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); - ld <= "11"; - ld_PC <= '1'; - end if; - when s302 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when RES => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_PC <= '1'; - ld_SP <= '1'; - sig_RWn <= '1'; - sig_RD <= '1'; - when s511 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - zw_REG_OP = X"E5") then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"E9" and - reg_F(3) = '0') then - ld <= "11"; - ld_PC <= '1'; - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU <= unsigned ('0' & q_a) + unsigned ('0' & NOT (D_IN)) + reg_F(0); - sig_SYNC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"F5") then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"ED") then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"FD") then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"F9") then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_y; - elsif (RDY = '1' and - zw_REG_OP = X"F1") then - a_ALU <= D_IN; - b_ALU <= X"01"; - elsif (RDY = '1' and - zw_REG_OP = X"E1") then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"E9" and - reg_F(3) = '1') then - ld <= "11"; - ld_PC <= '1'; - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + - unsigned ((zw_ALU4(8 downto 5))); - zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + - unsigned ((zw_ALU3(8 downto 5))); - - zw_ALU4(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & - (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; - zw_ALU3(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & - (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; - - zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; - zw_ALU2(4 downto 0) <= unsigned ('0' & q_a(7 downto 4)) + unsigned - ('0' & NOT (D_IN(7 downto 4))) + zw_ALU1(4); - - zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; - zw_ALU1(4 downto 0) <= unsigned ('0' & q_a(3 downto 0)) + unsigned - ('0' & NOT (D_IN(3 downto 0))) + reg_F(0); - sig_SYNC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"F2") then - a_ALU <= D_IN; - b_ALU <= X"01"; - end if; - when s559 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s567 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= X"01"; - ld <= "11"; - ld_PC <= '1'; - end if; - when s568 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= q_y; - end if; - when s569 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s570 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s571 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= X"01"; - ld <= "11"; - ld_PC <= '1'; - end if; - when s572 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= zw_b1; - b_ALU <= X"01"; - end if; - when s573 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '0') then - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU <= unsigned ('0' & q_a) + unsigned ('0' & NOT (D_IN)) + reg_F(0); - sig_SYNC <= '1'; - elsif (RDY = '1' AND - zw_b2(0) = '0' and - reg_F(3) = '1') then - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + - unsigned ((zw_ALU4(8 downto 5))); - zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + - unsigned ((zw_ALU3(8 downto 5))); - - zw_ALU4(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & - (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; - zw_ALU3(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & - (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; - - zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; - zw_ALU2(4 downto 0) <= unsigned ('0' & q_a(7 downto 4)) + unsigned - ('0' & NOT (D_IN(7 downto 4))) + zw_ALU1(4); - - zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; - zw_ALU1(4 downto 0) <= unsigned ('0' & q_a(3 downto 0)) + unsigned - ('0' & NOT (D_IN(3 downto 0))) + reg_F(0); - sig_SYNC <= '1'; - end if; - when s574 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - reg_F(3) = '0') then - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU <= unsigned ('0' & q_a) + unsigned ('0' & NOT (D_IN)) + reg_F(0); - sig_SYNC <= '1'; - elsif (RDY = '1' and - reg_F(3) = '1') then - d_REGS_out <= zw_ALU(7 downto 0); - load_REGS <= '1'; - zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + - unsigned ((zw_ALU4(8 downto 5))); - zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + - unsigned ((zw_ALU3(8 downto 5))); - - zw_ALU4(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & - (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; - zw_ALU3(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & - (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; - - zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; - zw_ALU2(4 downto 0) <= unsigned ('0' & q_a(7 downto 4)) + unsigned - ('0' & NOT (D_IN(7 downto 4))) + zw_ALU1(4); - - zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; - zw_ALU1(4 downto 0) <= unsigned ('0' & q_a(3 downto 0)) + unsigned - ('0' & NOT (D_IN(3 downto 0))) + reg_F(0); - sig_SYNC <= '1'; - end if; - when s548 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - ld_PC <= '1'; - end if; - when s551 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= adr_PC (15 downto 8); - when s552 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= adr_PC (7 downto 0); - when s575 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s576 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= reg_F; - when s577 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s532 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_SP <= '1'; - ld_PC <= '1'; - end if; - when s533 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= adr_PC (15 downto 8); - when s534 => - sig_RWn <= '1'; - sig_RD <= '1'; - ld <= "11"; - ld_SP <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= adr_PC (7 downto 0); - when s535 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s536 => - sig_RWn <= '1'; - sig_RD <= '1'; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= reg_F; - when s537 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - sig_SYNC <= '1'; - end if; - when s274 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - adr_out <= D_IN & zw_b1; - offset <= (X"00" & q_x); - ld <= "11"; - ld_PC <= '1'; - end if; - when s305 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s203 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and - zw_REG_OP = X"34") then - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"3C") then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= D_IN; - b_ALU <= q_x; - elsif (RDY = '1' and - zw_REG_OP = X"24") then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"2C") then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1' and - zw_REG_OP = X"89") then - ld <= "11"; - ld_PC <= '1'; - a_ALU <= q_a AND D_IN; - b_ALU <= X"00"; - sig_SYNC <= '1'; - end if; - when s212 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= D_IN; - b_ALU <= "0000000" & zw_b2(0); - ld <= "11"; - ld_PC <= '1'; - end if; - when s219 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - end if; - when s227 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - a_ALU <= q_a AND D_IN; - b_ALU <= X"00"; - sig_SYNC <= '1'; - end if; - when s228 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' AND - zw_b2(0) = '0') then - a_ALU <= q_a AND D_IN; - b_ALU <= X"00"; - sig_SYNC <= '1'; - end if; - when s267 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s268 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1' and ( - (zw_b2(0) = '1' and zw_REG_OP = X"8F") or - (zw_b2(1) = '1' and zw_REG_OP = X"9F") or - (zw_b2(2) = '1' and zw_REG_OP = X"AF") or - (zw_b2(3) = '1' and zw_REG_OP = X"BF") or - (zw_b2(4) = '1' and zw_REG_OP = X"CF") or - (zw_b2(5) = '1' and zw_REG_OP = X"DF") or - (zw_b2(6) = '1' and zw_REG_OP = X"EF") or - (zw_b2(7) = '1' and zw_REG_OP = X"FF") or - (zw_b2(0) = '0' and zw_REG_OP = X"0F") or - (zw_b2(1) = '0' and zw_REG_OP = X"1F") or - (zw_b2(2) = '0' and zw_REG_OP = X"2F") or - (zw_b2(3) = '0' and zw_REG_OP = X"3F") or - (zw_b2(4) = '0' and zw_REG_OP = X"4F") or - (zw_b2(5) = '0' and zw_REG_OP = X"5F") or - (zw_b2(6) = '0' and zw_REG_OP = X"6F") or - (zw_b2(7) = '0' and zw_REG_OP = X"7F"))) then - ld <= "11"; - ld_PC <= '1'; - elsif (RDY = '1') then - ld <= "11"; - ld_PC <= '1'; - sig_SYNC <= '1'; - end if; - when s269 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s578 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s580 => - sig_RWn <= '1'; - sig_RD <= '1'; - when s25 => - sig_RWn <= '1'; - sig_RD <= '1'; - if (RDY = '1') then - d_REGS_out <= d_ALU; - a_ALU <= d_REGS; - b_ALU <= zw_b4; - load_REGS <= '1'; - sig_SYNC <= '1'; - end if; - when others => - null; - end case; - end process output_proc; - - -- Concurrent Statements - -- Clocked output assignments - D_OUT <= D_OUT_cld; - RD <= RD_cld; - RWn <= RWn_cld; - SYNC <= SYNC_cld; - WR <= WR_cld; - sel_ALU_as <= sel_ALU_as_cld; - sel_ALU_out <= sel_ALU_out_cld; - sel_PC_as <= sel_PC_as_cld; - sel_PC_in <= sel_PC_in_cld; - sel_PC_val <= sel_PC_val_cld; - sel_RB_in <= sel_RB_in_cld; - sel_RB_out <= sel_RB_out_cld; - sel_SP_as <= sel_SP_as_cld; - sel_SP_in <= sel_SP_in_cld; - sel_SP_val <= sel_SP_val_cld; - sel_reg <= sel_reg_cld; -end fsm;
trunk/rtl/vhdl/fsm_core_v2_0.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/doc/65C02_opcodes_cycles_testet_V0_9_DRAFT.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/65C02_opcodes_cycles_testet_V0_9_DRAFT.pdf =================================================================== --- trunk/doc/65C02_opcodes_cycles_testet_V0_9_DRAFT.pdf (revision 7) +++ trunk/doc/65C02_opcodes_cycles_testet_V0_9_DRAFT.pdf (nonexistent)
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trunk/doc/src/EXAMPLE_6502 IP Core Specification_V0_4.doc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/src/65C02_opcodes_cycles_testet_V0_9_DRAFT.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/65C02_opcodes_cycles_testet_V0_9_DRAFT.doc =================================================================== --- trunk/doc/src/65C02_opcodes_cycles_testet_V0_9_DRAFT.doc (revision 7) +++ trunk/doc/src/65C02_opcodes_cycles_testet_V0_9_DRAFT.doc (nonexistent)
trunk/doc/src/65C02_opcodes_cycles_testet_V0_9_DRAFT.doc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/src/EXAMPLE_6502 IP Core Specification_V0_5.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/EXAMPLE_6502 IP Core Specification_V0_5.doc =================================================================== --- trunk/doc/src/EXAMPLE_6502 IP Core Specification_V0_5.doc (nonexistent) +++ trunk/doc/src/EXAMPLE_6502 IP Core Specification_V0_5.doc (revision 8)
trunk/doc/src/EXAMPLE_6502 IP Core Specification_V0_5.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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