Subversion Repositories neural_net_perceptron

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/neural_net_perceptron/trunk/neural_net_perceptron/doc/specification_NN_Perceptron_v01_20220720.pdf

neural_net_perceptron/trunk/neural_net_perceptron/doc/specification_NN_Perceptron_v01_20220720.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/memory_vhd_v03_pkg.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/memory_vhd_v03_pkg.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/memory_vhd_v03_pkg.vhd (revision 8) @@ -0,0 +1,190 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- Created: 24-02-2022 13:24:00 +-- +----------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY work; + +PACKAGE memory_vhd_v03_pkg IS + + -- /////////////////\\\\\\\\\\\\\\\\\\\ + -- ************************************ + -- *** User Settings *** + -- ************************************ + + -- Wishbone Bus + CONSTANT WB_DATA_WIDTH : integer := 32; -- Wishbone Data Bus width + CONSTANT WB_ADDR_WIDTH : integer := 5; -- Wishbone Address Bus width + + CONSTANT VENDOR : string := "generic"; -- (generic, altera, xilinx) + -- NOT IMPLEMENTED YET + + -- Bus width (DATA_T) of all memories (all are equal) + -- Chose a value high enough to hold all possible values cumulated in + -- y_inj_reg, + -- Memory t, + -- Memory bias, + -- Memory w + CONSTANT DATA_WIDTH : integer := 8; + + -- Address width of s input vector memory (maximum number of components/inputs = 2**MEM_S_ADDR_WIDTH) + CONSTANT MEM_S_ADDR_WIDTH : integer := 3; -- = 8 + + -- Address width of t output vector memory (maximum number of neurons/outputs = 2**MEM_T_ADDR_WIDTH) + CONSTANT MEM_T_ADDR_WIDTH : integer := 2; -- = 4 + -- /////////////////\\\\\\\\\\\\\\\\\\\ + -- /////////////////\\\\\\\\\\\\\\\\\\\ + + + + -- ************************************ + -- *** System Constants *** + -- *** DO NOT CHANGE *** + -- ************************************ + -- Number of maximum usable components/inputs - 1 + CONSTANT I_MAX : integer := ( 2 ** MEM_S_ADDR_WIDTH ) - 1; + -- Number of maximum usable neurons/outputs - 1 + CONSTANT J_MAX : integer := ( 2 ** MEM_T_ADDR_WIDTH ) - 1; + + -- Width of Memory Latency counter (mem_rd_lat_reg) + CONSTANT MEM_LAT_CNT_WIDTH : integer := 7; -- At least 3 bits width -> latency 0...2 + -- Value to reach for leaving counting loops + CONSTANT MEM_LAT_CNT_TRANSITION : integer := ( 2 ** MEM_LAT_CNT_WIDTH ) - 1; + + -- Number of memory write lines (to build up the RD/WR vector + CONSTANT MEM_WR_LINES : integer := 5; + CONSTANT MEM_S_BITPOS : integer := MEM_WR_LINES - 5; + CONSTANT MEM_T_BITPOS : integer := MEM_WR_LINES - 4; + CONSTANT MEM_W_BITPOS : integer := MEM_WR_LINES - 3; + CONSTANT MEM_Y_BITPOS : integer := MEM_WR_LINES - 2; + CONSTANT MEM_BIAS_BITPOS : integer := MEM_WR_LINES - 1; + + -- Status READY FOR COMMANDS bit position + CONSTANT STAT_RDY : integer := 0; + -- Status Latency Messurement in progress + CONSTANT STAT_LAT_RUN : integer := 1; + -- Status Controller is NOT ready -> RESET (while start of function TRAIN) + CONSTANT STAT_NOT_RDY : integer := 2; + -- Status Interrupt Enable + CONSTANT STAT_INT_EN : integer := 3; + -- Status Memory Error + CONSTANT STAT_MEMERR : integer := 4; + -- Status DATA OUTPUT READY bit position + CONSTANT STAT_RD_WR_COMPLETE : integer := 5; + -- Status Interrupt TEST pending + CONSTANT STAT_INT_TEST : integer := 6; + -- Status Interrupt TRAIN pending + CONSTANT STAT_INT_TRAIN : integer := 7; + + + -- Calculate all memory address widths and other dependencies + -- s input memory depth + CONSTANT MEM_S_DEPTH : integer := ( 2**MEM_S_ADDR_WIDTH ) - 1; + -- t output memory depth + CONSTANT MEM_T_DEPTH : integer := ( 2**MEM_T_ADDR_WIDTH ) - 1; + -- w (weights) memory address width calculation + CONSTANT MEM_W_ADDR_WIDTH : integer := MEM_S_ADDR_WIDTH + MEM_T_ADDR_WIDTH; + -- w (weights) memory depths calculation + CONSTANT MEM_W_DEPTH : integer := ( 2**MEM_W_ADDR_WIDTH ) - 1; + + -- ************************************ + -- Wishbone Address Map + CONSTANT WB_STAT_A : integer := 0; -- + CONSTANT WB_THRES : integer := 1; -- + CONSTANT WB_BIAS : integer := 2; -- + CONSTANT WB_OFFSET : integer := 3; -- + CONSTANT WB_MAXEPOCH : integer := 4; -- + CONSTANT WB_UNUSED_X05 : integer := 5; -- DO NOT USE, for feature use + CONSTANT WB_UNUSED_X06 : integer := 6; -- DO NOT USE, for feature use + CONSTANT WB_STARTI : integer := 7; -- + CONSTANT WB_STOPI : integer := 8; -- + CONSTANT WB_STARTJ : integer := 9; -- + + CONSTANT WB_STOPJ : integer := 10; -- + CONSTANT WB_EPOCH : integer := 11; -- + CONSTANT WB_WRLAT : integer := 12; -- + CONSTANT WB_RDLAT : integer := 13; -- + CONSTANT WB_ALLLAT : integer := 14; -- + CONSTANT WB_START3 : integer := 15; -- + CONSTANT WB_START4 : integer := 16; -- + CONSTANT WB_START5_S : integer := 17; -- + CONSTANT WB_START5_T : integer := 18; -- + CONSTANT WB_START5_W : integer := 19; -- + + CONSTANT WB_START5_Y : integer := 20; -- + CONSTANT WB_START5_BIAS : integer := 21; -- + CONSTANT WB_START6 : integer := 22; -- + CONSTANT WB_IMAX : integer := 23; -- + CONSTANT WB_JMAX : integer := 24; -- + CONSTANT WB_MEMDATA_WIDTH : integer := 25; -- + -- ************************************ + + -- ************************************ + -- *** Type Definitions *** + -- ************************************ + -- Wishbone data and address types + SUBTYPE WB_DATA_WIDTH_T IS std_logic_vector ( WB_DATA_WIDTH-1 downto 0 ); + SUBTYPE WB_ADDR_WIDTH_T IS std_logic_vector ( WB_ADDR_WIDTH-1 downto 0 ); + + -- Data bus type for all memories + SUBTYPE DATA_T IS std_logic_vector ( DATA_WIDTH-1 downto 0 ); + SUBTYPE DATA_N IS integer range DATA_WIDTH-1 downto 0; + + -- Memory Latency counter type + SUBTYPE MEM_LAT_CNT_WIDTH_T IS std_logic_vector ( MEM_LAT_CNT_WIDTH-1 downto 0 ); + -- Vector bus to select memory RD or WR + SUBTYPE MEM_WR_LINES_T IS std_logic_vector ( MEM_WR_LINES-1 downto 0 ); + + -- Declare the types for all memory address busses + -- s input memory + SUBTYPE ADDRESS_S_T IS std_logic_vector ( MEM_S_ADDR_WIDTH-1 downto 0 ); + SUBTYPE ADDRESS_S_N IS integer range MEM_S_ADDR_WIDTH-1 downto 0; + SUBTYPE ADDRESS_S_ZERO_T IS std_logic_vector ( MEM_S_ADDR_WIDTH-1 downto 1 ); + -- t input/output memory + SUBTYPE ADDRESS_T_T IS std_logic_vector ( MEM_T_ADDR_WIDTH-1 downto 0 ); + SUBTYPE ADDRESS_T_N IS integer range MEM_T_ADDR_WIDTH-1 downto 0; + SUBTYPE ADDRESS_T_ZERO_T IS std_logic_vector ( MEM_T_ADDR_WIDTH-1 downto 1 ); + -- w (weigths) memory + SUBTYPE ADDRESS_W_T IS std_logic_vector ( MEM_W_ADDR_WIDTH-1 downto 0 ); + + -- Declare the types for all memory arrays + -- s input memory + TYPE S_RAM_T IS ARRAY ( MEM_S_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 ); + -- t output memory + TYPE T_RAM_T IS ARRAY ( MEM_T_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 ); + -- w (weights) memory + TYPE W_RAM_T IS ARRAY ( MEM_W_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 ); + -- ************************************ + + SUBTYPE SIM_STATE_T IS integer; + + CONSTANT ST0 : SIM_STATE_T := 0; + CONSTANT INIT : SIM_STATE_T := 1; + CONSTANT WR1 : SIM_STATE_T := 2; + CONSTANT WR_13_BURST : SIM_STATE_T := 3; + CONSTANT WR_13_END : SIM_STATE_T := 4; + CONSTANT WR_7_SINGLE : SIM_STATE_T := 5; + CONSTANT WR_7_END : SIM_STATE_T := 6; + CONSTANT ST7 : SIM_STATE_T := 7; + +END memory_vhd_v03_pkg; + + Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00000_s_v03_top_level_blk.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00000_s_v03_top_level_blk.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00000_s_v03_top_level_blk.vhd (revision 8) @@ -0,0 +1,270 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00000_s_v03_top_level_blk IS + PORT( + wb_adr_i : IN WB_ADDR_WIDTH_T; + wb_clk_i : IN std_logic; + wb_cyc_i : IN std_logic; + wb_dat_i : IN WB_DATA_WIDTH_T; + wb_rst_i : IN std_logic; + wb_stb_i : IN std_logic; + wb_we_i : IN std_logic; + ctrl_int_o : OUT std_logic; + wb_ack_o : OUT std_logic; + wb_dat_o : OUT WB_DATA_WIDTH_T + ); + +-- Declarations + +END p0300_m00000_s_v03_top_level_blk ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- +-- Revision 3.0 2022/07/04 +-- - Update wiring and connections +-- - Insert new versioned symbol of U_0 +-- Revision 2.0 2022/06/13 +-- - Insert new versioned symbol of U_0 +-- Revision 1.0 2022/06/12 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + + +ARCHITECTURE struct OF p0300_m00000_s_v03_top_level_blk IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL addr_i_oi : ADDRESS_S_T; + SIGNAL addr_j_oi : ADDRESS_T_T; + SIGNAL dbias_oi : DATA_T; + SIGNAL dout1_oi : DATA_T; + SIGNAL dout2_oi : DATA_T; + SIGNAL dout3_oi : DATA_T; + SIGNAL dout4_oi : DATA_T; + SIGNAL dout5_oi : DATA_T; + SIGNAL dout7_oi : DATA_T; + SIGNAL ds_oi : DATA_T; + SIGNAL dt_oi : DATA_T; + SIGNAL dw_oi : DATA_T; + SIGNAL dy_oi : DATA_T; + SIGNAL we_bias2_oi : std_logic; + SIGNAL we_bias3_oi : std_logic; + SIGNAL we_bias5_oi : std_logic; + SIGNAL we_s3_oi : std_logic; + SIGNAL we_s4_oi : std_logic; + SIGNAL we_s5_oi : std_logic; + SIGNAL we_t3_oi : std_logic; + SIGNAL we_t4_oi : std_logic; + SIGNAL we_t5_oi : std_logic; + SIGNAL we_w2_oi : std_logic; + SIGNAL we_w3_oi : std_logic; + SIGNAL we_w4_oi : std_logic; + SIGNAL we_w5_oi : std_logic; + SIGNAL we_w7_oi : std_logic; + SIGNAL we_y1_oi : std_logic; + SIGNAL we_y3_oi : std_logic; + SIGNAL we_y5_oi : std_logic; + + + -- Component Declarations + COMPONENT p0300_m00020_s_v03_perceptron_blk + PORT ( + clk_i : IN std_logic ; + dbias_i : IN DATA_T ; + ds_i : IN DATA_T ; + dt_i : IN DATA_T ; + dw_i : IN DATA_T ; + dy_i : IN DATA_T ; + rst_i : IN std_logic ; + wb_adr_i : IN WB_ADDR_WIDTH_T ; + wb_cyc_i : IN std_logic ; + wb_dat_i : IN WB_DATA_WIDTH_T ; + wb_stb_i : IN std_logic ; + wb_we_i : IN std_logic ; + addr_i_o : OUT ADDRESS_S_T ; + addr_j_o : OUT ADDRESS_T_T ; + ctrl_int_o : OUT std_logic ; + dout1_o : OUT DATA_T ; + dout2_o : OUT DATA_T ; + dout3_o : OUT DATA_T ; + dout4_o : OUT DATA_T ; + dout5_o : OUT DATA_T ; + dout7_o : OUT DATA_T ; + wb_ack_o : OUT std_logic ; + wb_dat_o : OUT WB_DATA_WIDTH_T ; + we_bias2_o : OUT std_logic ; + we_bias3_o : OUT std_logic ; + we_bias5_o : OUT std_logic ; + we_s3_o : OUT std_logic ; + we_s4_o : OUT std_logic ; + we_s5_o : OUT std_logic ; + we_t3_o : OUT std_logic ; + we_t4_o : OUT std_logic ; + we_t5_o : OUT std_logic ; + we_w2_o : OUT std_logic ; + we_w3_o : OUT std_logic ; + we_w4_o : OUT std_logic ; + we_w5_o : OUT std_logic ; + we_w7_o : OUT std_logic ; + we_y1_o : OUT std_logic ; + we_y3_o : OUT std_logic ; + we_y5_o : OUT std_logic + ); + END COMPONENT; + COMPONENT p0300_m00100_s_v01_mem_gen_blk + PORT ( + addr_i_i : IN ADDRESS_S_T ; + addr_j_i : IN ADDRESS_T_T ; + clk_i : IN std_logic ; + din1_i : IN DATA_T ; + din2_i : IN DATA_T ; + din3_i : IN DATA_T ; + din4_i : IN DATA_T ; + din5_i : IN DATA_T ; + din7_i : IN DATA_T ; + we_bias2_i : IN std_logic ; + we_bias3_i : IN std_logic ; + we_bias5_i : IN std_logic ; + we_s3_i : IN std_logic ; + we_s4_i : IN std_logic ; + we_s5_i : IN std_logic ; + we_t3_i : IN std_logic ; + we_t4_i : IN std_logic ; + we_t5_i : IN std_logic ; + we_w2_i : IN std_logic ; + we_w3_i : IN std_logic ; + we_w4_i : IN std_logic ; + we_w5_i : IN std_logic ; + we_w7_i : IN std_logic ; + we_y1_i : IN std_logic ; + we_y3_i : IN std_logic ; + we_y5_i : IN std_logic ; + dbias_o : OUT DATA_T ; + ds_o : OUT DATA_T ; + dt_o : OUT DATA_T ; + dw_o : OUT DATA_T ; + dy_o : OUT DATA_T + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : p0300_m00020_s_v03_perceptron_blk USE ENTITY work.p0300_m00020_s_v03_perceptron_blk; + FOR ALL : p0300_m00100_s_v01_mem_gen_blk USE ENTITY work.p0300_m00100_s_v01_mem_gen_blk; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + U_0 : p0300_m00020_s_v03_perceptron_blk + PORT MAP ( + clk_i => wb_clk_i, + dbias_i => dbias_oi, + ds_i => ds_oi, + dt_i => dt_oi, + dw_i => dw_oi, + dy_i => dy_oi, + rst_i => wb_rst_i, + wb_adr_i => wb_adr_i, + wb_cyc_i => wb_cyc_i, + wb_dat_i => wb_dat_i, + wb_stb_i => wb_stb_i, + wb_we_i => wb_we_i, + addr_i_o => addr_i_oi, + addr_j_o => addr_j_oi, + ctrl_int_o => ctrl_int_o, + dout1_o => dout1_oi, + dout2_o => dout2_oi, + dout3_o => dout3_oi, + dout4_o => dout4_oi, + dout5_o => dout5_oi, + dout7_o => dout7_oi, + wb_ack_o => wb_ack_o, + wb_dat_o => wb_dat_o, + we_bias2_o => we_bias2_oi, + we_bias3_o => we_bias3_oi, + we_bias5_o => we_bias5_oi, + we_s3_o => we_s3_oi, + we_s4_o => we_s4_oi, + we_s5_o => we_s5_oi, + we_t3_o => we_t3_oi, + we_t4_o => we_t4_oi, + we_t5_o => we_t5_oi, + we_w2_o => we_w2_oi, + we_w3_o => we_w3_oi, + we_w4_o => we_w4_oi, + we_w5_o => we_w5_oi, + we_w7_o => we_w7_oi, + we_y1_o => we_y1_oi, + we_y3_o => we_y3_oi, + we_y5_o => we_y5_oi + ); + U_1 : p0300_m00100_s_v01_mem_gen_blk + PORT MAP ( + addr_i_i => addr_i_oi, + addr_j_i => addr_j_oi, + clk_i => wb_clk_i, + din1_i => dout1_oi, + din2_i => dout2_oi, + din3_i => dout3_oi, + din4_i => dout4_oi, + din5_i => dout5_oi, + din7_i => dout7_oi, + we_bias2_i => we_bias2_oi, + we_bias3_i => we_bias3_oi, + we_bias5_i => we_bias5_oi, + we_s3_i => we_s3_oi, + we_s4_i => we_s4_oi, + we_s5_i => we_s5_oi, + we_t3_i => we_t3_oi, + we_t4_i => we_t4_oi, + we_t5_i => we_t5_oi, + we_w2_i => we_w2_oi, + we_w3_i => we_w3_oi, + we_w4_i => we_w4_oi, + we_w5_i => we_w5_oi, + we_w7_i => we_w7_oi, + we_y1_i => we_y1_oi, + we_y3_i => we_y3_oi, + we_y5_i => we_y5_oi, + dbias_o => dbias_oi, + ds_o => ds_oi, + dt_o => dt_oi, + dw_o => dw_oi, + dy_o => dy_oi + ); + +END struct; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00020_s_v03_perceptron_blk.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00020_s_v03_perceptron_blk.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00020_s_v03_perceptron_blk.vhd (revision 8) @@ -0,0 +1,668 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00020_s_v03_perceptron_blk IS + PORT( + clk_i : IN std_logic; + dbias_i : IN DATA_T; + ds_i : IN DATA_T; + dt_i : IN DATA_T; + dw_i : IN DATA_T; + dy_i : IN DATA_T; + rst_i : IN std_logic; + wb_adr_i : IN WB_ADDR_WIDTH_T; + wb_cyc_i : IN std_logic; + wb_dat_i : IN WB_DATA_WIDTH_T; + wb_stb_i : IN std_logic; + wb_we_i : IN std_logic; + addr_i_o : OUT ADDRESS_S_T; + addr_j_o : OUT ADDRESS_T_T; + ctrl_int_o : OUT std_logic; + dout1_o : OUT DATA_T; + dout2_o : OUT DATA_T; + dout3_o : OUT DATA_T; + dout4_o : OUT DATA_T; + dout5_o : OUT DATA_T; + dout7_o : OUT DATA_T; + wb_ack_o : OUT std_logic; + wb_dat_o : OUT WB_DATA_WIDTH_T; + we_bias2_o : OUT std_logic; + we_bias3_o : OUT std_logic; + we_bias5_o : OUT std_logic; + we_s3_o : OUT std_logic; + we_s4_o : OUT std_logic; + we_s5_o : OUT std_logic; + we_t3_o : OUT std_logic; + we_t4_o : OUT std_logic; + we_t5_o : OUT std_logic; + we_w2_o : OUT std_logic; + we_w3_o : OUT std_logic; + we_w4_o : OUT std_logic; + we_w5_o : OUT std_logic; + we_w7_o : OUT std_logic; + we_y1_o : OUT std_logic; + we_y3_o : OUT std_logic; + we_y5_o : OUT std_logic + ); + +-- Declarations + +END p0300_m00020_s_v03_perceptron_blk ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 3.0 2022/07/04 +-- - Update wiring and connections +-- - Insert all new versioned symbols +-- Revision 2.0 2022/06/18 +-- - Update wiring and connections +-- - Insert all new versioned symbols +-- Revision 1.0 2022/06/12 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + + +ARCHITECTURE struct OF p0300_m00020_s_v03_perceptron_blk IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL cnt_alllat_oi : MEM_LAT_CNT_WIDTH_T; + SIGNAL cnteni1_oi : std_logic; + SIGNAL cnteni2_oi : std_logic; + SIGNAL cnteni3_oi : std_logic; + SIGNAL cnteni4_oi : std_logic; + SIGNAL cnteni5_oi : std_logic; + SIGNAL cnteni7_oi : std_logic; + SIGNAL cntenj1_oi : std_logic; + SIGNAL cntenj2_oi : std_logic; + SIGNAL cntenj3_oi : std_logic; + SIGNAL cntenj4_oi : std_logic; + SIGNAL cntenj5_oi : std_logic; + SIGNAL cntenj7_oi : std_logic; + SIGNAL cnti_end_oi : std_logic; + SIGNAL cnti_rdy_oi : std_logic; + SIGNAL cntj_end_oi : std_logic; + SIGNAL cntj_rdy_oi : std_logic; + SIGNAL ctrl_bias_oi : DATA_T; + SIGNAL ctrl_clear_epoch_oi : std_logic; + SIGNAL ctrl_complete_oi : std_logic; + SIGNAL ctrl_din_oi : DATA_T; + SIGNAL ctrl_dout_oi : DATA_T; + SIGNAL ctrl_dout_valid_oi : std_logic; + SIGNAL ctrl_epoch_oi : WB_DATA_WIDTH_T; + SIGNAL ctrl_int4_o : std_logic; + SIGNAL ctrl_int6_o : std_logic; + SIGNAL ctrl_maxepoch_oi : WB_DATA_WIDTH_T; + SIGNAL ctrl_memerr_oi : std_logic; + SIGNAL ctrl_not_rdy6_oi : std_logic; + SIGNAL ctrl_offset_oi : DATA_T; + SIGNAL ctrl_rd_vec_oi : MEM_WR_LINES_T; + SIGNAL ctrl_rdlat_oi : MEM_LAT_CNT_WIDTH_T; + SIGNAL ctrl_rdy1_oi : std_logic; + SIGNAL ctrl_rdy2_oi : std_logic; + SIGNAL ctrl_rdy3_oi : std_logic; + SIGNAL ctrl_rdy4_oi : std_logic; + SIGNAL ctrl_rdy5_oi : std_logic; + SIGNAL ctrl_rdy6_oi : std_logic; + SIGNAL ctrl_rdy7_oi : std_logic; + SIGNAL ctrl_run7_oi : std_logic; + SIGNAL ctrl_start1_oi : std_logic; + SIGNAL ctrl_start2_oi : std_logic; + SIGNAL ctrl_start3_oi : std_logic; + SIGNAL ctrl_start4_oi : std_logic; + SIGNAL ctrl_start5_oi : std_logic; + SIGNAL ctrl_start6_oi : std_logic; + SIGNAL ctrl_thres_oi : DATA_T; + SIGNAL ctrl_wchgd_oi : std_logic; + SIGNAL ctrl_wr_vec_oi : MEM_WR_LINES_T; + SIGNAL ctrl_wrlat_oi : MEM_LAT_CNT_WIDTH_T; + SIGNAL rst_n_oi : std_logic; + SIGNAL set_initi_oi : std_logic; + SIGNAL set_initj_oi : std_logic; + SIGNAL starti_val_oi : ADDRESS_S_T; + SIGNAL startj_val_oi : ADDRESS_T_T; + SIGNAL stopi_val_oi : ADDRESS_S_T; + SIGNAL stopj_val_oi : ADDRESS_T_T; + + + -- Component Declarations + COMPONENT p0300_m00021_s_v03_wishbone_fsm + PORT ( + clk_i : IN std_logic ; + ctrl_alllat_i : IN MEM_LAT_CNT_WIDTH_T ; + ctrl_complete_i : IN std_logic ; + ctrl_dout_i : IN DATA_T ; + ctrl_dout_valid_i : IN std_logic ; + ctrl_epoch_i : IN WB_DATA_WIDTH_T ; + ctrl_int_test_i : IN std_logic ; + ctrl_int_train_i : IN std_logic ; + ctrl_memerr_i : IN std_logic ; + ctrl_not_rdy6_i : IN std_logic ; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ; + ctrl_rdy1_i : IN std_logic ; + ctrl_rdy2_i : IN std_logic ; + ctrl_rdy3_i : IN std_logic ; + ctrl_rdy4_i : IN std_logic ; + ctrl_rdy5_i : IN std_logic ; + ctrl_rdy6_i : IN std_logic ; + ctrl_run7_i : IN std_logic ; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ; + rst_n_i : IN std_logic ; + wb_adr_i : IN WB_ADDR_WIDTH_T ; + wb_cyc_i : IN std_logic ; + wb_dat_i : IN WB_DATA_WIDTH_T ; + wb_stb_i : IN std_logic ; + wb_we_i : IN std_logic ; + ctrl_bias_o : OUT DATA_T ; + ctrl_clear_epoch_o : OUT std_logic ; + ctrl_din_o : OUT DATA_T ; + ctrl_int_o : OUT std_logic ; + ctrl_maxepoch_o : OUT WB_DATA_WIDTH_T ; + ctrl_offset_o : OUT DATA_T ; + ctrl_rd_vec_o : OUT MEM_WR_LINES_T ; + ctrl_set_starti_o : OUT std_logic ; + ctrl_set_startj_o : OUT std_logic ; + ctrl_start3_o : OUT std_logic ; + ctrl_start4_o : OUT std_logic ; + ctrl_start5_o : OUT std_logic ; + ctrl_start6_o : OUT std_logic ; + ctrl_starti_val_o : OUT ADDRESS_S_T ; + ctrl_startj_val_o : OUT ADDRESS_T_T ; + ctrl_stopi_val_o : OUT ADDRESS_S_T ; + ctrl_stopj_val_o : OUT ADDRESS_T_T ; + ctrl_thres_o : OUT DATA_T ; + ctrl_wr_vec_o : OUT MEM_WR_LINES_T ; + wb_ack_o : OUT std_logic ; + wb_dat_o : OUT WB_DATA_WIDTH_T + ); + END COMPONENT; + COMPONENT p0300_m00022_s_v02_cal_y_fsm + PORT ( + clk_i : IN std_logic ; + cnti_end_i : IN std_logic ; + cntj_end_i : IN std_logic ; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ; + ctrl_rdy7_i : IN std_logic ; + ctrl_start_i : IN std_logic ; + ctrl_thres_i : IN DATA_T ; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ; + dbias_i : IN DATA_T ; + ds_i : IN DATA_T ; + dw_i : IN DATA_T ; + rst_n_i : IN std_logic ; + cnteni_o : OUT std_logic ; + cntenj_o : OUT std_logic ; + ctrl_rdy_o : OUT std_logic ; + dout_o : OUT DATA_T ; + we_y_o : OUT std_logic + ); + END COMPONENT; + COMPONENT p0300_m00023_s_v02_cal_w_fsm + PORT ( + clk_i : IN std_logic ; + cnti_end_i : IN std_logic ; + cntj_end_i : IN std_logic ; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ; + ctrl_rdy7_i : IN std_logic ; + ctrl_start_i : IN std_logic ; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ; + dbias_i : IN DATA_T ; + ds_i : IN DATA_T ; + dt_i : IN DATA_T ; + dw_i : IN DATA_T ; + dy_i : IN DATA_T ; + rst_n_i : IN std_logic ; + cnteni_o : OUT std_logic ; + cntenj_o : OUT std_logic ; + ctrl_rdy_o : OUT std_logic ; + ctrl_wchgd_o : OUT std_logic ; + dout_o : OUT DATA_T ; + we_bias_o : OUT std_logic ; + we_w_o : OUT std_logic + ); + END COMPONENT; + COMPONENT p0300_m00024_s_v02_test_fsm + PORT ( + clk_i : IN std_logic ; + cnti_end_i : IN std_logic ; + cntj_end_i : IN std_logic ; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ; + ctrl_rdy7_i : IN std_logic ; + ctrl_start_i : IN std_logic ; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ; + ds_i : IN DATA_T ; + dt_i : IN DATA_T ; + dw_i : IN DATA_T ; + offset_i : IN DATA_T ; + rst_n_i : IN std_logic ; + cnteni_o : OUT std_logic ; + cntenj_o : OUT std_logic ; + ctrl_int_o : OUT std_logic ; + ctrl_rdy_o : OUT std_logic ; + dout_o : OUT DATA_T ; + we_s_o : OUT std_logic ; + we_t_o : OUT std_logic ; + we_w_o : OUT std_logic + ); + END COMPONENT; + COMPONENT p0300_m00025_s_v02_init_fsm + PORT ( + clk_i : IN std_logic ; + cnti_end_i : IN std_logic ; + cntj_end_i : IN std_logic ; + ctrl_bias_i : IN DATA_T ; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ; + ctrl_rdy7_i : IN std_logic ; + ctrl_start_i : IN std_logic ; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ; + rst_n_i : IN std_logic ; + cnteni_o : OUT std_logic ; + cntenj_o : OUT std_logic ; + ctrl_rdy_o : OUT std_logic ; + dout_o : OUT DATA_T ; + we_bias_o : OUT std_logic ; + we_s_o : OUT std_logic ; + we_t_o : OUT std_logic ; + we_w_o : OUT std_logic ; + we_y_o : OUT std_logic + ); + END COMPONENT; + COMPONENT p0300_m00026_s_v02_rd_wr_fsm + PORT ( + clk_i : IN std_logic ; + cnti_end_i : IN std_logic ; + cntj_end_i : IN std_logic ; + ctrl_din_i : IN DATA_T ; + ctrl_rd_vec_i : IN MEM_WR_LINES_T ; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ; + ctrl_rdy7_i : IN std_logic ; + ctrl_start_i : IN std_logic ; + ctrl_wr_vec_i : IN MEM_WR_LINES_T ; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ; + dbias_i : IN DATA_T ; + ds_i : IN DATA_T ; + dt_i : IN DATA_T ; + dw_i : IN DATA_T ; + dy_i : IN DATA_T ; + rst_n_i : IN std_logic ; + cnteni_o : OUT std_logic ; + cntenj_o : OUT std_logic ; + ctrl_complete_o : OUT std_logic ; + ctrl_dout_o : OUT DATA_T ; + ctrl_dout_valid_o : OUT std_logic ; + ctrl_rdy_o : OUT std_logic ; + dout_o : OUT DATA_T ; + we_bias_o : OUT std_logic ; + we_s_o : OUT std_logic ; + we_t_o : OUT std_logic ; + we_w_o : OUT std_logic ; + we_y_o : OUT std_logic + ); + END COMPONENT; + COMPONENT p0300_m00027_s_v01_train_fsm + PORT ( + clk_i : IN std_logic ; + cnti_rdy_i : IN std_logic ; + cntj_rdy_i : IN std_logic ; + ctrl_clear_epoch_i : IN std_logic ; + ctrl_maxepoch_i : IN WB_DATA_WIDTH_T ; + ctrl_rdy1_i : IN std_logic ; + ctrl_rdy2_i : IN std_logic ; + ctrl_rdy7_i : IN std_logic ; + ctrl_start_i : IN std_logic ; + ctrl_wchgd_i : IN std_logic ; + rst_n_i : IN std_logic ; + ctrl_epoch_o : OUT WB_DATA_WIDTH_T ; + ctrl_int_o : OUT std_logic ; + ctrl_not_rdy_o : OUT std_logic ; + ctrl_rdy_o : OUT std_logic ; + ctrl_start1_o : OUT std_logic ; + ctrl_start2_o : OUT std_logic + ); + END COMPONENT; + COMPONENT p0300_m00028_s_v02_latency_fsm + PORT ( + clk_i : IN std_logic ; + dw_i : IN DATA_T ; + rst_n_i : IN std_logic ; + cnt_alllat_o : OUT MEM_LAT_CNT_WIDTH_T ; + cnteni_o : OUT std_logic ; + cntenj_o : OUT std_logic ; + ctrl_memerr_o : OUT std_logic ; + ctrl_rdlat_o : OUT MEM_LAT_CNT_WIDTH_T ; + ctrl_rdy_o : OUT std_logic ; + ctrl_run_o : OUT std_logic ; + ctrl_wrlat_o : OUT MEM_LAT_CNT_WIDTH_T ; + dout_o : OUT DATA_T ; + we_w_o : OUT std_logic + ); + END COMPONENT; + COMPONENT p0300_m00033_s_v01_for_loop_memwi_fsm + PORT ( + clk_i : IN std_logic ; + cnten1_i : IN std_logic ; + cnten2_i : IN std_logic ; + cnten3_i : IN std_logic ; + cnten4_i : IN std_logic ; + cnten5_i : IN std_logic ; + cnten7_i : IN std_logic ; + rst_n_i : IN std_logic ; + set_init_i : IN std_logic ; + start_vali_i : IN ADDRESS_S_T ; + stop_vali_i : IN ADDRESS_S_T ; + cnt_end_o : OUT std_logic ; + cnt_rdy_o : OUT std_logic ; + cnt_val_o : OUT ADDRESS_S_T + ); + END COMPONENT; + COMPONENT p0300_m00034_s_v01_for_loop_memwj_fsm + PORT ( + clk_i : IN std_logic ; + cnten1_i : IN std_logic ; + cnten2_i : IN std_logic ; + cnten3_i : IN std_logic ; + cnten4_i : IN std_logic ; + cnten5_i : IN std_logic ; + cnten7_i : IN std_logic ; + rst_n_i : IN std_logic ; + set_init_i : IN std_logic ; + start_valj_i : IN ADDRESS_T_T ; + stop_valj_i : IN ADDRESS_T_T ; + cnt_end_o : OUT std_logic ; + cnt_rdy_o : OUT std_logic ; + cnt_val_o : OUT ADDRESS_T_T + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : p0300_m00021_s_v03_wishbone_fsm USE ENTITY work.p0300_m00021_s_v03_wishbone_fsm; + FOR ALL : p0300_m00022_s_v02_cal_y_fsm USE ENTITY work.p0300_m00022_s_v02_cal_y_fsm; + FOR ALL : p0300_m00023_s_v02_cal_w_fsm USE ENTITY work.p0300_m00023_s_v02_cal_w_fsm; + FOR ALL : p0300_m00024_s_v02_test_fsm USE ENTITY work.p0300_m00024_s_v02_test_fsm; + FOR ALL : p0300_m00025_s_v02_init_fsm USE ENTITY work.p0300_m00025_s_v02_init_fsm; + FOR ALL : p0300_m00026_s_v02_rd_wr_fsm USE ENTITY work.p0300_m00026_s_v02_rd_wr_fsm; + FOR ALL : p0300_m00027_s_v01_train_fsm USE ENTITY work.p0300_m00027_s_v01_train_fsm; + FOR ALL : p0300_m00028_s_v02_latency_fsm USE ENTITY work.p0300_m00028_s_v02_latency_fsm; + FOR ALL : p0300_m00033_s_v01_for_loop_memwi_fsm USE ENTITY work.p0300_m00033_s_v01_for_loop_memwi_fsm; + FOR ALL : p0300_m00034_s_v01_for_loop_memwj_fsm USE ENTITY work.p0300_m00034_s_v01_for_loop_memwj_fsm; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + -- eb1 1 + rst_n_oi <= NOT ( rst_i ); + + + -- Instance port mappings. + U_14 : p0300_m00021_s_v03_wishbone_fsm + PORT MAP ( + clk_i => clk_i, + ctrl_alllat_i => cnt_alllat_oi, + ctrl_complete_i => ctrl_complete_oi, + ctrl_dout_i => ctrl_dout_oi, + ctrl_dout_valid_i => ctrl_dout_valid_oi, + ctrl_epoch_i => ctrl_epoch_oi, + ctrl_int_test_i => ctrl_int4_o, + ctrl_int_train_i => ctrl_int6_o, + ctrl_memerr_i => ctrl_memerr_oi, + ctrl_not_rdy6_i => ctrl_not_rdy6_oi, + ctrl_rdlat_i => ctrl_rdlat_oi, + ctrl_rdy1_i => ctrl_rdy1_oi, + ctrl_rdy2_i => ctrl_rdy2_oi, + ctrl_rdy3_i => ctrl_rdy3_oi, + ctrl_rdy4_i => ctrl_rdy4_oi, + ctrl_rdy5_i => ctrl_rdy5_oi, + ctrl_rdy6_i => ctrl_rdy6_oi, + ctrl_run7_i => ctrl_run7_oi, + ctrl_wrlat_i => ctrl_wrlat_oi, + rst_n_i => rst_n_oi, + wb_adr_i => wb_adr_i, + wb_cyc_i => wb_cyc_i, + wb_dat_i => wb_dat_i, + wb_stb_i => wb_stb_i, + wb_we_i => wb_we_i, + ctrl_bias_o => ctrl_bias_oi, + ctrl_clear_epoch_o => ctrl_clear_epoch_oi, + ctrl_din_o => ctrl_din_oi, + ctrl_int_o => ctrl_int_o, + ctrl_maxepoch_o => ctrl_maxepoch_oi, + ctrl_offset_o => ctrl_offset_oi, + ctrl_rd_vec_o => ctrl_rd_vec_oi, + ctrl_set_starti_o => set_initi_oi, + ctrl_set_startj_o => set_initj_oi, + ctrl_start3_o => ctrl_start3_oi, + ctrl_start4_o => ctrl_start4_oi, + ctrl_start5_o => ctrl_start5_oi, + ctrl_start6_o => ctrl_start6_oi, + ctrl_starti_val_o => starti_val_oi, + ctrl_startj_val_o => startj_val_oi, + ctrl_stopi_val_o => stopi_val_oi, + ctrl_stopj_val_o => stopj_val_oi, + ctrl_thres_o => ctrl_thres_oi, + ctrl_wr_vec_o => ctrl_wr_vec_oi, + wb_ack_o => wb_ack_o, + wb_dat_o => wb_dat_o + ); + U_0 : p0300_m00022_s_v02_cal_y_fsm + PORT MAP ( + clk_i => clk_i, + cnti_end_i => cnti_end_oi, + cntj_end_i => cntj_end_oi, + ctrl_rdlat_i => ctrl_rdlat_oi, + ctrl_rdy7_i => ctrl_rdy7_oi, + ctrl_start_i => ctrl_start1_oi, + ctrl_thres_i => ctrl_thres_oi, + ctrl_wrlat_i => ctrl_wrlat_oi, + dbias_i => dbias_i, + ds_i => ds_i, + dw_i => dw_i, + rst_n_i => rst_n_oi, + cnteni_o => cnteni1_oi, + cntenj_o => cntenj1_oi, + ctrl_rdy_o => ctrl_rdy1_oi, + dout_o => dout1_o, + we_y_o => we_y1_o + ); + U_8 : p0300_m00023_s_v02_cal_w_fsm + PORT MAP ( + clk_i => clk_i, + cnti_end_i => cnti_end_oi, + cntj_end_i => cntj_end_oi, + ctrl_rdlat_i => ctrl_rdlat_oi, + ctrl_rdy7_i => ctrl_rdy7_oi, + ctrl_start_i => ctrl_start2_oi, + ctrl_wrlat_i => ctrl_wrlat_oi, + dbias_i => dbias_i, + ds_i => ds_i, + dt_i => dt_i, + dw_i => dw_i, + dy_i => dy_i, + rst_n_i => rst_n_oi, + cnteni_o => cnteni2_oi, + cntenj_o => cntenj2_oi, + ctrl_rdy_o => ctrl_rdy2_oi, + ctrl_wchgd_o => ctrl_wchgd_oi, + dout_o => dout2_o, + we_bias_o => we_bias2_o, + we_w_o => we_w2_o + ); + U_10 : p0300_m00024_s_v02_test_fsm + PORT MAP ( + clk_i => clk_i, + cnti_end_i => cnti_end_oi, + cntj_end_i => cntj_end_oi, + ctrl_rdlat_i => ctrl_rdlat_oi, + ctrl_rdy7_i => ctrl_rdy7_oi, + ctrl_start_i => ctrl_start4_oi, + ctrl_wrlat_i => ctrl_wrlat_oi, + ds_i => ds_i, + dt_i => dt_i, + dw_i => dw_i, + offset_i => ctrl_offset_oi, + rst_n_i => rst_n_oi, + cnteni_o => cnteni4_oi, + cntenj_o => cntenj4_oi, + ctrl_int_o => ctrl_int4_o, + ctrl_rdy_o => ctrl_rdy4_oi, + dout_o => dout4_o, + we_s_o => we_s4_o, + we_t_o => we_t4_o, + we_w_o => we_w4_o + ); + U_9 : p0300_m00025_s_v02_init_fsm + PORT MAP ( + clk_i => clk_i, + cnti_end_i => cnti_end_oi, + cntj_end_i => cntj_end_oi, + ctrl_bias_i => ctrl_bias_oi, + ctrl_rdlat_i => ctrl_rdlat_oi, + ctrl_rdy7_i => ctrl_rdy7_oi, + ctrl_start_i => ctrl_start3_oi, + ctrl_wrlat_i => ctrl_wrlat_oi, + rst_n_i => rst_n_oi, + cnteni_o => cnteni3_oi, + cntenj_o => cntenj3_oi, + ctrl_rdy_o => ctrl_rdy3_oi, + dout_o => dout3_o, + we_bias_o => we_bias3_o, + we_s_o => we_s3_o, + we_t_o => we_t3_o, + we_w_o => we_w3_o, + we_y_o => we_y3_o + ); + U_11 : p0300_m00026_s_v02_rd_wr_fsm + PORT MAP ( + clk_i => clk_i, + cnti_end_i => cnti_end_oi, + cntj_end_i => cntj_end_oi, + ctrl_din_i => ctrl_din_oi, + ctrl_rd_vec_i => ctrl_rd_vec_oi, + ctrl_rdlat_i => ctrl_rdlat_oi, + ctrl_rdy7_i => ctrl_rdy7_oi, + ctrl_start_i => ctrl_start5_oi, + ctrl_wr_vec_i => ctrl_wr_vec_oi, + ctrl_wrlat_i => ctrl_wrlat_oi, + dbias_i => dbias_i, + ds_i => ds_i, + dt_i => dt_i, + dw_i => dw_i, + dy_i => dy_i, + rst_n_i => rst_n_oi, + cnteni_o => cnteni5_oi, + cntenj_o => cntenj5_oi, + ctrl_complete_o => ctrl_complete_oi, + ctrl_dout_o => ctrl_dout_oi, + ctrl_dout_valid_o => ctrl_dout_valid_oi, + ctrl_rdy_o => ctrl_rdy5_oi, + dout_o => dout5_o, + we_bias_o => we_bias5_o, + we_s_o => we_s5_o, + we_t_o => we_t5_o, + we_w_o => we_w5_o, + we_y_o => we_y5_o + ); + U_12 : p0300_m00027_s_v01_train_fsm + PORT MAP ( + clk_i => clk_i, + cnti_rdy_i => cnti_rdy_oi, + cntj_rdy_i => cntj_rdy_oi, + ctrl_clear_epoch_i => ctrl_clear_epoch_oi, + ctrl_maxepoch_i => ctrl_maxepoch_oi, + ctrl_rdy1_i => ctrl_rdy1_oi, + ctrl_rdy2_i => ctrl_rdy2_oi, + ctrl_rdy7_i => ctrl_rdy7_oi, + ctrl_start_i => ctrl_start6_oi, + ctrl_wchgd_i => ctrl_wchgd_oi, + rst_n_i => rst_n_oi, + ctrl_epoch_o => ctrl_epoch_oi, + ctrl_int_o => ctrl_int6_o, + ctrl_not_rdy_o => ctrl_not_rdy6_oi, + ctrl_rdy_o => ctrl_rdy6_oi, + ctrl_start1_o => ctrl_start1_oi, + ctrl_start2_o => ctrl_start2_oi + ); + U_13 : p0300_m00028_s_v02_latency_fsm + PORT MAP ( + clk_i => clk_i, + dw_i => dw_i, + rst_n_i => rst_n_oi, + cnt_alllat_o => cnt_alllat_oi, + cnteni_o => cnteni7_oi, + cntenj_o => cntenj7_oi, + ctrl_memerr_o => ctrl_memerr_oi, + ctrl_rdlat_o => ctrl_rdlat_oi, + ctrl_rdy_o => ctrl_rdy7_oi, + ctrl_run_o => ctrl_run7_oi, + ctrl_wrlat_o => ctrl_wrlat_oi, + dout_o => dout7_o, + we_w_o => we_w7_o + ); + U_2 : p0300_m00033_s_v01_for_loop_memwi_fsm + PORT MAP ( + clk_i => clk_i, + cnten1_i => cnteni1_oi, + cnten2_i => cnteni2_oi, + cnten3_i => cnteni3_oi, + cnten4_i => cnteni4_oi, + cnten5_i => cnteni5_oi, + cnten7_i => cnteni7_oi, + rst_n_i => rst_n_oi, + set_init_i => set_initi_oi, + start_vali_i => starti_val_oi, + stop_vali_i => stopi_val_oi, + cnt_end_o => cnti_end_oi, + cnt_rdy_o => cnti_rdy_oi, + cnt_val_o => addr_i_o + ); + U_1 : p0300_m00034_s_v01_for_loop_memwj_fsm + PORT MAP ( + clk_i => clk_i, + cnten1_i => cntenj1_oi, + cnten2_i => cntenj2_oi, + cnten3_i => cntenj3_oi, + cnten4_i => cntenj4_oi, + cnten5_i => cntenj5_oi, + cnten7_i => cntenj7_oi, + rst_n_i => rst_n_oi, + set_init_i => set_initj_oi, + start_valj_i => startj_val_oi, + stop_valj_i => stopj_val_oi, + cnt_end_o => cntj_end_oi, + cnt_rdy_o => cntj_rdy_oi, + cnt_val_o => addr_j_o + ); + +END struct; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00021_s_v03_wishbone_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00021_s_v03_wishbone_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00021_s_v03_wishbone_fsm.vhd (revision 8) @@ -0,0 +1,867 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00021_s_v03_wishbone_fsm IS + PORT( + clk_i : IN std_logic; + ctrl_alllat_i : IN MEM_LAT_CNT_WIDTH_T; + ctrl_complete_i : IN std_logic; + ctrl_dout_i : IN DATA_T; + ctrl_dout_valid_i : IN std_logic; + ctrl_epoch_i : IN WB_DATA_WIDTH_T; + ctrl_int_test_i : IN std_logic; + ctrl_int_train_i : IN std_logic; + ctrl_memerr_i : IN std_logic; + ctrl_not_rdy6_i : IN std_logic; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T; + ctrl_rdy1_i : IN std_logic; + ctrl_rdy2_i : IN std_logic; + ctrl_rdy3_i : IN std_logic; + ctrl_rdy4_i : IN std_logic; + ctrl_rdy5_i : IN std_logic; + ctrl_rdy6_i : IN std_logic; + ctrl_run7_i : IN std_logic; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T; + rst_n_i : IN std_logic; + wb_adr_i : IN WB_ADDR_WIDTH_T; + wb_cyc_i : IN std_logic; + wb_dat_i : IN WB_DATA_WIDTH_T; + wb_stb_i : IN std_logic; + wb_we_i : IN std_logic; + ctrl_bias_o : OUT DATA_T; + ctrl_clear_epoch_o : OUT std_logic; + ctrl_din_o : OUT DATA_T; + ctrl_int_o : OUT std_logic; + ctrl_maxepoch_o : OUT WB_DATA_WIDTH_T; + ctrl_offset_o : OUT DATA_T; + ctrl_rd_vec_o : OUT MEM_WR_LINES_T; + ctrl_set_starti_o : OUT std_logic; + ctrl_set_startj_o : OUT std_logic; + ctrl_start3_o : OUT std_logic; + ctrl_start4_o : OUT std_logic; + ctrl_start5_o : OUT std_logic; + ctrl_start6_o : OUT std_logic; + ctrl_starti_val_o : OUT ADDRESS_S_T; + ctrl_startj_val_o : OUT ADDRESS_T_T; + ctrl_stopi_val_o : OUT ADDRESS_S_T; + ctrl_stopj_val_o : OUT ADDRESS_T_T; + ctrl_thres_o : OUT DATA_T; + ctrl_wr_vec_o : OUT MEM_WR_LINES_T; + wb_ack_o : OUT std_logic; + wb_dat_o : OUT WB_DATA_WIDTH_T + ); + +-- Declarations + +END p0300_m00021_s_v03_wishbone_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 3.0 2022/07/21 +-- - Delete alpha register and output +-- - Consolidate # cycles +-- Revision 2.0 2022/06/18 +-- - Introduce self-resets for status signals +-- - Remove states introduced for debugging +-- Revision 1.0 2022/06/11 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm OF p0300_m00021_s_v03_wishbone_fsm IS + + -- Architecture Declarations + SIGNAL ctrl_bias_reg : DATA_T; + SIGNAL ctrl_complete_reg : std_logic; + SIGNAL ctrl_din_reg : DATA_T; + SIGNAL ctrl_int_en_reg : std_logic; + SIGNAL ctrl_int_test_reg : std_logic; + SIGNAL ctrl_int_train_reg : std_logic; + SIGNAL ctrl_maxepoch_reg : WB_DATA_WIDTH_T; + SIGNAL ctrl_offset_reg : DATA_T; + SIGNAL ctrl_rd_vec_reg : MEM_WR_LINES_T; + SIGNAL ctrl_rdy_reg : std_logic; + SIGNAL ctrl_starti_val_reg : ADDRESS_S_T; + SIGNAL ctrl_startj_val_reg : ADDRESS_T_T; + SIGNAL ctrl_stat_a_reg : DATA_T; + SIGNAL ctrl_stopi_val_reg : ADDRESS_S_T; + SIGNAL ctrl_stopj_val_reg : ADDRESS_T_T; + SIGNAL ctrl_thres_reg : DATA_T; + SIGNAL ctrl_wr_vec_reg : MEM_WR_LINES_T; + SIGNAL wb_adr_reg : WB_ADDR_WIDTH_T; + SIGNAL wb_cyc_reg : std_logic; + SIGNAL wb_dat_reg : WB_DATA_WIDTH_T; + SIGNAL wb_stb_reg : std_logic; + SIGNAL wb_we_reg : std_logic; + SIGNAL zero_net_addrs : ADDRESS_S_ZERO_T; + SIGNAL zero_net_addrt : ADDRESS_T_ZERO_T; + + TYPE STATE_TYPE IS ( + S03, + S01, + S04, + S06, + S07, + S08, + S09, + S10, + S11, + S12, + S13, + S17, + S18, + S19, + S20, + S21, + S22, + S23, + S24, + S25, + S26, + S27, + S28, + S29, + S30, + S31, + S32, + S33, + S34, + S35, + S36, + S37, + S38, + S39, + S40, + S41, + S00, + S46, + S47, + S02, + S48, + S14, + S15, + S01a + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + ctrl_bias_reg <= (others => '0'); + ctrl_complete_reg <= '0'; + ctrl_din_reg <= (others => '0'); + ctrl_int_en_reg <= '0'; + ctrl_int_test_reg <= '0'; + ctrl_int_train_reg <= '0'; + ctrl_maxepoch_reg <= (others => '0'); + ctrl_offset_reg <= (others => '0'); + ctrl_rd_vec_reg <= (others => '0'); + ctrl_rdy_reg <= '0'; + ctrl_starti_val_reg <= (others => '0'); + ctrl_startj_val_reg <= (others => '0'); + ctrl_stat_a_reg <= (others => '0'); + ctrl_stopi_val_reg <= zero_net_addrs & '1'; + ctrl_stopj_val_reg <= zero_net_addrt & '1'; + ctrl_thres_reg <= (others => '0'); + ctrl_wr_vec_reg <= (others => '0'); + wb_adr_reg <= (others => '0'); + wb_cyc_reg <= '0'; + wb_dat_reg <= (others => '0'); + wb_stb_reg <= '0'; + wb_we_reg <= '0'; + ELSE + current_state <= next_state; + -- Default Assignment To Internals + ctrl_bias_reg <= ctrl_bias_reg; + ctrl_complete_reg <= ctrl_complete_reg OR ctrl_complete_i; + ctrl_din_reg <= ctrl_din_reg; + ctrl_int_en_reg <= ctrl_int_en_reg; + ctrl_int_test_reg <= ctrl_int_test_reg OR ctrl_int_test_i; + ctrl_int_train_reg <= ctrl_int_train_reg OR ctrl_int_train_i; + ctrl_maxepoch_reg <= ctrl_maxepoch_reg; + ctrl_offset_reg <= ctrl_offset_reg; + ctrl_rd_vec_reg <= ctrl_rd_vec_reg; + ctrl_rdy_reg <= ctrl_rdy1_i AND ctrl_rdy2_i AND ctrl_rdy3_i AND ctrl_rdy4_i AND ctrl_rdy5_i AND ctrl_rdy6_i; + ctrl_starti_val_reg <= ctrl_starti_val_reg; + ctrl_startj_val_reg <= ctrl_startj_val_reg; + ctrl_stat_a_reg <= ctrl_stat_a_reg; + ctrl_stopi_val_reg <= ctrl_stopi_val_reg; + ctrl_stopj_val_reg <= ctrl_stopj_val_reg; + ctrl_thres_reg <= ctrl_thres_reg; + ctrl_wr_vec_reg <= ctrl_wr_vec_reg; + wb_adr_reg <= wb_adr_i; + wb_cyc_reg <= wb_cyc_i; + wb_dat_reg <= wb_dat_i; + wb_stb_reg <= wb_stb_i; + wb_we_reg <= wb_we_i; + + -- Combined Actions + CASE current_state IS + -- READ Status A + WHEN S03 => + ctrl_complete_reg <= ctrl_complete_i OR ( ctrl_complete_reg AND ( NOT ( ctrl_stat_a_reg (STAT_RD_WR_COMPLETE) ) ) ); + ctrl_int_test_reg <= ctrl_int_test_i OR ( ctrl_int_test_reg AND ( NOT ( ctrl_stat_a_reg (STAT_INT_TEST) ) ) ); + ctrl_int_train_reg <= ctrl_int_train_i OR ( ctrl_int_train_reg AND ( NOT ( ctrl_stat_a_reg (STAT_INT_TRAIN) ) ) ); + -- Wait for + -- transfer/phase + WHEN S01 => + ctrl_stat_a_reg (STAT_RDY) <= ctrl_rdy_reg; + ctrl_stat_a_reg (STAT_LAT_RUN) <= ctrl_run7_i; + ctrl_stat_a_reg (STAT_NOT_RDY) <= ctrl_not_rdy6_i; + ctrl_stat_a_reg (STAT_INT_EN) <= ctrl_int_en_reg; + ctrl_stat_a_reg (STAT_MEMERR) <= ctrl_memerr_i; + ctrl_stat_a_reg (STAT_RD_WR_COMPLETE) <= ctrl_complete_reg AND ctrl_rdy_reg; + ctrl_stat_a_reg (STAT_INT_TEST) <= ctrl_int_test_reg AND ctrl_rdy_reg; + ctrl_stat_a_reg (STAT_INT_TRAIN) <= ctrl_int_train_reg AND ctrl_rdy_reg; + -- WRITE Threshold + -- register + WHEN S04 => + ctrl_thres_reg <= wb_dat_reg (DATA_N); + -- WRITE Bias + -- register + WHEN S08 => + ctrl_bias_reg <= wb_dat_reg (DATA_N); + -- WRITE Offset + -- register + WHEN S10 => + ctrl_offset_reg <= wb_dat_reg (DATA_N); + -- WRITE Maxepochs + -- register + WHEN S12 => + ctrl_maxepoch_reg <= wb_dat_reg; + -- WRITE Start i + -- register + WHEN S18 => + ctrl_starti_val_reg <= wb_dat_reg (ADDRESS_S_N); + -- WRITE Start j + -- register + WHEN S20 => + ctrl_startj_val_reg <= wb_dat_reg (ADDRESS_T_N); + -- WRITE Stop i + -- register + WHEN S22 => + ctrl_stopi_val_reg <= wb_dat_reg (ADDRESS_S_N); + -- WRITE Stop j + -- register + WHEN S24 => + ctrl_stopj_val_reg <= wb_dat_reg (ADDRESS_T_N); + -- WRITE SMEM + WHEN S32 => + ctrl_rd_vec_reg <= "00001"; + ctrl_wr_vec_reg <= "00001"; + ctrl_din_reg <= wb_dat_reg (DATA_N); + -- WRITE TMEM + WHEN S33 => + ctrl_rd_vec_reg <= "00010"; + ctrl_wr_vec_reg <= "00010"; + ctrl_din_reg <= wb_dat_reg (DATA_N); + -- WRITE WMEM + WHEN S34 => + ctrl_rd_vec_reg <= "00100"; + ctrl_wr_vec_reg <= "00100"; + ctrl_din_reg <= wb_dat_reg (DATA_N); + -- WRITE YMEM + WHEN S35 => + ctrl_rd_vec_reg <= "01000"; + ctrl_wr_vec_reg <= "01000"; + ctrl_din_reg <= wb_dat_reg (DATA_N); + -- WRITE BIASMEM + WHEN S36 => + ctrl_rd_vec_reg <= "10000"; + ctrl_wr_vec_reg <= "10000"; + ctrl_din_reg <= wb_dat_reg (DATA_N); + -- READ SMEM + WHEN S37 => + ctrl_rd_vec_reg <= "00001"; + -- READ TMEM + WHEN S38 => + ctrl_rd_vec_reg <= "00010"; + -- READ WMEM + WHEN S39 => + ctrl_rd_vec_reg <= "00100"; + -- READ YMEM + WHEN S40 => + ctrl_rd_vec_reg <= "01000"; + -- READ BIASMEM + WHEN S41 => + ctrl_rd_vec_reg <= "10000"; + -- WRITE Status A + WHEN S02 => + ctrl_int_en_reg <= wb_dat_reg (STAT_INT_EN); + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + ctrl_rdy3_i, + ctrl_rdy4_i, + ctrl_rdy5_i, + current_state, + wb_adr_reg, + wb_cyc_reg, + wb_stb_reg, + wb_we_reg + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- READ Status A + WHEN S03 => + next_state <= S01a; + -- Wait for + -- transfer/phase + WHEN S01 => + IF (unsigned (wb_adr_reg) = WB_STAT_A AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S03; + ELSIF (unsigned (wb_adr_reg) = WB_THRES AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S06; + ELSIF (unsigned (wb_adr_reg) = WB_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S07; + ELSIF (unsigned (wb_adr_reg) = WB_OFFSET AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S09; + ELSIF (unsigned (wb_adr_reg) = WB_MAXEPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S11; + ELSIF (unsigned (wb_adr_reg) = WB_IMAX AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S13; + ELSIF (unsigned (wb_adr_reg) = WB_STARTI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S17; + ELSIF (unsigned (wb_adr_reg) = WB_STOPI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S21; + ELSIF (unsigned (wb_adr_reg) = WB_STARTJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S19; + ELSIF (unsigned (wb_adr_reg) = WB_STOPJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S23; + ELSIF (unsigned (wb_adr_reg) = WB_EPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S25; + ELSIF (unsigned (wb_adr_reg) = WB_WRLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S26; + ELSIF (unsigned (wb_adr_reg) = WB_RDLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S27; + ELSIF (unsigned (wb_adr_reg) = WB_ALLLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S28; + ELSIF (unsigned (wb_adr_reg) = WB_START5_S AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S37; + ELSIF (unsigned (wb_adr_reg) = WB_START5_T AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S38; + ELSIF (unsigned (wb_adr_reg) = WB_START5_W AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S39; + ELSIF (unsigned (wb_adr_reg) = WB_START5_Y AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S40; + ELSIF (unsigned (wb_adr_reg) = WB_START5_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S41; + ELSIF (unsigned (wb_adr_reg) = WB_THRES AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S04; + ELSIF (unsigned (wb_adr_reg) = WB_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S08; + ELSIF (unsigned (wb_adr_reg) = WB_OFFSET AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S10; + ELSIF (unsigned (wb_adr_reg) = WB_MAXEPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S12; + ELSIF (unsigned (wb_adr_reg) = WB_STARTI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S18; + ELSIF (unsigned (wb_adr_reg) = WB_STOPI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S22; + ELSIF (unsigned (wb_adr_reg) = WB_STARTJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S20; + ELSIF (unsigned (wb_adr_reg) = WB_STOPJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S24; + ELSIF (unsigned (wb_adr_reg) = WB_START3 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S29; + ELSIF (unsigned (wb_adr_reg) = WB_START4 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S30; + ELSIF (unsigned (wb_adr_reg) = WB_START5_S AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S32; + ELSIF (unsigned (wb_adr_reg) = WB_START5_T AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S33; + ELSIF (unsigned (wb_adr_reg) = WB_START5_W AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S34; + ELSIF (unsigned (wb_adr_reg) = WB_START5_Y AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S35; + ELSIF (unsigned (wb_adr_reg) = WB_START5_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S36; + ELSIF (unsigned (wb_adr_reg) = WB_START6 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S31; + ELSIF (unsigned (wb_adr_reg) = WB_STAT_A AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN + next_state <= S02; + ELSIF (unsigned (wb_adr_reg) = WB_JMAX AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S14; + ELSIF (unsigned (wb_adr_reg) = WB_MEMDATA_WIDTH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN + next_state <= S15; + ELSIF (wb_stb_reg = '1' AND wb_cyc_reg = '1') THEN + next_state <= S48; + ELSE + next_state <= S01; + END IF; + -- WRITE Threshold + -- register + WHEN S04 => + next_state <= S01a; + -- READ Threshold + -- register + WHEN S06 => + next_state <= S01a; + -- READ Bias + -- register + WHEN S07 => + next_state <= S01a; + -- WRITE Bias + -- register + WHEN S08 => + next_state <= S01a; + -- READ Offset + -- register + WHEN S09 => + next_state <= S01a; + -- WRITE Offset + -- register + WHEN S10 => + next_state <= S01a; + -- READ Maxepochs + -- register + WHEN S11 => + next_state <= S01a; + -- WRITE Maxepochs + -- register + WHEN S12 => + next_state <= S01a; + -- READ maximum + -- rows i + WHEN S13 => + next_state <= S01a; + -- READ Start i + -- register + WHEN S17 => + next_state <= S01a; + -- WRITE Start i + -- register + WHEN S18 => + next_state <= S01a; + -- READ Start j + -- register + WHEN S19 => + next_state <= S01a; + -- WRITE Start j + -- register + WHEN S20 => + next_state <= S01a; + -- READ Stop i + -- register + WHEN S21 => + next_state <= S01a; + -- WRITE Stop i + -- register + WHEN S22 => + next_state <= S01a; + -- READ Stop j + -- register + WHEN S23 => + next_state <= S01a; + -- WRITE Stop j + -- register + WHEN S24 => + next_state <= S01a; + -- READ Epochs + -- register + WHEN S25 => + next_state <= S01a; + -- READ coded + -- WR Lat + -- register + WHEN S26 => + next_state <= S01a; + -- READ coded + -- RD Lat + -- register + WHEN S27 => + next_state <= S01a; + -- READ decimal + -- Latency register + WHEN S28 => + next_state <= S01a; + -- Start INIT + WHEN S29 => + IF (ctrl_rdy3_i = '0') THEN + next_state <= S01a; + ELSE + next_state <= S29; + END IF; + -- Start TEST + WHEN S30 => + IF (ctrl_rdy4_i = '0') THEN + next_state <= S01a; + ELSE + next_state <= S30; + END IF; + -- Start TRAIN + WHEN S31 => + next_state <= S01a; + -- WRITE SMEM + WHEN S32 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S47; + END IF; + -- WRITE TMEM + WHEN S33 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S47; + END IF; + -- WRITE WMEM + WHEN S34 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S47; + END IF; + -- WRITE YMEM + WHEN S35 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S47; + END IF; + -- WRITE BIASMEM + WHEN S36 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S47; + END IF; + -- READ SMEM + WHEN S37 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S46; + END IF; + -- READ TMEM + WHEN S38 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S46; + END IF; + -- READ WMEM + WHEN S39 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S46; + END IF; + -- READ YMEM + WHEN S40 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S46; + END IF; + -- READ BIASMEM + WHEN S41 => + IF (ctrl_rdy5_i = '0') THEN + next_state <= S46; + END IF; + -- Reset state + WHEN S00 => + next_state <= S01; + -- READ xMEM + WHEN S46 => + IF (ctrl_rdy5_i = '1') THEN + next_state <= S01a; + ELSE + next_state <= S46; + END IF; + -- WRITE xMEM + WHEN S47 => + IF (ctrl_rdy5_i = '1') THEN + next_state <= S01a; + ELSE + next_state <= S47; + END IF; + -- WRITE Status A + WHEN S02 => + next_state <= S01a; + -- Dummy + -- READ / WRITE + WHEN S48 => + next_state <= S01a; + -- READ maximum + -- colums j + WHEN S14 => + next_state <= S01a; + -- READ memory + -- data width + WHEN S15 => + next_state <= S01a; + -- Waite State + WHEN S01a => + next_state <= S01; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + ctrl_alllat_i, + ctrl_bias_reg, + ctrl_din_reg, + ctrl_dout_i, + ctrl_epoch_i, + ctrl_int_en_reg, + ctrl_int_test_reg, + ctrl_int_train_reg, + ctrl_maxepoch_reg, + ctrl_offset_reg, + ctrl_rd_vec_reg, + ctrl_rdlat_i, + ctrl_rdy3_i, + ctrl_rdy4_i, + ctrl_rdy5_i, + ctrl_starti_val_reg, + ctrl_startj_val_reg, + ctrl_stat_a_reg, + ctrl_stopi_val_reg, + ctrl_stopj_val_reg, + ctrl_thres_reg, + ctrl_wr_vec_reg, + ctrl_wrlat_i, + current_state, + wb_cyc_i, + wb_dat_reg, + wb_stb_i + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + ctrl_bias_o <= ctrl_bias_reg; + ctrl_clear_epoch_o <= '0'; + ctrl_din_o <= ctrl_din_reg; + ctrl_int_o <= ctrl_int_en_reg AND (ctrl_int_train_reg OR ctrl_int_test_reg); + ctrl_maxepoch_o <= ctrl_maxepoch_reg; + ctrl_offset_o <= ctrl_offset_reg; + ctrl_rd_vec_o <= ctrl_rd_vec_reg; + ctrl_set_starti_o <= '0'; + ctrl_set_startj_o <= '0'; + ctrl_start3_o <= '0'; + ctrl_start4_o <= '0'; + ctrl_start5_o <= '0'; + ctrl_start6_o <= '0'; + ctrl_starti_val_o <= ctrl_starti_val_reg; + ctrl_startj_val_o <= ctrl_startj_val_reg; + ctrl_stopi_val_o <= ctrl_stopi_val_reg; + ctrl_stopj_val_o <= ctrl_stopj_val_reg; + ctrl_thres_o <= ctrl_thres_reg; + ctrl_wr_vec_o <= ctrl_wr_vec_reg; + wb_ack_o <= '0'; + wb_dat_o <= (others => '0'); + -- Default Assignment To Internals + zero_net_addrs <= (others => '0'); + zero_net_addrt <= (others => '0'); + + -- Combined Actions + CASE current_state IS + -- READ Status A + WHEN S03 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stat_a_reg ) )), WB_DATA_WIDTH ) ); + -- WRITE Threshold + -- register + WHEN S04 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- READ Threshold + -- register + WHEN S06 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_thres_reg ) )), WB_DATA_WIDTH ) ); + -- READ Bias + -- register + WHEN S07 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_bias_reg ) )), WB_DATA_WIDTH ) ); + -- WRITE Bias + -- register + WHEN S08 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- READ Offset + -- register + WHEN S09 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_offset_reg ) )), WB_DATA_WIDTH ) ); + -- WRITE Offset + -- register + WHEN S10 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- READ Maxepochs + -- register + WHEN S11 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= ctrl_maxepoch_reg; + -- WRITE Maxepochs + -- register + WHEN S12 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- READ maximum + -- rows i + WHEN S13 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( I_MAX ) )), WB_DATA_WIDTH ) ); + -- READ Start i + -- register + WHEN S17 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_starti_val_reg ) )), WB_DATA_WIDTH ) ); + -- WRITE Start i + -- register + WHEN S18 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- READ Start j + -- register + WHEN S19 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_startj_val_reg ) )), WB_DATA_WIDTH ) ); + -- WRITE Start j + -- register + WHEN S20 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- READ Stop i + -- register + WHEN S21 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stopi_val_reg ) )), WB_DATA_WIDTH ) ); + -- WRITE Stop i + -- register + WHEN S22 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- READ Stop j + -- register + WHEN S23 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stopj_val_reg ) )), WB_DATA_WIDTH ) ); + -- WRITE Stop j + -- register + WHEN S24 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- READ Epochs + -- register + WHEN S25 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= ctrl_epoch_i; + -- READ coded + -- WR Lat + -- register + WHEN S26 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_wrlat_i ) )), WB_DATA_WIDTH ) ); + -- READ coded + -- RD Lat + -- register + WHEN S27 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_rdlat_i ) )), WB_DATA_WIDTH ) ); + -- READ decimal + -- Latency register + WHEN S28 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_alllat_i ) )), WB_DATA_WIDTH ) ); + -- Start INIT + WHEN S29 => + wb_ack_o <= NOT ctrl_rdy3_i AND wb_stb_i AND wb_cyc_i; + ctrl_start3_o <= '1'; + -- Start TEST + WHEN S30 => + wb_ack_o <= NOT ctrl_rdy4_i AND wb_stb_i AND wb_cyc_i; + ctrl_start4_o <= '1'; + -- Start TRAIN + WHEN S31 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + ctrl_start6_o <= '1'; + ctrl_clear_epoch_o <= wb_dat_reg (0); + -- WRITE SMEM + WHEN S32 => + ctrl_start5_o <= '1'; + -- WRITE TMEM + WHEN S33 => + ctrl_start5_o <= '1'; + -- WRITE WMEM + WHEN S34 => + ctrl_start5_o <= '1'; + -- WRITE YMEM + WHEN S35 => + ctrl_start5_o <= '1'; + -- WRITE BIASMEM + WHEN S36 => + ctrl_start5_o <= '1'; + -- READ SMEM + WHEN S37 => + ctrl_start5_o <= '1'; + -- READ TMEM + WHEN S38 => + ctrl_start5_o <= '1'; + -- READ WMEM + WHEN S39 => + ctrl_start5_o <= '1'; + -- READ YMEM + WHEN S40 => + ctrl_start5_o <= '1'; + -- READ BIASMEM + WHEN S41 => + ctrl_start5_o <= '1'; + -- READ xMEM + WHEN S46 => + wb_ack_o <= ctrl_rdy5_i AND wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_signed ( (conv_integer ( signed ( ctrl_dout_i ) )), WB_DATA_WIDTH ) ); + -- WRITE xMEM + WHEN S47 => + wb_ack_o <= ctrl_rdy5_i AND wb_stb_i AND wb_cyc_i; + -- WRITE Status A + WHEN S02 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + -- Dummy + -- READ / WRITE + WHEN S48 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= (others => '0'); + -- READ maximum + -- colums j + WHEN S14 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( J_MAX ) )), WB_DATA_WIDTH ) ); + -- READ memory + -- data width + WHEN S15 => + wb_ack_o <= wb_stb_i AND wb_cyc_i; + wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( DATA_WIDTH ) )), WB_DATA_WIDTH ) ); + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00022_s_v02_cal_y_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00022_s_v02_cal_y_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00022_s_v02_cal_y_fsm.vhd (revision 8) @@ -0,0 +1,375 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00022_s_v02_cal_y_fsm IS + PORT( + clk_i : IN std_logic; + cnti_end_i : IN std_logic; + cntj_end_i : IN std_logic; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T; + ctrl_rdy7_i : IN std_logic; + ctrl_start_i : IN std_logic; + ctrl_thres_i : IN DATA_T; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T; + dbias_i : IN DATA_T; + ds_i : IN DATA_T; + dw_i : IN DATA_T; + rst_n_i : IN std_logic; + cnteni_o : OUT std_logic; + cntenj_o : OUT std_logic; + ctrl_rdy_o : OUT std_logic; + dout_o : OUT DATA_T; + we_y_o : OUT std_logic + ); + +-- Declarations + +END p0300_m00022_s_v02_cal_y_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 2.0 2022/07/04 +-- - Introduced latency for write +-- Revision 1.0 2022/06/25 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm OF p0300_m00022_s_v02_cal_y_fsm IS + + -- Architecture Declarations + SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL ctrl_start_reg : std_logic; + SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL dbias_reg : DATA_T; + SIGNAL dw_reg : DATA_T; + SIGNAL y_inj_reg : DATA_T; + + TYPE STATE_TYPE IS ( + S00, + S03, + S02, + S05, + S04, + S07, + S08, + S10, + S11, + S12, + S13, + S01, + S16, + S06, + S15, + S09, + S14 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + ctrl_rdlat_reg <= (others => '0'); + ctrl_start_reg <= '0'; + ctrl_wrlat_reg <= (others => '0'); + dbias_reg <= (others => '0'); + dw_reg <= (others => '0'); + y_inj_reg <= (others => '0'); + ELSE + current_state <= next_state; + -- Default Assignment To Internals + ctrl_rdlat_reg <= ctrl_rdlat_reg; + ctrl_start_reg <= ctrl_start_i; + ctrl_wrlat_reg <= ctrl_wrlat_reg; + dbias_reg <= dbias_i; + dw_reg <= dw_i; + y_inj_reg <= y_inj_reg; + + -- Combined Actions + CASE current_state IS + -- ADD if + -- ds GT 0 + WHEN S03 => + --y_inj_reg <= signed (y_inj_reg) + signed (dw_i); + y_inj_reg <= signed (y_inj_reg) + signed (dw_reg); + -- Replacement of multiplication. + -- y_inj calculation and increment + -- i-address. + WHEN S02 => + ctrl_rdlat_reg <= ctrl_rdlat_i; + -- SUB if + -- ds LT 0 + WHEN S05 => + --y_inj_reg <= signed (y_inj_reg) - signed (dw_i); + y_inj_reg <= signed (y_inj_reg) - signed (dw_reg); + -- Dummy cycles. + -- Loop path for + -- next y_inj-value.. + WHEN S07 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Update y_inj-value + -- with bias + WHEN S08 => + --y_inj_reg <= (signed (y_inj_reg)) + (signed (dbias_i)); + y_inj_reg <= (signed (y_inj_reg)) + (signed (dbias_reg)); + -- Replacement of + -- multiplication. + -- y calculation. + WHEN S10 => + ctrl_wrlat_reg <= ctrl_wrlat_i; + -- Larency counter. + -- Return path last j + WHEN S16 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Dummy cycles to + -- equalize latency. + WHEN S06 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Increment + -- j-address + WHEN S15 => + y_inj_reg <= (others => '0'); + ctrl_rdlat_reg <= ctrl_rdlat_i; + -- Dummy cycles to + -- equalize latency. + WHEN S09 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Dummy cycles to + -- equalize latency. + WHEN S14 => + ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + cnti_end_i, + cntj_end_i, + ctrl_rdlat_reg, + ctrl_rdy7_i, + ctrl_start_reg, + ctrl_thres_i, + ctrl_wrlat_reg, + current_state, + ds_i, + y_inj_reg + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Reset state + WHEN S00 => + IF (ctrl_rdy7_i = '1') THEN + next_state <= S01; + ELSE + next_state <= S00; + END IF; + -- ADD if + -- ds GT 0 + WHEN S03 => + next_state <= S06; + -- Replacement of multiplication. + -- y_inj calculation and increment + -- i-address. + WHEN S02 => + IF (cnti_end_i = '1') THEN + next_state <= S08; + ELSIF (signed (ds_i) > 0) THEN + next_state <= S03; + ELSIF (signed (ds_i) < 0) THEN + next_state <= S05; + ELSE + next_state <= S04; + END IF; + -- SUB if + -- ds LT 0 + WHEN S05 => + next_state <= S06; + -- No function + -- if ds EQ 0 + WHEN S04 => + next_state <= S06; + -- Dummy cycles. + -- Loop path for + -- next y_inj-value.. + WHEN S07 => + IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN + next_state <= S02; + ELSE + next_state <= S07; + END IF; + -- Update y_inj-value + -- with bias + WHEN S08 => + next_state <= S09; + -- Replacement of + -- multiplication. + -- y calculation. + WHEN S10 => + IF (signed (y_inj_reg) < signed (ctrl_thres_i)) THEN + next_state <= S11; + ELSIF (signed (y_inj_reg) > signed (ctrl_thres_i)) THEN + next_state <= S13; + ELSE + next_state <= S12; + END IF; + -- ADD if + -- y_inj GT thres + WHEN S11 => + next_state <= S14; + -- No function if + -- y_inj EQ thres + WHEN S12 => + next_state <= S14; + -- SUB if + -- y_inj LT thres + WHEN S13 => + next_state <= S14; + -- Wait for next + -- calculation of + -- y-values + WHEN S01 => + IF (ctrl_start_reg = '1') THEN + next_state <= S02; + ELSE + next_state <= S01; + END IF; + -- Larency counter. + -- Return path last j + WHEN S16 => + IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN + next_state <= S01; + ELSE + next_state <= S16; + END IF; + -- Dummy cycles to + -- equalize latency. + WHEN S06 => + IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN + next_state <= S02; + ELSE + next_state <= S06; + END IF; + -- Increment + -- j-address + WHEN S15 => + IF (cntj_end_i = '1') THEN + next_state <= S16; + ELSE + next_state <= S07; + END IF; + -- Dummy cycles to + -- equalize latency. + WHEN S09 => + IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN + next_state <= S10; + ELSE + next_state <= S09; + END IF; + -- Dummy cycles to + -- equalize latency. + WHEN S14 => + IF (unsigned ( ctrl_wrlat_reg ) <= 3) THEN + next_state <= S15; + ELSE + next_state <= S14; + END IF; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + current_state + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + cnteni_o <= '0'; + cntenj_o <= '0'; + ctrl_rdy_o <= '0'; + dout_o <= (others => '0'); + we_y_o <= '0'; + + -- Combined Actions + CASE current_state IS + -- Replacement of multiplication. + -- y_inj calculation and increment + -- i-address. + WHEN S02 => + cnteni_o <= '1'; + -- ADD if + -- y_inj GT thres + WHEN S11 => + dout_o <= (others => '1'); + we_y_o <= '1'; + -- No function if + -- y_inj EQ thres + WHEN S12 => + dout_o <= (others => '0'); + we_y_o <= '1'; + -- SUB if + -- y_inj LT thres + WHEN S13 => + dout_o(0) <= '1'; + we_y_o <= '1'; + -- Wait for next + -- calculation of + -- y-values + WHEN S01 => + ctrl_rdy_o <= '1'; + -- Increment + -- j-address + WHEN S15 => + cntenj_o <= '1'; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00023_s_v02_cal_w_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00023_s_v02_cal_w_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00023_s_v02_cal_w_fsm.vhd (revision 8) @@ -0,0 +1,367 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00023_s_v02_cal_w_fsm IS + PORT( + clk_i : IN std_logic; + cnti_end_i : IN std_logic; + cntj_end_i : IN std_logic; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T; + ctrl_rdy7_i : IN std_logic; + ctrl_start_i : IN std_logic; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T; + dbias_i : IN DATA_T; + ds_i : IN DATA_T; + dt_i : IN DATA_T; + dw_i : IN DATA_T; + dy_i : IN DATA_T; + rst_n_i : IN std_logic; + cnteni_o : OUT std_logic; + cntenj_o : OUT std_logic; + ctrl_rdy_o : OUT std_logic; + ctrl_wchgd_o : OUT std_logic; + dout_o : OUT DATA_T; + we_bias_o : OUT std_logic; + we_w_o : OUT std_logic + ); + +-- Declarations + +END p0300_m00023_s_v02_cal_w_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 2.0 2022/07/02 +-- - Introduced latency for write +-- Revision 1.0 2022/06/29 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm OF p0300_m00023_s_v02_cal_w_fsm IS + + -- Architecture Declarations + SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL ctrl_start_reg : std_logic; + SIGNAL ctrl_wchgd_reg : std_logic; + SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL dbias_reg : DATA_T; + SIGNAL dt_reg : DATA_T; + SIGNAL dw_reg : DATA_T; + + TYPE STATE_TYPE IS ( + S00, + S14, + S06, + S05, + S08, + S07, + S11, + S13, + S03, + S12, + S04, + S15, + S01, + S02, + S10, + S09 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + ctrl_rdlat_reg <= (others => '0'); + ctrl_start_reg <= '0'; + ctrl_wchgd_reg <= '0'; + ctrl_wrlat_reg <= (others => '0'); + dbias_reg <= (others => '0'); + dt_reg <= (others => '0'); + dw_reg <= (others => '0'); + ELSE + current_state <= next_state; + -- Default Assignment To Internals + ctrl_rdlat_reg <= ctrl_rdlat_reg; + ctrl_start_reg <= ctrl_start_i; + ctrl_wchgd_reg <= ctrl_wchgd_reg; + ctrl_wrlat_reg <= ctrl_wrlat_reg; + dbias_reg <= dbias_i; + dt_reg <= dt_i; + dw_reg <= dw_i; + + -- Combined Actions + CASE current_state IS + -- Larency counter. + -- Loop path for + -- next w-/bias-value.. + WHEN S14 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Replacement of + -- multiplication. + -- W matrix calculation. + WHEN S05 => + ctrl_rdlat_reg <= ctrl_rdlat_i; + ctrl_wrlat_reg <= ctrl_wrlat_i; + -- Larency counter. + -- Loop path for + -- next w-value. + WHEN S11 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Increment + -- j-address + WHEN S13 => + ctrl_rdlat_reg <= ctrl_rdlat_i; + -- w-value + -- changed. + -- Last i + WHEN S12 => + ctrl_wchgd_reg <= '1'; + -- Larency counter. + -- Return path last j + WHEN S15 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Reset "w-value + -- changed" + WHEN S02 => + ctrl_wchgd_reg <= '0'; + -- Dummy cycles to + -- equalize latency. + WHEN S09 => + ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + cnti_end_i, + cntj_end_i, + ctrl_rdlat_reg, + ctrl_rdy7_i, + ctrl_start_reg, + ctrl_wrlat_reg, + current_state, + ds_i, + dt_i, + dy_i + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Reset state + WHEN S00 => + IF (ctrl_rdy7_i = '1') THEN + next_state <= S01; + ELSE + next_state <= S00; + END IF; + -- Larency counter. + -- Loop path for + -- next w-/bias-value.. + WHEN S14 => + IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN + next_state <= S03; + ELSE + next_state <= S14; + END IF; + -- ADD if + -- ds GT 0 + WHEN S06 => + next_state <= S09; + -- Replacement of + -- multiplication. + -- W matrix calculation. + WHEN S05 => + IF (signed (ds_i) > 0) THEN + next_state <= S06; + ELSIF (signed (ds_i) < 0) THEN + next_state <= S08; + ELSE + next_state <= S07; + END IF; + -- SUB if + -- ds LT 0 + WHEN S08 => + next_state <= S09; + -- No function + -- if ds EQ 0 + WHEN S07 => + next_state <= S09; + -- Larency counter. + -- Loop path for + -- next w-value. + WHEN S11 => + IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN + next_state <= S05; + ELSE + next_state <= S11; + END IF; + -- Increment + -- j-address + WHEN S13 => + IF (cntj_end_i = '1') THEN + next_state <= S15; + ELSE + next_state <= S14; + END IF; + -- Test for + -- dt EQ dy + WHEN S03 => + IF (dt_i = dy_i) THEN + next_state <= S13; + ELSE + next_state <= S04; + END IF; + -- w-value + -- changed. + -- Last i + WHEN S12 => + next_state <= S13; + -- Compute + -- new bias + WHEN S04 => + next_state <= S05; + -- Larency counter. + -- Return path last j + WHEN S15 => + IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN + next_state <= S01; + ELSE + next_state <= S15; + END IF; + -- Wait for next + -- calculation of + -- w-/bias-values + WHEN S01 => + IF (ctrl_start_reg = '1') THEN + next_state <= S02; + ELSE + next_state <= S01; + END IF; + -- Reset "w-value + -- changed" + WHEN S02 => + next_state <= S03; + -- Increment + -- i-address + WHEN S10 => + IF (cnti_end_i = '1') THEN + next_state <= S12; + ELSE + next_state <= S11; + END IF; + -- Dummy cycles to + -- equalize latency. + WHEN S09 => + IF (unsigned ( ctrl_wrlat_reg ) <= 3) THEN + next_state <= S10; + ELSE + next_state <= S09; + END IF; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + ctrl_wchgd_reg, + current_state, + dbias_reg, + dt_reg, + dw_reg + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + cnteni_o <= '0'; + cntenj_o <= '0'; + ctrl_rdy_o <= '0'; + ctrl_wchgd_o <= ctrl_wchgd_reg; + dout_o <= (others => '0'); + we_bias_o <= '0'; + we_w_o <= '0'; + + -- Combined Actions + CASE current_state IS + -- ADD if + -- ds GT 0 + WHEN S06 => + --dout_o <= signed (dw_i) + signed (dt_i); + dout_o <= signed (dw_reg) + signed (dt_reg); + we_w_o <= '1'; + -- SUB if + -- ds LT 0 + WHEN S08 => + --dout_o <= signed (dw_i) - signed (dt_i); + dout_o <= signed (dw_reg) - signed (dt_reg); + we_w_o <= '1'; + -- Increment + -- j-address + WHEN S13 => + cntenj_o <= '1'; + -- Compute + -- new bias + WHEN S04 => + --dout_o <= signed (dbias_i) + signed (dt_i); + dout_o <= signed (dbias_reg) + signed (dt_reg); + we_bias_o <= '1'; + -- Wait for next + -- calculation of + -- w-/bias-values + WHEN S01 => + ctrl_rdy_o <= '1'; + -- Increment + -- i-address + WHEN S10 => + cnteni_o <= '1'; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00024_s_v02_test_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00024_s_v02_test_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00024_s_v02_test_fsm.vhd (revision 8) @@ -0,0 +1,361 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00024_s_v02_test_fsm IS + PORT( + clk_i : IN std_logic; + cnti_end_i : IN std_logic; + cntj_end_i : IN std_logic; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T; + ctrl_rdy7_i : IN std_logic; + ctrl_start_i : IN std_logic; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T; + ds_i : IN DATA_T; + dt_i : IN DATA_T; + dw_i : IN DATA_T; + offset_i : IN DATA_T; + rst_n_i : IN std_logic; + cnteni_o : OUT std_logic; + cntenj_o : OUT std_logic; + ctrl_int_o : OUT std_logic; + ctrl_rdy_o : OUT std_logic; + dout_o : OUT DATA_T; + we_s_o : OUT std_logic; + we_t_o : OUT std_logic; + we_w_o : OUT std_logic + ); + +-- Declarations + +END p0300_m00024_s_v02_test_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 2.0 2022/07/02 +-- - Introduced latency for write +-- Revision 1.0 2022/06/17 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm OF p0300_m00024_s_v02_test_fsm IS + + -- Architecture Declarations + SIGNAL ctrl_int_reg : std_logic; + SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL ctrl_start_reg : std_logic; + SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL dt_reg : DATA_T; + SIGNAL dw_reg : DATA_T; + + TYPE STATE_TYPE IS ( + S02, + S05, + S04, + S07, + S06, + S11, + S12, + S13, + S14, + S15, + S01, + S00, + S09, + S08, + S10, + S03 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + ctrl_int_reg <= '0'; + ctrl_rdlat_reg <= (others => '0'); + ctrl_start_reg <= '0'; + ctrl_wrlat_reg <= (others => '0'); + dt_reg <= (others => '0'); + dw_reg <= (others => '0'); + ELSE + current_state <= next_state; + -- Default Assignment To Internals + ctrl_int_reg <= '0'; + ctrl_rdlat_reg <= ctrl_rdlat_reg; + ctrl_start_reg <= ctrl_start_i; + ctrl_wrlat_reg <= ctrl_wrlat_reg; + dt_reg <= dt_i; + dw_reg <= dw_i; + + -- Combined Actions + CASE current_state IS + -- Clear T + WHEN S02 => + ctrl_wrlat_reg <= ctrl_wrlat_i; + -- Replace + -- multiplication + WHEN S04 => + ctrl_wrlat_reg <= ctrl_wrlat_i; + -- Dummy cycles to + -- equalize latency. + -- j-path + WHEN S13 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Set interrupt + -- flag + WHEN S14 => + ctrl_int_reg <= '1'; + -- Dummy cycles to + -- equalize latency. + -- End-path + WHEN S15 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Next i + WHEN S09 => + ctrl_rdlat_reg <= ctrl_rdlat_i; + -- Dummy cycles to + -- equalize latency. + -- Write-path (i) + WHEN S08 => + ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Dummy cycles to + -- equalize latency. + -- i-path + WHEN S10 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Dummy cycles to + -- equalize latency. + -- Write-path (i) + WHEN S03 => + ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + cnti_end_i, + cntj_end_i, + ctrl_rdlat_reg, + ctrl_rdy7_i, + ctrl_start_reg, + ctrl_wrlat_reg, + current_state, + ds_i + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Clear T + WHEN S02 => + next_state <= S03; + -- ADD if + -- DS > 0 + WHEN S05 => + next_state <= S08; + -- Replace + -- multiplication + WHEN S04 => + IF (signed (ds_i) > 0) THEN + next_state <= S05; + ELSIF (signed (ds_i) < 0) THEN + next_state <= S07; + ELSE + next_state <= S06; + END IF; + -- SUB if + -- DS < 0 + WHEN S07 => + next_state <= S08; + -- Do nothing if + -- DS = 0 + WHEN S06 => + next_state <= S08; + -- Add offset to T + WHEN S11 => + next_state <= S12; + -- Next j + WHEN S12 => + IF (cntj_end_i = '1') THEN + next_state <= S14; + ELSE + next_state <= S13; + END IF; + -- Dummy cycles to + -- equalize latency. + -- j-path + WHEN S13 => + IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN + next_state <= S02; + ELSE + next_state <= S13; + END IF; + -- Set interrupt + -- flag + WHEN S14 => + next_state <= S15; + -- Dummy cycles to + -- equalize latency. + -- End-path + WHEN S15 => + IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN + next_state <= S01; + ELSE + next_state <= S15; + END IF; + -- Wait for next + -- TEST request + WHEN S01 => + IF (ctrl_start_reg = '1') THEN + next_state <= S02; + ELSE + next_state <= S01; + END IF; + -- Reset state + WHEN S00 => + IF (ctrl_rdy7_i = '1') THEN + next_state <= S01; + ELSE + next_state <= S00; + END IF; + -- Next i + WHEN S09 => + IF (cnti_end_i = '1') THEN + next_state <= S11; + ELSE + next_state <= S10; + END IF; + -- Dummy cycles to + -- equalize latency. + -- Write-path (i) + WHEN S08 => + IF (unsigned ( ctrl_wrlat_reg ) <= 3) THEN + next_state <= S09; + ELSE + next_state <= S08; + END IF; + -- Dummy cycles to + -- equalize latency. + -- i-path + WHEN S10 => + IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN + next_state <= S04; + ELSE + next_state <= S10; + END IF; + -- Dummy cycles to + -- equalize latency. + -- Write-path (i) + WHEN S03 => + IF (unsigned ( ctrl_wrlat_reg ) <= 1) THEN + next_state <= S04; + ELSE + next_state <= S03; + END IF; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + ctrl_int_reg, + current_state, + dt_reg, + dw_reg, + offset_i + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + cnteni_o <= '0'; + cntenj_o <= '0'; + ctrl_int_o <= ctrl_int_reg; + ctrl_rdy_o <= '0'; + dout_o <= (others => '0'); + we_s_o <= '0'; + we_t_o <= '0'; + we_w_o <= '0'; + + -- Combined Actions + CASE current_state IS + -- Clear T + WHEN S02 => + dout_o <= (others => '0'); + we_t_o <= '1'; + -- ADD if + -- DS > 0 + WHEN S05 => + --dout_o <= signed (dt_i) + signed (dw_i); + dout_o <= signed (dt_reg) + signed (dw_reg); + we_t_o <= '1'; + -- SUB if + -- DS < 0 + WHEN S07 => + --dout_o <= signed (dt_i) - signed (dw_i); + dout_o <= signed (dt_reg) - signed (dw_reg); + we_t_o <= '1'; + -- Add offset to T + WHEN S11 => + --dout_o <= signed (dt_i) + signed (offset_i); + dout_o <= signed (dt_reg) + signed (offset_i); + we_t_o <= '1'; + -- Next j + WHEN S12 => + cntenj_o <= '1'; + -- Wait for next + -- TEST request + WHEN S01 => + ctrl_rdy_o <= '1'; + -- Next i + WHEN S09 => + cnteni_o <= '1'; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00025_s_v02_init_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00025_s_v02_init_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00025_s_v02_init_fsm.vhd (revision 8) @@ -0,0 +1,272 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00025_s_v02_init_fsm IS + PORT( + clk_i : IN std_logic; + cnti_end_i : IN std_logic; + cntj_end_i : IN std_logic; + ctrl_bias_i : IN DATA_T; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T; + ctrl_rdy7_i : IN std_logic; + ctrl_start_i : IN std_logic; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T; + rst_n_i : IN std_logic; + cnteni_o : OUT std_logic; + cntenj_o : OUT std_logic; + ctrl_rdy_o : OUT std_logic; + dout_o : OUT DATA_T; + we_bias_o : OUT std_logic; + we_s_o : OUT std_logic; + we_t_o : OUT std_logic; + we_w_o : OUT std_logic; + we_y_o : OUT std_logic + ); + +-- Declarations + +END p0300_m00025_s_v02_init_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 2.0 2022/07/03 +-- - Introduced latency for write +-- Revision 1.0 2022/06/12 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm OF p0300_m00025_s_v02_init_fsm IS + + -- Architecture Declarations + SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL ctrl_start_reg : std_logic; + SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T; + + TYPE STATE_TYPE IS ( + S00, + S06, + S02, + S03, + S04, + S01, + S08, + S07, + S05 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + ctrl_rdlat_reg <= (others => '0'); + ctrl_start_reg <= '0'; + ctrl_wrlat_reg <= (others => '0'); + ELSE + current_state <= next_state; + -- Default Assignment To Internals + ctrl_rdlat_reg <= ctrl_rdlat_reg; + ctrl_start_reg <= ctrl_start_i; + ctrl_wrlat_reg <= ctrl_wrlat_reg; + + -- Combined Actions + CASE current_state IS + -- Write W, S. Next i. + -- S also on j-path + WHEN S04 => + ctrl_rdlat_reg <= ctrl_rdlat_i; + ctrl_wrlat_reg <= ctrl_wrlat_i; + -- Dummy cycles to + -- equalize latency. + -- End-path + WHEN S08 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Dummy cycles to + -- equalize latency. + -- j-path + WHEN S07 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + -- Dummy cycles to + -- equalize latency. + -- i-path + WHEN S05 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + cnti_end_i, + cntj_end_i, + ctrl_rdlat_reg, + ctrl_rdy7_i, + ctrl_start_reg, + ctrl_wrlat_reg, + current_state + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Reset state + WHEN S00 => + IF (ctrl_rdy7_i = '1') THEN + next_state <= S01; + ELSE + next_state <= S00; + END IF; + -- Next j + WHEN S06 => + IF (cntj_end_i = '1') THEN + next_state <= S08; + ELSE + next_state <= S07; + END IF; + -- Write BIAS + WHEN S02 => + next_state <= S03; + -- Write T and Y + WHEN S03 => + next_state <= S04; + -- Write W, S. Next i. + -- S also on j-path + WHEN S04 => + IF (cnti_end_i = '1') THEN + next_state <= S06; + ELSE + next_state <= S05; + END IF; + -- Wait for next + -- INIT request + WHEN S01 => + IF (ctrl_start_reg = '1') THEN + next_state <= S02; + ELSE + next_state <= S01; + END IF; + -- Dummy cycles to + -- equalize latency. + -- End-path + WHEN S08 => + IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN + next_state <= S01; + ELSE + next_state <= S08; + END IF; + -- Dummy cycles to + -- equalize latency. + -- j-path + WHEN S07 => + IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN + next_state <= S02; + ELSE + next_state <= S07; + END IF; + -- Dummy cycles to + -- equalize latency. + -- i-path + WHEN S05 => + IF (unsigned ( ctrl_rdlat_reg ) <= 7 AND + unsigned ( ctrl_wrlat_reg ) <= 7) THEN + next_state <= S04; + ELSE + next_state <= S05; + END IF; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + ctrl_bias_i, + current_state + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + cnteni_o <= '0'; + cntenj_o <= '0'; + ctrl_rdy_o <= '0'; + dout_o <= (others => '0'); + we_bias_o <= '0'; + we_s_o <= '0'; + we_t_o <= '0'; + we_w_o <= '0'; + we_y_o <= '0'; + + -- Combined Actions + CASE current_state IS + -- Next j + WHEN S06 => + cntenj_o <= '1'; + -- Write BIAS + WHEN S02 => + dout_o <= ctrl_bias_i; + we_bias_o <= '1'; + -- Write T and Y + WHEN S03 => + dout_o <= (others => '0'); + we_t_o <= '1'; + we_y_o <= '1'; + -- Write W, S. Next i. + -- S also on j-path + WHEN S04 => + dout_o <= (others => '0'); + we_w_o <= '1'; + we_s_o <= '1'; + cnteni_o <= '1'; + -- Wait for next + -- INIT request + WHEN S01 => + ctrl_rdy_o <= '1'; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00026_s_v02_rd_wr_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00026_s_v02_rd_wr_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00026_s_v02_rd_wr_fsm.vhd (revision 8) @@ -0,0 +1,306 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00026_s_v02_rd_wr_fsm IS + PORT( + clk_i : IN std_logic; + cnti_end_i : IN std_logic; + cntj_end_i : IN std_logic; + ctrl_din_i : IN DATA_T; + ctrl_rd_vec_i : IN MEM_WR_LINES_T; + ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T; + ctrl_rdy7_i : IN std_logic; + ctrl_start_i : IN std_logic; + ctrl_wr_vec_i : IN MEM_WR_LINES_T; + ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T; + dbias_i : IN DATA_T; + ds_i : IN DATA_T; + dt_i : IN DATA_T; + dw_i : IN DATA_T; + dy_i : IN DATA_T; + rst_n_i : IN std_logic; + cnteni_o : OUT std_logic; + cntenj_o : OUT std_logic; + ctrl_complete_o : OUT std_logic; + ctrl_dout_o : OUT DATA_T; + ctrl_dout_valid_o : OUT std_logic; + ctrl_rdy_o : OUT std_logic; + dout_o : OUT DATA_T; + we_bias_o : OUT std_logic; + we_s_o : OUT std_logic; + we_t_o : OUT std_logic; + we_w_o : OUT std_logic; + we_y_o : OUT std_logic + ); + +-- Declarations + +END p0300_m00026_s_v02_rd_wr_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 2.0 2022/07/02 +-- - Introduced latency for write +-- Revision 1.0 2022/06/09 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm OF p0300_m00026_s_v02_rd_wr_fsm IS + + -- Architecture Declarations + SIGNAL ctrl_complete_reg : std_logic; + SIGNAL ctrl_dout_reg : DATA_T; + SIGNAL ctrl_dout_valid_reg : std_logic; + SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL ctrl_start_reg : std_logic; + SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T; + + TYPE STATE_TYPE IS ( + S01, + S02, + S12, + S22, + S32, + S42, + S03, + S00 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + ctrl_complete_reg <= '0'; + ctrl_dout_reg <= (others => '0'); + ctrl_dout_valid_reg <= '0'; + ctrl_rdlat_reg <= (others => '0'); + ctrl_start_reg <= '0'; + ctrl_wrlat_reg <= (others => '0'); + ELSE + current_state <= next_state; + -- Default Assignment To Internals + ctrl_complete_reg <= '0'; + ctrl_dout_reg <= ctrl_dout_reg; + ctrl_dout_valid_reg <= '0'; + ctrl_rdlat_reg <= ctrl_rdlat_reg; + ctrl_start_reg <= ctrl_start_i; + ctrl_wrlat_reg <= ctrl_wrlat_reg; + + -- Combined Actions + CASE current_state IS + -- Wait for next + -- RD/WR. + WHEN S01 => + ctrl_rdlat_reg <= ctrl_rdlat_i; + ctrl_wrlat_reg <= ctrl_wrlat_i; + -- RD/WR W + WHEN S02 => + ctrl_dout_reg <= dw_i; + ctrl_dout_valid_reg <= '1'; + ctrl_complete_reg <= cnti_end_i AND cntj_end_i; + -- RD/WR S + WHEN S12 => + ctrl_dout_reg <= ds_i; + ctrl_dout_valid_reg <= '1'; + ctrl_complete_reg <= cnti_end_i; + -- RD/WR Y + WHEN S22 => + ctrl_dout_reg <= dy_i; + ctrl_dout_valid_reg <= '1'; + ctrl_complete_reg <= cntj_end_i; + -- RD/WR BIAS + WHEN S32 => + ctrl_dout_reg <= dbias_i; + ctrl_dout_valid_reg <= '1'; + ctrl_complete_reg <= cntj_end_i; + -- RD/WR T + WHEN S42 => + ctrl_dout_reg <= dt_i; + ctrl_dout_valid_reg <= '1'; + ctrl_complete_reg <= cntj_end_i; + -- Dummy cycles to + -- equalize latency. + WHEN S03 => + ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 ); + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + ctrl_rd_vec_i, + ctrl_rdlat_reg, + ctrl_rdy7_i, + ctrl_start_reg, + ctrl_wrlat_reg, + current_state + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Wait for next + -- RD/WR. + WHEN S01 => + IF (ctrl_start_reg = '1' AND + (ctrl_rd_vec_i( MEM_W_BITPOS ) = '1')) THEN + next_state <= S02; + ELSIF (ctrl_start_reg = '1' AND + (ctrl_rd_vec_i( MEM_S_BITPOS ) = '1')) THEN + next_state <= S12; + ELSIF (ctrl_start_reg = '1' AND + (ctrl_rd_vec_i( MEM_Y_BITPOS ) = '1')) THEN + next_state <= S22; + ELSIF (ctrl_start_reg = '1' AND + (ctrl_rd_vec_i( MEM_BIAS_BITPOS ) = '1')) THEN + next_state <= S32; + ELSIF (ctrl_start_reg = '1' AND + (ctrl_rd_vec_i( MEM_T_BITPOS ) = '1')) THEN + next_state <= S42; + ELSE + next_state <= S01; + END IF; + -- RD/WR W + WHEN S02 => + next_state <= S03; + -- RD/WR S + WHEN S12 => + next_state <= S03; + -- RD/WR Y + WHEN S22 => + next_state <= S03; + -- RD/WR BIAS + WHEN S32 => + next_state <= S03; + -- RD/WR T + WHEN S42 => + next_state <= S03; + -- Dummy cycles to + -- equalize latency. + WHEN S03 => + IF (unsigned ( ctrl_rdlat_reg ) <= 3 AND + unsigned ( ctrl_wrlat_reg ) <= 3) THEN + next_state <= S01; + ELSE + next_state <= S03; + END IF; + -- Reset state + WHEN S00 => + IF (ctrl_rdy7_i = '1') THEN + next_state <= S01; + ELSE + next_state <= S00; + END IF; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + cnti_end_i, + ctrl_complete_reg, + ctrl_din_i, + ctrl_dout_reg, + ctrl_dout_valid_reg, + ctrl_wr_vec_i, + current_state + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + cnteni_o <= '0'; + cntenj_o <= '0'; + ctrl_complete_o <= ctrl_complete_reg; + ctrl_dout_o <= ctrl_dout_reg; + ctrl_dout_valid_o <= ctrl_dout_valid_reg; + ctrl_rdy_o <= '0'; + dout_o <= (others => '0'); + we_bias_o <= '0'; + we_s_o <= '0'; + we_t_o <= '0'; + we_w_o <= '0'; + we_y_o <= '0'; + + -- Combined Actions + CASE current_state IS + -- Wait for next + -- RD/WR. + WHEN S01 => + ctrl_rdy_o <= '1'; + -- RD/WR W + WHEN S02 => + cnteni_o <= '1'; + cntenj_o <= cnti_end_i; + dout_o <= ctrl_din_i; + we_w_o <= ctrl_wr_vec_i( MEM_W_BITPOS ); + -- RD/WR S + WHEN S12 => + cnteni_o <= '1'; + dout_o <= ctrl_din_i; + we_s_o <= ctrl_wr_vec_i( MEM_S_BITPOS ); + -- RD/WR Y + WHEN S22 => + cntenj_o <= '1'; + dout_o <= ctrl_din_i; + we_y_o <= ctrl_wr_vec_i( MEM_Y_BITPOS ); + -- RD/WR BIAS + WHEN S32 => + cntenj_o <= '1'; + dout_o <= ctrl_din_i; + we_bias_o <= ctrl_wr_vec_i( MEM_BIAS_BITPOS ); + -- RD/WR T + WHEN S42 => + cntenj_o <= '1'; + dout_o <= ctrl_din_i; + we_t_o <= ctrl_wr_vec_i( MEM_T_BITPOS ); + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00027_s_v01_train_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00027_s_v01_train_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00027_s_v01_train_fsm.vhd (revision 8) @@ -0,0 +1,308 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00027_s_v01_train_fsm IS + PORT( + clk_i : IN std_logic; + cnti_rdy_i : IN std_logic; + cntj_rdy_i : IN std_logic; + ctrl_clear_epoch_i : IN std_logic; + ctrl_maxepoch_i : IN WB_DATA_WIDTH_T; + ctrl_rdy1_i : IN std_logic; + ctrl_rdy2_i : IN std_logic; + ctrl_rdy7_i : IN std_logic; + ctrl_start_i : IN std_logic; + ctrl_wchgd_i : IN std_logic; + rst_n_i : IN std_logic; + ctrl_epoch_o : OUT WB_DATA_WIDTH_T; + ctrl_int_o : OUT std_logic; + ctrl_not_rdy_o : OUT std_logic; + ctrl_rdy_o : OUT std_logic; + ctrl_start1_o : OUT std_logic; + ctrl_start2_o : OUT std_logic + ); + +-- Declarations + +END p0300_m00027_s_v01_train_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.0 2022/07/04 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm OF p0300_m00027_s_v01_train_fsm IS + + -- Architecture Declarations + SIGNAL cnti_rdy_reg : std_logic; + SIGNAL cntj_rdy_reg : std_logic; + SIGNAL ctrl_clear_epoch_reg : std_logic; + SIGNAL ctrl_epoch_reg : WB_DATA_WIDTH_T; + SIGNAL ctrl_int_reg : std_logic; + SIGNAL ctrl_not_rdy_reg : std_logic; + SIGNAL ctrl_rdy1_reg : std_logic; + SIGNAL ctrl_rdy2_reg : std_logic; + SIGNAL ctrl_start_reg : std_logic; + + TYPE STATE_TYPE IS ( + S00, + S02, + S03, + S06, + S07, + S10, + S01, + S11, + S12, + S05, + S08, + S04, + S09, + S13 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + cnti_rdy_reg <= '0'; + cntj_rdy_reg <= '0'; + ctrl_clear_epoch_reg <= '0'; + ctrl_epoch_reg <= (others => '0'); + ctrl_int_reg <= '0'; + ctrl_not_rdy_reg <= '0'; + ctrl_rdy1_reg <= '0'; + ctrl_rdy2_reg <= '0'; + ctrl_start_reg <= '0'; + ELSE + current_state <= next_state; + -- Default Assignment To Internals + cnti_rdy_reg <= cnti_rdy_i; + cntj_rdy_reg <= cntj_rdy_i; + ctrl_clear_epoch_reg <= ctrl_clear_epoch_i; + ctrl_epoch_reg <= ctrl_epoch_reg; + ctrl_int_reg <= '0'; + ctrl_not_rdy_reg <= ctrl_not_rdy_reg; + ctrl_rdy1_reg <= ctrl_rdy1_i; + ctrl_rdy2_reg <= ctrl_rdy2_i; + ctrl_start_reg <= ctrl_start_i; + + -- Combined Actions + CASE current_state IS + -- Clear NOT READY + -- register and test for + -- READY + WHEN S02 => + ctrl_not_rdy_reg <= '0'; + -- Set interrupt + -- flag + WHEN S11 => + ctrl_int_reg <= '1'; + -- Set NOT READY + -- register if modules + -- are NOT READY + WHEN S12 => + ctrl_not_rdy_reg <= '1'; + -- Dummy cycle + -- and update + -- EPOCH + WHEN S04 => + ctrl_epoch_reg <= unsigned (ctrl_epoch_reg) + ctrl_wchgd_i; + -- Clear EPOCH + -- register + WHEN S13 => + ctrl_epoch_reg <= (others => '0'); + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + cnti_rdy_reg, + ctrl_clear_epoch_reg, + ctrl_epoch_reg, + ctrl_maxepoch_i, + ctrl_rdy1_reg, + ctrl_rdy2_reg, + ctrl_rdy7_i, + ctrl_start_reg, + ctrl_wchgd_i, + current_state + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Reset state + WHEN S00 => + IF (ctrl_rdy7_i = '1') THEN + next_state <= S01; + ELSE + next_state <= S00; + END IF; + -- Clear NOT READY + -- register and test for + -- READY + WHEN S02 => + IF (ctrl_rdy1_reg = '0' OR + ctrl_rdy2_reg = '0' OR + cnti_rdy_reg = '0') THEN + next_state <= S12; + ELSE + next_state <= S03; + END IF; + -- Start calculation + -- of Y + WHEN S03 => + next_state <= S04; + -- Wait for CAL_Y + -- is ready + WHEN S06 => + IF (ctrl_rdy1_reg = '1') THEN + next_state <= S07; + ELSE + next_state <= S06; + END IF; + -- Start calculation + -- of BIAS and W + WHEN S07 => + next_state <= S08; + -- Loop again if + -- W was changed + WHEN S10 => + IF (ctrl_rdy2_reg = '1' AND + ctrl_wchgd_i = '1' AND + ( unsigned (ctrl_maxepoch_i) = 0 OR + unsigned (ctrl_maxepoch_i) >= unsigned (ctrl_epoch_reg) )) THEN + next_state <= S03; + ELSIF (ctrl_rdy2_reg = '1') THEN + next_state <= S11; + ELSE + next_state <= S10; + END IF; + -- Wait for next + -- training or clear + -- EPOCH register + WHEN S01 => + IF (ctrl_start_reg = '1' AND + ctrl_clear_epoch_reg = '1') THEN + next_state <= S13; + ELSIF (ctrl_start_reg = '1') THEN + next_state <= S02; + ELSE + next_state <= S01; + END IF; + -- Set interrupt + -- flag + WHEN S11 => + next_state <= S01; + -- Set NOT READY + -- register if modules + -- are NOT READY + WHEN S12 => + next_state <= S01; + -- Dummy cycle + WHEN S05 => + next_state <= S06; + -- Dummy cycle + WHEN S08 => + next_state <= S09; + -- Dummy cycle + -- and update + -- EPOCH + WHEN S04 => + next_state <= S05; + -- Dummy cycle + WHEN S09 => + next_state <= S10; + -- Clear EPOCH + -- register + WHEN S13 => + next_state <= S02; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + ctrl_epoch_reg, + ctrl_int_reg, + ctrl_not_rdy_reg, + current_state + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + ctrl_epoch_o <= ctrl_epoch_reg; + ctrl_int_o <= ctrl_int_reg; + ctrl_not_rdy_o <= ctrl_not_rdy_reg; + ctrl_rdy_o <= '0'; + ctrl_start1_o <= '0'; + ctrl_start2_o <= '0'; + + -- Combined Actions + CASE current_state IS + -- Start calculation + -- of Y + WHEN S03 => + ctrl_start1_o <= '1'; + -- Start calculation + -- of BIAS and W + WHEN S07 => + ctrl_start2_o <= '1'; + -- Wait for next + -- training or clear + -- EPOCH register + WHEN S01 => + ctrl_rdy_o <= '1'; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00028_s_v02_latency_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00028_s_v02_latency_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00028_s_v02_latency_fsm.vhd (revision 8) @@ -0,0 +1,358 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00028_s_v02_latency_fsm IS + PORT( + clk_i : IN std_logic; + dw_i : IN DATA_T; + rst_n_i : IN std_logic; + cnt_alllat_o : OUT MEM_LAT_CNT_WIDTH_T; + cnteni_o : OUT std_logic; + cntenj_o : OUT std_logic; + ctrl_memerr_o : OUT std_logic; + ctrl_rdlat_o : OUT MEM_LAT_CNT_WIDTH_T; + ctrl_rdy_o : OUT std_logic; + ctrl_run_o : OUT std_logic; + ctrl_wrlat_o : OUT MEM_LAT_CNT_WIDTH_T; + dout_o : OUT DATA_T; + we_w_o : OUT std_logic + ); + +-- Declarations + +END p0300_m00028_s_v02_latency_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 2.0 2022/07/04 +-- - Introsuced latency for write +-- Revision 1.0 2022/07/02 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm OF p0300_m00028_s_v02_latency_fsm IS + + -- Architecture Declarations + SIGNAL cnt_alllat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL ctrl_memerr_reg : std_logic; + SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL ctrl_rdy_reg : std_logic; + SIGNAL ctrl_run_reg : std_logic; + SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T; + SIGNAL dw_reg : DATA_T; + + TYPE STATE_TYPE IS ( + S00, + S01, + S02, + S03, + S04, + S06, + S05, + S08, + SERR, + S07, + SRDY, + S11, + S7, + S8 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + cnt_alllat_reg <= (others => '0'); + ctrl_memerr_reg <= '0'; + ctrl_rdlat_reg <= (others => '0'); + ctrl_rdy_reg <= '0'; + ctrl_run_reg <= '0'; + ctrl_wrlat_reg <= (others => '0'); + dw_reg <= (others => '0'); + ELSE + current_state <= next_state; + -- Default Assignment To Internals + cnt_alllat_reg <= cnt_alllat_reg; + ctrl_memerr_reg <= ctrl_memerr_reg; + ctrl_rdlat_reg <= ctrl_rdlat_reg; + ctrl_rdy_reg <= ctrl_rdy_reg; + ctrl_run_reg <= ctrl_run_reg; + ctrl_wrlat_reg <= ctrl_wrlat_reg; + dw_reg <= dw_i; + + -- Combined Actions + CASE current_state IS + -- Reset state + WHEN S00 => + ctrl_run_reg <= '1'; + ctrl_rdy_reg <= '0'; + -- Init values + WHEN S01 => + ctrl_wrlat_reg <= (others => '0'); + ctrl_memerr_reg <= '0'; + -- Wait for max + -- latency + WHEN S03 => + ctrl_wrlat_reg <= ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1'; + -- Last address + -- [1][1] + WHEN S04 => + ctrl_wrlat_reg <= (others => '0'); + -- Write -1 to + -- last address + -- [1][1] + WHEN S06 => + ctrl_wrlat_reg <= (others => '0'); + -- Wait for max + -- latency + WHEN S05 => + ctrl_wrlat_reg <= ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1'; + -- Release END + -- conditions (for) + WHEN S08 => + cnt_alllat_reg <= (others => '0'); + ctrl_wrlat_reg <= (others => '0'); + ctrl_rdlat_reg <= (others => '0'); + -- Memory + -- ERROR + WHEN SERR => + ctrl_memerr_reg <= '1'; + ctrl_run_reg <= '0'; + -- Wait for max + -- latency + WHEN S07 => + ctrl_wrlat_reg <= ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1'; + -- END / READY + -- state + WHEN SRDY => + ctrl_rdy_reg <= '1'; + ctrl_run_reg <= '0'; + -- Address [0][0] + -- reaches memory + -- WS=1...max + WHEN S11 => + cnt_alllat_reg <= unsigned (cnt_alllat_reg) + 1; + ctrl_rdlat_reg <= ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1'; + IF (signed (dw_reg) = 0) THEN + cnt_alllat_reg <= cnt_alllat_reg; + ctrl_rdlat_reg <= ctrl_rdlat_reg; + END IF; + -- Wait for + -- dw_i = -1 + WHEN S8 => + ctrl_wrlat_reg <= ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1'; + IF (signed (dw_reg) = -1) THEN + ctrl_wrlat_reg <= ctrl_wrlat_reg; + END IF; + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + ctrl_rdlat_reg, + ctrl_wrlat_reg, + current_state, + dw_reg + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Reset state + WHEN S00 => + next_state <= S01; + -- Init values + WHEN S01 => + next_state <= S02; + -- Write 0 to + -- first address + -- [0][0] + WHEN S02 => + next_state <= S03; + -- Wait for max + -- latency + WHEN S03 => + IF (signed (ctrl_wrlat_reg) = -1) THEN + next_state <= S04; + ELSE + next_state <= S03; + END IF; + -- Last address + -- [1][1] + WHEN S04 => + next_state <= S05; + -- Write -1 to + -- last address + -- [1][1] + WHEN S06 => + next_state <= S07; + -- Wait for max + -- latency + WHEN S05 => + IF (signed (ctrl_wrlat_reg) = -1) THEN + next_state <= S06; + ELSE + next_state <= S05; + END IF; + -- Release END + -- conditions (for) + WHEN S08 => + IF (signed (dw_reg) = -1) THEN + next_state <= S11; + ELSE + -- -1 not read on dw + -- after max latency + -- time causes ERROR + next_state <= SERR; + END IF; + -- Memory + -- ERROR + WHEN SERR => + next_state <= SERR; + -- Wait for max + -- latency + WHEN S07 => + IF (signed (ctrl_wrlat_reg) = -1) THEN + next_state <= S08; + ELSE + next_state <= S07; + END IF; + -- END / READY + -- state + WHEN SRDY => + next_state <= SRDY; + -- Address [0][0] + -- reaches memory + -- WS=1...max + WHEN S11 => + IF (signed (dw_reg) = 0) THEN + next_state <= S7; + ELSIF (signed (ctrl_rdlat_reg) = -1) THEN + next_state <= SERR; + ELSE + next_state <= S11; + END IF; + -- Write -1 to + -- last address + -- [1][1] + WHEN S7 => + next_state <= S8; + -- Wait for + -- dw_i = -1 + WHEN S8 => + IF (signed (dw_reg) = -1) THEN + next_state <= SRDY; + ELSIF (signed (ctrl_wrlat_reg) = -1) THEN + next_state <= SERR; + ELSE + next_state <= S8; + END IF; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + cnt_alllat_reg, + ctrl_memerr_reg, + ctrl_rdlat_reg, + ctrl_rdy_reg, + ctrl_run_reg, + ctrl_wrlat_reg, + current_state + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + cnt_alllat_o <= cnt_alllat_reg; + cnteni_o <= '0'; + cntenj_o <= '0'; + ctrl_memerr_o <= ctrl_memerr_reg; + ctrl_rdlat_o <= ctrl_rdlat_reg; + ctrl_rdy_o <= ctrl_rdy_reg; + ctrl_run_o <= ctrl_run_reg; + ctrl_wrlat_o <= ctrl_wrlat_reg; + dout_o <= (others => '0'); + we_w_o <= '0'; + + -- Combined Actions + CASE current_state IS + -- Write 0 to + -- first address + -- [0][0] + WHEN S02 => + dout_o <= (others => '0'); + we_w_o <= '1'; + -- Last address + -- [1][1] + WHEN S04 => + cnteni_o <= '1'; + cntenj_o <= '1'; + -- Write -1 to + -- last address + -- [1][1] + WHEN S06 => + dout_o <= (others => '1'); + we_w_o <= '1'; + -- Release END + -- conditions (for) + WHEN S08 => + cnteni_o <= '1'; + cntenj_o <= '1'; + -- Write -1 to + -- last address + -- [1][1] + WHEN S7 => + dout_o <= (others => '1'); + we_w_o <= '1'; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00033_s_v01_for_loop_memwi_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00033_s_v01_for_loop_memwi_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00033_s_v01_for_loop_memwi_fsm.vhd (revision 8) @@ -0,0 +1,252 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00033_s_v01_for_loop_memwi_fsm IS + PORT( + clk_i : IN std_logic; + cnten1_i : IN std_logic; + cnten2_i : IN std_logic; + cnten3_i : IN std_logic; + cnten4_i : IN std_logic; + cnten5_i : IN std_logic; + cnten7_i : IN std_logic; + rst_n_i : IN std_logic; + set_init_i : IN std_logic; + start_vali_i : IN ADDRESS_S_T; + stop_vali_i : IN ADDRESS_S_T; + cnt_end_o : OUT std_logic; + cnt_rdy_o : OUT std_logic; + cnt_val_o : OUT ADDRESS_S_T + ); + +-- Declarations + +END p0300_m00033_s_v01_for_loop_memwi_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.0 2022/06/09 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm_behv OF p0300_m00033_s_v01_for_loop_memwi_fsm IS + + -- Architecture Declarations + SIGNAL cnt_end_reg : std_logic; + SIGNAL cnt_reg : ADDRESS_S_T; + SIGNAL cnten_reg : std_logic; + SIGNAL set_init_reg : std_logic; + + TYPE STATE_TYPE IS ( + S01, + S02, + S03, + S06, + S04, + S05, + S00 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + cnt_end_reg <= '0'; + cnt_reg <= (others => '0'); + cnten_reg <= '0'; + set_init_reg <= '0'; + ELSE + current_state <= next_state; + -- Default Assignment To Internals + cnt_end_reg <= '0'; + cnt_reg <= cnt_reg; + cnten_reg <= cnten1_i OR cnten2_i OR cnten3_i OR cnten4_i OR cnten5_i OR cnten7_i; + set_init_reg <= set_init_i; + + -- Combined Actions + CASE current_state IS + -- Start loop + WHEN S01 => + cnt_reg <= start_vali_i; + -- COUNT + + WHEN S02 => + cnt_reg <= unsigned (cnt_reg) + 1; + IF (cnt_reg = unsigned (stop_vali_i) - 1 OR + set_init_reg = '1') THEN + cnt_end_reg <= '1'; + END IF; + -- Wait for next + -- count enable. + WHEN S03 => + IF (set_init_reg = '1') THEN + cnt_end_reg <= '1'; + END IF; + -- COUNT - + WHEN S04 => + cnt_reg <= unsigned (cnt_reg) - 1; + IF (cnt_reg = unsigned (stop_vali_i) + 1 OR + set_init_reg = '1') THEN + cnt_end_reg <= '1'; + END IF; + -- Wait for next + -- count enable. + WHEN S05 => + IF (set_init_reg = '1') THEN + cnt_end_reg <= '1'; + END IF; + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + cnt_reg, + cnten_reg, + current_state, + set_init_reg, + start_vali_i, + stop_vali_i + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Start loop + WHEN S01 => + IF (cnten_reg = '1' AND + unsigned (stop_vali_i) > unsigned (start_vali_i)) THEN + next_state <= S02; + ELSIF (cnten_reg = '1' AND + unsigned (stop_vali_i) < unsigned (start_vali_i)) THEN + next_state <= S04; + ELSE + next_state <= S01; + END IF; + -- COUNT + + WHEN S02 => + IF (cnt_reg = unsigned (stop_vali_i) - 1 OR + set_init_reg = '1') THEN + next_state <= S06; + ELSIF (cnten_reg = '0') THEN + next_state <= S03; + ELSE + next_state <= S02; + END IF; + -- Wait for next + -- count enable. + WHEN S03 => + IF (set_init_reg = '1') THEN + next_state <= S06; + ELSIF (cnten_reg = '1') THEN + next_state <= S02; + ELSE + next_state <= S03; + END IF; + -- End-of-count + -- or cancel. + WHEN S06 => + IF (cnten_reg = '1' OR + set_init_reg = '1') THEN + next_state <= S01; + ELSE + next_state <= S06; + END IF; + -- COUNT - + WHEN S04 => + IF (cnt_reg = unsigned (stop_vali_i) + 1 OR + set_init_reg = '1') THEN + next_state <= S06; + ELSIF (cnten_reg = '0') THEN + next_state <= S05; + ELSE + next_state <= S04; + END IF; + -- Wait for next + -- count enable. + WHEN S05 => + IF (set_init_reg = '1') THEN + next_state <= S06; + ELSIF (cnten_reg = '1') THEN + next_state <= S04; + ELSE + next_state <= S05; + END IF; + -- Reset state + WHEN S00 => + next_state <= S01; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + cnt_end_reg, + cnt_reg, + current_state + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + cnt_end_o <= cnt_end_reg; + cnt_rdy_o <= '0'; + cnt_val_o <= cnt_reg; + + -- Combined Actions + CASE current_state IS + -- Start loop + WHEN S01 => + cnt_rdy_o <= '1'; + -- End-of-count + -- or cancel. + WHEN S06 => + cnt_end_o <= '1'; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm_behv; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00034_s_v01_for_loop_memwj_fsm.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00034_s_v01_for_loop_memwj_fsm.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00034_s_v01_for_loop_memwj_fsm.vhd (revision 8) @@ -0,0 +1,252 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00034_s_v01_for_loop_memwj_fsm IS + PORT( + clk_i : IN std_logic; + cnten1_i : IN std_logic; + cnten2_i : IN std_logic; + cnten3_i : IN std_logic; + cnten4_i : IN std_logic; + cnten5_i : IN std_logic; + cnten7_i : IN std_logic; + rst_n_i : IN std_logic; + set_init_i : IN std_logic; + start_valj_i : IN ADDRESS_T_T; + stop_valj_i : IN ADDRESS_T_T; + cnt_end_o : OUT std_logic; + cnt_rdy_o : OUT std_logic; + cnt_val_o : OUT ADDRESS_T_T + ); + +-- Declarations + +END p0300_m00034_s_v01_for_loop_memwj_fsm ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.0 2022/06/09 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ARCHITECTURE fsm_behv OF p0300_m00034_s_v01_for_loop_memwj_fsm IS + + -- Architecture Declarations + SIGNAL cnt_end_reg : std_logic; + SIGNAL cnt_reg : ADDRESS_T_T; + SIGNAL cnten_reg : std_logic; + SIGNAL set_init_reg : std_logic; + + TYPE STATE_TYPE IS ( + S01, + S02, + S03, + S06, + S04, + S05, + S00 + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk_i + ) + ----------------------------------------------------------------- + BEGIN + IF (clk_i'EVENT AND clk_i = '1') THEN + IF (rst_n_i = '0') THEN + current_state <= S00; + -- Default Reset Values + cnt_end_reg <= '0'; + cnt_reg <= (others => '0'); + cnten_reg <= '0'; + set_init_reg <= '0'; + ELSE + current_state <= next_state; + -- Default Assignment To Internals + cnt_end_reg <= '0'; + cnt_reg <= cnt_reg; + cnten_reg <= cnten1_i OR cnten2_i OR cnten3_i OR cnten4_i OR cnten5_i OR cnten7_i; + set_init_reg <= set_init_i; + + -- Combined Actions + CASE current_state IS + -- Start loop + WHEN S01 => + cnt_reg <= start_valj_i; + -- COUNT + + WHEN S02 => + cnt_reg <= unsigned (cnt_reg) + 1; + IF (cnt_reg = unsigned (stop_valj_i) - 1 OR + set_init_reg = '1') THEN + cnt_end_reg <= '1'; + END IF; + -- Wait for next + -- count enable. + WHEN S03 => + IF (set_init_reg = '1') THEN + cnt_end_reg <= '1'; + END IF; + -- COUNT - + WHEN S04 => + cnt_reg <= unsigned (cnt_reg) - 1; + IF (cnt_reg = unsigned (stop_valj_i) + 1 OR + set_init_reg = '1') THEN + cnt_end_reg <= '1'; + END IF; + -- Wait for next + -- count enable. + WHEN S05 => + IF (set_init_reg = '1') THEN + cnt_end_reg <= '1'; + END IF; + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + cnt_reg, + cnten_reg, + current_state, + set_init_reg, + start_valj_i, + stop_valj_i + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + -- Start loop + WHEN S01 => + IF (cnten_reg = '1' AND + unsigned (stop_valj_i) > unsigned (start_valj_i)) THEN + next_state <= S02; + ELSIF (cnten_reg = '1' AND + unsigned (stop_valj_i) < unsigned (start_valj_i)) THEN + next_state <= S04; + ELSE + next_state <= S01; + END IF; + -- COUNT + + WHEN S02 => + IF (cnt_reg = unsigned (stop_valj_i) - 1 OR + set_init_reg = '1') THEN + next_state <= S06; + ELSIF (cnten_reg = '0') THEN + next_state <= S03; + ELSE + next_state <= S02; + END IF; + -- Wait for next + -- count enable. + WHEN S03 => + IF (set_init_reg = '1') THEN + next_state <= S06; + ELSIF (cnten_reg = '1') THEN + next_state <= S02; + ELSE + next_state <= S03; + END IF; + -- End-of-count + -- or cancel. + WHEN S06 => + IF (cnten_reg = '1' OR + set_init_reg = '1') THEN + next_state <= S01; + ELSE + next_state <= S06; + END IF; + -- COUNT - + WHEN S04 => + IF (cnt_reg = unsigned (stop_valj_i) + 1 OR + set_init_reg = '1') THEN + next_state <= S06; + ELSIF (cnten_reg = '0') THEN + next_state <= S05; + ELSE + next_state <= S04; + END IF; + -- Wait for next + -- count enable. + WHEN S05 => + IF (set_init_reg = '1') THEN + next_state <= S06; + ELSIF (cnten_reg = '1') THEN + next_state <= S04; + ELSE + next_state <= S05; + END IF; + -- Reset state + WHEN S00 => + next_state <= S01; + WHEN OTHERS => + next_state <= S00; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + cnt_end_reg, + cnt_reg, + current_state + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + cnt_end_o <= cnt_end_reg; + cnt_rdy_o <= '0'; + cnt_val_o <= cnt_reg; + + -- Combined Actions + CASE current_state IS + -- Start loop + WHEN S01 => + cnt_rdy_o <= '1'; + -- End-of-count + -- or cancel. + WHEN S06 => + cnt_end_o <= '1'; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm_behv; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00100_s_v01_mem_gen_blk.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00100_s_v01_mem_gen_blk.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00100_s_v01_mem_gen_blk.vhd (revision 8) @@ -0,0 +1,185 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +ENTITY p0300_m00100_s_v01_mem_gen_blk IS + PORT( + addr_i_i : IN ADDRESS_S_T; + addr_j_i : IN ADDRESS_T_T; + clk_i : IN std_logic; + din1_i : IN DATA_T; + din2_i : IN DATA_T; + din3_i : IN DATA_T; + din4_i : IN DATA_T; + din5_i : IN DATA_T; + din7_i : IN DATA_T; + we_bias2_i : IN std_logic; + we_bias3_i : IN std_logic; + we_bias5_i : IN std_logic; + we_s3_i : IN std_logic; + we_s4_i : IN std_logic; + we_s5_i : IN std_logic; + we_t3_i : IN std_logic; + we_t4_i : IN std_logic; + we_t5_i : IN std_logic; + we_w2_i : IN std_logic; + we_w3_i : IN std_logic; + we_w4_i : IN std_logic; + we_w5_i : IN std_logic; + we_w7_i : IN std_logic; + we_y1_i : IN std_logic; + we_y3_i : IN std_logic; + we_y5_i : IN std_logic; + dbias_o : OUT DATA_T; + ds_o : OUT DATA_T; + dt_o : OUT DATA_T; + dw_o : OUT DATA_T; + dy_o : OUT DATA_T + ); + +-- Declarations + +END p0300_m00100_s_v01_mem_gen_blk ; +-- COPYRIGHT (C) 2022 Jens Gutschmidt / +-- VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.0 2022/05/25 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + + +ARCHITECTURE struct OF p0300_m00100_s_v01_mem_gen_blk IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL addr_ij_oi : ADDRESS_W_T; + SIGNAL din_oi : DATA_T; + SIGNAL we_bias_oi : std_logic; + SIGNAL we_s_oi : std_logic; + SIGNAL we_t_oi : std_logic; + SIGNAL we_w_oi : std_logic; + SIGNAL we_y_oi : std_logic; + + + -- Component Declarations + COMPONENT p0300_m00101_m_v01_mem_t + PORT ( + addr_i : IN ADDRESS_T_T; + clk_i : IN std_logic; + d_i : IN DATA_T; + we_i : IN std_logic; + d_o : OUT DATA_T + ); + END COMPONENT; + COMPONENT p0300_m00102_s_v01_mem_w + PORT ( + addr_i : IN ADDRESS_W_T; + clk_i : IN std_logic; + d_i : IN DATA_T; + we_i : IN std_logic; + d_o : OUT DATA_T + ); + END COMPONENT; + COMPONENT p0300_m00103_s_v01_mem_s + PORT ( + addr_i : IN ADDRESS_S_T; + clk_i : IN std_logic; + d_i : IN DATA_T; + we_i : IN std_logic; + d_o : OUT DATA_T + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : p0300_m00101_m_v01_mem_t USE ENTITY work.p0300_m00101_m_v01_mem_t; + FOR ALL : p0300_m00102_s_v01_mem_w USE ENTITY work.p0300_m00102_s_v01_mem_w; + FOR ALL : p0300_m00103_s_v01_mem_s USE ENTITY work.p0300_m00103_s_v01_mem_s; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + -- eb1 1 + addr_ij_oi <= addr_j_i & addr_i_i; + we_s_oi <= we_s3_i OR we_s4_i OR we_s5_i; + we_t_oi <= we_t3_i OR we_t4_i OR we_t5_i; + we_w_oi <= we_w2_i OR we_w3_i OR we_w4_i OR we_w5_i OR we_w7_i; + we_y_oi <= we_y1_i OR we_y3_i OR we_y5_i; + we_bias_oi <= we_bias2_i OR we_bias3_i OR we_bias5_i; + din_oi <= din1_i OR din2_i OR din3_i OR din4_i OR din5_i OR din7_i; + + + -- Instance port mappings. + U_1 : p0300_m00101_m_v01_mem_t + PORT MAP ( + clk_i => clk_i, + we_i => we_t_oi, + d_i => din_oi, + addr_i => addr_j_i, + d_o => dt_o + ); + U_2 : p0300_m00101_m_v01_mem_t + PORT MAP ( + clk_i => clk_i, + we_i => we_y_oi, + d_i => din_oi, + addr_i => addr_j_i, + d_o => dy_o + ); + U_3 : p0300_m00101_m_v01_mem_t + PORT MAP ( + clk_i => clk_i, + we_i => we_bias_oi, + d_i => din_oi, + addr_i => addr_j_i, + d_o => dbias_o + ); + U_4 : p0300_m00102_s_v01_mem_w + PORT MAP ( + clk_i => clk_i, + we_i => we_w_oi, + d_i => din_oi, + addr_i => addr_ij_oi, + d_o => dw_o + ); + U_0 : p0300_m00103_s_v01_mem_s + PORT MAP ( + clk_i => clk_i, + we_i => we_s_oi, + d_i => din_oi, + addr_i => addr_i_i, + d_o => ds_o + ); + +END struct; Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00101_m_v01_mem_t.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00101_m_v01_mem_t.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00101_m_v01_mem_t.vhd (revision 8) @@ -0,0 +1,69 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +-- Versions: +-- +-- Revision 1.0 2022/06/12 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.all; + +LIBRARY work; + +entity p0300_m00101_m_v01_mem_t is + port( + clk_i : in std_logic; -- Single Clock Input + we_i : in std_logic; -- Write Enable Input + d_i : in DATA_T; -- Data Input + addr_i : in ADDRESS_T_T; -- Address Input + d_o : out DATA_T -- Data Output + ); +end entity p0300_m00101_m_v01_mem_t; + +-- +architecture p0300_mem_t_arch of p0300_m00101_m_v01_mem_t is + + signal addr_reg : ADDRESS_T_T; -- Address register + signal din_reg : DATA_T; + signal we_reg : std_logic; + signal t_ram : T_RAM_T; -- "t output" memory array + attribute logic_block : boolean; + attribute logic_block of t_ram : signal is true; + + +begin + + mem_s_proc: process (clk_i) + begin + if (clk_i'event and clk_i='1') then + if (we_reg = '1') then + t_ram(CONV_INTEGER(unsigned(addr_i))) <= din_reg; + end if; + addr_reg <= addr_i; + din_reg <= d_i; + we_reg <= we_i; + end if; + end process mem_s_proc; + d_o <= t_ram(CONV_INTEGER(unsigned(addr_reg))); + +end architecture p0300_mem_t_arch; + Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00102_s_v01_mem_w.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00102_s_v01_mem_w.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00102_s_v01_mem_w.vhd (revision 8) @@ -0,0 +1,69 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +-- Versions: +-- +-- Revision 1.0 2022/06/12 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.all; + +LIBRARY work; + +entity p0300_m00102_s_v01_mem_w is + port( + clk_i : in std_logic; -- Single Clock Input + we_i : in std_logic; -- Write Enable Input + d_i : in DATA_T; -- Data Input + addr_i : in ADDRESS_W_T; -- Address Input + d_o : out DATA_T -- Data Output + ); +end entity p0300_m00102_s_v01_mem_w; + +-- +architecture p0300_mem_w_arch of p0300_m00102_s_v01_mem_w is + + signal addr_reg : ADDRESS_W_T; -- Address register + signal din_reg : DATA_T; + signal we_reg : std_logic; + signal w_ram : W_RAM_T; -- w (weights) memory + attribute logic_block : boolean; + attribute logic_block of w_ram : signal is true; + + +begin + + mem_s_proc: process (clk_i) + begin + if (clk_i'event and clk_i='1') then + if (we_reg = '1') then + w_ram(CONV_INTEGER(unsigned(addr_i))) <= din_reg; + end if; + addr_reg <= addr_i; + din_reg <= d_i; + we_reg <= we_i; + end if; + end process mem_s_proc; + d_o <= w_ram(CONV_INTEGER(unsigned(addr_reg))); + +end architecture p0300_mem_w_arch; + Index: neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00103_s_v01_mem_s.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00103_s_v01_mem_s.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/rtl/vhdl/p0300_m00103_s_v01_mem_s.vhd (revision 8) @@ -0,0 +1,69 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +-- Versions: +-- +-- Revision 1.0 2022/06/12 +-- -- First draft +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--USE ieee.numeric_std.all; +LIBRARY work; +USE work.memory_vhd_v03_pkg.all; + +LIBRARY work; + +entity p0300_m00103_s_v01_mem_s is + port( + clk_i : in std_logic; -- Single Clock Input + we_i : in std_logic; -- Write Enable Input + d_i : in DATA_T; -- Data Input + addr_i : in ADDRESS_S_T; -- Address Input + d_o : out DATA_T -- Data Output + ); +end entity p0300_m00103_s_v01_mem_s; + +-- +architecture p0300_mem_s_arch of p0300_m00103_s_v01_mem_s is + + signal addr_reg : ADDRESS_S_T; -- Address register + signal din_reg : DATA_T; + signal we_reg : std_logic; + signal s_ram : S_RAM_T; -- "s input" memory array + attribute logic_block : boolean; + attribute logic_block of s_ram : signal is true; + + +begin + + mem_s_proc: process (clk_i) + begin + if (clk_i'event and clk_i='1') then + if (we_reg = '1') then + s_ram(CONV_INTEGER(unsigned(addr_i))) <= din_reg; + end if; + addr_reg <= addr_i; + din_reg <= d_i; + we_reg <= we_i; + end if; + end process mem_s_proc; + d_o <= s_ram(CONV_INTEGER(unsigned(addr_reg))); + +end architecture p0300_mem_s_arch; + Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/00_README.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/00_README.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/00_README.txt (revision 8) @@ -0,0 +1,8 @@ +Your environment must point to a valid installation of Questasim. +You need Questasim to run all tests and features. +It was NOT tested with Modelsim DE/PE or SE (SE:2021.3 last version - Questasim since 2021.Q4) +Intel's Questa FPGA Edition runs well also. + +Run "sim_start" to run the pre-defined test bench "tb_avm_instruction_gen_v04_public.vhd" +located in folder /tb/vhdl/. + Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/01_sim_start.bat =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/01_sim_start.bat (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/01_sim_start.bat (revision 8) @@ -0,0 +1,2 @@ +rem Script to start the simulation +vsim -f 02_sim_args.txt Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/02_sim_args.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/02_sim_args.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/02_sim_args.txt (revision 8) @@ -0,0 +1 @@ + -do 04_tb_avm_instruction_gen_v04_public.do \ No newline at end of file Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/03_file_list.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/03_file_list.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/03_file_list.txt (revision 8) @@ -0,0 +1,19 @@ +"../rtl/vhdl/memory_vhd_v03_pkg.vhd" +"../rtl/vhdl/p0300_m00022_s_v02_cal_y_fsm.vhd" +"../rtl/vhdl/p0300_m00034_s_v01_for_loop_memwj_fsm.vhd" +"../rtl/vhdl/p0300_m00024_s_v02_test_fsm.vhd" +"../rtl/vhdl/p0300_m00026_s_v02_rd_wr_fsm.vhd" +"../rtl/vhdl/p0300_m00027_s_v01_train_fsm.vhd" +"../rtl/vhdl/p0300_m00028_s_v02_latency_fsm.vhd" +"../rtl/vhdl/p0300_m00021_s_v03_wishbone_fsm.vhd" +"../rtl/vhdl/p0300_m00033_s_v01_for_loop_memwi_fsm.vhd" +"../rtl/vhdl/p0300_m00023_s_v02_cal_w_fsm.vhd" +"../rtl/vhdl/p0300_m00025_s_v02_init_fsm.vhd" +"../rtl/vhdl/p0300_m00020_s_v03_perceptron_blk.vhd" +"../rtl/vhdl/p0300_m00103_s_v01_mem_s.vhd" +"../rtl/vhdl/p0300_m00101_m_v01_mem_t.vhd" +"../rtl/vhdl/p0300_m00102_s_v01_mem_w.vhd" +"../rtl/vhdl/p0300_m00100_s_v01_mem_gen_blk.vhd" +"../rtl/vhdl/p0300_m00000_s_v03_top_level_blk.vhd" + + Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/04_tb_avm_instruction_gen_v04_public.do =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/04_tb_avm_instruction_gen_v04_public.do (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/04_tb_avm_instruction_gen_v04_public.do (revision 8) @@ -0,0 +1,292 @@ +# generate foreign module declaration +onerror {resume} + +# create library +if [file exists {./work}] { + vdel -all {./work} +} +vlib {./work} + +# +# Add logical mapping >work< to the local design simulation library +# +vmap work {./work} + +#pwd + + +# +# Open debugging windows +# +quietly view * + +# +# Start and run simulation +# +set StdArithNoWarnings 1 +vcom -work "work" -nologo -2008 -F 03_file_list.txt +vcom -work "work" -nologo -93 ../tb/vhdl/tb_avm_instruction_gen_v04_public.vhd + +vsim -no_autoacc -L work -coverage -voptargs="+cover=bcesfx" -l transcript.txt -i -multisource_delay latest -t ns +typdelays work.tb_avm_instruction_gen_v04_public(testbench) + +assertion active +assertion profile on +assertion report -verbose + + +configure wave -namecolwidth 450 +#configure wave -valuecolwidth 145 +configure wave -valuecolwidth 120 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update + + +# View the results. +#if {![batch_mode]} { + + quietly add wave -divider TB_TOP_LEVEL + quietly add wave -expand /stream01 + quietly add wave -expand /stream02 + quietly add wave -group TB_TOP_LEVEL /* + + quietly add wave -divider TOP_LEVEL + quietly add wave -group TOP_LEVEL /u_0/* + + quietly add wave -divider PERCEPTRON + quietly add wave -group PERCEPTRON /u_0/u_0/* + + quietly add wave -divider WISHBONE + quietly add wave -group WISHBONE /u_0/u_0/u_14/* + + quietly add wave -divider FOR_LOOP_I + quietly add wave -group FOR_LOOP_I /u_0/u_0/u_2/* + + quietly add wave -divider FOR_LOOP_J + quietly add wave -group FOR_LOOP_J /u_0/u_0/u_1/* + + quietly add wave -divider CAL_Y + quietly add wave -group CAL_Y /u_0/u_0/u_0/* + + quietly add wave -divider CAL_W + quietly add wave -group CAL_W /u_0/u_0/u_8/* + + quietly add wave -divider INIT + quietly add wave -group INIT /u_0/u_0/u_9/* + + quietly add wave -divider TEST + quietly add wave -group TEST /u_0/u_0/u_10/* + + quietly add wave -divider READ_WRITE + quietly add wave -group READ_WRITE /u_0/u_0/u_11/* + + quietly add wave -divider TRAINING + quietly add wave -group TRAINING /u_0/u_0/u_12/* + + quietly add wave -divider LATENCY + quietly add wave -group LATENCY /u_0/u_0/u_13/* + + quietly add wave -divider S-MEMORY + quietly add wave -group S-MEMORY /u_0/u_1/u_0/* + + quietly add wave -divider T-MEMORY + quietly add wave -group T-MEMORY /u_0/u_1/u_1/* + + quietly add wave -divider Y-MEMORY + quietly add wave -group Y-MEMORY /u_0/u_1/u_2/* + + quietly add wave -divider BIAS-MEMORY + quietly add wave -group BIAS-MEMORY /u_0/u_1/u_3/* + + quietly add wave -divider W-MEMORY + quietly add wave -group W-MEMORY /u_0/u_1/u_4/* + + #quietly add wave -r /* + +#} + +run -all +quietly wave zoomfull +update + +#U_0/U_0/U_0 +coverage exclude -du p0300_m00022_s_v02_cal_y_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 \ + S07->S00 \ + S08->S00 \ + S09->S00 \ + S10->S00 \ + S11->S00 \ + S12->S00 \ + S13->S00 \ + S14->S00 \ + S15->S00 \ + S16->S00 + +#U_0/U_0/U_1 +coverage exclude -du p0300_m00034_s_v01_for_loop_memwj_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 + +#U_0/U_0/U_2 +coverage exclude -du p0300_m00033_s_v01_for_loop_memwi_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 + +#U_0/U_0/U_8 +coverage exclude -du p0300_m00023_s_v02_cal_w_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 \ + S07->S00 \ + S08->S00 \ + S09->S00 \ + S10->S00 \ + S11->S00 \ + S12->S00 \ + S13->S00 \ + S14->S00 \ + S15->S00 \ + S16->S00 + +#U_0/U_0/U_9 +coverage exclude -du p0300_m00025_s_v02_init_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 \ + S07->S00 \ + S08->S00 + +#U_0/U_0/U_10 +coverage exclude -du p0300_m00024_s_v02_test_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 \ + S07->S00 \ + S08->S00 \ + S09->S00 \ + S10->S00 \ + S11->S00 \ + S12->S00 \ + S13->S00 \ + S14->S00 \ + S15->S00 \ + S16->S00 \ + S17->S00 + +#U_0/U_0/U_11 +coverage exclude -du p0300_m00026_s_v02_rd_wr_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S12->S00 \ + S22->S00 \ + S32->S00 \ + S42->S00 \ + S03->S00 \ + S04->S00 + +#U_0/U_0/U_12 +coverage exclude -du p0300_m00027_s_v01_train_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 \ + S07->S00 \ + S08->S00 \ + S09->S00 \ + S10->S00 \ + S11->S00 \ + S12->S00 \ + S13->S00 + +#U_0/U_0/U_13 +coverage exclude -du p0300_m00028_s_v02_latency_fsm -ftrans current_state S01->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 \ + S07->S00 \ + S08->S00 \ + S09->S00 \ + S10->S00 \ + S11->S00 \ + SRDY->S00 \ + SERR->S00 + +#U_0/U_0/U_14 +coverage exclude -du p0300_m00021_s_v03_wishbone_fsm -ftrans current_state S01->S00 \ + S01a->S00 \ + S02->S00 \ + S03->S00 \ + S04->S00 \ + S05->S00 \ + S06->S00 \ + S07->S00 \ + S08->S00 \ + S09->S00 \ + S10->S00 \ + S11->S00 \ + S12->S00 \ + S13->S00 \ + S14->S00 \ + S15->S00 \ + S16->S00 \ + S17->S00 \ + S18->S00 \ + S19->S00 \ + S20->S00 \ + S21->S00 \ + S22->S00 \ + S23->S00 \ + S24->S00 \ + S25->S00 \ + S26->S00 \ + S27->S00 \ + S28->S00 \ + S29->S00 \ + S30->S00 \ + S31->S00 \ + S32->S00 \ + S33->S00 \ + S34->S00 \ + S35->S00 \ + S36->S00 \ + S37->S00 \ + S38->S00 \ + S39->S00 \ + S40->S00 \ + S41->S00 \ + S42->S00 \ + S43->S00 \ + S44->S00 \ + S45->S00 \ + S46->S00 \ + S47->S00 \ + S48->S00 + Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/11_wave_golden_20220721.do =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/11_wave_golden_20220721.do (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/11_wave_golden_20220721.do (revision 8) @@ -0,0 +1,541 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider TB_TOP_LEVEL +add wave -noupdate /tb_avm_instruction_gen_v04_public/stream01 +add wave -noupdate -height 29 /tb_avm_instruction_gen_v04_public/stream02 +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/clk_gen_o +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/rst_proc_o +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/rst_run_proc_o +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_adri_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_adro_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_dout_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_stb_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_cyc_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_we_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_ack_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_din_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_clear_epoch_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/tb_wb_thres_oi +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/done +add wave -noupdate -group TB_TOP_LEVEL -height 29 /tb_avm_instruction_gen_v04_public/stream02 +add wave -noupdate -group TB_TOP_LEVEL /tb_avm_instruction_gen_v04_public/stream01 +add wave -noupdate -divider TOP_LEVEL +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_adr_i +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_clk_i +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_cyc_i +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_dat_i +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_rst_i +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_stb_i +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_we_i +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/ctrl_int_o +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_ack_o +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/wb_dat_o +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/addr_i_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/addr_j_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dbias_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dout1_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dout2_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dout3_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dout4_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dout5_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dout7_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/ds_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dt_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dw_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/dy_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_bias2_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_bias3_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_bias5_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_s3_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_s4_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_s5_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_t3_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_t4_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_t5_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_w2_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_w3_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_w4_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_w5_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_w7_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_y1_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_y3_oi +add wave -noupdate -group TOP_LEVEL /tb_avm_instruction_gen_v04_public/U_0/we_y5_oi +add wave -noupdate -divider PERCEPTRON +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/clk_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dbias_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ds_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dt_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dw_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dy_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/rst_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/wb_adr_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/wb_cyc_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/wb_dat_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/wb_stb_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/wb_we_i +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/addr_i_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/addr_j_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_int_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dout1_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dout2_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dout3_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dout4_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dout5_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/dout7_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/wb_ack_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/wb_dat_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_bias2_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_bias3_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_bias5_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_s3_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_s4_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_s5_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_t3_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_t4_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_t5_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_w2_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_w3_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_w4_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_w5_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_w7_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_y1_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_y3_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/we_y5_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnt_alllat_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnteni1_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnteni2_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnteni3_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnteni4_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnteni5_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnteni7_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cntenj1_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cntenj2_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cntenj3_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cntenj4_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cntenj5_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cntenj7_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnti_end_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cnti_rdy_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cntj_end_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/cntj_rdy_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_bias_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_clear_epoch_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_complete_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_din_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_dout_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_dout_valid_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_epoch_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_int4_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_int6_o +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_maxepoch_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_memerr_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_not_rdy6_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_offset_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rd_vec_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rdlat_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rdy1_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rdy2_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rdy3_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rdy4_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rdy5_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rdy6_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_rdy7_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_run7_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_start1_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_start2_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_start3_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_start4_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_start5_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_start6_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_thres_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_wchgd_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_wr_vec_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/ctrl_wrlat_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/rst_n_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/set_initi_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/set_initj_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/starti_val_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/startj_val_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/stopi_val_oi +add wave -noupdate -group PERCEPTRON /tb_avm_instruction_gen_v04_public/U_0/U_0/stopj_val_oi +add wave -noupdate -divider WISHBONE +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/clk_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_alllat_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_complete_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_dout_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_dout_valid_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_epoch_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_int_test_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_int_train_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_memerr_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_not_rdy6_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rdlat_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rdy1_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rdy2_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rdy3_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rdy4_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rdy5_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rdy6_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_run7_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_wrlat_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/rst_n_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_adr_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_cyc_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_dat_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_stb_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_we_i +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_bias_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_clear_epoch_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_din_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_int_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_maxepoch_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_offset_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rd_vec_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_set_starti_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_set_startj_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_start3_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_start4_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_start5_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_start6_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_starti_val_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_startj_val_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_stopi_val_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_stopj_val_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_thres_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_wr_vec_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_ack_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_dat_o +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_bias_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_complete_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_din_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_int_en_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_int_test_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_int_train_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_maxepoch_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_offset_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rd_vec_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_rdy_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_starti_val_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_startj_val_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_stat_a_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_stopi_val_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_stopj_val_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_thres_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/ctrl_wr_vec_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_adr_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_cyc_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_dat_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_stb_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/wb_we_reg +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/zero_net_addrs +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/zero_net_addrt +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/current_state +add wave -noupdate -group WISHBONE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_14/next_state +add wave -noupdate -divider FOR_LOOP_I +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/clk_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnten1_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnten2_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnten3_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnten4_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnten5_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnten7_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/rst_n_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/set_init_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/start_vali_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/stop_vali_i +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnt_end_o +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnt_rdy_o +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnt_val_o +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnt_end_reg +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnt_reg +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/cnten_reg +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/set_init_reg +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/current_state +add wave -noupdate -group FOR_LOOP_I /tb_avm_instruction_gen_v04_public/U_0/U_0/U_2/next_state +add wave -noupdate -divider FOR_LOOP_J +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/clk_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnten1_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnten2_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnten3_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnten4_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnten5_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnten7_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/rst_n_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/set_init_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/start_valj_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/stop_valj_i +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnt_end_o +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnt_rdy_o +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnt_val_o +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnt_end_reg +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnt_reg +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/cnten_reg +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/set_init_reg +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/current_state +add wave -noupdate -group FOR_LOOP_J /tb_avm_instruction_gen_v04_public/U_0/U_0/U_1/next_state +add wave -noupdate -divider CAL_Y +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/clk_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/cnti_end_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/cntj_end_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_rdlat_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_rdy7_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_start_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_thres_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_wrlat_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/dbias_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ds_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/dw_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/rst_n_i +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/cnteni_o +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/cntenj_o +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_rdy_o +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/dout_o +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/we_y_o +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_rdlat_reg +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_start_reg +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/ctrl_wrlat_reg +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/dbias_reg +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/dw_reg +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/y_inj_reg +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/current_state +add wave -noupdate -group CAL_Y /tb_avm_instruction_gen_v04_public/U_0/U_0/U_0/next_state +add wave -noupdate -divider CAL_W +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/clk_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/cnti_end_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/cntj_end_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_rdlat_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_rdy7_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_start_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_wrlat_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/dbias_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ds_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/dt_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/dw_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/dy_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/rst_n_i +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/cnteni_o +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/cntenj_o +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_rdy_o +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_wchgd_o +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/dout_o +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/we_bias_o +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/we_w_o +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_rdlat_reg +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_start_reg +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_wchgd_reg +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/ctrl_wrlat_reg +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/dbias_reg +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/dt_reg +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/dw_reg +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/current_state +add wave -noupdate -group CAL_W /tb_avm_instruction_gen_v04_public/U_0/U_0/U_8/next_state +add wave -noupdate -divider INIT +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/clk_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/cnti_end_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/cntj_end_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_bias_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_rdlat_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_rdy7_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_start_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_wrlat_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/rst_n_i +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/cnteni_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/cntenj_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_rdy_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/dout_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/we_bias_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/we_s_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/we_t_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/we_w_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/we_y_o +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_rdlat_reg +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_start_reg +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/ctrl_wrlat_reg +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/current_state +add wave -noupdate -group INIT /tb_avm_instruction_gen_v04_public/U_0/U_0/U_9/next_state +add wave -noupdate -divider TEST +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/clk_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/cnti_end_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/cntj_end_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_rdlat_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_rdy7_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_start_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_wrlat_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ds_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/dt_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/dw_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/offset_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/rst_n_i +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/cnteni_o +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/cntenj_o +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_int_o +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_rdy_o +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/dout_o +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/we_s_o +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/we_t_o +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/we_w_o +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_int_reg +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_rdlat_reg +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_start_reg +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/ctrl_wrlat_reg +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/dt_reg +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/dw_reg +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/current_state +add wave -noupdate -group TEST /tb_avm_instruction_gen_v04_public/U_0/U_0/U_10/next_state +add wave -noupdate -divider READ_WRITE +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/clk_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/cnti_end_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/cntj_end_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_din_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_rd_vec_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_rdlat_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_rdy7_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_start_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_wr_vec_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_wrlat_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/dbias_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ds_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/dt_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/dw_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/dy_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/rst_n_i +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/cnteni_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/cntenj_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_complete_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_dout_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_dout_valid_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_rdy_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/dout_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/we_bias_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/we_s_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/we_t_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/we_w_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/we_y_o +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_complete_reg +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_dout_reg +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_dout_valid_reg +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_rdlat_reg +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_start_reg +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/ctrl_wrlat_reg +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/current_state +add wave -noupdate -group READ_WRITE /tb_avm_instruction_gen_v04_public/U_0/U_0/U_11/next_state +add wave -noupdate -divider TRAINING +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/clk_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/cnti_rdy_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/cntj_rdy_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_clear_epoch_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_maxepoch_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_rdy1_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_rdy2_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_rdy7_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_start_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_wchgd_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/rst_n_i +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_epoch_o +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_int_o +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_not_rdy_o +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_rdy_o +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_start1_o +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_start2_o +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/cnti_rdy_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/cntj_rdy_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_clear_epoch_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_epoch_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_int_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_not_rdy_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_rdy1_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_rdy2_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/ctrl_start_reg +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/current_state +add wave -noupdate -group TRAINING /tb_avm_instruction_gen_v04_public/U_0/U_0/U_12/next_state +add wave -noupdate -divider LATENCY +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/clk_i +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/dw_i +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/rst_n_i +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/cnt_alllat_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/cnteni_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/cntenj_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_memerr_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_rdlat_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_rdy_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_run_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_wrlat_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/dout_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/we_w_o +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/cnt_alllat_reg +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_memerr_reg +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_rdlat_reg +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_rdy_reg +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_run_reg +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/ctrl_wrlat_reg +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/dw_reg +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/current_state +add wave -noupdate -group LATENCY /tb_avm_instruction_gen_v04_public/U_0/U_0/U_13/next_state +add wave -noupdate -divider S-MEMORY +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/clk_i +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/we_i +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/d_i +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/addr_i +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/d_o +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/addr_reg +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/din_reg +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/we_reg +add wave -noupdate -group S-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_0/s_ram +add wave -noupdate -divider T-MEMORY +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/clk_i +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/we_i +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/d_i +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/addr_i +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/d_o +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/addr_reg +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/din_reg +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/we_reg +add wave -noupdate -group T-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_1/t_ram +add wave -noupdate -divider Y-MEMORY +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/clk_i +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/we_i +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/d_i +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/addr_i +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/d_o +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/addr_reg +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/din_reg +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/we_reg +add wave -noupdate -group Y-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_2/t_ram +add wave -noupdate -divider BIAS-MEMORY +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/clk_i +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/we_i +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/d_i +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/addr_i +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/d_o +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/addr_reg +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/din_reg +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/we_reg +add wave -noupdate -group BIAS-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_3/t_ram +add wave -noupdate -divider W-MEMORY +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/clk_i +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/we_i +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/d_i +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/addr_i +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/d_o +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/addr_reg +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/din_reg +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/we_reg +add wave -noupdate -group W-MEMORY /tb_avm_instruction_gen_v04_public/U_0/U_1/U_4/w_ram +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ns} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 450 +configure wave -valuecolwidth 120 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ns} {753333 ns} Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/answer.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/answer.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/answer.txt (revision 8) @@ -0,0 +1,64 @@ +0,00000004,1,00000000,1,0000001C,-1 +1,0000000E,1,0000000E,-1,0000000E,-1 +2,00000006,-1,0000000E,1,0000000E,-1 +3,00000004,1,00000000,1,00000000,1 +4,0000000E,1,0000000E,-1,0000002A,-1 +5,00000018,1,0000001C,-1,0000001C,-1 +6,00000004,1,00000000,1,0000001C,-1 +7,0000000E,1,0000000E,-1,0000000E,-1 +8,00000006,-1,0000000E,1,0000000E,-1 +9,00000004,1,00000000,1,00000000,1 +10,00000010,-1,0000001C,1,00000000,1 +11,00000006,-1,0000000E,1,0000000E,1 +12,00000004,1,00000000,1,0000001C,-1 +13,0000000E,1,0000000E,-1,0000000E,-1 +14,00000006,-1,0000000E,1,0000000E,-1 +15,00000004,1,00000000,1,00000000,1 +16,0000000E,1,0000000E,-1,0000000E,-1 +17,00000018,1,0000001C,-1,00000000,1 +18,00000004,1,00000000,1,00000000,1 +19,0000000E,1,0000000E,-1,0000000E,1 +20,00000018,1,0000001C,-1,0000001C,-1 +21,00000022,1,0000002A,-1,0000000E,-1 +22,0000000E,1,0000000E,-1,0000000E,-1 +23,00000018,1,0000001C,-1,00000000,1 +24,00000004,1,00000000,1,00000000,1 +25,0000000E,1,0000000E,-1,0000000E,1 +26,00000006,-1,0000000E,1,0000000E,1 +27,00000004,1,00000000,1,0000001C,1 +28,0000000E,1,0000000E,-1,0000000E,-1 +29,00000018,1,0000001C,-1,00000000,1 +30,00000004,1,00000000,1,00000000,1 +31,0000000E,1,0000000E,-1,0000000E,1 +32,0000000E,-1,0000000E,1,0000000E,-1 +33,00000004,-1,00000000,1,00000000,1 +34,00000018,-1,0000001C,1,00000000,1 +35,0000000E,-1,0000000E,1,0000000E,1 +36,00000004,-1,00000000,1,0000001C,-1 +37,00000006,1,0000000E,-1,0000000E,-1 +38,0000000E,-1,0000000E,1,0000000E,-1 +39,00000004,-1,00000000,1,00000000,1 +40,00000018,-1,0000001C,1,00000000,1 +41,0000000E,-1,0000000E,1,0000000E,1 +42,00000022,-1,0000002A,1,0000000E,1 +43,00000018,-1,0000001C,1,0000001C,1 +44,0000000E,-1,0000000E,1,0000000E,-1 +45,00000004,-1,00000000,1,00000000,1 +46,00000018,-1,0000001C,1,00000000,1 +47,0000000E,-1,0000000E,1,0000000E,1 +48,00000004,-1,00000000,1,00000000,1 +49,00000006,1,0000000E,-1,0000000E,1 +50,0000000E,-1,0000000E,1,0000000E,1 +51,00000004,-1,00000000,1,0000001C,1 +52,00000006,1,0000000E,-1,0000000E,-1 +53,00000010,1,0000001C,-1,00000000,1 +54,00000004,-1,00000000,1,00000000,1 +55,00000006,1,0000000E,-1,0000000E,1 +56,0000000E,-1,0000000E,1,0000000E,1 +57,00000004,-1,00000000,1,0000001C,1 +58,00000018,-1,0000001C,1,0000001C,1 +59,0000000E,-1,0000000E,1,0000002A,1 +60,00000004,-1,00000000,1,00000000,1 +61,00000006,1,0000000E,-1,0000000E,1 +62,0000000E,-1,0000000E,1,0000000E,1 +63,00000004,-1,00000000,1,0000001C,1 Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/bias_memory_up_down.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/bias_memory_up_down.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/bias_memory_up_down.txt (revision 8) @@ -0,0 +1,4 @@ +-- BIAS-Memory content for UP/DOWN/STOP pattern +00000000000000000000000000000110 +00000000000000000000000000001000 +00000000000000000000000000001000 Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/modelsim.ini =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/modelsim.ini (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/modelsim.ini (revision 8) @@ -0,0 +1,2191 @@ +[Version] +INIVersion = "2021.1" + +; Copyright 1991-2021 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = ./work +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset " syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = [,]{:[,]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = [ ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for automatically checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, the solver will abort with an error. +; The default value is 10000. The maximum value is 10000000. A value of 0 is +; equivalent to specifying the maximum value. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-][,[+|-]]*" +' Valid settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Switch to specify options that control the behavior of the solver profiler.. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate testcases for profiled randsets (only when randsets option is enabled) (default is off) +; SolverFProf = [+|-][,[+|-]*] + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Enable/disable non-LRM compliant SystemVerilog language extensions. +; Valid extensions are: +; altdpiheader - Alternative style function signature generated in DPI header", +; cfce - generate an error if $cast fails as a function +; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') +; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks +; expdfmt - enable format string extensions for $display/$sformatf +; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) +; fmtcap - prints capital hex digits with %X/%H in display calls +; iddp - ignore DPI disable protocol check +; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") +; noexptc - ignore DPI export type name overloading check +; realrand - support randomize() with real variables and constraints (Default) +; SvExtensions = [+|-][,[+|-]*] + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; funcback - enable function backtracking (ACT only) +; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) +; impvecindex - inject constraints on random indices of 2-state vectors +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; pathseed - enable unique seeding of module instances based on hierarchical path name +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; strictstab - strict random stability +; SvRandExtensions = [+|-][,[+|-]*] + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L limits the output to lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C limits the output to characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/outimgvhdl.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/outimgvhdl.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/outimgvhdl.txt (revision 8) @@ -0,0 +1,768 @@ +-- Pattern Number: 0 000000 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 1 000001 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 2 000010 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 3 000011 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 4 000100 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 5 000101 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 6 000110 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 7 000111 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 8 001000 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 9 001001 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 10 001010 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 11 001011 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 12 001100 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 13 001101 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 14 001110 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 15 001111 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 16 010000 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 17 010001 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 18 010010 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 19 010011 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 20 010100 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 21 010101 UP +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 22 010110 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 23 010111 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 24 011000 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 25 011001 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 26 011010 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 27 011011 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 28 011100 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 29 011101 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 30 011110 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 31 011111 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 32 100000 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 33 100001 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 34 100010 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 35 100011 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 36 100100 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 37 100101 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 38 100110 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 39 100111 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 40 101000 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 41 101001 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 42 101010 DOWN +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Pattern Number: 43 101011 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 44 101100 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 45 101101 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 46 101110 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 47 101111 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 48 110000 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 49 110001 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 50 110010 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 51 110011 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 52 110100 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 53 110101 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 54 110110 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 55 110111 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 56 111000 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 57 111001 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 58 111010 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 59 111011 STOP +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Pattern Number: 60 111100 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 61 111101 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 62 111110 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Pattern Number: 63 111111 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/test.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/test.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/test.txt (revision 8) @@ -0,0 +1,640 @@ +-- Pattern Number: 0 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 11111111111111111111111111100100 +-- Pattern Number: 1 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 11111111111111111111111111110010 +-- Pattern Number: 2 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111010 00000000000000000000000000001110 11111111111111111111111111110010 +-- Pattern Number: 3 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 4 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 11111111111111111111111111010110 +-- Pattern Number: 5 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000011000 11111111111111111111111111100100 11111111111111111111111111100100 +-- Pattern Number: 6 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 11111111111111111111111111100100 +-- Pattern Number: 7 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 11111111111111111111111111110010 +-- Pattern Number: 8 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111010 00000000000000000000000000001110 11111111111111111111111111110010 +-- Pattern Number: 9 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 10 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111110000 00000000000000000000000000011100 00000000000000000000000000000000 +-- Pattern Number: 11 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111010 00000000000000000000000000001110 00000000000000000000000000001110 +-- Pattern Number: 12 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 11111111111111111111111111100100 +-- Pattern Number: 13 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 11111111111111111111111111110010 +-- Pattern Number: 14 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111010 00000000000000000000000000001110 11111111111111111111111111110010 +-- Pattern Number: 15 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 16 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 11111111111111111111111111110010 +-- Pattern Number: 17 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000011000 11111111111111111111111111100100 00000000000000000000000000000000 +-- Pattern Number: 18 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 19 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 00000000000000000000000000001110 +-- Pattern Number: 20 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000011000 11111111111111111111111111100100 11111111111111111111111111100100 +-- Pattern Number: 21 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000100010 11111111111111111111111111010110 11111111111111111111111111110010 +-- Pattern Number: 22 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 11111111111111111111111111110010 +-- Pattern Number: 23 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000011000 11111111111111111111111111100100 00000000000000000000000000000000 +-- Pattern Number: 24 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 25 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 00000000000000000000000000001110 +-- Pattern Number: 26 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +11111111111111111111111111111010 00000000000000000000000000001110 00000000000000000000000000001110 +-- Pattern Number: 27 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 00000000000000000000000000011100 +-- Pattern Number: 28 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 11111111111111111111111111110010 +-- Pattern Number: 29 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000011000 11111111111111111111111111100100 00000000000000000000000000000000 +-- Pattern Number: 30 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000000100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 31 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +-- Answer +00000000000000000000000000001110 11111111111111111111111111110010 00000000000000000000000000001110 +-- Pattern Number: 32 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 11111111111111111111111111110010 +-- Pattern Number: 33 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 34 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111101000 00000000000000000000000000011100 00000000000000000000000000000000 +-- Pattern Number: 35 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 00000000000000000000000000001110 +-- Pattern Number: 36 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 11111111111111111111111111100100 +-- Pattern Number: 37 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +00000000000000000000000000000110 11111111111111111111111111110010 11111111111111111111111111110010 +-- Pattern Number: 38 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 11111111111111111111111111110010 +-- Pattern Number: 39 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 40 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111101000 00000000000000000000000000011100 00000000000000000000000000000000 +-- Pattern Number: 41 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 00000000000000000000000000001110 +-- Pattern Number: 42 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111011110 00000000000000000000000000101010 00000000000000000000000000001110 +-- Pattern Number: 43 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111101000 00000000000000000000000000011100 00000000000000000000000000011100 +-- Pattern Number: 44 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 11111111111111111111111111110010 +-- Pattern Number: 45 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 46 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111101000 00000000000000000000000000011100 00000000000000000000000000000000 +-- Pattern Number: 47 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 00000000000000000000000000001110 +-- Pattern Number: 48 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 49 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +00000000000000000000000000000110 11111111111111111111111111110010 00000000000000000000000000001110 +-- Pattern Number: 50 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 00000000000000000000000000001110 +-- Pattern Number: 51 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000011100 +-- Pattern Number: 52 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +00000000000000000000000000000110 11111111111111111111111111110010 11111111111111111111111111110010 +-- Pattern Number: 53 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +00000000000000000000000000010000 11111111111111111111111111100100 00000000000000000000000000000000 +-- Pattern Number: 54 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 55 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +00000000000000000000000000000110 11111111111111111111111111110010 00000000000000000000000000001110 +-- Pattern Number: 56 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 00000000000000000000000000001110 +-- Pattern Number: 57 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000011100 +-- Pattern Number: 58 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111101000 00000000000000000000000000011100 00000000000000000000000000011100 +-- Pattern Number: 59 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 00000000000000000000000000101010 +-- Pattern Number: 60 +-- Components +11111111111111111111111111111111 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000000000 +-- Pattern Number: 61 +-- Components +00000000000000000000000000000001 +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +00000000000000000000000000000110 11111111111111111111111111110010 00000000000000000000000000001110 +-- Pattern Number: 62 +-- Components +11111111111111111111111111111111 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111110010 00000000000000000000000000001110 00000000000000000000000000001110 +-- Pattern Number: 63 +-- Components +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +00000000000000000000000000000001 +-- Answer +11111111111111111111111111111100 00000000000000000000000000000000 00000000000000000000000000011100 Index: neural_net_perceptron/trunk/neural_net_perceptron/sim/w_memory_up_down.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/sim/w_memory_up_down.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/sim/w_memory_up_down.txt (revision 8) @@ -0,0 +1,19 @@ +-- W-Memory content for UP/DOWN/STOP pattern +00000000000000000000000000000101 +11111111111111111111111111111011 +00000000000000000000000000000101 +11111111111111111111111111111011 +00000000000000000000000000000101 +11111111111111111111111111110111 +11111111111111111111111111111001 +00000000000000000000000000000111 +11111111111111111111111111111001 +00000000000000000000000000000111 +11111111111111111111111111111001 +00000000000000000000000000000111 +00000000000000000000000000000111 +00000000000000000000000000000111 +11111111111111111111111111111001 +00000000000000000000000000000111 +00000000000000000000000000000111 +00000000000000000000000000000111 Index: neural_net_perceptron/trunk/neural_net_perceptron/tb/vhdl/README.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/tb/vhdl/README.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/tb/vhdl/README.txt (revision 8) @@ -0,0 +1,16 @@ +This test bench "tb_avm_instruction_gen_v04_public.vhd" is only for your information. +First, its doing some tests (e.g. from early stage of development) and implement a +transaction environment to document each stage of testing while simulation. + +Its do a setup, training and testing of the sample application (look at +the core's specification /doc/specification_NN_Perceptron_v01_20220720 +"Appendix B - Sample Application" for detailed information) too. + +Files are written to the file system while simulation too (work folder) as described +in Appendix B. + +Take a closer look at these files and find out more by yourself. +More information about scoreboards, simulation, verification and requirement +tracing of this core are NOT public. + +opencores@vivare-services.com Index: neural_net_perceptron/trunk/neural_net_perceptron/tb/vhdl/tb_avm_instruction_gen_v04_public.vhd =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/tb/vhdl/tb_avm_instruction_gen_v04_public.vhd (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/tb/vhdl/tb_avm_instruction_gen_v04_public.vhd (revision 8) @@ -0,0 +1,1157 @@ +-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland +-- (email: opencores@vivare-services.com) +-- +-- This program is free software: you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any +-- later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- +-- ************************************** +-- +-- File: tb_avm_instruction_gen_v04.vhd +-- +-- Version: 4.0 +-- Date: 20.Jul.2022 +-- Author: Jens Gutschmidt / opencores@vivare-services.com +-- Cause: Adoptions for public +-- +-- THIS TEST BENCH IS ONLY FOR INFORMATION. +-- IT CONTAINS TESTS FOR SYMANTIC EXPERIMENTS AND OTHER NON-PROJECT +-- RELATED STUFF. +-- USE IT ON OWN RISC !!! +-- ************************************** + +USE std.textio.all; + +LIBRARY work; +USE work.memory_vhd_v03_pkg.ALL; + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_textio.all; + +LIBRARY modelsim_lib; +USE modelsim_lib.transactions.all; + +ENTITY tb_avm_instruction_gen_v04_public IS +END ENTITY tb_avm_instruction_gen_v04_public; + +-- +ARCHITECTURE testbench OF tb_avm_instruction_gen_v04_public IS + + -- Component Declarations + COMPONENT p0300_m00000_s_v03_top_level_blk + PORT ( + wb_clk_i : IN std_logic ; + wb_rst_i : IN std_logic ; + wb_adr_i : IN WB_ADDR_WIDTH_T ; + wb_dat_i : IN WB_DATA_WIDTH_T ; + wb_stb_i : IN std_logic ; + wb_cyc_i : IN std_logic ; + wb_we_i : IN std_logic ; + + wb_ack_o : OUT std_logic ; + wb_dat_o : OUT WB_DATA_WIDTH_T + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : p0300_m00000_s_v03_top_level_blk USE ENTITY work.p0300_m00000_s_v03_top_level_blk; + -- pragma synthesis_on + + + signal clk_gen_o : std_ulogic := '0'; + signal rst_proc_o : std_ulogic := '0'; +-- signal res_proc_o_i : std_ulogic := '0'; + signal rst_run_proc_o : std_logic; + + -- WN internal signals + signal tb_wb_adri_oi : WB_ADDR_WIDTH_T ; + signal tb_wb_adro_oi : WB_ADDR_WIDTH_T := (others => '0') ; +-- signal tb_wb_adro_oi : WB_ADDR_WIDTH_T ; + signal tb_wb_dout_oi : WB_DATA_WIDTH_T ; + signal tb_wb_stb_oi : std_logic := '0' ; + signal tb_wb_cyc_oi : std_logic := '0' ; + signal tb_wb_we_oi : std_logic := '0' ; + + signal tb_wb_ack_oi : std_logic ; + signal tb_wb_din_oi : WB_DATA_WIDTH_T ; + signal tb_wb_clear_epoch_oi : WB_DATA_WIDTH_T ; + signal tb_wb_thres_oi : WB_DATA_WIDTH_T ; + -- //////////////////////////////////////////////////////// + + signal done : boolean := FALSE; + + constant PERIOD : Time := 20 ns; + constant PD : Time := 0 ns; + + constant PLUS_ONE : integer := 1; + constant MINUS_ONE : integer := -1; + +BEGIN + tb_avm_test: process + variable count_pattern : integer; + variable count_loop : integer; + variable count_data : integer; + + variable hStream02 : TrStream := create_transaction_stream("stream02", "transaction"); + variable hStream01 : TrStream := create_transaction_stream("stream01", "transaction2"); + + variable hTrans01 : TrTransaction := 0; + variable hTrans02 : TrTransaction := 0; + variable hTrans03 : TrTransaction := 0; + variable hTrans04 : TrTransaction := 0; + + variable loop_finished : boolean := FALSE; + variable loop_finished_a : boolean := FALSE; + variable wb_adr_oi : WB_ADDR_WIDTH_T ; + + variable mem_matrix_i_len : integer := 6; + variable mem_matrix_j_len : integer := 3; + type tb_s_mem_t is array ( 0 to ( mem_matrix_i_len - 1 ) ) of integer; -- + type tb_t_mem_t is array ( 0 to ( mem_matrix_j_len - 1 ) ) of integer; -- + type tb_w_mem_t is array ( 0 to ( mem_matrix_i_len * mem_matrix_j_len ) - 1 ) of integer; -- matrix 3 x 2 + + variable tb_s_mem : tb_s_mem_t; + variable tb_t_mem : tb_t_mem_t; + variable tb_w_mem : tb_w_mem_t; + + file outfile : text is out "outimgvhdl.txt"; + file outfile_w : text is out "w_memory_up_down.txt"; + file outfile_bias : text is out "bias_memory_up_down.txt"; + file outfile_test : text is out "test.txt"; + file outfile_answer : text is out "answer.txt"; + variable buff_out : line; --line number declaration + variable buff_out_answer : line; --line number declaration + variable component_lv : std_logic_vector ( mem_matrix_i_len - 1 downto 0 ); + + +-- ////////////////////////////////////////*\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ +-- /////////////////////////////////// WB READ \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ +-- ////////////////////////////////////////*\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ + procedure wb_read_proc_bfm + ( + signal clk_i : IN std_logic ; + signal wb_ack_i : IN std_logic ; + constant wb_adr_i : IN WB_ADDR_WIDTH_T ; + constant wb_dat_o : IN WB_DATA_WIDTH_T ; + + signal wb_adr_o : OUT WB_ADDR_WIDTH_T ; + signal wb_stb_o : OUT std_logic ; + signal wb_cyc_o : OUT std_logic ; + signal wb_we_o : OUT std_logic + ) is + begin + hTrans02 := begin_transaction(hStream02, "WB-READ"); + add_color(hTrans02, "green yellow"); + add_attribute(hTrans02, wb_adr_i, "wb_adr"); + + wb_adr_o <= wb_adr_i after PD; + wb_we_o <= '0' after PD; + wb_stb_o <= '1' after PD; + wb_cyc_o <= '1' after PD; + wait until clk_i'event and clk_i = '1' and wb_ack_i = '1'; +-- wb_stb_o <= '0' after PD; +-- wb_cyc_o <= '0' after PD; + wb_stb_o <= '0'; + wb_cyc_o <= '0'; +-- wait until clk_i'event and clk_i = '1'; + add_attribute(hTrans02, wb_dat_o, "wb_dat_o"); +-- wait until clk_i'event and clk_i = '1'; + + end_transaction(hTrans02); + free_transaction(hTrans02); + end wb_read_proc_bfm; +-- ********************************************************************************* + +-- ////////////////////////////////////////*\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ +-- /////////////////////////////////// WB WRITE \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ +-- ////////////////////////////////////////*\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ + procedure wb_write_proc_bfm + ( + signal clk_i : IN std_logic ; + signal wb_ack_i : IN std_logic ; + constant wb_adr_i : IN WB_ADDR_WIDTH_T ; + constant wb_dat_i : IN WB_DATA_WIDTH_T ; + + signal wb_adr_o : OUT WB_ADDR_WIDTH_T ; + signal wb_dat_o : OUT WB_DATA_WIDTH_T ; + signal wb_stb_o : OUT std_logic ; + signal wb_cyc_o : OUT std_logic ; + signal wb_we_o : OUT std_logic + ) is + begin + hTrans02 := begin_transaction(hStream02, "WB-WRITE"); + add_color(hTrans02, "thistle"); + add_attribute(hTrans02, wb_adr_i, "wb_adr"); + add_attribute(hTrans02, wb_dat_i, "wb_dat_i"); + + wb_adr_o <= wb_adr_i after PD; + wb_dat_o <= wb_dat_i after PD; + wb_we_o <= '1' after PD; + wb_stb_o <= '1' after PD; + wb_cyc_o <= '1' after PD; + wait until clk_i'event and clk_i = '1' and wb_ack_i = '1'; +-- wb_we_o <= '0' after PD; +-- wb_stb_o <= '0' after PD; +-- wb_cyc_o <= '0' after PD; + wb_we_o <= '0'; + wb_stb_o <= '0'; + wb_cyc_o <= '0'; +-- wait until clk_i'event and clk_i = '1'; +-- wait until clk_i'event and clk_i = '1'; + + end_transaction(hTrans02); + free_transaction(hTrans02); + end wb_write_proc_bfm; +-- ********************************************************************************* + +-- ////////////////////////////////////////*\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ +-- //////////////////////////////// WB READ READY \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ +-- ////////////////////////////////////////*\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ + procedure wb_read_ready_proc_bfm + ( + signal clk_i : IN std_logic ; + signal wb_ack_i : IN std_logic ; + constant wb_adr_i : IN WB_ADDR_WIDTH_T ; + constant wb_dat_o : IN WB_DATA_WIDTH_T ; + + signal wb_adr_o : OUT WB_ADDR_WIDTH_T ; + signal wb_stb_o : OUT std_logic ; + signal wb_cyc_o : OUT std_logic ; + signal wb_we_o : OUT std_logic + ) is + begin + + hTrans02 := begin_transaction(hStream02, "WB-READ-READY"); + add_color(hTrans02, "yellow"); + add_attribute(hTrans02, wb_adr_i, "wb_adr"); + + wb_adr_o <= wb_adr_i after PD; + wb_we_o <= '0' after PD; + wb_stb_o <= '1' after PD; + wb_cyc_o <= '1' after PD; + wait until clk_i'event and clk_i = '1' and wb_ack_i = '1'; +-- wb_stb_o <= '0' after PD; +-- wb_cyc_o <= '0' after PD; + wb_stb_o <= '0'; + wb_cyc_o <= '0'; +-- wait until clk_i'event and clk_i = '1'; + add_attribute(hTrans02, wb_dat_o, "wb_dat_o"); +-- wait until clk_i'event and clk_i = '1'; + + end_transaction(hTrans02); + free_transaction(hTrans02); + end wb_read_ready_proc_bfm; +-- ********************************************************************************* + + begin + count_loop := 0 ; + tb_wb_adri_oi <= (others => '0') ; + tb_wb_din_oi <= (others => '0') ; + tb_wb_thres_oi <= X"00000025" ; + + hTrans01 := begin_transaction(hStream01, "RESET"); + add_color(hTrans01, "blue"); + + wait until clk_gen_o'event and clk_gen_o = '0'; + rst_proc_o <= '1' after PD; + wait until clk_gen_o'event and clk_gen_o = '1'; + wait until clk_gen_o'event and clk_gen_o = '1'; + wait until clk_gen_o'event and clk_gen_o = '1'; -- delay for 3 clks to init. + rst_proc_o <= '0' after PD; + + end_transaction(hTrans01); + free_transaction(hTrans01); + +-- ************************************************************************* + + hTrans01 := begin_transaction ( hStream01, "First_WB_Test" ); + add_color ( hTrans01, "green" ); + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + +-- READ All Latency Register, tb_wb_adri_oi <= "01110", d14, 0x0E + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_ALLLAT, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + +-- WRITE Threshold Register, tb_wb_adri_oi <= "00001", d01, 0x01 + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_THRES, WB_ADDR_WIDTH ) ) , + tb_wb_thres_oi , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + +-- READ Threshold Register, tb_wb_adri_oi <= "00001", d01, 0x01 + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_THRES, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + +-- WRITE Bias Register + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_BIAS, WB_ADDR_WIDTH ) ) , + X"00000001" , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + +-- READ Bias Register + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_BIAS, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + end_transaction(hTrans01); + free_transaction(hTrans01); + + hTrans01 := begin_transaction ( hStream01, "Wait_for_core_is_ready" ); + add_color ( hTrans01, "yellow" ); + +-- READ Status Register, tb_wb_adri_oi <= "00000" + wb_read_ready_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STARTI, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + hTrans01 := begin_transaction ( hStream01, "Start_Stop_values" ); + add_color ( hTrans01, "cyan" ); + +-- WRITE STARTI Register, tb_wb_adri_oi <= "00111" + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STARTI, WB_ADDR_WIDTH ) ) , + X"00000000" , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + +-- WRITE STARTJ Register, tb_wb_adri_oi <= "01001" + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STARTJ, WB_ADDR_WIDTH ) ) , + X"00000000" , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + +-- WRITE STOPI Register, tb_wb_adri_oi <= "01000" + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STOPI, WB_ADDR_WIDTH ) ) , + std_logic_vector ( conv_unsigned ( mem_matrix_i_len-1, WB_DATA_WIDTH ) ) , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + +-- WRITE STOPJ Register, tb_wb_adri_oi <= "01010" + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STOPJ, WB_ADDR_WIDTH ) ) , + std_logic_vector ( conv_unsigned ( mem_matrix_j_len-1, WB_DATA_WIDTH ) ) , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + hTrans01 := begin_transaction ( hStream01, "Wait_for_READY" ); + add_color ( hTrans01, "white" ); + + wb_adr_oi := "00000"; + loop_finished := FALSE; + while ( NOT loop_finished ) loop + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + wb_adr_oi , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + if ( (tb_wb_dout_oi (STAT_RDY) = '1') ) then + loop_finished := TRUE; + end if; + + end loop; + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + + hTrans01 := begin_transaction ( hStream01, "WRITE-W-Memory_until_end" ); + add_color ( hTrans01, "orange" ); + +-- READ W-MEM, tb_wb_adri_oi <= "10011" + count_data := 0; + count_loop := 0; + loop_finished_a := FALSE; + + while ( NOT loop_finished_a ) loop + + tb_w_mem (count_loop) := count_data; + +-- WRITE W-MEM + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START5_W, WB_ADDR_WIDTH ) ) , + std_logic_vector ( conv_unsigned ( count_data, WB_DATA_WIDTH ) ) , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_data := count_data + 1 ; + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi (STAT_RD_WR_COMPLETE) = '1') ) then + loop_finished_a := TRUE; + end if; + + end loop; + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + hTrans01 := begin_transaction ( hStream01, "READ-W-Memory_until_end" ); + add_color ( hTrans01, "yellow" ); + +-- READ W-MEM, tb_wb_adri_oi <= "10011" + count_loop := 0; + loop_finished_a := FALSE; + while ( NOT loop_finished_a ) loop + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START5_W, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + if ( NOT (tb_wb_dout_oi = std_logic_vector ( conv_unsigned ( tb_w_mem (count_loop), WB_DATA_WIDTH ) )) ) then + loop_finished_a := TRUE; + hTrans04 := begin_transaction ( hStream02, "READ-W-Memory_MISMATCH" ); + add_color ( hTrans04, "red" ); + add_attribute ( hTrans04, tb_wb_dout_oi, "exp_tb_wb_dout_oi" ); + add_attribute ( hTrans04, std_logic_vector ( conv_unsigned ( tb_w_mem (count_loop), WB_DATA_WIDTH ) ), "rd_tb_wb_dout_oi" ); + + wait for 100ns; + end_transaction ( hTrans04 ); + free_transaction ( hTrans04 ); + + end if; + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi ( STAT_RD_WR_COMPLETE) = '1' ) ) then + loop_finished_a := TRUE; + end if; + + end loop; + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + hTrans01 := begin_transaction ( hStream01, "Start_INIT_Process" ); + add_color ( hTrans01, "medium sea green" ); + + loop_finished_a := FALSE; + +-- INIT + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START3, WB_ADDR_WIDTH ) ) , + X"00000000" , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + while ( NOT loop_finished_a ) loop + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + if ( (tb_wb_dout_oi ( STAT_RDY) = '1' ) ) then + loop_finished_a := TRUE; + end if; + + end loop; + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + hTrans01 := begin_transaction ( hStream01, "Enable_Interrupt" ); + add_color ( hTrans01, "Magenta" ); + +-- Enable Interrupt, tb_wb_adri_oi <= "00000" + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + X"00000008" , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + + hTrans01 := begin_transaction ( hStream01, "Training" ); + add_color ( hTrans01, "violett" ); + tb_wb_clear_epoch_oi <= (others => '1') ; + + for count_pattern in 0 to 63 loop + component_lv := std_logic_vector ( conv_signed ( count_pattern, mem_matrix_i_len ) ); + write ( buff_out, string'("-- Pattern Number: ") ); + write ( buff_out, count_pattern ); + write ( buff_out, string'(" ") ); + write ( buff_out, component_lv ); + + tb_s_mem (0) := MINUS_ONE; + tb_s_mem (1) := MINUS_ONE; + tb_s_mem (2) := MINUS_ONE; + tb_s_mem (3) := MINUS_ONE; + tb_s_mem (4) := MINUS_ONE; + tb_s_mem (5) := MINUS_ONE; + + if ( ( component_lv (0) = '1' ) ) then + tb_s_mem (0) := PLUS_ONE; + end if; + if ( ( component_lv (1) = '1' ) ) then + tb_s_mem (1) := PLUS_ONE; + end if; + if ( ( component_lv (2) = '1' ) ) then + tb_s_mem (2) := PLUS_ONE; + end if; + if ( ( component_lv (3) = '1' ) ) then + tb_s_mem (3) := PLUS_ONE; + end if; + if ( ( component_lv (4) = '1' ) ) then + tb_s_mem (4) := PLUS_ONE; + end if; + if ( ( component_lv (5) = '1' ) ) then + tb_s_mem (5) := PLUS_ONE; + end if; + + tb_t_mem (0) := MINUS_ONE; -- UP + tb_t_mem (1) := MINUS_ONE; -- DOWN + tb_t_mem (2) := MINUS_ONE; -- STOP + + if ( (component_lv = "010101" ) ) then + tb_t_mem (0) := PLUS_ONE; -- UP + tb_t_mem (1) := MINUS_ONE; -- DOWN + tb_t_mem (2) := MINUS_ONE; -- STOP + write ( buff_out, string'(" UP") ); + end if; + if ( (component_lv = "101010" ) ) then + tb_t_mem (0) := MINUS_ONE; -- UP + tb_t_mem (1) := PLUS_ONE; -- DOWN + tb_t_mem (2) := MINUS_ONE; -- STOP + write ( buff_out, string'(" DOWN") ); + end if; + if ( (component_lv = "111011" ) ) then + tb_t_mem (0) := MINUS_ONE; -- UP + tb_t_mem (1) := MINUS_ONE; -- DOWN + tb_t_mem (2) := PLUS_ONE; -- STOP + write ( buff_out, string'(" STOP") ); + end if; + + writeline ( outfile, buff_out ); + write ( buff_out, string'("-- Components") ); + writeline ( outfile, buff_out ); + + hTrans04 := begin_transaction ( hStream02, "WRITE-S-Memory" ); + add_color ( hTrans04, "light blue" ); + + count_data := 0; + count_loop := 0; + loop_finished_a := FALSE; + while ( NOT loop_finished_a ) loop + + -- WRITE S-MEM + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START5_S, WB_ADDR_WIDTH ) ) , + std_logic_vector ( conv_signed ( tb_s_mem (count_loop), WB_DATA_WIDTH ) ) , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + write ( buff_out, std_logic_vector ( conv_signed ( tb_s_mem (count_loop), WB_DATA_WIDTH ) ) ); + writeline ( outfile, buff_out ); + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_data := count_data + 1 ; + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi (STAT_RD_WR_COMPLETE) = '1') ) then + loop_finished_a := TRUE; + end if; + end loop; + + end_transaction ( hTrans04 ); + free_transaction ( hTrans04 ); + + hTrans04 := begin_transaction ( hStream02, "WRITE-T-Memory" ); + add_color ( hTrans04, "light yellow" ); + write ( buff_out, string'("-- Answer") ); + writeline ( outfile, buff_out ); + + count_data := 0; + count_loop := 0; + loop_finished_a := FALSE; + while ( NOT loop_finished_a ) loop + + -- WRITE T-MEM + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START5_T, WB_ADDR_WIDTH ) ) , + std_logic_vector ( conv_signed ( tb_t_mem (count_loop), WB_DATA_WIDTH ) ) , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + write ( buff_out, std_logic_vector ( conv_signed ( tb_t_mem (count_loop), WB_DATA_WIDTH ) ) ); + writeline ( outfile, buff_out ); + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_data := count_data + 1 ; + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi (STAT_RD_WR_COMPLETE) = '1') ) then + loop_finished_a := TRUE; + end if; + end loop; + + end_transaction ( hTrans04 ); + free_transaction ( hTrans04 ); + + hTrans04 := begin_transaction ( hStream02, "Start_Training_Process" ); + add_color ( hTrans04, "light blue" ); + + loop_finished_a := FALSE; + + -- Training + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START6, WB_ADDR_WIDTH ) ) , + tb_wb_clear_epoch_oi , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + tb_wb_clear_epoch_oi <= (others => '0') ; + + while ( NOT loop_finished_a ) loop + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi ( STAT_INT_TRAIN) = '1' ) ) then + loop_finished_a := TRUE; + end if; + end loop; + + end_transaction ( hTrans04 ); + free_transaction ( hTrans04 ); + end loop; + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + hTrans01 := begin_transaction ( hStream01, "READ-W-Memory_to_file" ); + add_color ( hTrans01, "violet red" ); + write ( buff_out, string'("-- W-Memory content for UP/DOWN/STOP pattern") ); + writeline ( outfile_w, buff_out ); + +-- READ W-MEM, tb_wb_adri_oi <= "10011" + count_loop := 0; + loop_finished_a := FALSE; + while ( NOT loop_finished_a ) loop + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START5_W, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + write ( buff_out, tb_wb_dout_oi ); + writeline ( outfile_w, buff_out ); + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi ( STAT_RD_WR_COMPLETE) = '1' ) ) then + loop_finished_a := TRUE; + end if; + end loop; + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + hTrans01 := begin_transaction ( hStream01, "READ-BIAS-Memory_to_file" ); + add_color ( hTrans01, "violet red" ); + write ( buff_out, string'("-- BIAS-Memory content for UP/DOWN/STOP pattern") ); + writeline ( outfile_bias, buff_out ); + + count_loop := 0; + loop_finished_a := FALSE; + while ( NOT loop_finished_a ) loop + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START5_BIAS, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + write ( buff_out, tb_wb_dout_oi ); + writeline ( outfile_bias, buff_out ); + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi ( STAT_RD_WR_COMPLETE) = '1' ) ) then + loop_finished_a := TRUE; + end if; + end loop; + + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + hTrans01 := begin_transaction ( hStream01, "Test" ); + add_color ( hTrans01, "maroon" ); + + for count_pattern in 0 to 63 loop + component_lv := std_logic_vector ( conv_signed ( count_pattern, mem_matrix_i_len ) ); + write ( buff_out, string'("-- Pattern Number: ") ); + write ( buff_out, count_pattern ); + writeline ( outfile_test, buff_out ); + + tb_s_mem (0) := MINUS_ONE; + tb_s_mem (1) := MINUS_ONE; + tb_s_mem (2) := MINUS_ONE; + tb_s_mem (3) := MINUS_ONE; + tb_s_mem (4) := MINUS_ONE; + tb_s_mem (5) := MINUS_ONE; + + if ( ( component_lv (0) = '1' ) ) then + tb_s_mem (0) := PLUS_ONE; + end if; + if ( ( component_lv (1) = '1' ) ) then + tb_s_mem (1) := PLUS_ONE; + end if; + if ( ( component_lv (2) = '1' ) ) then + tb_s_mem (2) := PLUS_ONE; + end if; + if ( ( component_lv (3) = '1' ) ) then + tb_s_mem (3) := PLUS_ONE; + end if; + if ( ( component_lv (4) = '1' ) ) then + tb_s_mem (4) := PLUS_ONE; + end if; + if ( ( component_lv (5) = '1' ) ) then + tb_s_mem (5) := PLUS_ONE; + end if; + + write ( buff_out, string'("-- Components") ); + writeline ( outfile_test, buff_out ); + + hTrans04 := begin_transaction ( hStream02, "WRITE-S-Memory" ); + add_color ( hTrans04, "light blue" ); + + count_data := 0; + count_loop := 0; + loop_finished_a := FALSE; + + while ( NOT loop_finished_a ) loop + + -- WRITE S-MEM + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START5_S, WB_ADDR_WIDTH ) ) , + std_logic_vector ( conv_signed ( tb_s_mem (count_loop), WB_DATA_WIDTH ) ) , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + write ( buff_out, std_logic_vector ( conv_signed ( tb_s_mem (count_loop), WB_DATA_WIDTH ) ) ); + writeline ( outfile_test, buff_out ); + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_data := count_data + 1 ; + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi (STAT_RD_WR_COMPLETE) = '1') ) then + loop_finished_a := TRUE; + end if; + end loop; + + end_transaction ( hTrans04 ); + free_transaction ( hTrans04 ); + + + hTrans04 := begin_transaction ( hStream02, "Start_Test_Process" ); + add_color ( hTrans04, "light blue" ); + + loop_finished_a := FALSE; + + -- Training + wb_write_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START4, WB_ADDR_WIDTH ) ) , + X"00000000" , + tb_wb_adro_oi , + tb_wb_din_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + while ( NOT loop_finished_a ) loop + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi ( STAT_INT_TEST) = '1' ) ) then + loop_finished_a := TRUE; + end if; + end loop; + + end_transaction ( hTrans04 ); + free_transaction ( hTrans04 ); + + hTrans04 := begin_transaction ( hStream02, "READ-T-Memory" ); + add_color ( hTrans04, "sate blue" ); + write ( buff_out, string'("-- Answer") ); + writeline ( outfile_test, buff_out ); + + count_data := 0; + count_loop := 0; + loop_finished_a := FALSE; + write ( buff_out_answer, count_pattern ); + + while ( NOT loop_finished_a ) loop + + -- READ T-MEM + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_START5_T, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + write ( buff_out, tb_wb_dout_oi ); + write ( buff_out, string'(" ") ); + + write ( buff_out_answer, string'(",") ); + if ( signed ( tb_wb_dout_oi ) < 0 ) then + hwrite ( buff_out_answer, std_logic_vector ( conv_unsigned ( (unsigned ( not std_logic_vector (tb_wb_dout_oi) ) + 1), WB_DATA_WIDTH )) ); + write ( buff_out_answer, string'(",-1") ); + else + hwrite ( buff_out_answer, ( ( tb_wb_dout_oi ) ) ); + write ( buff_out_answer, string'(",1") ); + end if; + + wb_read_proc_bfm + ( + clk_gen_o , + tb_wb_ack_oi , + std_logic_vector ( conv_unsigned ( WB_STAT_A, WB_ADDR_WIDTH ) ) , + tb_wb_dout_oi , + tb_wb_adro_oi , + tb_wb_stb_oi , + tb_wb_cyc_oi , + tb_wb_we_oi + ); + + count_loop := count_loop + 1 ; + if ( (tb_wb_dout_oi ( STAT_RD_WR_COMPLETE ) = '1' ) ) then + loop_finished_a := TRUE; + end if; + end loop; + writeline ( outfile_test, buff_out ); + writeline ( outfile_answer, buff_out_answer ); + + end_transaction ( hTrans04 ); + free_transaction ( hTrans04 ); + end loop; + end_transaction ( hTrans01 ); + free_transaction ( hTrans01 ); + + + done <= TRUE; + end process tb_avm_test; + + clk_gen : process + begin + while (not done) loop + clk_gen_o <= '0','1' after PERIOD/2; + wait for PERIOD; + end loop; + wait; + end process clk_gen; + +-- Instance port mappings. +U_0 : p0300_m00000_s_v03_top_level_blk + PORT MAP ( + wb_clk_i => clk_gen_o , + wb_rst_i => rst_proc_o , + wb_adr_i => tb_wb_adro_oi , + wb_dat_i => tb_wb_din_oi , + wb_stb_i => tb_wb_stb_oi , + wb_cyc_i => tb_wb_cyc_oi , + wb_we_i => tb_wb_we_oi , + + wb_ack_o => tb_wb_ack_oi , + wb_dat_o => tb_wb_dout_oi + ); + +END ARCHITECTURE testbench; + Index: neural_net_perceptron/trunk/neural_net_perceptron/01_copyright_GNU_V3.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/01_copyright_GNU_V3.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/01_copyright_GNU_V3.txt (revision 8) @@ -0,0 +1,223 @@ +GNU General Public License version 3 (GPLv3) +Submitted by nelson on Tue, 2007-10-23 03:13. :: +GNU GENERAL PUBLIC LICENSE +Version 3, 29 June 2007 + +Copyright (C) 2007 Free Software Foundation, Inc. + +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. + +Preamble +The GNU General Public License is a free, copyleft license for software and other kinds of works. + +The licenses for most software and other practical works are designed to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. +If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the copyright line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode: + + Copyright (C) + + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an about box . + +You should also get your employer (if you work as a programmer) or school, if any, to sign a copyright disclaimer for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see . + +The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read . + Index: neural_net_perceptron/trunk/neural_net_perceptron/02_TO_DO_list_20220720.txt =================================================================== --- neural_net_perceptron/trunk/neural_net_perceptron/02_TO_DO_list_20220720.txt (nonexistent) +++ neural_net_perceptron/trunk/neural_net_perceptron/02_TO_DO_list_20220720.txt (revision 8) @@ -0,0 +1,6 @@ +(July 20th 2022) +- (FINISHED) Documentation (Specification and VHDL core internals) +- (FINISHED) Simulation's file structure +- (FINISHED) Test Bench +- (FINISHED) VHDL +