URL
https://opencores.org/ocsvn/nocem/nocem/trunk
Subversion Repositories nocem
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/bridge/noc2proc_bridge2.vhd
File deleted
/trunk/VHDL/mux2to1.vhd
File deleted
/trunk/VHDL/fifo_reg.vhd
File deleted
/trunk/VHDL/mux4to1.vhd
File deleted
/trunk/VHDL/fifo_gfs.vhd
File deleted
/trunk/VHDL/access_point_exerciser.vhd
File deleted
/trunk/VHDL/packetbuffer2.vhd
File deleted
/trunk/VHDL/barrelshift4_wrapper.sch
File deleted
/trunk/VHDL/ic_bus_nocem.vhd
File deleted
/trunk/VHDL/barrelshift8_wrapper.sch
File deleted
/trunk/VHDL/fifo_allvhdl.vhd
File deleted
\ No newline at end of file
/trunk/VHDL/ic_pkt_nocem.vhd
File deleted
/trunk/VHDL/vc_vc_alloc_arb.vhd
File deleted
/trunk/VHDL/arb_bus_nocem.vhd
File deleted
/trunk/VHDL/vc_node_ch_arbiter.vhd
File deleted
/trunk/VHDL/vc_channel.vhd
File deleted
/trunk/VHDL/vc_channel_destap.vhd
File deleted
/trunk/VHDL/ap_exerciser_vc.vhd
File deleted
/trunk/VHDL/nocem.vhd
File deleted
/trunk/VHDL/simple_pkt_local_switch.vhd
File deleted
/trunk/VHDL/pkg_nocem.vhd
File deleted
/trunk/VHDL/Xto1_arbiter.vhd
File deleted
/trunk/VHDL/vc_node_vc_allocator.vhd
File deleted
/trunk/VHDL/simple_pkt_local_arb.vhd
File deleted
/trunk/VHDL/vc_controller.vhd
File deleted
/trunk/VHDL/channel_fifo.vhd
File deleted
/trunk/VHDL/simple_pkt_node.vhd
File deleted
/trunk/VHDL/arb_simple_pkt_nocem.vhd
File deleted
/trunk/VHDL/vc_node.vhd
File deleted
/trunk/doc/gpl.txt
File deleted
trunk/doc/gpl.txt
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/doc/userguide_nocem.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/userguide_nocem.pdf
===================================================================
--- trunk/doc/userguide_nocem.pdf (revision 7)
+++ trunk/doc/userguide_nocem.pdf (nonexistent)
trunk/doc/userguide_nocem.pdf
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/WARFP.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/WARFP.pdf
===================================================================
--- trunk/doc/WARFP.pdf (revision 7)
+++ trunk/doc/WARFP.pdf (nonexistent)
trunk/doc/WARFP.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/sim/testbench.vhd
===================================================================
--- trunk/sim/testbench.vhd (revision 7)
+++ trunk/sim/testbench.vhd (nonexistent)
@@ -1,221 +0,0 @@
-
------------------------------------------------------------------------------
--- NoCem -- Network on Chip Emulation Tool for System on Chip Research
--- and Implementations
---
--- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
---
--- This program is free software; you can redistribute it and/or
--- modify it under the terms of the GNU General Public License
--- as published by the Free Software Foundation; either version 2
--- of the License, or (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
--- 02110-1301, USA.
---
--- The authors can be contacted by email: @cs.colorado.edu
---
--- or by mail: Campus Box 430, Department of Computer Science,
--- University of Colorado at Boulder, Boulder, Colorado 80309
---------------------------------------------------------------------------------
-
-
---
--- Filename: testbench.vhd
---
--- Description:
---
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.pkg_nocem.all;
-
-
-
-entity testbench is
-end testbench;
-
-architecture Behavioral of testbench is
-
-
- signal clk,rst : std_logic;
-
-
- -- arbitration lines (usage depends on underlying network)
- signal arb_req : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
- signal arb_cntrl_noc2proc : arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
- signal arb_grant : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
- signal arb_cntrl_proc2noc : arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
- signal noc_node_data : data_array(NOCEM_NUM_AP-1 downto 0);
- signal noc_node_data_valid : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
- signal noc_node_data_recvd : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
-
- signal node_noc_data : data_array(NOCEM_NUM_AP-1 downto 0);
- signal node_noc_data_valid : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
- signal node_noc_data_recvd : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
-
- signal noc_node_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
- signal noc_node_pkt_cntrl_valid : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
- signal noc_node_pkt_cntrl_recvd : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
-
- signal node_noc_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
- signal node_noc_pkt_cntrl_valid : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
- signal node_noc_pkt_cntrl_recvd : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
-
- signal test_val0,test_val1,test_val2,test_val3 : integer;
-
-
- type int_array is array(natural range <>) of integer;
- --constant DATAOUT_INTERVAL : int_array(NOCEM_NUM_AP-1 downto 0) := (60000,60000,32,16);
- constant DATAOUT_INTERVAL : int_array(NOCEM_NUM_AP-1 downto 0) := (48,16,32,16);
-
-begin
-
-
-
-
- test_val0 <= DATAOUT_INTERVAL(0);
- test_val1 <= DATAOUT_INTERVAL(1);
- test_val2 <= DATAOUT_INTERVAL(2);
- test_val3 <= DATAOUT_INTERVAL(3);
-
-
- I_noc: nocem PORT MAP(
- arb_req => arb_req,
- arb_cntrl_in => arb_cntrl_proc2noc,
- arb_grant => arb_grant,
- arb_cntrl_out => arb_cntrl_noc2proc,
- datain => node_noc_data,
- datain_valid => node_noc_data_valid,
- datain_recvd => noc_node_data_recvd,
- dataout => noc_node_data,
- dataout_valid => noc_node_data_valid,
- dataout_recvd => node_noc_data_recvd,
- pkt_cntrl_in => node_noc_pkt_cntrl,
- pkt_cntrl_in_valid => node_noc_pkt_cntrl_valid,
- pkt_cntrl_in_recvd => noc_node_pkt_cntrl_recvd,
- pkt_cntrl_out => noc_node_pkt_cntrl,
- pkt_cntrl_out_valid => noc_node_pkt_cntrl_valid,
- pkt_cntrl_out_recvd => node_noc_pkt_cntrl_recvd,
- clk => clk,
- rst => rst
- );
-
-
-
-
-
-
- g1: for I in NOCEM_NUM_AP-1 downto 0 generate
-
-
-
- g11: if NOCEM_TYPE = NOCEM_VC_TYPE generate
- I_ap_ex: ap_exerciser_vc
-
- Generic map(
- DELAY_START_COUNTER_WIDTH => 8,
- DELAY_START_CYCLES => 10+I*8,
- INTERVAL_COUNTER_WIDTH => 16,
- PKT_LENGTH => 4+I,
- INIT_DEST_ADDR => (I+1) mod NOCEM_NUM_AP,
- MY_ADDR => I,
- DATA_OUT_INTERVAL => DATAOUT_INTERVAL(I)
- )
-
- PORT MAP(
- arb_req => arb_req(I),
- arb_cntrl_in => arb_cntrl_noc2proc(I),
- arb_grant => arb_grant(I),
- arb_cntrl_out => arb_cntrl_proc2noc(I),
- dataout => node_noc_data(I),
- dataout_valid => node_noc_data_valid(I),
- dataout_recvd => noc_node_data_recvd(I),
- datain => noc_node_data(I),
- datain_valid => noc_node_data_valid(I),
- datain_recvd => node_noc_data_recvd(I),
- pkt_cntrl_out => node_noc_pkt_cntrl(I),
- pkt_cntrl_out_valid => node_noc_pkt_cntrl_valid(I),
- pkt_cntrl_out_recvd => noc_node_pkt_cntrl_recvd(I),
- pkt_cntrl_in => noc_node_pkt_cntrl(I),
- pkt_cntrl_in_valid => noc_node_pkt_cntrl_valid(I),
- pkt_cntrl_in_recvd => node_noc_pkt_cntrl_recvd(I),
- clk => clk,
- rst => rst
- );
- end generate;
-
- g12: if NOCEM_TYPE = NOCEM_SIMPLE_PKT_TYPE generate
-
- I_ap_ex: access_point_exerciser
-
- Generic map(
- DELAY_START_COUNTER_WIDTH => 8,
- DELAY_START_CYCLES => 10+I*8,
- INIT_DATA_OUT => CONV_STD_LOGIC_VECTOR(I+1+2**I,NOCEM_DW),
- INTERVAL_COUNTER_WIDTH => 16,
- BURST_LENGTH => 1,
- INIT_DEST_ADDR => (I+1) mod NOCEM_NUM_AP,
-
- DATA_OUT_INTERVAL => 15
- )
-
- PORT MAP(
- arb_req => arb_req(I),
- arb_cntrl_in => arb_cntrl_noc2proc(I),
- arb_grant => arb_grant(I),
- arb_cntrl_out => arb_cntrl_proc2noc(I),
- dataout => node_noc_data(I),
- dataout_valid => node_noc_data_valid(I),
- dataout_recvd => noc_node_data_recvd(I),
- datain => noc_node_data(I),
- datain_valid => noc_node_data_valid(I),
- datain_recvd => node_noc_data_recvd(I),
- pkt_cntrl_out => node_noc_pkt_cntrl(I),
- pkt_cntrl_out_valid => node_noc_pkt_cntrl_valid(I),
- pkt_cntrl_out_recvd => noc_node_pkt_cntrl_recvd(I),
- pkt_cntrl_in => noc_node_pkt_cntrl(I),
- pkt_cntrl_in_valid => noc_node_pkt_cntrl_valid(I),
- pkt_cntrl_in_recvd => node_noc_pkt_cntrl_recvd(I),
- clk => clk,
- rst => rst
- );
- end generate;
- end generate;
-
-
-
-
- P_STIMULUS: process
- begin -- process P_STIMULUS
- rst <= '1';
- wait for 250 ns;
- rst <= '0';
- wait for 1000 ms; -- forever!
- end process P_STIMULUS;
-
-p_clk : process -- drives clk
- begin
- clk <= '0';
- wait for 2 ns;
- loop
- wait for 4 ns;
- clk <= '1';
- wait for 4 ns;
- clk <= '0';
- end loop;
- end process p_clk;
-
-
-
-end Behavioral;
Index: nocem/trunk/VHDL/nocem.vhd
===================================================================
--- nocem/trunk/VHDL/nocem.vhd (nonexistent)
+++ nocem/trunk/VHDL/nocem.vhd (revision 8)
@@ -0,0 +1,173 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: nocem.vhd
+--
+-- Description: toplevel nocem entity
+--
+
+
+---------------------------------------
+--
+-- NOCEM toplevel: defines generics and input interfaces
+-- for this NoC Emulator
+--
+---------------------------------------
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+use work.pkg_nocem.all;
+
+entity nocem is
+ Port(
+
+ -- arbitration lines (usage depends on underlying network)
+ arb_req : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_cntrl_in : in arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ arb_grant : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_cntrl_out : out arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ --data and control incoming/outgoing line (usage depends on underlying network)
+ datain : in data_array(NOCEM_NUM_AP-1 downto 0);
+ datain_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ datain_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ dataout : out data_array(NOCEM_NUM_AP-1 downto 0);
+ dataout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ dataout_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ pkt_cntrl_in : in pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ pkt_cntrl_out : out pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+
+
+end nocem;
+
+
+
+
+architecture Behavioral of nocem is
+
+
+signal arb_grant_i : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+signal vcc_num_ap : std_logic_vector( NOCEM_NUM_AP-1 downto 0);
+
+begin
+
+
+ vcc_num_ap <= (others => '1');
+
+
+---------------------------------------------------------------
+-- BUS TYPE: only for legacy testing of bus architectures ---
+-- not specifically a NoC ---
+---------------------------------------------------------------
+
+ g1 : if NOCEM_TYPE = NOCEM_BUS_TYPE generate
+
+ arb_grant <= arb_grant_i;
+
+ -- bus arbitration logic goes here
+ I_arb_bus_nocem: arb_bus_nocem
+ PORT MAP(
+ arb_req => arb_req,
+ arb_grant => arb_grant_i,
+ clk => clk,
+ rst => rst
+ );
+
+ -- bus interconnect logic goes here
+ I_ic_bus_nocem: ic_bus_nocem
+ PORT MAP(
+ arb_grant => arb_grant_i,
+ datain => datain,
+ dataout => dataout,
+ dataout_valid => dataout_valid,
+ addrin => pkt_cntrl_in,
+ addrout => pkt_cntrl_out,
+ addrout_valid => pkt_cntrl_out_valid,
+ clk => clk,
+ rst => rst
+ );
+
+
+ end generate;
+
+
+-------------------------------------------------------------------------
+-- PACKET BASED: packet based noc (i.e. not a BUS!) ---
+-------------------------------------------------------------------------
+ g2 : if NOCEM_TYPE = NOCEM_SIMPLE_PKT_TYPE or NOCEM_TYPE = NOCEM_VC_TYPE generate
+
+
+ I_ic_nocem : ic_pkt_nocem
+ PORT MAP(
+ arb_req => arb_req,
+ arb_cntrl_in => arb_cntrl_in,
+ arb_grant => arb_grant,
+ arb_cntrl_out => arb_cntrl_out,
+ datain => datain,
+ datain_valid => datain_valid,
+ datain_recvd => datain_recvd,
+ dataout => dataout,
+ dataout_valid => dataout_valid,
+ dataout_recvd => dataout_recvd,
+ pkt_cntrl_in => pkt_cntrl_in,
+ pkt_cntrl_in_valid => pkt_cntrl_in_valid,
+ pkt_cntrl_in_recvd => pkt_cntrl_in_recvd,
+ pkt_cntrl_out => pkt_cntrl_out,
+ pkt_cntrl_out_valid => pkt_cntrl_out_valid,
+ pkt_cntrl_out_recvd => pkt_cntrl_out_recvd,
+ clk => clk,
+ rst => rst
+ );
+ end generate;
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/vc_node_ch_arbiter.vhd
===================================================================
--- nocem/trunk/VHDL/vc_node_ch_arbiter.vhd (nonexistent)
+++ nocem/trunk/VHDL/vc_node_ch_arbiter.vhd (revision 8)
@@ -0,0 +1,422 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+
+entity vc_node_ch_arbiter is
+ Port (
+ -- needed to mux outputs for the accompanying switch
+ arb_grant_output : out arb_decision_array(4 downto 0);
+
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+end vc_node_ch_arbiter;
+
+architecture Behavioral of vc_node_ch_arbiter is
+
+ constant VCS_ALL_FULL : std_logic_vector(NOCEM_NUM_VC-1 downto 0) := (others => '1');
+
+
+ signal dest_local_port : arb_decision_array(4 downto 0);
+ signal arb_decision_enum : arb_decision_array(4 downto 0);
+ signal channel_cntrl_in_array_i : channel_cntrl_array(4 downto 0);
+ signal channel_cntrl_out_array_ureg : channel_cntrl_array(4 downto 0);
+ signal dest_local_vc_ureg,dest_local_vc_reg : vc_addr_array(4 downto 0);
+ signal channel_cntrl_out_array : channel_cntrl_array(4 downto 0);
+ signal n_channel_cntrl_out_reg : channel_cntrl_word;
+ signal s_channel_cntrl_out_reg : channel_cntrl_word;
+ signal e_channel_cntrl_out_reg : channel_cntrl_word;
+ signal w_channel_cntrl_out_reg : channel_cntrl_word;
+ signal ap_channel_cntrl_out_reg : channel_cntrl_word;
+ signal arb_grant_output_reg,arb_grant_output_ureg : arb_decision_array(4 downto 0);
+
+ signal zeroes_bv : bit_vector(NOCEM_NUM_VC-1 downto 0);
+
+begin
+
+ zeroes_bv <= (others => '0');
+
+
+ -- just setting up an array or two for "easy" looping
+ arb_decision_enum(NOCEM_AP_IX) <= ARB_AP;
+ arb_decision_enum(NOCEM_NORTH_IX) <= ARB_NORTH;
+ arb_decision_enum(NOCEM_SOUTH_IX) <= ARB_SOUTH;
+ arb_decision_enum(NOCEM_EAST_IX) <= ARB_EAST;
+ arb_decision_enum(NOCEM_WEST_IX) <= ARB_WEST;
+
+ dest_local_port(NOCEM_AP_IX) <= ap_channel_cntrl_in(NOCEM_CHFIFO_VC_CHDEST_HIX downto NOCEM_CHFIFO_VC_CHDEST_LIX);
+ dest_local_port(NOCEM_NORTH_IX) <= n_channel_cntrl_in(NOCEM_CHFIFO_VC_CHDEST_HIX downto NOCEM_CHFIFO_VC_CHDEST_LIX);
+ dest_local_port(NOCEM_SOUTH_IX) <= s_channel_cntrl_in(NOCEM_CHFIFO_VC_CHDEST_HIX downto NOCEM_CHFIFO_VC_CHDEST_LIX);
+ dest_local_port(NOCEM_EAST_IX) <= e_channel_cntrl_in(NOCEM_CHFIFO_VC_CHDEST_HIX downto NOCEM_CHFIFO_VC_CHDEST_LIX);
+ dest_local_port(NOCEM_WEST_IX) <= w_channel_cntrl_in(NOCEM_CHFIFO_VC_CHDEST_HIX downto NOCEM_CHFIFO_VC_CHDEST_LIX);
+
+ dest_local_vc_ureg(NOCEM_AP_IX) <= ap_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+ dest_local_vc_ureg(NOCEM_NORTH_IX) <= n_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+ dest_local_vc_ureg(NOCEM_SOUTH_IX) <= s_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+ dest_local_vc_ureg(NOCEM_EAST_IX) <= e_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+ dest_local_vc_ureg(NOCEM_WEST_IX) <= w_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+
+
+
+
+ channel_cntrl_in_array_i(NOCEM_NORTH_IX) <= n_channel_cntrl_in;
+ channel_cntrl_in_array_i(NOCEM_SOUTH_IX) <= s_channel_cntrl_in;
+ channel_cntrl_in_array_i(NOCEM_EAST_IX) <= e_channel_cntrl_in;
+ channel_cntrl_in_array_i(NOCEM_WEST_IX) <= w_channel_cntrl_in;
+ channel_cntrl_in_array_i(NOCEM_AP_IX) <= ap_channel_cntrl_in;
+
+
+
+ n_channel_cntrl_out <= channel_cntrl_out_array(NOCEM_NORTH_IX);
+ s_channel_cntrl_out <= channel_cntrl_out_array(NOCEM_SOUTH_IX);
+ e_channel_cntrl_out <= channel_cntrl_out_array(NOCEM_EAST_IX);
+ w_channel_cntrl_out <= channel_cntrl_out_array(NOCEM_WEST_IX);
+ ap_channel_cntrl_out <= channel_cntrl_out_array(NOCEM_AP_IX);
+
+
+
+outputs_regd : process (clk,rst)
+begin
+
+ if rst='1' then
+
+ n_channel_cntrl_out_reg <= (others => '0');
+ s_channel_cntrl_out_reg <= (others => '0');
+ e_channel_cntrl_out_reg <= (others => '0');
+ w_channel_cntrl_out_reg <= (others => '0');
+ ap_channel_cntrl_out_reg <= (others => '0');
+ arb_grant_output_reg <= (others => ARB_NODECISION);
+ dest_local_vc_reg <= (others => (others => '0'));
+ elsif clk='1' and clk'event then
+
+ n_channel_cntrl_out_reg <= channel_cntrl_out_array_ureg(NOCEM_NORTH_IX);
+ s_channel_cntrl_out_reg <= channel_cntrl_out_array_ureg(NOCEM_SOUTH_IX);
+ e_channel_cntrl_out_reg <= channel_cntrl_out_array_ureg(NOCEM_EAST_IX);
+ w_channel_cntrl_out_reg <= channel_cntrl_out_array_ureg(NOCEM_WEST_IX);
+ ap_channel_cntrl_out_reg <= channel_cntrl_out_array_ureg(NOCEM_AP_IX);
+ arb_grant_output_reg <= arb_grant_output_ureg;
+ dest_local_vc_reg <= dest_local_vc_ureg;
+ end if;
+
+
+end process;
+
+
+outputs_post_regd : process (n_channel_cntrl_in, s_channel_cntrl_in, e_channel_cntrl_in, w_channel_cntrl_in, ap_channel_cntrl_in, n_channel_cntrl_out_reg, s_channel_cntrl_out_reg, e_channel_cntrl_out_reg, w_channel_cntrl_out_reg, ap_channel_cntrl_out_reg, arb_grant_output_reg, dest_local_vc_reg, channel_cntrl_in_array_i, zeroes_bv)
+begin
+
+
+
+
+
+
+
+ -- need to do a sanity check that the incoming channel still has
+ -- data to give. This is an artifact of the register pushing inside the
+ -- the arbitration process;
+
+ channel_cntrl_out_array(NOCEM_NORTH_IX) <= n_channel_cntrl_out_reg;
+ channel_cntrl_out_array(NOCEM_SOUTH_IX) <= s_channel_cntrl_out_reg;
+ channel_cntrl_out_array(NOCEM_EAST_IX) <= e_channel_cntrl_out_reg;
+ channel_cntrl_out_array(NOCEM_WEST_IX) <= w_channel_cntrl_out_reg;
+ channel_cntrl_out_array(NOCEM_AP_IX) <= ap_channel_cntrl_out_reg;
+
+ arb_grant_output <= arb_grant_output_reg;
+
+
+ -- looking to see that what is being read is still there after some pipeline stages
+ -- if not, just kill the read/write and switch allocation. Also need to check if outgoing
+ -- VC is not full now
+
+
+ -- I iterates over output channels
+ lll: for I in 4 downto 0 loop
+
+ if arb_grant_output_reg(I) = ARB_NORTH and
+ -- if incoming FIFO is now empty
+ ((((TO_BITVECTOR(n_channel_cntrl_in(NOCEM_CHFIFO_VC_EMPTY_HIX downto NOCEM_CHFIFO_VC_EMPTY_LIX)))
+ and (TO_BITVECTOR(n_channel_cntrl_out_reg(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)))) /= zeroes_bv) or
+ -- if outgoing is FIFO is mow full
+ ((TO_BITVECTOR(dest_local_vc_reg(NOCEM_NORTH_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) /= zeroes_bv) )
+ then
+
+ arb_grant_output(I) <= ARB_NODECISION;
+
+ channel_cntrl_out_array(NOCEM_NORTH_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_NORTH_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_NORTH_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= (others => '0');
+
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= (others => '0');
+
+ end if;
+
+ if arb_grant_output_reg(I) = ARB_SOUTH and
+ -- if incoming FIFO is now empty
+ ((((TO_BITVECTOR(s_channel_cntrl_in(NOCEM_CHFIFO_VC_EMPTY_HIX downto NOCEM_CHFIFO_VC_EMPTY_LIX)))
+ and (TO_BITVECTOR(s_channel_cntrl_out_reg(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)))) /= zeroes_bv) or
+ -- if outgoing is FIFO is mow full
+ ((TO_BITVECTOR(dest_local_vc_reg(NOCEM_SOUTH_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) /= zeroes_bv) )
+ then
+
+
+
+ arb_grant_output(I) <= ARB_NODECISION;
+
+ channel_cntrl_out_array(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= (others => '0');
+
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= (others => '0');
+
+ end if;
+
+ if arb_grant_output_reg(I) = ARB_EAST and
+ -- if incoming FIFO is now empty
+ ((((TO_BITVECTOR(e_channel_cntrl_in(NOCEM_CHFIFO_VC_EMPTY_HIX downto NOCEM_CHFIFO_VC_EMPTY_LIX)))
+ and (TO_BITVECTOR(e_channel_cntrl_out_reg(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)))) /= zeroes_bv) or
+ -- if outgoing is FIFO is mow full
+ ((TO_BITVECTOR(dest_local_vc_reg(NOCEM_EAST_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) /= zeroes_bv) )
+ then
+
+
+
+
+
+ arb_grant_output(I) <= ARB_NODECISION;
+
+ channel_cntrl_out_array(NOCEM_EAST_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_EAST_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_EAST_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= (others => '0');
+
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= (others => '0');
+
+ end if;
+
+ if arb_grant_output_reg(I) = ARB_WEST and
+ -- if incoming FIFO is now empty
+ ((((TO_BITVECTOR(w_channel_cntrl_in(NOCEM_CHFIFO_VC_EMPTY_HIX downto NOCEM_CHFIFO_VC_EMPTY_LIX)))
+ and (TO_BITVECTOR(w_channel_cntrl_out_reg(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)))) /= zeroes_bv) or
+ -- if outgoing is FIFO is mow full
+ ((TO_BITVECTOR(dest_local_vc_reg(NOCEM_WEST_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) /= zeroes_bv) )
+ then
+
+
+ arb_grant_output(I) <= ARB_NODECISION;
+
+ channel_cntrl_out_array(NOCEM_WEST_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_WEST_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_WEST_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= (others => '0');
+
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= (others => '0');
+
+ end if;
+
+ if arb_grant_output_reg(I) = ARB_AP and
+ -- if incoming FIFO is now empty
+ ((((TO_BITVECTOR(ap_channel_cntrl_in(NOCEM_CHFIFO_VC_EMPTY_HIX downto NOCEM_CHFIFO_VC_EMPTY_LIX)))
+ and (TO_BITVECTOR(ap_channel_cntrl_out_reg(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)))) /= zeroes_bv) or
+ -- if outgoing is FIFO is mow full
+ ((TO_BITVECTOR(dest_local_vc_reg(NOCEM_AP_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) /= zeroes_bv) )
+ then
+
+ arb_grant_output(I) <= ARB_NODECISION;
+
+ channel_cntrl_out_array(NOCEM_AP_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_AP_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '0';
+ channel_cntrl_out_array(NOCEM_AP_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= (others => '0');
+
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '0';
+ channel_cntrl_out_array(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= (others => '0');
+
+
+
+
+
+ end if;
+
+ end loop;
+
+end process;
+
+
+
+
+
+
+-- THIS IS WHERE THE DECISION IS MADE...
+
+arb_gen : process (channel_cntrl_in_array_i,dest_local_port, dest_local_vc_ureg, ap_channel_cntrl_in, n_channel_cntrl_in, s_channel_cntrl_in, e_channel_cntrl_in, w_channel_cntrl_in, arb_decision_enum, zeroes_bv)
+begin
+
+
+ arb_grant_output_ureg <= (others => ARB_NODECISION);
+ channel_cntrl_out_array_ureg <= (others => (others => '0'));
+
+
+l3: for I in 4 downto 0 loop
+
+ -- I iterates over the OUTPUT ports
+ if channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX) /= VCS_ALL_FULL then
+
+
+ -- determining if data can flow....
+ -- incoming channel wants to travel to THIS (I) channel AND
+ -- destination VC is not full
+ -- (done by AND'ing dest_local_vc, full_vector --> 0: dest_vc not full, /= 0, dest_vc is full)
+
+ if dest_local_port(NOCEM_AP_IX) = arb_decision_enum(I) and
+ ((TO_BITVECTOR(dest_local_vc_ureg(NOCEM_AP_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) = zeroes_bv) then
+
+ --arb grant will push data through switch
+ arb_grant_output_ureg(I) <= ARB_AP;
+
+ -- do read enable for selected incoming data
+ channel_cntrl_out_array_ureg(NOCEM_AP_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_ureg(NOCEM_AP_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+
+
+ channel_cntrl_out_array_ureg(NOCEM_AP_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)
+ <= channel_cntrl_in_array_i(NOCEM_AP_IX)(NOCEM_CHFIFO_VC_VCSRC_HIX downto NOCEM_CHFIFO_VC_VCSRC_LIX);
+
+
+ -- do write enable for outgoing port
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ -- do correct WR mux on virtual channel
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX)
+ <= ap_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+
+ elsif dest_local_port(NOCEM_NORTH_IX) = arb_decision_enum(I) and
+ ((TO_BITVECTOR(dest_local_vc_ureg(NOCEM_NORTH_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) = zeroes_bv) then
+
+ arb_grant_output_ureg(I) <= ARB_NORTH;
+
+ -- do read enable for selected incoming data
+ channel_cntrl_out_array_ureg(NOCEM_NORTH_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_ureg(NOCEM_NORTH_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+
+ channel_cntrl_out_array_ureg(NOCEM_NORTH_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)
+ <= channel_cntrl_in_array_i(NOCEM_NORTH_IX)(NOCEM_CHFIFO_VC_VCSRC_HIX downto NOCEM_CHFIFO_VC_VCSRC_LIX);
+
+
+ -- do write enable for outgoing port
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ -- do correct WR mux on virtual channel
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX)
+ <= n_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+
+
+ elsif dest_local_port(NOCEM_SOUTH_IX) = arb_decision_enum(I) and
+ ((TO_BITVECTOR(dest_local_vc_ureg(NOCEM_SOUTH_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) = zeroes_bv) then
+
+ arb_grant_output_ureg(I) <= ARB_SOUTH;
+
+ -- do read enable for selected incoming data
+ channel_cntrl_out_array_ureg(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_ureg(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+
+ channel_cntrl_out_array_ureg(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)
+ <= channel_cntrl_in_array_i(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_VC_VCSRC_HIX downto NOCEM_CHFIFO_VC_VCSRC_LIX);
+
+
+ -- do write enable for outgoing port
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ -- do correct WR mux on virtual channel
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX)
+ <= s_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+
+
+ elsif dest_local_port(NOCEM_EAST_IX) = arb_decision_enum(I) and
+ ((TO_BITVECTOR(dest_local_vc_ureg(NOCEM_EAST_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) = zeroes_bv) then
+
+ arb_grant_output_ureg(I) <= ARB_EAST;
+
+ -- do read enable for selected incoming data
+ channel_cntrl_out_array_ureg(NOCEM_EAST_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_ureg(NOCEM_EAST_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+
+ channel_cntrl_out_array_ureg(NOCEM_EAST_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)
+ <= channel_cntrl_in_array_i(NOCEM_EAST_IX)(NOCEM_CHFIFO_VC_VCSRC_HIX downto NOCEM_CHFIFO_VC_VCSRC_LIX);
+
+
+ -- do write enable for outgoing port
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ -- do correct WR mux on virtual channel
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX)
+ <= e_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+
+
+ elsif dest_local_port(NOCEM_WEST_IX) = arb_decision_enum(I) and
+ ((TO_BITVECTOR(dest_local_vc_ureg(NOCEM_WEST_IX)) and TO_BITVECTOR(channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX))) = zeroes_bv) then
+
+ arb_grant_output_ureg(I) <= ARB_WEST;
+
+ -- do read enable for selected incoming data
+ channel_cntrl_out_array_ureg(NOCEM_WEST_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_ureg(NOCEM_WEST_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+
+ channel_cntrl_out_array_ureg(NOCEM_WEST_IX)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX)
+ <= channel_cntrl_in_array_i(NOCEM_WEST_IX)(NOCEM_CHFIFO_VC_VCSRC_HIX downto NOCEM_CHFIFO_VC_VCSRC_LIX);
+
+
+ -- do write enable for outgoing port
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ -- do correct WR mux on virtual channel
+ channel_cntrl_out_array_ureg(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX)
+ <= w_channel_cntrl_in(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX);
+
+
+ end if;
+ end if;
+
+
+
+
+end loop;
+
+
+
+end process;
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/vc_channel_destap.vhd
===================================================================
--- nocem/trunk/VHDL/vc_channel_destap.vhd (nonexistent)
+++ nocem/trunk/VHDL/vc_channel_destap.vhd (revision 8)
@@ -0,0 +1,241 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: vc_channel_destap.vhd
+--
+-- Description: vc channel with destination being an access point
+--
+
+
+--
+--a different vc_channel is used for the channel fifo that has its destination
+--being the actual access point. This is necessary for a variety of reasons. Any bug
+--fixes here will probably need to be fixed in vc_channel.vhd as well
+--(I'm sure a software engineer just died somewhere).
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.pkg_nocem.all;
+
+entity vc_channel_destap is
+port (
+ -- id of destination node
+ node_dest_id : in node_addr_word;
+
+
+ vc_mux_wr : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_mux_rd : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ wr_pkt_cntrl : in std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ wr_pkt_data : in std_logic_vector(NOCEM_DW-1 downto 0);
+
+ rd_pkt_cntrl : out std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ rd_pkt_data : out std_logic_vector(NOCEM_DW-1 downto 0);
+
+ rd_pkt_chdest : out std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+ rd_pkt_vcdest : out vc_addr_word;
+ rd_pkt_vcsrc : out vc_addr_word;
+ vc_empty : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_full : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ -- VC allocation signals
+ vc_allocate_from_node : in vc_addr_word;
+ vc_requester_from_node : in vc_addr_word;
+
+ vc_allocate_destch_to_node : out std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+ vc_requester_to_node : out vc_addr_word;
+ vc_eop_rd_status : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_eop_wr_status : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ RE : in std_logic;
+ WE : in std_logic;
+
+ clk : in std_logic;
+ rst : in std_logic
+);
+end vc_channel_destap;
+
+architecture Behavioral of vc_channel_destap is
+
+ signal vc_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_VC-1 downto 0);
+ signal vc_pkt_data : data_array(NOCEM_NUM_VC-1 downto 0);
+
+ signal fifo_wr_en : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal fifo_rd_en : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal datain_pad,dataout_pad : std_logic_vector(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+
+ type array_packed is array(natural range <>) of std_logic_vector(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ signal fifo_rd_data : array_packed(NOCEM_NUM_VC-1 downto 0);
+
+
+ -- signal vc_mux_rd : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ signal dummy_vcid : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal vc_alloc_mux_sel : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal vc_empty_i : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ -- needed for Modelsim Simulator to work....
+ signal vc_myid_conv : vc_addr_array(NOCEM_NUM_VC-1 downto 0);
+
+
+begin
+
+ rd_pkt_vcsrc <= vc_mux_rd;
+
+
+ vc_requester_to_node <= (others => '0');
+ rd_pkt_vcdest <= (others => '0');
+ vc_allocate_destch_to_node <= (others => '0');
+ rd_pkt_chdest <= (others => '0');
+ vc_alloc_mux_sel <= (others => '0');
+
+
+ -- for accesspoint vc_req lines
+ dummy_vcid <= ('1',others=>'0');
+
+ gen_vcids : process (rst)
+ begin
+ lgen : for I in NOCEM_NUM_VC-1 downto 0 loop
+ vc_myid_conv(I) <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_VC_ID_WIDTH);
+ end loop;
+ end process;
+
+
+ --FIFO data format: (...) pkt_cntrl,pkt_data (0)
+
+ datain_pad(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto NOCEM_DW) <= wr_pkt_cntrl;
+ datain_pad(NOCEM_DW-1 downto 0) <= wr_pkt_data;
+
+
+
+
+vc_read_sel : process (vc_empty_i,vc_mux_rd,rst,RE, vc_mux_wr, WE, dataout_pad,fifo_rd_data)
+begin
+
+ rd_pkt_data <= (others => '0');
+ rd_pkt_cntrl <= (others => '0');
+ vc_pkt_cntrl <= (others => (others => '0'));
+ vc_pkt_data <= (others => (others => '0'));
+ fifo_wr_en <= (others => '0');
+ fifo_rd_en <= (others => '0');
+ dataout_pad <= (others => '0');
+ vc_empty <= vc_empty_i;
+
+ if rst = '1' then
+ null;
+ else
+
+
+
+ -- push dataout from the correct fifo
+ l1: for I in NOCEM_NUM_VC-1 downto 0 loop
+
+ fifo_wr_en(I) <= vc_mux_wr(I) and WE;
+ fifo_rd_en(I) <= vc_mux_rd(I) and RE;
+ vc_pkt_cntrl(I) <= fifo_rd_data(I)(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto NOCEM_DW);
+ vc_pkt_data(I) <= fifo_rd_data(I)(NOCEM_DW-1 downto 0);
+
+
+ if vc_mux_rd(I) = '1' then
+ dataout_pad <= fifo_rd_data(I);
+ end if;
+ end loop;
+
+ -- breakout the padded dataout lines
+ rd_pkt_cntrl <= dataout_pad(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto NOCEM_DW);
+ rd_pkt_data <= dataout_pad(NOCEM_DW-1 downto 0);
+
+ end if;
+
+end process;
+
+
+ g1: for I in NOCEM_NUM_VC-1 downto 0 generate
+
+
+
+
+
+
+ I_vc : fifo_allvhdl
+ generic map(
+ WIDTH => NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH,
+ ADDR_WIDTH => Log2(NOCEM_MAX_PACKET_LENGTH)
+ )
+ PORT MAP(
+ din => datain_pad,
+ clk => clk,
+ rd_en => fifo_rd_en(I),
+ rst => rst,
+ wr_en => fifo_wr_en(I),
+ dout => fifo_rd_data(I),
+ empty => vc_empty_i(I),
+ full => vc_full(I)
+ );
+
+
+
+ I_vc_cntrlr : vc_controller PORT MAP(
+ vc_my_id => vc_myid_conv(I),
+ node_my_id => node_dest_id,
+ pkt_cntrl_rd => vc_pkt_cntrl(I),
+ pkt_cntrl_wr => wr_pkt_cntrl,
+ pkt_re => fifo_rd_en(I),
+ pkt_we => fifo_wr_en(I),
+ vc_fifo_empty => vc_empty_i(I),
+ vc_eop_rd_status => vc_eop_rd_status(I), -- directly outputted to channel_fifo
+ vc_eop_wr_status => vc_eop_wr_status(I), -- directly outputted to channel_fifo
+
+ vc_allocation_req => open,
+ vc_req_id => open,
+ vc_allocate_from_node => dummy_vcid,
+ vc_requester_from_node => vc_myid_conv(I),
+ channel_dest => open,
+ vc_dest => open,
+ vc_switch_req => open,
+ rst => rst,
+ clk => clk
+ );
+
+
+
+ end generate;
+
+-----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+
+
+
+end Behavioral;
+
+
Index: nocem/trunk/VHDL/vc_channel.vhd
===================================================================
--- nocem/trunk/VHDL/vc_channel.vhd (nonexistent)
+++ nocem/trunk/VHDL/vc_channel.vhd (revision 8)
@@ -0,0 +1,570 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: vc_channel.vhd
+--
+-- Description: toplevel instantion of a virtual channel
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.pkg_nocem.all;
+
+entity vc_channel is
+generic (
+ IS_AN_ACCESS_POINT_CHANNEL : boolean := FALSE
+ ) ;
+port (
+
+ node_dest_id : in node_addr_word;
+ vc_mux_wr : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_mux_rd : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ wr_pkt_cntrl : in std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ wr_pkt_data : in std_logic_vector(NOCEM_DW-1 downto 0);
+
+ rd_pkt_cntrl : out std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ rd_pkt_data : out std_logic_vector(NOCEM_DW-1 downto 0);
+
+ rd_pkt_chdest : out std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+ rd_pkt_vcdest : out vc_addr_word;
+ rd_pkt_vcsrc : out vc_addr_word;
+
+
+ vc_empty : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_full : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+
+ -- VC allocation signals
+ vc_allocate_from_node : in vc_addr_word;
+ vc_requester_from_node : in vc_addr_word;
+
+ vc_allocate_destch_to_node : out std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+ vc_requester_to_node : out vc_addr_word;
+ vc_eop_rd_status : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_eop_wr_status : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ RE : in std_logic;
+ WE : in std_logic;
+
+ clk : in std_logic;
+ rst : in std_logic
+);
+
+
+end vc_channel;
+
+architecture Behavioral of vc_channel is
+
+ signal vc_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_VC-1 downto 0);
+ signal vc_allocation_req : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+
+ signal vc_req_id : vc_addr_array(7 downto 0);
+ signal channel_dest : arb_decision_array(7 downto 0);
+ signal vc_dest : vc_addr_array(7 downto 0);
+ signal vc_switch_req : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ signal fifo_wr_en : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal fifo_rd_en : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ -- pack the data and control lines of the packet into one word
+ signal datain_packed,dataout_packed : std_logic_vector(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+
+ --------------------------------------------------------------------
+ --------- for the BRAM implementation a 32b line is used -----------
+ --------------------------------------------------------------------
+ signal datain_32 : std_logic_vector(31 downto 0);
+
+ subtype slv32 is std_logic_vector(31 downto 0);
+ type array_slv32 is array(natural range <>) of slv32;
+
+ signal fifo_rd_data_32 : array_slv32(NOCEM_NUM_VC-1 downto 0);
+ --------------------------------------------------------------------
+ --------------------------------------------------------------------
+
+ subtype packedstdlogic is std_logic_vector(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ type array_packed is array(natural range <>) of packedstdlogic;
+
+ signal fifo_rd_data : array_packed(NOCEM_NUM_VC-1 downto 0);
+
+ signal vc_switch_grant : std_logic_vector(7 downto 0);
+
+
+ signal vc_alloc_mux_sel : std_logic_vector(7 downto 0);
+ signal vc_empty_i : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ -- needed for Modelsim Simulator ....
+ signal vc_myid_conv : vc_addr_array(NOCEM_NUM_VC-1 downto 0);
+
+
+ -- debug signals
+ signal db_error : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal db_want_eop : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal db_want_sop : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+
+begin
+
+
+ gen_vcids : process (rst)
+ begin
+ lgen : for I in NOCEM_NUM_VC-1 downto 0 loop
+ vc_myid_conv(I) <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_VC_ID_WIDTH);
+ end loop;
+ end process;
+
+ datain_packed(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto NOCEM_DW) <= wr_pkt_cntrl;
+ datain_packed(NOCEM_DW-1 downto 0) <= wr_pkt_data;
+
+
+
+ vc_read_sel : process (vc_empty_i,vc_mux_rd,rst,RE, vc_mux_wr, WE, dataout_packed,fifo_rd_data)
+ begin
+
+ vc_pkt_cntrl <= (others => (others => '0'));
+ fifo_wr_en <= (others => '0');
+ fifo_rd_en <= (others => '0');
+ dataout_packed <= (others => '0');
+ vc_empty <= vc_empty_i;
+
+
+
+
+ -- push dataout from the correct fifo
+ l1: for I in NOCEM_NUM_VC-1 downto 0 loop
+
+ fifo_wr_en(I) <= vc_mux_wr(I) and WE;
+ fifo_rd_en(I) <= vc_mux_rd(I) and RE;
+ vc_pkt_cntrl(I) <= fifo_rd_data(I)(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto NOCEM_DW);
+
+ if vc_mux_rd(I) = '1' then
+ dataout_packed <= fifo_rd_data(I);
+ end if;
+ end loop;
+
+ end process;
+
+
+ data_packed_handling : process (dataout_packed,datain_packed)
+ begin
+
+ -- breakout the padded dataout lines
+ rd_pkt_cntrl <= dataout_packed(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto NOCEM_DW);
+ rd_pkt_data <= dataout_packed(NOCEM_DW-1 downto 0);
+
+ datain_32 <= (others => '0');
+ datain_32(NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH-1 downto 0) <= datain_packed;
+
+
+
+
+ end process;
+
+
+ ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- GENERATE THE NEEDED FIFOS AND DATA PADDING AS NEEDED --
+ ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+
+
+ g1: for I in NOCEM_NUM_VC-1 downto 0 generate
+
+ -- ONLY difference is:
+ -- if FIFO is attached to an accesspoint, it must be able to
+ -- hold an ENTIRE packet, where inside the NoC, this is not the case
+ g11: if IS_AN_ACCESS_POINT_CHANNEL = FALSE generate
+
+
+ g111: if NOCEM_FIFO_IMPLEMENTATION= NOCEM_FIFO_LUT_TYPE generate
+
+ I_vc : fifo_allvhdl
+ generic map(
+ WIDTH => NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH,
+ ADDR_WIDTH => Log2(NOCEM_CHFIFO_DEPTH) -- LENGTH: CHFIFO_DEPTH
+ )
+ PORT MAP(
+ din => datain_packed,
+ clk => clk,
+ rd_en => fifo_rd_en(I),
+ rst => rst,
+ wr_en => fifo_wr_en(I),
+ dout => fifo_rd_data(I),
+ empty => vc_empty_i(I),
+ full => vc_full(I)
+ );
+
+ end generate;
+
+
+ end generate;
+
+
+
+ g12: if IS_AN_ACCESS_POINT_CHANNEL = TRUE generate
+
+
+
+ g121: if NOCEM_FIFO_IMPLEMENTATION= NOCEM_FIFO_LUT_TYPE generate
+
+
+
+ I_vc : fifo_allvhdl
+ generic map(
+ WIDTH => NOCEM_DW+NOCEM_PKT_CNTRL_WIDTH,
+ ADDR_WIDTH => Log2(NOCEM_MAX_PACKET_LENGTH) -- LENGTH: PACKET LENGTH
+ )
+ PORT MAP(
+ din => datain_packed,
+ clk => clk,
+ rd_en => fifo_rd_en(I),
+ rst => rst,
+ wr_en => fifo_wr_en(I),
+ dout => fifo_rd_data(I),
+ empty => vc_empty_i(I),
+ full => vc_full(I)
+ );
+
+ end generate;
+
+
+ end generate;
+
+
+ -- generate a virtual FIFO controller.
+ I_vc_cntrlr : vc_controller PORT MAP(
+ vc_my_id => vc_myid_conv(I),
+ node_my_id => node_dest_id,
+ pkt_cntrl_rd => vc_pkt_cntrl(I),
+ pkt_cntrl_wr => wr_pkt_cntrl,
+ pkt_re => fifo_rd_en(I),
+ pkt_we => fifo_wr_en(I),
+ vc_fifo_empty => vc_empty_i(I),
+ vc_eop_rd_status => vc_eop_rd_status(I), -- directly outputted to channel_fifo
+ vc_eop_wr_status => vc_eop_wr_status(I), -- directly outputted to channel_fifo
+
+ vc_allocation_req => vc_allocation_req(I),
+ vc_req_id => vc_req_id(I),
+ vc_allocate_from_node => vc_allocate_from_node,
+ vc_requester_from_node => vc_requester_from_node,
+ channel_dest => channel_dest(I),
+ vc_dest => vc_dest(I),
+ vc_switch_req => vc_switch_req(I),
+ rst => rst,
+ clk => clk
+ );
+
+
+
+
+ end generate;
+
+-----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+-- VC Allocation muxing, arbitration, marshalling/demarshalling of arguments
+-----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+
+
+-- currently, only 2 and 4 virtual channel per physical channel are implemented
+-- this is due to needed a power of 2 virtual channel count and with 8 virtual channels
+-- the design gets very large very fast!
+
+
+ I_vc_ch_alloc_arb: xto1_arbiter
+
+ generic map(
+ NUM_REQS => NOCEM_NUM_VC,
+ REG_OUTPUT => 0
+ )
+ PORT MAP(
+ arb_req => vc_allocation_req,
+ arb_grant => vc_alloc_mux_sel(NOCEM_NUM_VC-1 downto 0),
+ clk => clk,
+ rst => rst
+ );
+
+
+ vc_alloc_mux4_gen: if NOCEM_NUM_VC = 4 generate
+
+ I_vc_ch_alloc_mux1 : mux4to1
+ generic map(
+ DWIDTH => 5, -- one hot encoding for ch-dest
+ REG_OUTPUT => 0
+ )
+ PORT MAP(
+ din0 => channel_dest(0),
+ din1 => channel_dest(1),
+ din2 => channel_dest(2),
+ din3 => channel_dest(3),
+ sel => vc_alloc_mux_sel(3 downto 0),
+ dout => vc_allocate_destch_to_node,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_ch_alloc_mux2 : mux4to1
+ generic map(
+ DWIDTH => NOCEM_VC_ID_WIDTH,
+ REG_OUTPUT => 0
+ )
+ PORT MAP(
+ din0 => vc_req_id(0),
+ din1 => vc_req_id(1),
+ din2 => vc_req_id(2),
+ din3 => vc_req_id(3),
+ sel => vc_alloc_mux_sel(3 downto 0),
+ dout => vc_requester_to_node,
+ clk => clk,
+ rst => rst
+ );
+
+ end generate;
+
+
+
+ vc_alloc_mux2_gen: if NOCEM_NUM_VC = 2 generate
+
+ I_vc_ch_alloc_mux1 : mux2to1
+ generic map(
+ DWIDTH => 5, -- one hot encoding for ch-dest
+ REG_OUTPUT => 0
+ )
+ PORT MAP(
+ din0 => channel_dest(0),
+ din1 => channel_dest(1),
+ sel => vc_alloc_mux_sel(1 downto 0),
+ dout => vc_allocate_destch_to_node,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_ch_alloc_mux2 : mux2to1
+ generic map(
+ DWIDTH => NOCEM_VC_ID_WIDTH,
+ REG_OUTPUT => 0
+ )
+ PORT MAP(
+ din0 => vc_req_id(0),
+ din1 => vc_req_id(1),
+ sel => vc_alloc_mux_sel(1 downto 0),
+ dout => vc_requester_to_node,
+ clk => clk,
+ rst => rst
+ );
+
+ end generate;
+
+
+
+-----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+-- switch allocation muxing, arbitration, marshalling/demarshalling of arguments
+-----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+
+-- currently, only 2 and 4 virtual channel per physical channel are implemented
+-- this is due to needed a power of 2 virtual channel count and with 8 virtual channels
+-- the design gets very large very fast!
+
+
+ I_ch_switch_arb: xto1_arbiter
+
+ generic map(
+ NUM_REQS => NOCEM_NUM_VC,
+ REG_OUTPUT => 1
+ )
+ PORT MAP(
+ arb_req => vc_switch_req,
+ arb_grant => vc_switch_grant(NOCEM_NUM_VC-1 downto 0),
+ clk => clk,
+ rst => rst
+ );
+
+
+
+ ch_alloc_mux4_gen: if NOCEM_NUM_VC = 4 generate
+
+
+ I_vc_switch_alloc4_mux1 : mux4to1
+ generic map
+ (
+ DWIDTH => NOCEM_ARB_IX_SIZE,
+ REG_OUTPUT => 1
+
+ )
+ PORT MAP(
+ din0 => channel_dest(0),
+ din1 => channel_dest(1),
+ din2 => channel_dest(2),
+ din3 => channel_dest(3),
+ sel => vc_switch_grant(3 downto 0),
+ dout => rd_pkt_chdest,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_switch_alloc4_mux2 : mux4to1
+ generic map(
+ DWIDTH => NOCEM_VC_ID_WIDTH,
+ REG_OUTPUT => 1
+ )
+ PORT MAP(
+ din0 => vc_dest(0),
+ din1 => vc_dest(1),
+ din2 => vc_dest(2),
+ din3 => vc_dest(3),
+ sel => vc_switch_grant(3 downto 0),
+ dout => rd_pkt_vcdest,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_switch_alloc4_mux3 : mux4to1
+ generic map(
+ DWIDTH => NOCEM_VC_ID_WIDTH,
+ REG_OUTPUT => 1
+ )
+ PORT MAP(
+ din0 => "0001",
+ din1 => "0010",
+ din2 => "0100",
+ din3 => "1000",
+ sel => vc_switch_grant(3 downto 0),
+ dout => rd_pkt_vcsrc,
+ clk => clk,
+ rst => rst
+ );
+
+ end generate;
+
+
+ ch_alloc_mux2_gen: if NOCEM_NUM_VC = 2 generate
+
+
+ I_vc_switch_alloc2_mux1 : mux2to1
+ generic map
+ (
+ DWIDTH => NOCEM_ARB_IX_SIZE,
+ REG_OUTPUT => 1
+
+ )
+ PORT MAP(
+ din0 => channel_dest(0),
+ din1 => channel_dest(1),
+ sel => vc_switch_grant(1 downto 0),
+ dout => rd_pkt_chdest,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_switch_alloc2_mux2 : mux2to1
+ generic map(
+ DWIDTH => NOCEM_VC_ID_WIDTH,
+ REG_OUTPUT => 1
+ )
+ PORT MAP(
+ din0 => vc_dest(0),
+ din1 => vc_dest(1),
+ sel => vc_switch_grant(1 downto 0),
+ dout => rd_pkt_vcdest,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_switch_alloc2_mux3 : mux2to1
+ generic map(
+ DWIDTH => NOCEM_VC_ID_WIDTH,
+ REG_OUTPUT => 1
+ )
+ PORT MAP(
+ din0 => "01",
+ din1 => "10",
+ sel => vc_switch_grant(1 downto 0),
+ dout => rd_pkt_vcsrc,
+ clk => clk,
+ rst => rst
+ );
+
+ end generate;
+
+
+---------------------------------------------------------------------------------
+--debugging process: simply for debugging purposes. These signals would get --
+--eaten during synthesis as they do not affect downstream logic --
+-- ....delete if needed.... --
+---------------------------------------------------------------------------------
+
+db_gen : process (clk,rst)
+begin
+
+
+ if rst='1' then
+ db_error <= (others => '0');
+ db_want_eop <= (others => '0');
+ db_want_sop <= (others => '1');
+ elsif clk='1' and clk'event then
+
+ db_loop: for I in NOCEM_NUM_VC-1 downto 0 loop
+ if fifo_wr_en(I)='1' and wr_pkt_cntrl(NOCEM_PKTCNTRL_SOP_IX)='1' then
+ db_want_eop(I) <= '1';
+ db_want_sop(I) <= '0';
+
+ elsif fifo_wr_en(I)='1' and wr_pkt_cntrl(NOCEM_PKTCNTRL_EOP_IX)='1' then
+ db_want_eop(I) <= '0';
+ db_want_sop(I) <= '1';
+ end if;
+
+ if fifo_wr_en(I)='1' and db_want_eop(I)='1' and wr_pkt_cntrl(NOCEM_PKTCNTRL_SOP_IX)='1' then
+ db_error(I) <= '1';
+ elsif fifo_wr_en(I)='1' and db_want_sop(I)='1' and wr_pkt_cntrl(NOCEM_PKTCNTRL_EOP_IX)='1' then
+ db_error(I) <= '1';
+ else
+ db_error(I) <= '0';
+ end if;
+
+ end loop;
+ end if;
+
+
+
+end process;
+
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/ap_exerciser_vc.vhd
===================================================================
--- nocem/trunk/VHDL/ap_exerciser_vc.vhd (nonexistent)
+++ nocem/trunk/VHDL/ap_exerciser_vc.vhd (revision 8)
@@ -0,0 +1,416 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: ap_exerciser_vc.vhd
+--
+-- Description: access point exerciser for VC designs
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.pkg_nocem.all;
+
+
+entity ap_exerciser_vc is
+ Generic(
+
+ DELAY_START_COUNTER_WIDTH : integer := 32;
+ DELAY_START_CYCLES : integer := 500;
+ PKT_LENGTH : integer := 5;
+ INTERVAL_COUNTER_WIDTH : integer := 8;
+ DATA_OUT_INTERVAL : integer := 16;
+ INIT_DEST_ADDR : integer := 0;
+ MY_ADDR : integer := 0;
+ EXERCISER_MODE : integer := EXERCISER_MODE_SIM
+ ) ;
+ Port (
+
+ -- arbitration lines (usage depends on underlying network)
+ arb_req : out std_logic;
+ arb_cntrl_out : out arb_cntrl_word;
+
+ arb_grant : in std_logic;
+ arb_cntrl_in : in arb_cntrl_word;
+
+ datain : in data_word;
+ datain_valid : in std_logic;
+ datain_recvd : out std_logic;
+
+ dataout : out data_word;
+ dataout_valid : out std_logic;
+ dataout_recvd : in std_logic;
+
+ pkt_cntrl_in : in pkt_cntrl_word;
+ pkt_cntrl_in_valid : in std_logic;
+ pkt_cntrl_in_recvd : out std_logic;
+
+ pkt_cntrl_out : out pkt_cntrl_word;
+ pkt_cntrl_out_valid : out std_logic;
+ pkt_cntrl_out_recvd : in std_logic;
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+end ap_exerciser_vc;
+
+architecture Behavioral of ap_exerciser_vc is
+
+ signal rst_i : std_logic;
+ signal rst_counter : std_logic_vector(DELAY_START_COUNTER_WIDTH-1 downto 0);
+ signal interval_counter : std_logic_vector(INTERVAL_COUNTER_WIDTH-1 downto 0);
+ signal dataout_reg : std_logic_vector(NOCEM_DW-1 downto 0);
+ signal pkt_cntrl_out_reg : pkt_cntrl_word;
+
+
+ signal burst_counter : std_logic_vector(7 downto 0);
+
+ signal datain_reg : data_word;
+ signal pkt_cntrl_in_reg : pkt_cntrl_word;
+
+
+ type stateType is (init_st,sending_st,getting_vc_st);
+ signal state,nextState : stateType;
+
+ -- determine the next free outgoing VC
+ signal next_free_vc : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal vc_state : std_logic_Vector(NOCEM_NUM_VC-1 downto 0); -- 0: free, 1: allocated --
+ signal vc_allocate : std_logic;
+ signal free_this_vc : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal vc_mux_wr_reg : std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+
+
+ -- data gathering signals
+ signal next_vc_with_pkt,finished_pkt,eop_wr_sig,pkt_rdy : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal recv_idle : std_logic;
+
+ -- arbcntrl out signals used for ORing together
+ signal arb_sending_word,arb_receiving_word : arb_cntrl_word;
+
+ signal allones_vcwidth : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ -- any debug signals
+ signal debug_vc_mux_wr : std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+
+
+begin
+
+allones_vcwidth <= (others => '1');
+
+-- arbcntrl out signals used for ORing together
+arb_cntrl_out <= arb_sending_word or arb_receiving_word;
+
+
+rst_gen : process (clk,rst)
+begin
+ if rst='1' then
+ rst_i <= '1';
+ rst_counter <= (others => '0');
+ elsif clk'event and clk ='1' then
+ rst_counter <= rst_counter+1;
+ if rst_counter = DELAY_START_CYCLES then
+ rst_i <= '0';
+ end if;
+ end if;
+end process;
+
+
+----------------------------------------------------------------------------------
+--------KEEPING TRACK OF OUTGOING VC STATES --------------------------------------
+----------------------------------------------------------------------------------
+
+gen_vc_status_uclkd : process (vc_state)
+begin
+
+end process;
+
+gen_vc_status_clkd : process (clk,rst)
+begin
+
+
+ if rst='1' then
+ --next_free_vc <= ('1',others => '0');
+ vc_state <= (others => '0');
+ free_this_vc <= (others => '0');
+ next_free_vc <= (others => '0');
+ elsif clk'event and clk='1' then
+
+
+ l2: for I in NOCEM_NUM_VC-1 downto 0 loop
+ if vc_state(I) = '0' then
+ next_free_vc <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_VC);
+ end if;
+ end loop;
+
+ if vc_state = allones_vcwidth then
+ next_free_vc <= (others => '0');
+ end if;
+
+
+ free_this_vc <= arb_cntrl_in(NOCEM_ARB_CNTRL_VC_EOP_RD_HIX downto NOCEM_ARB_CNTRL_VC_EOP_RD_LIX);
+
+ -- 0: free, 1: allocated --
+ l1: for I in NOCEM_NUM_VC-1 downto 0 loop
+ if vc_state(I) = '0' and next_free_vc(I) = '1' and vc_allocate = '1' then -- free going to allocated
+ vc_state(I) <= '1';
+ elsif vc_state(I) = '1' and free_this_vc(I) = '1' then -- allocated going to free
+ vc_state(I) <= '0';
+ end if;
+ end loop;
+
+ end if;
+end process;
+
+----------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+
+
+dataout_gen_clkd : process (clk,rst_i,nextState)
+begin
+ if rst_i = '1' then
+ state <= init_st;
+ interval_counter <= (others => '0');
+ dataout_reg <= (others => '0');
+ vc_mux_wr_reg <= (others => '0');
+ -- setup pkt_cntrl correctly
+ pkt_cntrl_out_reg <= (others => '0');
+ pkt_cntrl_out_reg(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) <= addr_gen(INIT_DEST_ADDR,NOCEM_NUM_ROWS,NOCEM_NUM_COLS,NOCEM_AW);
+
+
+ burst_counter <= (others => '0');
+ elsif clk'event and clk='1' then
+ state <= nextState;
+ case state is
+ when init_st =>
+ interval_counter <= interval_counter+1;
+ --dataout_reg <= (others => '0');
+-- pkt_cntrl_out_reg(NOCEM_PKTCNTRL_SOP_IX) <= '1';
+--
+-- if PKT_LENGTH = 1 then
+-- pkt_cntrl_out_reg(NOCEM_PKTCNTRL_EOP_IX) <= '1';
+-- else
+-- pkt_cntrl_out_reg(NOCEM_PKTCNTRL_EOP_IX) <= '0';
+-- end if;
+ vc_mux_wr_reg <= (others => '0');
+
+
+
+
+ burst_counter <= (others => '0');
+
+ when getting_vc_st =>
+ --pkt_cntrl_out_reg <= (others => '0');
+ interval_counter <= (others => '0');
+ vc_mux_wr_reg <= next_free_vc;
+ when sending_st =>
+ -- marking packets with src addrs...
+ dataout_reg(NOCEM_DW-1 downto NOCEM_AW) <= dataout_reg(NOCEM_DW-1 downto NOCEM_AW) + 1;
+ dataout_reg(NOCEM_AW-1 downto 0) <= addr_gen(MY_ADDR,NOCEM_NUM_ROWS,NOCEM_NUM_COLS,NOCEM_AW);
+
+ -- handle the pkt_control reg
+
+ -- increment the data inside
+ if arb_grant = '1' and dataout_recvd = '1' then
+ burst_counter <= burst_counter + 1;
+ end if;
+
+ if nextState = init_st then
+
+ -- increment destination field (making sure it doesn't send a packet to myself)
+ if pkt_cntrl_out_reg(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX)+1 = addr_gen(MY_ADDR,NOCEM_NUM_ROWS,NOCEM_NUM_COLS,NOCEM_AW) then
+ pkt_cntrl_out_reg(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) <= pkt_cntrl_out_reg(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) + 2;
+ else
+ pkt_cntrl_out_reg(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) <= pkt_cntrl_out_reg(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) + 1;
+ end if;
+ end if;
+
+
+
+ when others =>
+ null;
+ end case;
+ end if;
+end process;
+
+
+dataout_gen_uclkd : process (next_free_vc, vc_mux_wr_reg,pkt_cntrl_out_reg, pkt_cntrl_out_recvd,state, interval_counter, dataout_reg, arb_grant, dataout_recvd, burst_counter)
+begin
+
+ arb_req <= '0';
+ arb_sending_word <= (others => '0');
+ dataout <= (others => '0');
+ dataout_valid <= '0';
+ --nextState <= init_st;
+
+ pkt_cntrl_out <= (others => '0');
+ pkt_cntrl_out_valid <= '0';
+ vc_allocate <= '0';
+
+ case state is
+ when init_st =>
+
+ if interval_counter = CONV_STD_LOGIC_VECTOR(DATA_OUT_INTERVAL,INTERVAL_COUNTER_WIDTH) then
+ nextState <= getting_vc_st;
+ else
+ nextState <= init_st;
+ end if;
+
+ when getting_vc_st =>
+
+ if next_free_vc /= 0 then
+ vc_allocate <= '1';
+ nextState <= sending_st;
+ else
+ nextState <= getting_vc_st;
+ end if;
+
+
+ when sending_st =>
+
+ arb_req <= '1';
+ arb_sending_word(NOCEM_ARB_CNTRL_VC_MUX_WR_HIX downto NOCEM_ARB_CNTRL_VC_MUX_WR_LIX) <= vc_mux_wr_reg;
+
+ dataout <= dataout_reg;
+ dataout_valid <= '1';
+
+ pkt_cntrl_out <= pkt_cntrl_out_reg;
+ pkt_cntrl_out_valid <= '1';
+
+
+ if burst_counter = 0 then
+ pkt_cntrl_out(NOCEM_PKTCNTRL_SOP_IX) <= '1';
+ end if;
+
+ if burst_counter = PKT_LENGTH then
+ pkt_cntrl_out(NOCEM_PKTCNTRL_EOP_IX) <= '1';
+ nextState <= init_st;
+ else
+ nextState <= sending_st;
+ end if;
+
+ when others =>
+ null;
+ end case;
+end process;
+
+
+
+----------------------------------------------------
+----------------------------------------------------
+----------- DATAIN SIGNALLING -------------
+----------------------------------------------------
+----------------------------------------------------
+
+vc_datain_st_gen_clkd : process(clk,rst,arb_cntrl_in)
+begin
+
+ eop_wr_sig <= arb_cntrl_in(NOCEM_ARB_CNTRL_VC_EOP_WR_HIX downto NOCEM_ARB_CNTRL_VC_EOP_WR_LIX);
+
+ if rst='1' then
+ pkt_rdy <= (others => '0');
+ next_vc_with_pkt <= (others => '0');
+ datain_reg <= (others => '0');
+ pkt_cntrl_in_reg <= (others => '0');
+ recv_idle <= '1';
+ elsif clk'event and clk='1' then
+
+
+ l1: for I in NOCEM_NUM_VC-1 downto 0 loop
+
+ -- is the pkt rdy for reading?
+ if eop_wr_sig(I) = '1' then
+ pkt_rdy(I) <= '1';
+ elsif finished_pkt(I) = '1' then
+ pkt_rdy(I) <= '0';
+ end if;
+
+ -- what is the next pkt to read from VCs?
+ if pkt_rdy(I) = '1' and recv_idle = '1' then
+ next_vc_with_pkt <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_VC);
+ recv_idle <= '0';
+ elsif finished_pkt /= 0 then
+ recv_idle <= '1';
+ end if;
+
+ end loop;
+
+ if pkt_rdy = 0 then
+ next_vc_with_pkt <= (others => '0');
+ end if;
+
+
+ end if;
+
+end process;
+
+
+
+datain_gather_uclkd : process (next_vc_with_pkt, pkt_cntrl_in,datain_valid,pkt_cntrl_in_valid)
+begin
+
+ datain_recvd <= '0';
+ pkt_cntrl_in_recvd <= '0';
+ finished_pkt <= (others => '0');
+ arb_receiving_word <= (others => '0');
+
+
+ if next_vc_with_pkt /= 0 then
+ arb_receiving_word(NOCEM_ARB_CNTRL_VC_MUX_RD_HIX downto NOCEM_ARB_CNTRL_VC_MUX_RD_LIX) <= next_vc_with_pkt;
+ datain_recvd <= '1';
+ end if;
+
+ if next_vc_with_pkt /= 0 then
+ pkt_cntrl_in_recvd <= '1';
+ if pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ finished_pkt <= next_vc_with_pkt;
+ end if;
+ end if;
+
+
+end process;
+
+
+
+debug_gen : process (arb_sending_word)
+begin
+
+ debug_vc_mux_wr <= arb_sending_word(NOCEM_ARB_CNTRL_VC_MUX_WR_HIX downto NOCEM_ARB_CNTRL_VC_MUX_WR_LIX);
+
+end process;
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/simple_pkt_local_switch.vhd
===================================================================
--- nocem/trunk/VHDL/simple_pkt_local_switch.vhd (nonexistent)
+++ nocem/trunk/VHDL/simple_pkt_local_switch.vhd (revision 8)
@@ -0,0 +1,256 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: simple_pkt_local_switch.vhd
+--
+-- Description: simple switch design
+--
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+
+
+entity simple_pkt_local_switch is
+ Port (
+
+
+ -- the arbitration logic controls the switches of data
+ arb_grant_output : in arb_decision_array(4 downto 0);
+ --arb_grant_input : in std_logic_vector(4 downto 0);
+
+
+ ap_datain : in data_word;
+ ap_dataout : out data_word;
+ n_datain : in data_word;
+ n_dataout : out data_word;
+ s_datain : in data_word;
+ s_dataout : out data_word;
+ e_datain : in data_word;
+ e_dataout : out data_word;
+ w_datain : in data_word;
+ w_dataout : out data_word;
+
+ n_pkt_cntrl_in : in pkt_cntrl_word;
+ n_pkt_cntrl_out : out pkt_cntrl_word;
+
+ s_pkt_cntrl_in : in pkt_cntrl_word;
+ s_pkt_cntrl_out : out pkt_cntrl_word;
+
+ e_pkt_cntrl_in : in pkt_cntrl_word;
+ e_pkt_cntrl_out : out pkt_cntrl_word;
+
+ w_pkt_cntrl_in : in pkt_cntrl_word;
+ w_pkt_cntrl_out : out pkt_cntrl_word;
+
+ ap_pkt_cntrl_in : in pkt_cntrl_word;
+ ap_pkt_cntrl_out : out pkt_cntrl_word;
+
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+end simple_pkt_local_switch;
+
+architecture Behavioral of simple_pkt_local_switch is
+
+
+
+
+
+begin
+
+switch_gen_process : process (ap_pkt_cntrl_in, n_pkt_cntrl_in, s_pkt_cntrl_in, e_pkt_cntrl_in, w_pkt_cntrl_in,arb_grant_output, ap_datain, n_datain, s_datain, e_datain, w_datain)
+
+
+begin
+
+ ----------------------------------------------
+ ---------- do output arbitration -------------
+ ----------------------------------------------
+
+
+-- ap_dataout_valid <= '0';
+-- n_dataout_valid <= '0';
+-- south_dataout_valid <= '0';
+-- east_dataout_valid <= '0';
+-- west_dataout_valid <= '0';
+
+
+ ap_dataout <= (others => '0');
+ n_dataout <= (others => '0');
+ s_dataout <= (others => '0');
+ e_dataout <= (others => '0');
+ w_dataout <= (others => '0');
+
+
+ ap_pkt_cntrl_out <= (others => '0');
+ n_pkt_cntrl_out <= (others => '0');
+ s_pkt_cntrl_out <= (others => '0');
+ e_pkt_cntrl_out <= (others => '0');
+ w_pkt_cntrl_out <= (others => '0');
+
+
+
+
+ -- foreach output line, simply mux in the incoming lines
+ -- based on arbitration decision
+ -- arb_grant_output(4) : NORTH
+ -- arb_grant_output(3) : SOUTH
+ -- arb_grant_output(2) : EAST
+ -- arb_grant_output(1) : WEST
+ -- arb_grant_output(0) : AP
+
+
+ case arb_grant_output(NOCEM_AP_IX) is
+ when ARB_AP =>
+ ap_dataout <= ap_datain;
+ ap_pkt_cntrl_out <= ap_pkt_cntrl_in;
+ when ARB_NORTH =>
+ ap_dataout <= n_datain;
+ ap_pkt_cntrl_out <= n_pkt_cntrl_in;
+ when ARB_SOUTH =>
+ ap_dataout <= s_datain;
+ ap_pkt_cntrl_out <= s_pkt_cntrl_in;
+ when ARB_EAST =>
+ ap_dataout <= e_datain;
+ ap_pkt_cntrl_out <= e_pkt_cntrl_in;
+ when ARB_WEST =>
+ ap_dataout <= w_datain;
+ ap_pkt_cntrl_out <= w_pkt_cntrl_in;
+ when others =>
+ null;
+ end case;
+
+
+
+ case arb_grant_output(NOCEM_NORTH_IX) is
+ when ARB_AP =>
+ n_dataout <= ap_datain;
+ n_pkt_cntrl_out <= ap_pkt_cntrl_in;
+ when ARB_NORTH =>
+ n_dataout <= n_datain;
+ n_pkt_cntrl_out <= n_pkt_cntrl_in;
+ when ARB_SOUTH =>
+ n_dataout <= s_datain;
+ n_pkt_cntrl_out <= s_pkt_cntrl_in;
+ when ARB_EAST =>
+ n_dataout <= e_datain;
+ n_pkt_cntrl_out <= e_pkt_cntrl_in;
+ when ARB_WEST =>
+ n_dataout <= w_datain;
+ n_pkt_cntrl_out <= w_pkt_cntrl_in;
+ when others =>
+ null;
+ end case;
+
+ case arb_grant_output(NOCEM_SOUTH_IX) is
+ when ARB_AP =>
+ s_dataout <= ap_datain;
+ s_pkt_cntrl_out <= ap_pkt_cntrl_in;
+ when ARB_NORTH =>
+ s_dataout <= n_datain;
+ s_pkt_cntrl_out <= n_pkt_cntrl_in;
+ when ARB_SOUTH =>
+ s_dataout <= s_datain;
+ s_pkt_cntrl_out <= s_pkt_cntrl_in;
+ when ARB_EAST =>
+ s_dataout <= e_datain;
+ s_pkt_cntrl_out <= e_pkt_cntrl_in;
+ when ARB_WEST =>
+ s_dataout <= w_datain;
+ s_pkt_cntrl_out <= w_pkt_cntrl_in;
+ when others =>
+ null;
+ end case;
+
+
+ case arb_grant_output(NOCEM_EAST_IX) is
+ when ARB_AP =>
+ e_dataout <= ap_datain;
+ e_pkt_cntrl_out <= ap_pkt_cntrl_in;
+ when ARB_NORTH =>
+ e_dataout <= n_datain;
+ e_pkt_cntrl_out <= n_pkt_cntrl_in;
+ when ARB_SOUTH =>
+ e_dataout <= s_datain;
+ e_pkt_cntrl_out <= s_pkt_cntrl_in;
+ when ARB_EAST =>
+ e_dataout <= e_datain;
+ e_pkt_cntrl_out <= e_pkt_cntrl_in;
+ when ARB_WEST =>
+ e_dataout <= w_datain;
+ e_pkt_cntrl_out <= w_pkt_cntrl_in;
+ when others =>
+ null;
+ end case;
+
+ case arb_grant_output(NOCEM_WEST_IX) is
+ when ARB_AP =>
+ w_dataout <= ap_datain;
+ w_pkt_cntrl_out <= ap_pkt_cntrl_in;
+ when ARB_NORTH =>
+ w_dataout <= n_datain;
+ w_pkt_cntrl_out <= n_pkt_cntrl_in;
+ when ARB_SOUTH =>
+ w_dataout <= s_datain;
+ w_pkt_cntrl_out <= s_pkt_cntrl_in;
+ when ARB_EAST =>
+ w_dataout <= e_datain;
+ w_pkt_cntrl_out <= e_pkt_cntrl_in;
+ when ARB_WEST =>
+ w_dataout <= w_datain;
+ w_pkt_cntrl_out <= w_pkt_cntrl_in;
+ when others =>
+ null;
+ end case;
+
+
+ ----------------------------------------------
+ ---------- END do output arbitration ---------
+ ----------------------------------------------
+
+
+
+
+
+
+
+end process;
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/pkg_nocem.vhd
===================================================================
--- nocem/trunk/VHDL/pkg_nocem.vhd (nonexistent)
+++ nocem/trunk/VHDL/pkg_nocem.vhd (revision 8)
@@ -0,0 +1,1181 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: pkg_nocem.vhd
+--
+-- Description: toplevel package file for nocem
+--
+
+
+-- THE Package File For NOCEM
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions. Any design utilizing Nocem
+-- must include this file....
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+---------------------------------------------------------
+---------------------------------------------------------
+-- enumerations and derivative type definitions are --
+-- given here. The values can be changed to change --
+-- the underlying functionality/performance of the NoC --
+---------------------------------------------------------
+---------------------------------------------------------
+
+
+package pkg_nocem is
+
+
+-- enumerate the NOC types here
+constant NOCEM_BUS_TYPE : integer := 0;
+constant NOCEM_SIMPLE_PKT_TYPE : integer := 1;
+constant NOCEM_SIMPLE_PKT_ARBSIZE_TYPE : integer := 2;
+constant NOCEM_VC_TYPE : integer := 3;
+
+
+-- enumerate channel FIFO types here
+constant NOCEM_CHFIFO_NOVC_TYPE : integer := 2;
+constant NOCEM_CHFIFO_VC_TYPE : integer := 3;
+
+
+--enumerate FIFO implementation type here
+-----------------------------------------------------------
+-- WITHIN THE NOC CHANNELS CAN USE EITHER BRAM OR LUT --
+-- BASED FIFO IMPLEMENTATIONS. --
+-----------------------------------------------------------
+constant NOCEM_FIFO_LUT_TYPE : integer := 0;
+
+
+
+-- enumerate topology types here
+--
+-- MESH: connections in grid style, no torus
+--
+--
+-- TORUS STRUCTURE: mesh connections plus connections looping
+-- top to bottom
+--
+-- DOUBLE TORUS STRUCTURE: torus structure plus connections
+-- looping left edge to right edge
+--
+constant NOCEM_TOPOLOGY_MESH : integer := 0;
+constant NOCEM_TOPOLOGY_TORUS : integer := 1;
+constant NOCEM_TOPOLOGY_DTORUS : integer := 2;
+
+
+
+
+
+
+
+
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+-- system wide constants. This is where the NoC is defined and these constants can --
+-- can be changed and modified to change behavior of the network --
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------
+
+
+constant NOCEM_TYPE : integer := NOCEM_CHFIFO_VC_TYPE;
+constant NOCEM_CHFIFO_TYPE : integer := NOCEM_CHFIFO_VC_TYPE;
+constant NOCEM_TOPOLOGY_TYPE : integer := NOCEM_TOPOLOGY_MESH;
+constant NOCEM_FIFO_IMPLEMENTATION : integer := NOCEM_FIFO_LUT_TYPE;
+
+constant NOCEM_NUM_AP : integer := 4;
+constant NOCEM_NUM_COLS : integer := 2;
+constant NOCEM_NUM_ROWS : integer := NOCEM_NUM_AP / NOCEM_NUM_COLS;
+
+constant NOCEM_DW : integer := 8;
+constant NOCEM_AW : integer := 2;
+
+
+constant NOCEM_NUM_VC : integer := 2; -- 2,4 VC's supported
+constant NOCEM_VC_ID_WIDTH : integer := NOCEM_NUM_VC; -- one hot encoding (do not change this!)
+
+constant NOCEM_CHFIFO_DEPTH : integer := 4; -- MUST BE POWER OF 2 for LUTRAM,VC CHANNEL TYPES
+constant NOCEM_MAX_PACKET_LENGTH : integer := 8; -- MUST BE POWER OF 2 for LUTRAM,VC CHANNEL TYPES
+
+
+
+
+--------------------------------------------------------------
+-- channel indexing for a variety of arbitration decisions --
+--------------------------------------------------------------
+
+constant NOCEM_NORTH_IX : integer := 4;
+constant NOCEM_SOUTH_IX : integer := 3;
+constant NOCEM_EAST_IX : integer := 2;
+constant NOCEM_WEST_IX : integer := 1;
+constant NOCEM_AP_IX : integer := 0;
+
+constant ARB_NORTH : std_logic_vector(4 downto 0) := "10000";
+constant ARB_SOUTH : std_logic_vector(4 downto 0) := "01000";
+constant ARB_EAST : std_logic_vector(4 downto 0) := "00100";
+constant ARB_WEST : std_logic_vector(4 downto 0) := "00010";
+constant ARB_AP : std_logic_vector(4 downto 0) := "00001";
+constant ARB_NODECISION : std_logic_vector(4 downto 0) := "00000";
+constant NOCEM_ARB_IX_SIZE : integer := 5;
+
+
+------------------------------------------------------
+--------------- STANDARD CHANNEL CONSTANTS -----------
+------------------------------------------------------
+
+constant NOCEM_CHFIFO_DATA_RE_IX : integer := 0;
+constant NOCEM_CHFIFO_DATA_WE_IX : integer := 1;
+constant NOCEM_CHFIFO_DATA_FULL_N_IX : integer := 2;
+constant NOCEM_CHFIFO_DATA_EMPTY_N_IX : integer := 3;
+
+constant NOCEM_CHFIFO_CNTRL_RE_IX : integer := 4;
+constant NOCEM_CHFIFO_CNTRL_WE_IX : integer := 5;
+constant NOCEM_CHFIFO_CNTRL_FULL_N_IX : integer := 6;
+constant NOCEM_CHFIFO_CNTRL_EMPTY_N_IX : integer := 7;
+
+constant NOCEM_CHFIFO_CNTRL_STANDARD_WIDTH : integer := NOCEM_CHFIFO_CNTRL_EMPTY_N_IX+1;
+
+------------------------------------------------------
+--------------- VC CHANNEL CONSTANTS -----------------
+------------------------------------------------------
+
+constant NOCEM_CHFIFO_VC_WR_ADDR_LIX : integer := NOCEM_CHFIFO_CNTRL_STANDARD_WIDTH; --8
+constant NOCEM_CHFIFO_VC_WR_ADDR_HIX : integer := NOCEM_CHFIFO_VC_WR_ADDR_LIX+NOCEM_VC_ID_WIDTH-1;
+
+constant NOCEM_CHFIFO_VC_CHDEST_LIX : integer := NOCEM_CHFIFO_VC_WR_ADDR_HIX+1;--12 --10
+constant NOCEM_CHFIFO_VC_CHDEST_HIX : integer := NOCEM_CHFIFO_VC_CHDEST_LIX+NOCEM_ARB_IX_SIZE-1;
+
+constant NOCEM_CHFIFO_VC_VCDEST_LIX : integer := NOCEM_CHFIFO_VC_CHDEST_HIX+1; --17 --15
+constant NOCEM_CHFIFO_VC_VCDEST_HIX : integer := NOCEM_CHFIFO_VC_VCDEST_LIX+NOCEM_VC_ID_WIDTH-1;
+
+constant NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX : integer := NOCEM_CHFIFO_VC_VCDEST_HIX+1; --21 --17
+constant NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX : integer := NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX+NOCEM_VC_ID_WIDTH-1;
+
+constant NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX : integer := NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX+1; --25 --19
+constant NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX : integer := NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX+NOCEM_VC_ID_WIDTH-1;
+
+constant NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX : integer := NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX+1; --29 --21
+constant NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX : integer := NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX+NOCEM_ARB_IX_SIZE-1;
+
+constant NOCEM_CHFIFO_VC_REQER_VCID_LIX : integer := NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX+1; --34 --26
+constant NOCEM_CHFIFO_VC_REQER_VCID_HIX : integer := NOCEM_CHFIFO_VC_REQER_VCID_LIX+NOCEM_VC_ID_WIDTH-1;
+
+constant NOCEM_CHFIFO_VC_EMPTY_LIX : integer := NOCEM_CHFIFO_VC_REQER_VCID_HIX+1; --38 --28
+constant NOCEM_CHFIFO_VC_EMPTY_HIX : integer := NOCEM_CHFIFO_VC_EMPTY_LIX+NOCEM_NUM_VC-1;
+
+constant NOCEM_CHFIFO_VC_FULL_LIX : integer := NOCEM_CHFIFO_VC_EMPTY_HIX+1; --42 --30
+constant NOCEM_CHFIFO_VC_FULL_HIX : integer := NOCEM_CHFIFO_VC_FULL_LIX+NOCEM_NUM_VC-1;
+
+constant NOCEM_CHFIFO_VC_EOP_RD_LIX : integer := NOCEM_CHFIFO_VC_FULL_HIX+1; --46 --32
+constant NOCEM_CHFIFO_VC_EOP_RD_HIX : integer := NOCEM_CHFIFO_VC_EOP_RD_LIX+NOCEM_NUM_VC-1;
+
+constant NOCEM_CHFIFO_VC_EOP_WR_LIX : integer := NOCEM_CHFIFO_VC_EOP_RD_HIX+1; --50 --34
+constant NOCEM_CHFIFO_VC_EOP_WR_HIX : integer := NOCEM_CHFIFO_VC_EOP_WR_LIX+NOCEM_NUM_VC-1;
+
+constant NOCEM_CHFIFO_VC_RD_ADDR_LIX : integer := NOCEM_CHFIFO_VC_EOP_WR_HIX+1; --54 --36
+constant NOCEM_CHFIFO_VC_RD_ADDR_HIX : integer := NOCEM_CHFIFO_VC_RD_ADDR_LIX+NOCEM_VC_ID_WIDTH-1;
+
+constant NOCEM_CHFIFO_VC_VCSRC_LIX : integer := NOCEM_CHFIFO_VC_RD_ADDR_HIX+1; -- 58 --38
+constant NOCEM_CHFIFO_VC_VCSRC_HIX : integer := NOCEM_CHFIFO_VC_VCSRC_LIX+NOCEM_VC_ID_WIDTH-1;
+
+
+
+constant NOCEM_CHFIFO_CNTRL_WIDTH : integer := NOCEM_CHFIFO_VC_VCSRC_HIX+1; --62 --40
+
+
+
+--------------------------------------------------------------------------------
+-- constants that have their usage defined by the underlying noc. --
+--------------------------------------------------------------------------------
+
+-- depending on what is in the control packet, can set an arbitrary width
+-- e.g. for simple packets, dest_addr/SOP/EOP are all that is needed and are
+-- both placed in a single word
+
+
+
+-- pkt control structure
+constant NOCEM_PKTCNTRL_DEST_ADDR_LIX : integer := 0;
+constant NOCEM_PKTCNTRL_DEST_ADDR_HIX : integer := NOCEM_AW-1; --1
+constant NOCEM_PKTCNTRL_SOP_IX : integer := NOCEM_PKTCNTRL_DEST_ADDR_HIX+1; --2
+constant NOCEM_PKTCNTRL_EOP_IX : integer := NOCEM_PKTCNTRL_SOP_IX+1; --3
+constant NOCEM_PKTCNTRL_OS_PKT_IX : integer := NOCEM_PKTCNTRL_EOP_IX+1;
+
+
+constant NOCEM_PKT_CNTRL_WIDTH : integer := NOCEM_PKTCNTRL_OS_PKT_IX+1; --4
+
+
+
+
+constant NOCEM_ARB_CNTRL_VC_MUX_WR_LIX : integer := 0;
+constant NOCEM_ARB_CNTRL_VC_MUX_WR_HIX : integer := NOCEM_ARB_CNTRL_VC_MUX_WR_LIX+NOCEM_VC_ID_WIDTH-1;
+
+constant NOCEM_ARB_CNTRL_VC_MUX_RD_LIX : integer := NOCEM_ARB_CNTRL_VC_MUX_WR_HIX+1; --4 --2
+constant NOCEM_ARB_CNTRL_VC_MUX_RD_HIX : integer := NOCEM_ARB_CNTRL_VC_MUX_RD_LIX+NOCEM_VC_ID_WIDTH-1;
+
+
+constant NOCEM_ARB_CNTRL_VC_EOP_RD_LIX : integer := NOCEM_ARB_CNTRL_VC_MUX_RD_HIX+1; --8 --4
+constant NOCEM_ARB_CNTRL_VC_EOP_RD_HIX : integer := NOCEM_ARB_CNTRL_VC_EOP_RD_LIX+NOCEM_NUM_VC-1;
+
+constant NOCEM_ARB_CNTRL_VC_EOP_WR_LIX : integer := NOCEM_ARB_CNTRL_VC_EOP_RD_HIX+1; --12 --6
+constant NOCEM_ARB_CNTRL_VC_EOP_WR_HIX : integer := NOCEM_ARB_CNTRL_VC_EOP_WR_LIX+NOCEM_NUM_VC-1;
+
+constant NOCEM_ARB_CNTRL_WIDTH : integer := NOCEM_ARB_CNTRL_VC_EOP_WR_HIX+1;
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--These are the various subtypes that are used to easily index multibit words --
+--that are needed within nocem. They are also used on interfaces to the --
+--toplevel nocem instantiation --
+--------------------------------------------------------------------------------
+
+subtype pkt_cntrl_word is std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+type pkt_cntrl_array is array(natural range <>) of pkt_cntrl_word;
+
+subtype data_word is std_logic_vector(NOCEM_DW-1 downto 0);
+type data_array is array(natural range <>) of data_word;
+
+subtype arb_cntrl_word is std_logic_vector(NOCEM_ARB_CNTRL_WIDTH-1 downto 0);
+type arb_cntrl_array is array(natural range <>) of arb_cntrl_word;
+
+subtype channel_cntrl_word is std_logic_vector(NOCEM_CHFIFO_CNTRL_WIDTH-1 downto 0);
+type channel_cntrl_array is array(natural range <>) of channel_cntrl_word;
+
+subtype node_addr_word is std_logic_vector(NOCEM_AW-1 downto 0);
+type node_addr_array is array(natural range <>) of node_addr_word;
+
+subtype arb_decision is std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+type arb_decision_array is array(natural range <>) of arb_decision;
+
+subtype vc_addr_word is std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+type vc_addr_array is array(natural range <>) of vc_addr_word;
+
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- components used in nocem, including the bridges --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+
+component fifo_fwft_bram_nfc_v5
+ port (
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+end component;
+
+component fifo_fwft_bram_v5
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+end component;
+
+component fifo_fwft_bram_v2p
+ port (
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+end component;
+
+component fifo_fwft_bram
+ port (
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+end component;
+
+
+ COMPONENT noc2proc_bridge2
+ generic
+ (
+ C_AWIDTH : integer := 32;
+ C_DWIDTH : integer := 64;
+ C_NUM_CS : integer := 1;
+ C_NUM_CE : integer := 2;
+ C_IP_INTR_NUM : integer := 1
+ );
+ port
+ (
+ noc_arb_req : out std_logic;
+ noc_arb_cntrl_out : out arb_cntrl_word;
+ noc_arb_grant : in std_logic;
+ noc_arb_cntrl_in : in arb_cntrl_word;
+ noc_datain : in std_logic_vector(NOCEM_DW-1 downto 0);
+ noc_datain_valid : in std_logic;
+ noc_datain_recvd : out std_logic;
+ noc_dataout : out std_logic_vector(NOCEM_DW-1 downto 0);
+ noc_dataout_valid : out std_logic;
+ noc_dataout_recvd : in std_logic;
+ noc_pkt_cntrl_in : in pkt_cntrl_word;
+ noc_pkt_cntrl_in_valid : in std_logic;
+ noc_pkt_cntrl_in_recvd : out std_logic;
+ noc_pkt_cntrl_out : out pkt_cntrl_word;
+ noc_pkt_cntrl_out_valid : out std_logic;
+ noc_pkt_cntrl_out_recvd : in std_logic;
+ Bus2IP_Clk : in std_logic;
+ Bus2IP_Reset : in std_logic;
+ IP2Bus_IntrEvent : out std_logic_vector(0 to C_IP_INTR_NUM-1);
+ Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
+ Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
+ Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
+ Bus2IP_Burst : in std_logic;
+ Bus2IP_CS : in std_logic_vector(0 to C_NUM_CS-1);
+ Bus2IP_CE : in std_logic_vector(0 to C_NUM_CE-1);
+ Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
+ Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
+ Bus2IP_RdReq : in std_logic;
+ Bus2IP_WrReq : in std_logic;
+ IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
+ IP2Bus_Retry : out std_logic;
+ IP2Bus_Error : out std_logic;
+ IP2Bus_ToutSup : out std_logic;
+ IP2Bus_RdAck : out std_logic;
+ IP2Bus_WrAck : out std_logic
+
+ );
+ END COMPONENT;
+
+
+
+
+ COMPONENT vc_node_ch_arbiter
+ Port (
+ -- needed to mux outputs for the accompanying switch
+ arb_grant_output : out arb_decision_array(4 downto 0);
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+
+ COMPONENT vc_node_vc_allocator
+ Port (
+ local_ch_addr : in std_logic_vector(4 downto 0);
+ outoing_vc_status : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT mux2to1
+ generic (
+ DWIDTH : integer;
+ REG_OUTPUT : integer
+ );
+ port (
+ din0 : in std_logic_vector( DWIDTH-1 downto 0);
+ din1 : in std_logic_vector( DWIDTH-1 downto 0);
+ sel : in std_logic_vector( 1 downto 0);
+ dout : out std_logic_vector( DWIDTH-1 downto 0);
+
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT mux4to1
+ generic (
+ DWIDTH : integer;
+ REG_OUTPUT : integer
+ );
+ port (
+ din0 : in std_logic_vector( DWIDTH-1 downto 0);
+ din1 : in std_logic_vector( DWIDTH-1 downto 0);
+ din2 : in std_logic_vector( DWIDTH-1 downto 0);
+ din3 : in std_logic_vector( DWIDTH-1 downto 0);
+ sel : in std_logic_vector( 3 downto 0);
+ dout : out std_logic_vector( DWIDTH-1 downto 0);
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+
+ COMPONENT xto1_arbiter
+ Generic (
+ NUM_REQS : integer;
+ REG_OUTPUT : integer
+ );
+ Port (
+ arb_req : in std_logic_vector(NUM_REQS-1 downto 0);
+ arb_grant : out std_logic_vector(NUM_REQS-1 downto 0);
+ clk : in std_logic;
+ rst : in std_logic);
+ END COMPONENT;
+
+ COMPONENT vc_controller
+ Port (
+ vc_my_id : in std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0); -- should be tied to constant
+ node_my_id : in std_logic_vector(NOCEM_AW-1 downto 0);
+ pkt_cntrl_rd : in pkt_cntrl_word;
+ pkt_cntrl_wr : in pkt_cntrl_word;
+ pkt_re : in std_logic;
+ pkt_we : in std_logic;
+ vc_fifo_empty : in std_logic;
+ vc_eop_rd_status : out std_logic; -- 0: no eop with rden, 1: eop and rden
+ vc_eop_wr_status : out std_logic; -- 0: no eop with wren, 1: eop and wren
+ vc_allocation_req : out std_logic;
+ vc_req_id : out std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+ vc_allocate_from_node : in std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+ vc_requester_from_node : in std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+ channel_dest : out arb_decision;
+ vc_dest : out std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+ vc_switch_req : out std_logic;
+ rst : in std_logic;
+ clk : in std_logic
+ );
+ END COMPONENT;
+
+
+ COMPONENT vc_channel
+ Generic (
+ IS_AN_ACCESS_POINT_CHANNEL : boolean
+ );
+ port (
+
+ node_dest_id : in node_addr_word;
+ vc_mux_wr : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_mux_rd : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ wr_pkt_cntrl : in std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ wr_pkt_data : in std_logic_vector(NOCEM_DW-1 downto 0);
+ rd_pkt_cntrl : out std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ rd_pkt_data : out std_logic_vector(NOCEM_DW-1 downto 0);
+ rd_pkt_chdest : out std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+ rd_pkt_vcdest : out vc_addr_word;
+ rd_pkt_vcsrc : out vc_addr_word;
+ vc_allocate_from_node : in vc_addr_word;
+ vc_requester_from_node : in vc_addr_word;
+ vc_eop_rd_status : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_eop_wr_status : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_allocate_destch_to_node : out std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+ vc_requester_to_node : out vc_addr_word;
+ vc_empty : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_full : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ RE : in std_logic;
+ WE : in std_logic;
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+
+ COMPONENT vc_channel_destap
+ port (
+ node_dest_id : in node_addr_word;
+ vc_mux_wr : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_mux_rd : IN std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ wr_pkt_cntrl : in std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ wr_pkt_data : in std_logic_vector(NOCEM_DW-1 downto 0);
+ rd_pkt_cntrl : out std_logic_vector(NOCEM_PKT_CNTRL_WIDTH-1 downto 0);
+ rd_pkt_data : out std_logic_vector(NOCEM_DW-1 downto 0);
+ rd_pkt_chdest : out std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+ rd_pkt_vcdest : out vc_addr_word;
+ rd_pkt_vcsrc : out vc_addr_word;
+ vc_allocate_from_node : in vc_addr_word;
+ vc_requester_from_node : in vc_addr_word;
+ vc_eop_rd_status : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_eop_wr_status : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_allocate_destch_to_node : out std_logic_vector(NOCEM_ARB_IX_SIZE-1 downto 0);
+ vc_requester_to_node : out vc_addr_word;
+ vc_empty : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ vc_full : out std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ RE : in std_logic;
+ WE : in std_logic;
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+
+
+ COMPONENT vc_node
+ Port (
+ local_arb_addr : std_logic_vector(NOCEM_AW-1 downto 0);
+ n_datain : in data_word;
+ n_pkt_cntrl_in : in pkt_cntrl_word;
+ n_dataout : out data_word;
+ n_pkt_cntrl_out : out pkt_cntrl_word;
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+ s_datain : in data_word;
+ s_pkt_cntrl_in : in pkt_cntrl_word;
+ s_dataout : out data_word;
+ s_pkt_cntrl_out : out pkt_cntrl_word;
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+ e_datain : in data_word;
+ e_pkt_cntrl_in : in pkt_cntrl_word;
+ e_dataout : out data_word;
+ e_pkt_cntrl_out : out pkt_cntrl_word;
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+ w_datain : in data_word;
+ w_pkt_cntrl_in : in pkt_cntrl_word;
+ w_dataout : out data_word;
+ w_pkt_cntrl_out : out pkt_cntrl_word;
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+ ap_datain : in data_word;
+ ap_pkt_cntrl_in : in pkt_cntrl_word;
+ ap_dataout : out data_word;
+ ap_pkt_cntrl_out : out pkt_cntrl_word;
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+-- COMPONENT noc2proc_bridge
+-- generic
+-- (
+--
+-- NOC_ADDR_WIDTH : integer := 4;
+-- NOC_ARB_CNTRL_WIDTH : integer := 4;
+-- NOC_DATA_WIDTH : integer := 16;
+-- NOC_PKT_CNTRL_WIDTH : integer := 4;
+--
+-- C_AWIDTH : integer := 32;
+-- C_DWIDTH : integer := 64;
+-- C_NUM_CS : integer := 1;
+-- C_NUM_CE : integer := 2;
+-- C_IP_INTR_NUM : integer := 1
+--
+-- );
+-- port
+-- (
+-- noc_arb_req : out std_logic;
+-- noc_arb_cntrl_req : out std_logic_vector(NOC_ARB_CNTRL_WIDTH-1 downto 0);
+--
+-- noc_arb_grant : in std_logic;
+-- noc_arb_cntrl_grant : in std_logic_vector(NOC_ARB_CNTRL_WIDTH-1 downto 0);
+--
+-- noc_datain : in std_logic_vector(NOC_DATA_WIDTH-1 downto 0);
+-- noc_datain_valid : in std_logic;
+-- noc_datain_recvd : out std_logic;
+--
+-- noc_dataout : out std_logic_vector(NOC_DATA_WIDTH-1 downto 0);
+-- noc_dataout_valid : out std_logic;
+-- noc_dataout_recvd : in std_logic;
+--
+-- noc_pkt_cntrl_in : in std_logic_vector(NOC_PKT_CNTRL_WIDTH-1 downto 0);
+-- noc_pkt_cntrl_in_valid : in std_logic;
+-- noc_pkt_cntrl_in_recvd : out std_logic;
+--
+-- noc_pkt_cntrl_out : out std_logic_vector(NOC_PKT_CNTRL_WIDTH-1 downto 0);
+-- noc_pkt_cntrl_out_valid : out std_logic;
+-- noc_pkt_cntrl_out_recvd : in std_logic;
+--
+--
+-- Bus2IP_Clk : in std_logic;
+-- Bus2IP_Reset : in std_logic;
+-- IP2Bus_IntrEvent : out std_logic_vector(0 to C_IP_INTR_NUM-1);
+-- Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
+-- Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
+-- Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
+-- Bus2IP_Burst : in std_logic;
+-- Bus2IP_CS : in std_logic_vector(0 to C_NUM_CS-1);
+-- Bus2IP_CE : in std_logic_vector(0 to C_NUM_CE-1);
+-- Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
+-- Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
+-- Bus2IP_RdReq : in std_logic;
+-- Bus2IP_WrReq : in std_logic;
+-- IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
+-- IP2Bus_Retry : out std_logic;
+-- IP2Bus_Error : out std_logic;
+-- IP2Bus_ToutSup : out std_logic;
+-- IP2Bus_RdAck : out std_logic;
+-- IP2Bus_WrAck : out std_logic;
+-- Bus2IP_MstError : in std_logic;
+-- Bus2IP_MstLastAck : in std_logic;
+-- Bus2IP_MstRdAck : in std_logic;
+-- Bus2IP_MstWrAck : in std_logic;
+-- Bus2IP_MstRetry : in std_logic;
+-- Bus2IP_MstTimeOut : in std_logic;
+-- IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
+-- IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
+-- IP2Bus_MstBurst : out std_logic;
+-- IP2Bus_MstBusLock : out std_logic;
+-- IP2Bus_MstNum : out std_logic_vector(0 to 4);
+-- IP2Bus_MstRdReq : out std_logic;
+-- IP2Bus_MstWrReq : out std_logic;
+-- IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
+-- );
+-- END COMPONENT;
+--
+
+
+
+
+-- COMPONENT packet_buffer
+-- generic(
+-- DATAIN_WIDTH : integer := 64;
+-- DATAOUT_WIDTH : integer := 32
+-- );
+-- port (
+-- din: IN std_logic_VECTOR(DATAIN_WIDTH-1 downto 0);
+-- clk: IN std_logic;
+-- rd_en: IN std_logic;
+-- rst: IN std_logic;
+-- wr_en : IN std_logic;
+-- dout: OUT std_logic_VECTOR(DATAOUT_WIDTH-1 downto 0);
+-- empty: OUT std_logic;
+-- full: OUT std_logic;
+-- wr_ack : out std_logic;
+-- pkt_len : in std_logic_vector(7 downto 0);
+-- pkt_metadata_din : in std_logic_vector(255 downto 0);
+-- pkt_metadata_re : IN std_logic;
+-- pkt_metadata_we : IN std_logic;
+-- pkt_metadata_dout : out std_logic_vector(255 downto 0);
+-- pkt_metadata_empty : out std_logic;
+-- pkt_metadata_full : out std_logic
+--
+-- );
+-- END COMPONENT;
+
+
+--
+-- COMPONENT nocem_net_layer
+-- Port (
+-- noc_arb_req : out std_logic;
+-- noc_arb_cntrl_req : out arb_cntrl_word;
+-- noc_arb_grant : in std_logic;
+-- noc_arb_cntrl_grant : in arb_cntrl_word;
+-- noc_datain : in data_word;
+-- noc_datain_valid : in std_logic;
+-- noc_datain_recvd : out std_logic;
+-- noc_dataout : out data_word;
+-- noc_dataout_valid : out std_logic;
+-- noc_dataout_recvd : in std_logic;
+-- noc_pkt_cntrl_in : in pkt_cntrl_word;
+-- noc_pkt_cntrl_in_valid : in std_logic;
+-- noc_pkt_cntrl_in_recvd : out std_logic;
+-- noc_pkt_cntrl_out : out pkt_cntrl_word;
+-- noc_pkt_cntrl_out_valid : out std_logic;
+-- noc_pkt_cntrl_out_recvd : in std_logic;
+-- ip2noc_addr : in std_logic_vector(NOCEM_AW-1 downto 0);
+-- ip2noc_packet_len : in std_logic_vector(7 downto 0);
+-- ip2noc_pkt_cntrl_we : in std_logic;
+-- ip2noc_packet : in std_logic_vector(63 downto 0);
+-- ip2noc_packet_we : in std_logic;
+-- ip2noc_pb_rdy : out std_logic;
+-- noc2ip_addr : out std_logic_vector(NOCEM_AW-1 downto 0);
+-- noc2ip_packet_len : out std_logic_vector(7 downto 0);
+-- noc2ip_pkt_cntrl_re : in std_logic;
+-- noc2ip_packet : out std_logic_vector(63 downto 0);
+-- noc2ip_packet_re : in std_logic;
+-- noc2ip_pb_rdy : out std_logic;
+-- clk : in std_logic;
+-- rst : in std_logic
+-- );
+-- END COMPONENT;
+
+
+
+
+
+ COMPONENT nocem
+ Port(
+ arb_req : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_cntrl_in : in arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ arb_grant : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_cntrl_out : out arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ datain : in data_array(NOCEM_NUM_AP-1 downto 0);
+ datain_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ datain_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ dataout : out data_array(NOCEM_NUM_AP-1 downto 0);
+ dataout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ dataout_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in : in pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out : out pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+
+constant EXERCISER_MODE_SIM : integer := 0;
+constant EXERCISER_MODE_IMPLEMENT1 : integer := 0;
+
+
+ COMPONENT ap_exerciser_vc
+ Generic(
+
+ DELAY_START_COUNTER_WIDTH : integer := 32;
+ DELAY_START_CYCLES : integer := 500;
+ PKT_LENGTH : integer := 5;
+ INTERVAL_COUNTER_WIDTH : integer := 8;
+ DATA_OUT_INTERVAL : integer := 16;
+ INIT_DEST_ADDR : integer := 2;
+ MY_ADDR : integer := 0;
+ EXERCISER_MODE : integer := EXERCISER_MODE_SIM
+ ) ;
+ Port (
+ arb_req : out std_logic;
+ arb_cntrl_out : out arb_cntrl_word;
+ arb_grant : in std_logic;
+ arb_cntrl_in : in arb_cntrl_word;
+ datain : in data_word;
+ datain_valid : in std_logic;
+ datain_recvd : out std_logic;
+ dataout : out data_word;
+ dataout_valid : out std_logic;
+ dataout_recvd : in std_logic;
+ pkt_cntrl_in : in pkt_cntrl_word;
+ pkt_cntrl_in_valid : in std_logic;
+ pkt_cntrl_in_recvd : out std_logic;
+ pkt_cntrl_out : out pkt_cntrl_word;
+ pkt_cntrl_out_valid : out std_logic;
+ pkt_cntrl_out_recvd : in std_logic;
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+ END COMPONENT;
+
+
+ COMPONENT access_point_exerciser
+ Generic(
+ DELAY_START_COUNTER_WIDTH: integer;
+ DELAY_START_CYCLES: integer;
+ BURST_LENGTH: integer;
+ INIT_DATA_OUT : data_word;
+ INTERVAL_COUNTER_WIDTH: integer;
+ DATA_OUT_INTERVAL : integer;
+ INIT_DEST_ADDR : integer
+ ) ;
+ Port (
+
+ -- arbitration lines (usage depends on underlying network)
+ arb_req : out std_logic;
+ arb_cntrl_out : out arb_cntrl_word;
+ arb_grant : in std_logic;
+ arb_cntrl_in : in arb_cntrl_word;
+ datain : in data_word;
+ datain_valid : in std_logic;
+ datain_recvd : out std_logic;
+ dataout : out data_word;
+ dataout_valid : out std_logic;
+ dataout_recvd : in std_logic;
+ pkt_cntrl_in : in pkt_cntrl_word;
+ pkt_cntrl_in_valid : in std_logic;
+ pkt_cntrl_in_recvd : out std_logic;
+ pkt_cntrl_out : out pkt_cntrl_word;
+ pkt_cntrl_out_valid : out std_logic;
+ pkt_cntrl_out_recvd : in std_logic;
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+ END COMPONENT;
+
+
+
+
+
+ COMPONENT channel_fifo
+ generic (
+ P0_NODE_ADDR : integer;
+ P1_NODE_ADDR : integer;
+ IS_AN_ACCESS_POINT_CHANNEL : boolean
+ );
+ port (
+ p0_datain : in data_word;
+ p0_pkt_cntrl_in : in pkt_cntrl_word;
+ p0_dataout : out data_word;
+ p0_pkt_cntrl_out : out pkt_cntrl_word;
+ p0_channel_cntrl_in : in channel_cntrl_word;
+ p0_channel_cntrl_out : out channel_cntrl_word;
+ p1_datain : in data_word;
+ p1_pkt_cntrl_in : in pkt_cntrl_word;
+ p1_dataout : out data_word;
+ p1_pkt_cntrl_out : out pkt_cntrl_word;
+ p1_channel_cntrl_in : in channel_cntrl_word;
+ p1_channel_cntrl_out : out channel_cntrl_word;
+ clk: IN std_logic;
+ rst: IN std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT channel_fifo_reg
+ PORT(
+ clk : IN std_logic;
+ din : IN std_logic_vector(255 downto 0);
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_en : IN std_logic;
+ dout : OUT std_logic_vector(255 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic
+ );
+ END COMPONENT;
+
+
+COMPONENT fifo_allvhdl
+ GENERIC(
+ WIDTH : integer;
+ ADDR_WIDTH : integer
+ );
+ PORT(
+ din : in std_logic_vector(WIDTH-1 downto 0); -- Input data
+ dout : out std_logic_vector(WIDTH-1 downto 0); -- Output data
+ clk : in std_logic; -- System Clock
+ rst : in std_logic; -- System global Reset
+ rd_en : in std_logic; -- Read Enable
+ wr_en : in std_logic; -- Write Enable
+ full : out std_logic; -- Full Flag
+ empty : out std_logic -- Empty Flag
+ );
+END COMPONENT;
+
+
+
+ COMPONENT fifo_gfs
+ generic (
+ WIDTH : integer; -- FIFO word width
+ ADD_WIDTH : integer -- Address Width
+ );
+
+ PORT(
+ Data_in : IN std_logic_vector(WIDTH-1 downto 0);
+ clk : IN std_logic;
+ Reset : IN std_logic;
+ RE : IN std_logic;
+ WE : IN std_logic;
+ Data_out : OUT std_logic_vector(WIDTH-1 downto 0);
+ Full : OUT std_logic;
+ Half_full : OUT std_logic;
+ empty : OUT std_logic
+ );
+ END COMPONENT;
+
+
+COMPONENT ic_bus_nocem
+ Port (
+
+ arb_grant : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ --data and addr incoming/outgoing line (usage depends on underlying network)
+ datain : in data_array(NOCEM_NUM_AP-1 downto 0);
+ dataout : out data_array(NOCEM_NUM_AP-1 downto 0);
+
+ dataout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ addrin : in pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ addrout : out pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ addrout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ clk : in std_logic;
+ rst : in std_logic
+
+
+
+ );
+END COMPONENT;
+
+
+COMPONENT simple_pkt_node
+ port (
+ local_arb_addr : std_logic_vector(NOCEM_AW-1 downto 0);
+ n_datain : in data_word;
+ n_pkt_cntrl_in : in pkt_cntrl_word;
+ n_dataout : out data_word;
+ n_pkt_cntrl_out : out pkt_cntrl_word;
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+ s_datain : in data_word;
+ s_pkt_cntrl_in : in pkt_cntrl_word;
+ s_dataout : out data_word;
+ s_pkt_cntrl_out : out pkt_cntrl_word;
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+ e_datain : in data_word;
+ e_pkt_cntrl_in : in pkt_cntrl_word;
+ e_dataout : out data_word;
+ e_pkt_cntrl_out : out pkt_cntrl_word;
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+ w_datain : in data_word;
+ w_pkt_cntrl_in : in pkt_cntrl_word;
+ w_dataout : out data_word;
+ w_pkt_cntrl_out : out pkt_cntrl_word;
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+ ap_datain : in data_word;
+ ap_pkt_cntrl_in : in pkt_cntrl_word;
+ ap_dataout : out data_word;
+ ap_pkt_cntrl_out : out pkt_cntrl_word;
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+ clk : in std_logic;
+ rst : in std_logic
+ );
+END COMPONENT;
+
+
+
+
+
+
+
+
+
+
+
+COMPONENT arb_bus_nocem
+ Port(
+ arb_req : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_grant : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ clk : in std_logic;
+ rst : in std_logic
+ );
+END COMPONENT;
+
+
+
+ COMPONENT simple_pkt_local_arb
+ Port (
+
+ -- local arb info (should be held constant on incoming signal)
+ local_arb_addr : std_logic_vector(NOCEM_AW-1 downto 0);
+
+ -- needed to mux outputs for the accompanying switch
+ arb_grant_output : out arb_decision_array(4 downto 0);
+
+ n_pkt_cntrl_in : in pkt_cntrl_word;
+ n_pkt_cntrl_out : out pkt_cntrl_word;
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+
+ s_pkt_cntrl_in : in pkt_cntrl_word;
+ s_pkt_cntrl_out : out pkt_cntrl_word;
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+
+ e_pkt_cntrl_in : in pkt_cntrl_word;
+ e_pkt_cntrl_out : out pkt_cntrl_word;
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+
+ w_pkt_cntrl_in : in pkt_cntrl_word;
+ w_pkt_cntrl_out : out pkt_cntrl_word;
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+
+
+ ap_pkt_cntrl_in : in pkt_cntrl_word;
+ ap_pkt_cntrl_out : out pkt_cntrl_word;
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+
+ COMPONENT simple_pkt_local_switch
+ Port (
+ arb_grant_output : in arb_decision_array(4 downto 0);
+ ap_datain : in data_word;
+ ap_dataout : out data_word;
+ n_datain : in data_word;
+ n_dataout : out data_word;
+ s_datain : in data_word;
+ s_dataout : out data_word;
+ e_datain : in data_word;
+ e_dataout : out data_word;
+ w_datain : in data_word;
+ w_dataout : out data_word;
+
+ n_pkt_cntrl_in : in pkt_cntrl_word;
+ n_pkt_cntrl_out : out pkt_cntrl_word;
+
+ s_pkt_cntrl_in : in pkt_cntrl_word;
+ s_pkt_cntrl_out : out pkt_cntrl_word;
+
+ e_pkt_cntrl_in : in pkt_cntrl_word;
+ e_pkt_cntrl_out : out pkt_cntrl_word;
+
+ w_pkt_cntrl_in : in pkt_cntrl_word;
+ w_pkt_cntrl_out : out pkt_cntrl_word;
+
+ ap_pkt_cntrl_in : in pkt_cntrl_word;
+ ap_pkt_cntrl_out : out pkt_cntrl_word;
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+ END COMPONENT;
+
+
+ COMPONENT ic_pkt_nocem
+ Port (
+ arb_req : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_cntrl_in : in arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ arb_grant : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_cntrl_out : out arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ datain : in data_array(NOCEM_NUM_AP-1 downto 0);
+ datain_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ datain_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ dataout : out data_array(NOCEM_NUM_AP-1 downto 0);
+ dataout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ dataout_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in : in pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out : out pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ clk : in std_logic;
+ rst : in std_logic
+ );
+ END COMPONENT;
+
+
+
+
+
+
+
+
+ function addr_gen (I,num_rows,num_cols,addr_width : integer) return std_logic_vector;
+ function Log2 (input : integer) return integer;
+
+end pkg_nocem;
+
+
+package body pkg_nocem is
+
+-- Example 1
+ function addr_gen (I,num_rows,num_cols,addr_width : integer) return std_logic_vector is
+ variable final_addr : std_logic_vector(addr_width-1 downto 0);
+ variable x_coord, y_coord : integer;
+ begin
+ x_coord := I mod num_cols;
+ y_coord := I / num_cols;
+
+ final_addr(addr_width-1 downto addr_width/2) := CONV_STD_LOGIC_VECTOR(x_coord,addr_width/2);
+ final_addr(addr_width/2-1 downto 0) := CONV_STD_LOGIC_VECTOR(y_coord,addr_width/2);
+ return final_addr;
+ end addr_gen;
+
+
+ -- it'll do for now
+ function Log2 (input : integer) return integer is
+ begin
+
+ case input is
+ when 1 => return 0;
+ when 2 => return 1;
+ when 4 => return 2;
+ when 8 => return 3;
+ when 16 => return 4;
+ when 32 => return 5;
+ when 64 => return 6;
+ when others => return -1;
+ end case;
+
+
+ end Log2;
+
+
+
+end pkg_nocem;
Index: nocem/trunk/VHDL/Xto1_arbiter.vhd
===================================================================
--- nocem/trunk/VHDL/Xto1_arbiter.vhd (nonexistent)
+++ nocem/trunk/VHDL/Xto1_arbiter.vhd (revision 8)
@@ -0,0 +1,302 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: Xto1_arbiter.vhd
+--
+-- Description: a simple arbiter
+--
+
+
+--a X to 1 arbiter takes in X arbitration requests and puts
+--out 1 grant signal. This is done by:
+--
+--1. barrelshift inputs every cycle in a loop
+--2. take results of that output and take highest reqs
+-- (where req priorities change every cycle)
+--3. determine which input really won and in parallel,
+-- barrelshift back out the masked result
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity Xto1_arbiter is
+ Generic (
+ NUM_REQS : integer := 2; -- 2,4 supported.
+ REG_OUTPUT : integer := 0
+ );
+ Port (
+ arb_req : in std_logic_vector(NUM_REQS-1 downto 0);
+ arb_grant : out std_logic_vector(NUM_REQS-1 downto 0);
+ clk : in std_logic;
+ rst : in std_logic);
+end Xto1_arbiter;
+
+architecture Behavioral of Xto1_arbiter is
+
+
+ -- specifically for a 4 input arbiter -----------------------------
+ constant constant4 : std_logic_vector(2 downto 0) := "100";
+ signal shift_reqs4 : std_logic_vector(1 downto 0);
+ signal shift_grants4 : std_logic_vector(2 downto 0);
+ -------------------------------------------------------------------
+
+ -- specifically for a 2 input arbiter -----------------------------
+ signal arb2_order : std_logic;
+ -------------------------------------------------------------------
+
+
+
+
+ signal reqs_shifted : std_logic_vector(NUM_REQS-1 downto 0);
+ signal reqs_shifted_masked : std_logic_vector(NUM_REQS-1 downto 0);
+
+ signal arb_grant_i : std_logic_vector(NUM_REQS-1 downto 0);
+
+
+ -- wrapped up primitive, since not sure how to "infer" this element
+ -- in VHDL...
+ COMPONENT barrelshift4_wrapper
+ PORT( I0 : IN STD_LOGIC;
+ I1 : IN STD_LOGIC;
+ I2 : IN STD_LOGIC;
+ I3 : IN STD_LOGIC;
+ S0 : IN STD_LOGIC;
+ S1 : IN STD_LOGIC;
+ O3 : OUT STD_LOGIC;
+ O2 : OUT STD_LOGIC;
+ O1 : OUT STD_LOGIC;
+ O0 : OUT STD_LOGIC);
+ END COMPONENT;
+
+
+ COMPONENT barrelshift8_wrapper
+ PORT( I0 : IN STD_LOGIC;
+ I1 : IN STD_LOGIC;
+ I2 : IN STD_LOGIC;
+ I3 : IN STD_LOGIC;
+ I4 : IN STD_LOGIC;
+ I5 : IN STD_LOGIC;
+ I6 : IN STD_LOGIC;
+ I7 : IN STD_LOGIC;
+ O7 : OUT STD_LOGIC;
+ O6 : OUT STD_LOGIC;
+ O5 : OUT STD_LOGIC;
+ O4 : OUT STD_LOGIC;
+ O3 : OUT STD_LOGIC;
+ O2 : OUT STD_LOGIC;
+ O1 : OUT STD_LOGIC;
+ O0 : OUT STD_LOGIC;
+ S2 : IN STD_LOGIC;
+ S1 : IN STD_LOGIC;
+ S0 : IN STD_LOGIC);
+ END COMPONENT;
+
+-- UUT: barrelshift8_wrapper PORT MAP(
+-- I0 => ,
+-- I1 => ,
+-- I2 => ,
+-- I3 => ,
+-- I4 => ,
+-- I5 => ,
+-- I6 => ,
+-- I7 => ,
+-- O7 => ,
+-- O6 => ,
+-- O5 => ,
+-- O4 => ,
+-- O3 => ,
+-- O2 => ,
+-- O1 => ,
+-- O0 => ,
+-- S2 => ,
+-- S1 => ,
+-- S0 =>
+-- );
+
+
+
+
+
+begin
+
+
+ arb4_gen : if NUM_REQS = 4 generate
+
+ bshift_req4 : barrelshift4_wrapper PORT MAP(
+ I0 => arb_req(0),
+ I1 => arb_req(1),
+ I2 => arb_req(2),
+ I3 => arb_req(3),
+ S0 => shift_reqs4(0),
+ S1 => shift_reqs4(1),
+ O3 => reqs_shifted(3),
+ O2 => reqs_shifted(2),
+ O1 => reqs_shifted(1),
+ O0 => reqs_shifted(0)
+ );
+
+
+ bshift_grant4 : barrelshift4_wrapper PORT MAP(
+ I0 => reqs_shifted_masked(0),
+ I1 => reqs_shifted_masked(1),
+ I2 => reqs_shifted_masked(2),
+ I3 => reqs_shifted_masked(3),
+ S0 => shift_grants4(0),
+ S1 => shift_grants4(1),
+ O3 => arb_grant_i(3),
+ O2 => arb_grant_i(2),
+ O1 => arb_grant_i(1),
+ O0 => arb_grant_i(0)
+ );
+
+
+
+
+ gen_grant_mask : process (reqs_shifted,rst)
+ begin
+
+ reqs_shifted_masked <= (others => '0');
+
+ if rst = '1' then
+ reqs_shifted_masked <= (others => '0');
+ else
+ if reqs_shifted(3) = '1' then
+ reqs_shifted_masked(3) <= '1';
+ elsif reqs_shifted(2) = '1' then
+ reqs_shifted_masked(2) <= '1';
+ elsif reqs_shifted(1) = '1' then
+ reqs_shifted_masked(1) <= '1';
+ elsif reqs_shifted(0) = '1' then
+ reqs_shifted_masked(0) <= '1';
+ else
+ null;
+ end if;
+ end if;
+
+ end process;
+
+
+ gen_shift_value_clkd : process (clk,rst)
+ begin
+ if rst = '1' then
+ shift_reqs4 <= (others => '0');
+ elsif clk'event and clk='1' then
+ shift_reqs4 <= shift_reqs4+1;
+ end if;
+ end process;
+
+ gen_shift_value_uclkd : process (shift_reqs4,rst)
+ begin
+ if rst = '1' then
+ shift_grants4 <= (others => '0');
+ else
+ shift_grants4 <= (constant4 - ("0" & shift_reqs4) );
+ end if;
+ end process;
+
+
+end generate;
+
+
+
+arb2_gen: if NUM_REQS = 2 generate
+
+ gen_arb2_order_clkd : process (clk,rst)
+ begin
+ if rst='1' then
+ arb2_order <= '0';
+ elsif clk='1' and clk'event then
+ arb2_order <= not arb2_order;
+ end if;
+ end process;
+
+
+ gen_arb2_grant : process (arb2_order,arb_req)
+ begin
+
+ arb_grant_i <= (others => '0');
+
+ if arb2_order = '0' then
+ if arb_req(0) = '1' then
+ arb_grant_i(0) <= '1';
+ elsif arb_req(1) = '1' then
+ arb_grant_i(1) <= '1';
+ end if;
+ end if;
+
+ if arb2_order = '1' then
+ if arb_req(1) = '1' then
+ arb_grant_i(1) <= '1';
+ elsif arb_req(0) = '1' then
+ arb_grant_i(0) <= '1';
+ end if;
+ end if;
+
+ end process;
+
+
+
+end generate;
+
+
+
+----------------------------------------
+-- REGISTERING OUTPUTS IF NEEDED --
+----------------------------------------
+
+g_reg: if REG_OUTPUT = 1 generate
+ gen_regd_output : process (clk,rst)
+ begin
+ if rst='1' then
+ arb_grant <= (others => '0');
+ elsif clk='1' and clk'event then
+ arb_grant <= arb_grant_i;
+ end if;
+
+ end process;
+end generate;
+
+g_ureg: if REG_OUTPUT = 0 generate
+ gen_uregd_output : process (arb_grant_i)
+ begin
+ arb_grant <= arb_grant_i;
+ end process;
+end generate;
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/vc_node_vc_allocator.vhd
===================================================================
--- nocem/trunk/VHDL/vc_node_vc_allocator.vhd (nonexistent)
+++ nocem/trunk/VHDL/vc_node_vc_allocator.vhd (revision 8)
@@ -0,0 +1,404 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: vc_node_vc_allocator.vhd
+--
+-- Description: vc_node virtual channel allocator
+--
+
+
+--
+--VC Allocator will do
+-- 1. manage vc allocation and deallocation for incoming packets looking for outgoing VC
+--
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+
+
+entity vc_node_vc_allocator is
+ Port (
+ local_ch_addr : in std_logic_vector(4 downto 0);
+ outoing_vc_status : in std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+end vc_node_vc_allocator;
+
+architecture Behavioral of vc_node_vc_allocator is
+
+ -- determining if there is a valid request on a per INCOMING channel basis
+ signal vc_req_array : std_logic_vector(4 downto 0);
+
+ -- determine the next free outgoing VC
+ signal next_free_vc : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal vc_state : std_logic_Vector(NOCEM_NUM_VC-1 downto 0); -- 0: free, 1: allocated --
+ signal vc_allocate : std_logic;
+ signal free_this_vc : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal allocated_vc : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+
+ -- DEBUG SIGNALS
+ signal debug_allocated_vc : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+ signal debug_alloc_counter : std_logic_vector(15 downto 0);
+ signal debug_dealloc_counter : std_logic_vector(15 downto 0);
+
+
+
+begin
+
+ -- setting up incoming request signals
+ vc_req_array(NOCEM_NORTH_IX) <= '1' when n_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX) /= 0 and n_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX downto NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX) = local_ch_addr else '0';
+ vc_req_array(NOCEM_SOUTH_IX) <= '1' when s_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX) /= 0 and s_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX downto NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX) = local_ch_addr else '0';
+ vc_req_array(NOCEM_WEST_IX) <= '1' when w_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX) /= 0 and w_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX downto NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX) = local_ch_addr else '0';
+ vc_req_array(NOCEM_EAST_IX) <= '1' when e_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX) /= 0 and e_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX downto NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX) = local_ch_addr else '0';
+ vc_req_array(NOCEM_AP_IX) <= '1' when ap_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX) /= 0 and ap_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX downto NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX) = local_ch_addr else '0';
+
+ -- currently, vc status is '1' when eop is read out of VC
+ free_this_vc <= outoing_vc_status;
+
+
+
+----------------------------------------------------------
+----------------------------------------------------------
+----------------------------------------------------------
+----------------------------------------------------------
+
+
+vc_state_gen_clkd : process (clk,rst)
+begin
+
+ if rst='1' then
+ vc_state <= (others => '0');
+ elsif clk'event and clk='1' then
+
+ -- an interesting bit play that should work to keep vc_state happy....
+ vc_state <= (allocated_vc or vc_state) xor free_this_vc;
+
+ end if;
+
+
+end process;
+
+
+
+
+
+gen_vc_status_uclkd : process (vc_state)
+begin
+ next_free_vc <= (others => '0');
+
+ l2: for I in NOCEM_NUM_VC-1 downto 0 loop
+ if vc_state(I) = '0' then
+ next_free_vc <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_VC);
+ end if;
+
+ end loop;
+
+end process;
+
+
+
+
+gen_grant_clkd : process (clk,rst)
+begin
+
+ if rst='1' then
+
+
+ n_channel_cntrl_out <= (others => '0');
+ e_channel_cntrl_out <= (others => '0');
+ s_channel_cntrl_out <= (others => '0');
+ w_channel_cntrl_out <= (others => '0');
+ ap_channel_cntrl_out <= (others => '0');
+ vc_allocate <= '0';
+
+ allocated_vc <= (others => '0');
+
+
+ elsif clk'event and clk='1' then
+
+ allocated_vc <= (others => '0');
+
+
+ -- zero them out if nothing is happening
+ n_channel_cntrl_out <= (others => '0');
+ e_channel_cntrl_out <= (others => '0');
+ s_channel_cntrl_out <= (others => '0');
+ w_channel_cntrl_out <= (others => '0');
+ ap_channel_cntrl_out <= (others => '0');
+ vc_allocate <= '0';
+
+ -- go through requests and satisfy one of them per cycle
+ if vc_req_array(NOCEM_NORTH_IX) = '1' and vc_allocate = '0' then
+ n_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+ n_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= n_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+ if next_free_vc /= 0 then
+ vc_allocate <= '1';
+ allocated_vc <= next_free_vc;
+ end if;
+ elsif vc_req_array(NOCEM_SOUTH_IX) = '1' and vc_allocate = '0' then
+ s_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+ s_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= s_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+ if next_free_vc /= 0 then
+ vc_allocate <= '1';
+ allocated_vc <= next_free_vc;
+ end if;
+ elsif vc_req_array(NOCEM_EAST_IX) = '1' and vc_allocate = '0' then
+ e_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+ e_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= e_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+ if next_free_vc /= 0 then
+ vc_allocate <= '1';
+ allocated_vc <= next_free_vc;
+ end if;
+ elsif vc_req_array(NOCEM_WEST_IX) = '1' and vc_allocate = '0' then
+ w_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+ w_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= w_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+ if next_free_vc /= 0 then
+ vc_allocate <= '1';
+ allocated_vc <= next_free_vc;
+ end if;
+ elsif vc_req_array(NOCEM_AP_IX) = '1' and vc_allocate = '0' then
+ ap_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+ ap_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= ap_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+ if next_free_vc /= 0 then
+ vc_allocate <= '1';
+ allocated_vc <= next_free_vc;
+ end if;
+ else
+ null;
+ end if;
+ end if;
+
+
+
+end process;
+
+
+
+
+
+
+
+----------------------------------------------------------
+----------------------------------------------------------
+----------------------------------------------------------
+----------------------------------------------------------
+--
+--gen_vc_status_clkd : process (clk,rst)
+--begin
+--
+-- if rst='1' then
+-- --next_free_vc <= ('1',others => '0');
+-- vc_state <= (others => '0');
+--
+-- elsif clk'event and clk='1' then
+--
+--
+--
+--
+--
+---- if vc_state = "11" then
+---- next_free_vc <= (others => '0');
+---- end if;
+--
+--
+-- l1: for I in NOCEM_NUM_VC-1 downto 0 loop
+-- if vc_state(I) = '0' and next_free_vc(I) = '1' and vc_allocate = '1' then -- free going to allocated
+-- vc_state(I) <= '1';
+-- elsif vc_state(I) = '1' and free_this_vc(I) = '1' then -- allocated going to free
+-- vc_state(I) <= '0';
+-- end if;
+-- end loop;
+--
+-- end if;
+--end process;
+--
+----gen_vc_status_cclkd : process (clk,rst)
+----begin
+----
+---- if rst='1' then
+---- next_free_vc <= (others => '0');
+---- elsif clk'event and clk='1' then
+---- l2: for I in NOCEM_NUM_VC-1 downto 0 loop
+---- if vc_state(I) = '0' then
+---- next_free_vc <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_VC);
+---- end if;
+----
+---- end loop;
+---- end if;
+----
+----end process;
+--
+--
+--gen_vc_status_uclkd : process (vc_state)
+--begin
+-- next_free_vc <= (others => '0');
+--
+-- l2: for I in NOCEM_NUM_VC-1 downto 0 loop
+-- if vc_state(I) = '0' then
+-- next_free_vc <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_VC);
+-- end if;
+--
+-- end loop;
+--end process;
+--
+--
+--
+--
+--
+--
+--
+--gen_grant_clkd : process (clk,rst)
+--begin
+--
+-- if rst='1' then
+--
+--
+-- n_channel_cntrl_out <= (others => '0');
+-- e_channel_cntrl_out <= (others => '0');
+-- s_channel_cntrl_out <= (others => '0');
+-- w_channel_cntrl_out <= (others => '0');
+-- ap_channel_cntrl_out <= (others => '0');
+-- vc_allocate <= '0';
+--
+-- debug_allocated_vc <= (others => '0');
+--
+--
+-- elsif clk'event and clk='1' then
+--
+-- debug_allocated_vc <= (others => '0');
+--
+--
+-- -- zero them out if nothing is happening
+-- n_channel_cntrl_out <= (others => '0');
+-- e_channel_cntrl_out <= (others => '0');
+-- s_channel_cntrl_out <= (others => '0');
+-- w_channel_cntrl_out <= (others => '0');
+-- ap_channel_cntrl_out <= (others => '0');
+-- vc_allocate <= '0';
+--
+-- -- go through requests and satisfy one of them per cycle
+-- if vc_req_array(NOCEM_NORTH_IX) = '1' and vc_allocate = '0' then
+-- n_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+-- n_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= n_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+-- if next_free_vc /= 0 then
+-- vc_allocate <= '1';
+-- debug_allocated_vc <= next_free_vc;
+-- end if;
+-- elsif vc_req_array(NOCEM_SOUTH_IX) = '1' and vc_allocate = '0' then
+-- s_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+-- s_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= s_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+-- if next_free_vc /= 0 then
+-- vc_allocate <= '1';
+-- debug_allocated_vc <= next_free_vc;
+-- end if;
+-- elsif vc_req_array(NOCEM_EAST_IX) = '1' and vc_allocate = '0' then
+-- e_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+-- e_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= e_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+-- if next_free_vc /= 0 then
+-- vc_allocate <= '1';
+-- debug_allocated_vc <= next_free_vc;
+-- end if;
+-- elsif vc_req_array(NOCEM_WEST_IX) = '1' and vc_allocate = '0' then
+-- w_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+-- w_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= w_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+-- if next_free_vc /= 0 then
+-- vc_allocate <= '1';
+-- debug_allocated_vc <= next_free_vc;
+-- end if;
+-- elsif vc_req_array(NOCEM_AP_IX) = '1' and vc_allocate = '0' then
+-- ap_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= next_free_vc;
+-- ap_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= ap_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX);
+-- if next_free_vc /= 0 then
+-- vc_allocate <= '1';
+-- debug_allocated_vc <= next_free_vc;
+-- end if;
+-- else
+-- null;
+-- end if;
+-- end if;
+--
+--
+--
+--end process;
+--
+
+
+
+-- signal debug_alloc_counter : std_logic_vector(15 downto 0);
+-- signal debug_dealloc_counter : std_logic_vector(15 downto 0);
+debug_proc : process (clk,rst)
+begin
+
+ if rst='1' then
+ debug_alloc_counter <= (others => '0');
+ debug_dealloc_counter <= (others => '0');
+ elsif clk'event and clk='1' then
+ if vc_allocate = '1' then
+ debug_alloc_counter <= debug_alloc_counter+1;
+ end if;
+
+ if free_this_vc /= 0 then
+ debug_dealloc_counter <= debug_dealloc_counter+1;
+ end if;
+
+
+ end if;
+
+end process;
+
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/simple_pkt_local_arb.vhd
===================================================================
--- nocem/trunk/VHDL/simple_pkt_local_arb.vhd (nonexistent)
+++ nocem/trunk/VHDL/simple_pkt_local_arb.vhd (revision 8)
@@ -0,0 +1,445 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: simple_pkt_local_arb.vhd
+--
+-- Description: nonVC design arbiter
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+use work.pkg_nocem.all;
+
+
+entity simple_pkt_local_arb is
+ Port (
+
+ -- local arb info (should be held constant on incoming signal)
+ local_arb_addr : std_logic_vector(NOCEM_AW-1 downto 0);
+
+ -- needed to mux outputs for the accompanying switch
+ arb_grant_output : out arb_decision_array(4 downto 0);
+
+
+ n_pkt_cntrl_in : in pkt_cntrl_word;
+ n_pkt_cntrl_out : out pkt_cntrl_word;
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+
+ s_pkt_cntrl_in : in pkt_cntrl_word;
+ s_pkt_cntrl_out : out pkt_cntrl_word;
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+
+ e_pkt_cntrl_in : in pkt_cntrl_word;
+ e_pkt_cntrl_out : out pkt_cntrl_word;
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+
+ w_pkt_cntrl_in : in pkt_cntrl_word;
+ w_pkt_cntrl_out : out pkt_cntrl_word;
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+
+
+ ap_pkt_cntrl_in : in pkt_cntrl_word;
+ ap_pkt_cntrl_out : out pkt_cntrl_word;
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+
+ clk : in std_logic;
+ rst : in std_logic
+ );
+end simple_pkt_local_arb;
+
+architecture Behavioral of simple_pkt_local_arb is
+
+
+signal local_addr_x : std_logic_vector(NOCEM_AW/2 -1 downto 0);
+signal local_addr_y : std_logic_vector(NOCEM_AW/2 -1 downto 0);
+
+
+
+
+ -- since much of the work is repetitive, can use looping w/ indexing
+ -- to save massive repetitive coding
+
+ --many operations can be easily written if inputs are in array form
+ signal dest_local_port : arb_decision_array(4 downto 0);
+ signal dest_addr_array : node_addr_array(4 downto 0);
+ signal datain_valid_array : std_logic_vector(4 downto 0);
+ signal pkt_cntrl_valid_array : std_logic_vector(4 downto 0);
+ signal pkt_cntrl_data_array : pkt_cntrl_array(4 downto 0);
+ signal arb_decision_enum : arb_decision_array(4 downto 0);
+ signal channel_cntrl_in_array_i : channel_cntrl_array(4 downto 0);
+ signal channel_cntrl_out_array_i : channel_cntrl_array(4 downto 0);
+
+
+ --signal srcToDstTimes2 : node_addr_array(4 downto 0);
+
+
+
+begin
+
+
+
+ datain_valid_array(NOCEM_NORTH_IX) <= n_channel_cntrl_in(NOCEM_CHFIFO_DATA_EMPTY_N_IX);
+ datain_valid_array(NOCEM_SOUTH_IX) <= s_channel_cntrl_in(NOCEM_CHFIFO_DATA_EMPTY_N_IX);
+ datain_valid_array(NOCEM_EAST_IX) <= e_channel_cntrl_in(NOCEM_CHFIFO_DATA_EMPTY_N_IX);
+ datain_valid_array(NOCEM_WEST_IX) <= w_channel_cntrl_in(NOCEM_CHFIFO_DATA_EMPTY_N_IX);
+ datain_valid_array(NOCEM_AP_IX) <= ap_channel_cntrl_in(NOCEM_CHFIFO_DATA_EMPTY_N_IX);
+
+ channel_cntrl_in_array_i(NOCEM_NORTH_IX) <= n_channel_cntrl_in;
+ channel_cntrl_in_array_i(NOCEM_SOUTH_IX) <= s_channel_cntrl_in;
+ channel_cntrl_in_array_i(NOCEM_EAST_IX) <= e_channel_cntrl_in;
+ channel_cntrl_in_array_i(NOCEM_WEST_IX) <= w_channel_cntrl_in;
+ channel_cntrl_in_array_i(NOCEM_AP_IX) <= ap_channel_cntrl_in;
+
+ n_channel_cntrl_out <= channel_cntrl_out_array_i(NOCEM_NORTH_IX);
+ s_channel_cntrl_out <= channel_cntrl_out_array_i(NOCEM_SOUTH_IX);
+ e_channel_cntrl_out <= channel_cntrl_out_array_i(NOCEM_EAST_IX);
+ w_channel_cntrl_out <= channel_cntrl_out_array_i(NOCEM_WEST_IX);
+ ap_channel_cntrl_out <= channel_cntrl_out_array_i(NOCEM_AP_IX);
+
+ pkt_cntrl_valid_array(NOCEM_NORTH_IX) <= n_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX);
+ pkt_cntrl_valid_array(NOCEM_SOUTH_IX) <= s_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX);
+ pkt_cntrl_valid_array(NOCEM_EAST_IX) <= e_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX);
+ pkt_cntrl_valid_array(NOCEM_WEST_IX) <= w_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX);
+ pkt_cntrl_valid_array(NOCEM_AP_IX) <= ap_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX);
+
+ pkt_cntrl_data_array(NOCEM_NORTH_IX) <= n_pkt_cntrl_in;
+ pkt_cntrl_data_array(NOCEM_SOUTH_IX) <= s_pkt_cntrl_in;
+ pkt_cntrl_data_array(NOCEM_EAST_IX) <= e_pkt_cntrl_in;
+ pkt_cntrl_data_array(NOCEM_WEST_IX) <= w_pkt_cntrl_in;
+ pkt_cntrl_data_array(NOCEM_AP_IX) <= ap_pkt_cntrl_in;
+
+ arb_decision_enum(NOCEM_AP_IX) <= ARB_AP;
+ arb_decision_enum(NOCEM_NORTH_IX) <= ARB_NORTH;
+ arb_decision_enum(NOCEM_SOUTH_IX) <= ARB_SOUTH;
+ arb_decision_enum(NOCEM_EAST_IX) <= ARB_EAST;
+ arb_decision_enum(NOCEM_WEST_IX) <= ARB_WEST;
+
+
+
+
+ --local address breakdown for readibility....
+ local_addr_x <= local_arb_addr(NOCEM_AW-1 downto NOCEM_AW/2);
+ local_addr_y <= local_arb_addr(NOCEM_AW/2 -1 downto 0);
+
+ -- simply pass on the pkt_cntrl signals to the switch
+ -- (may modify in other configs)
+ n_pkt_cntrl_out <= n_pkt_cntrl_in;
+ s_pkt_cntrl_out <= s_pkt_cntrl_in;
+ e_pkt_cntrl_out <= e_pkt_cntrl_in;
+ w_pkt_cntrl_out <= w_pkt_cntrl_in;
+ ap_pkt_cntrl_out <= ap_pkt_cntrl_in;
+
+
+
+
+-- process to generate destination address from pkt_cntrl line
+
+dest_addr_gen_process : process (pkt_cntrl_valid_array, pkt_cntrl_data_array)
+begin
+
+ l1: for I in 4 downto 0 loop
+ if pkt_cntrl_valid_array(I) = '1' then
+ dest_addr_array(I) <= pkt_cntrl_data_array(I)(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX);
+ else
+ dest_addr_array(I) <= (others => '0');
+ end if;
+ end loop;
+
+
+end process;
+
+
+
+
+
+
+
+-- process to determine routing based on incoming addr and data valid
+-- decision determined by topology and datain destination address
+
+port_dest_gen_process : process (datain_valid_array, local_addr_x, local_addr_y, dest_addr_array)
+begin
+
+
+
+ -- DOUBLE TORUS: north/south have loop around, east/west have looparound....
+ if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_DTORUS then
+ l20 : for I in 4 downto 0 loop
+ dest_local_port(I) <= ARB_NODECISION;
+
+ if datain_valid_array(I) = '1' then
+
+ -- src > dst address. go east if ROWS >= 2(SRC-DST) . go west if ROWS < 2(SRC-DST)
+ if dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) < local_addr_x then
+
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(local_addr_x - dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2)) sll 1) then
+ dest_local_port(I) <= ARB_EAST;
+ else
+ dest_local_port(I) <= ARB_WEST;
+ end if;
+ end if;
+
+ -- dst > src address. go east if ROWS >= 2(DST-SRC) . go west if ROWS < 2(DST-SRC)
+ if dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) > local_addr_x then
+
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2)- local_addr_x) sll 1) then
+ dest_local_port(I) <= ARB_EAST;
+ else
+ dest_local_port(I) <= ARB_WEST;
+ end if;
+
+ end if;
+
+ -- src > dst address. go north if ROWS >= 2(SRC-DST) . go south if ROWS < 2(SRC-DST)
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) < local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(local_addr_y - dest_addr_array(I)(NOCEM_AW/2 -1 downto 0)) sll 1) then
+ dest_local_port(I) <= ARB_NORTH;
+ else
+ dest_local_port(I) <= ARB_SOUTH;
+ end if;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) > local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ -- dst > src address. go north if ROWS >= 2(DST-SRC) . go south if ROWS < 2(DST-SRC)
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) - local_addr_y) sll 1) then
+ dest_local_port(I) <= ARB_NORTH;
+ else
+ dest_local_port(I) <= ARB_SOUTH;
+ end if;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) = local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ dest_local_port(I) <= ARB_AP;
+ end if;
+
+ else
+ dest_local_port(I) <= ARB_NODECISION;
+
+ end if;
+
+ end loop;
+
+ end if;
+
+ -- TORUS: north/south have loop around, east/west do not....
+ if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_TORUS then
+ l21 : for I in 4 downto 0 loop
+ dest_local_port(I) <= ARB_NODECISION;
+
+ if datain_valid_array(I) = '1' then
+
+ if dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) < local_addr_x then
+ dest_local_port(I) <= ARB_WEST;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) > local_addr_x then
+ dest_local_port(I) <= ARB_EAST;
+ end if;
+
+ -- src > dst address. go north if ROWS >= 2(SRC-DST) . go south if ROWS < 2(SRC-DST)
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) < local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(local_addr_y - dest_addr_array(I)(NOCEM_AW/2 -1 downto 0)) sll 1) then
+ dest_local_port(I) <= ARB_NORTH;
+ else
+ dest_local_port(I) <= ARB_SOUTH;
+ end if;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) > local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ -- dst > src address. go north if ROWS >= 2(DST-SRC) . go south if ROWS < 2(DST-SRC)
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) - local_addr_y) sll 1) then
+ dest_local_port(I) <= ARB_NORTH;
+ else
+ dest_local_port(I) <= ARB_SOUTH;
+ end if;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) = local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ dest_local_port(I) <= ARB_AP;
+ end if;
+
+ else
+ dest_local_port(I) <= ARB_NODECISION;
+
+ end if;
+
+ end loop;
+
+ end if;
+
+
+
+ -- MESH: simple deterministic routing....
+ if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_MESH then
+ l22 : for I in 4 downto 0 loop
+
+ dest_local_port(I) <= ARB_NODECISION;
+ if datain_valid_array(I) = '1' then
+
+ if dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) < local_addr_x then
+ dest_local_port(I) <= ARB_WEST;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) > local_addr_x then
+ dest_local_port(I) <= ARB_EAST;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) < local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ dest_local_port(I) <= ARB_SOUTH;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) > local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ dest_local_port(I) <= ARB_NORTH;
+ end if;
+
+ if dest_addr_array(I)(NOCEM_AW/2 -1 downto 0) = local_addr_y and
+ dest_addr_array(I)(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ dest_local_port(I) <= ARB_AP;
+ end if;
+
+ else
+ dest_local_port(I) <= ARB_NODECISION;
+
+ end if;
+
+
+ end loop;
+
+ end if;
+
+
+
+
+
+
+
+
+
+end process;
+
+
+arb_gen_process : process (channel_cntrl_in_array_i, dest_local_port)
+begin
+
+
+
+ arb_grant_output <= (others => ARB_NODECISION);
+ channel_cntrl_out_array_i <= (others => (others => '0'));
+
+
+
+l3: for I in 4 downto 0 loop
+
+ -- I iterates over the OUTPUT ports
+ if channel_cntrl_in_array_i(I)(NOCEM_CHFIFO_DATA_FULL_N_IX) = '1' then
+
+ if dest_local_port(NOCEM_AP_IX) = arb_decision_enum(I) then
+ --arb grant will push data through switch
+ arb_grant_output(I) <= ARB_AP;
+
+ -- do read enable for selected incoming data
+ channel_cntrl_out_array_i(NOCEM_AP_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_i(NOCEM_AP_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+
+ -- do write enable for outgoing port
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ elsif dest_local_port(NOCEM_NORTH_IX) = arb_decision_enum(I) then
+ arb_grant_output(I) <= ARB_NORTH;
+ channel_cntrl_out_array_i(NOCEM_NORTH_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_i(NOCEM_NORTH_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+
+ elsif dest_local_port(NOCEM_SOUTH_IX) = arb_decision_enum(I) then
+ arb_grant_output(I) <= ARB_SOUTH;
+ channel_cntrl_out_array_i(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_i(NOCEM_SOUTH_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ elsif dest_local_port(NOCEM_EAST_IX) = arb_decision_enum(I) then
+ arb_grant_output(I) <= ARB_EAST;
+ channel_cntrl_out_array_i(NOCEM_EAST_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_i(NOCEM_EAST_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ elsif dest_local_port(NOCEM_WEST_IX) = arb_decision_enum(I) then
+ arb_grant_output(I) <= ARB_WEST;
+ channel_cntrl_out_array_i(NOCEM_WEST_IX)(NOCEM_CHFIFO_DATA_RE_IX) <= '1';
+ channel_cntrl_out_array_i(NOCEM_WEST_IX)(NOCEM_CHFIFO_CNTRL_RE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_DATA_WE_IX) <= '1';
+ channel_cntrl_out_array_i(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= '1';
+
+ end if;
+ end if;
+
+
+
+
+end loop;
+
+
+
+end process;
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/vc_controller.vhd
===================================================================
--- nocem/trunk/VHDL/vc_controller.vhd (nonexistent)
+++ nocem/trunk/VHDL/vc_controller.vhd (revision 8)
@@ -0,0 +1,411 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: vc_controller.vhd
+--
+-- Description: vc controller -- state, allocation status, etc.
+--
+
+
+--The VC controller is instantiated on a per VC basis and keeps track
+--of the state of the VC and outputs the appropriate signals to the node
+--that is switching this data and the node that originally provided the data.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.pkg_nocem.all;
+
+entity vc_controller is
+ Port (
+
+ -- id's for this vc and its node (for routing)
+ vc_my_id : in std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0); -- should be tied to constant
+ node_my_id : in std_logic_vector(NOCEM_AW-1 downto 0);
+
+ -- packet fields from/to FIFO that are being snooped
+ pkt_cntrl_rd : in pkt_cntrl_word;
+ pkt_cntrl_wr : in pkt_cntrl_word;
+ pkt_re : in std_logic;
+ pkt_we : in std_logic;
+ vc_fifo_empty : in std_logic;
+
+ -- this VC's status
+ vc_eop_rd_status : out std_logic; -- 0: no eop with rden, 1: eop and rden
+ vc_eop_wr_status : out std_logic; -- 0: no eop with wren, 1: eop and wren
+
+
+ -- requesting a outgoing VC
+ vc_allocation_req : out std_logic;
+ vc_req_id : out std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+
+ -- virtual channel request RESPONSE SIGNALS
+ vc_allocate_from_node : in std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+ vc_requester_from_node : in std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+
+ -- destination signals (channel,VC) for packet transmission
+ channel_dest : out arb_decision;
+ vc_dest : out std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+ vc_switch_req : out std_logic;
+
+ rst : in std_logic;
+ clk : in std_logic
+ );
+end vc_controller;
+
+architecture Behavioral of vc_controller is
+
+--STATE MACHINE SUMMARY --
+--
+--will see the SOP and then attempt to get a virtual channel on
+--the outgoing physical CHANNEL. Once we have a vc, we can start
+--to send the packet, waiting for a EOP to show up/be read out. Once we do,
+--will signal back to previous router that channel is now deallocated.
+--
+
+ type stateType is (idle_st,getting_vc_st,sending_st);
+ signal state,nextState : stateType;
+
+ signal local_addr_x : std_logic_vector(NOCEM_AW/2 -1 downto 0);
+ signal local_addr_y : std_logic_vector(NOCEM_AW/2 -1 downto 0);
+
+ signal channel_dest_routed,channel_dest_reg : arb_decision;
+
+ signal final_dest_addr : std_logic_vector(NOCEM_AW-1 downto 0);
+
+ signal vc_allocated_reg : std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+ signal sop_wr : std_logic;
+ signal eop_rd,eop_wr : std_logic;
+
+ -- register the incoming cntrl_wr signal for performance reasons (higher clock speed)
+ signal pkt_cntrl_wr_1stword : pkt_cntrl_word;
+
+
+begin
+
+ -- setup signals coming/going to FIFO
+ sop_wr <= pkt_cntrl_wr(NOCEM_PKTCNTRL_SOP_IX) when pkt_we = '1' else '0';
+ eop_wr <= pkt_cntrl_wr(NOCEM_PKTCNTRL_EOP_IX) when pkt_we = '1' else '0';
+ eop_rd <= pkt_cntrl_rd(NOCEM_PKTCNTRL_EOP_IX) when pkt_re = '1' else '0';
+
+
+ vc_eop_rd_status <= eop_rd; -- 0: no eop with rden, 1: eop and rden
+ vc_eop_wr_status <= eop_wr;
+
+
+ --local address breakdown for readibility....
+ local_addr_x <= node_my_id(NOCEM_AW-1 downto NOCEM_AW/2);
+ local_addr_y <= node_my_id(NOCEM_AW/2 -1 downto 0);
+ final_dest_addr <= pkt_cntrl_wr_1stword(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX);
+
+
+ state_clkd : process (clk,rst,nextState)
+ begin
+ if rst = '1' then
+ state <= idle_st;
+ channel_dest_reg <= ARB_NODECISION;
+ vc_allocated_reg <= (others => '0');
+ pkt_cntrl_wr_1stword <= (others => '0');
+ elsif clk'event and clk='1' then
+ state <= nextState;
+ case state is
+
+ when idle_st =>
+
+ vc_allocated_reg <= (others => '0');
+
+ if sop_wr='1' then
+ pkt_cntrl_wr_1stword <= pkt_cntrl_wr;
+ end if;
+ when getting_vc_st =>
+ channel_dest_reg <= channel_dest_routed;
+ if vc_allocate_from_node /= 0 and vc_requester_from_node = vc_my_id then
+ vc_allocated_reg <= vc_allocate_from_node;
+ else
+ null;
+ end if;
+ when sending_st =>
+ when others =>
+ null;
+
+
+ end case;
+ end if;
+ end process;
+
+
+
+ state_uclkd : process (vc_fifo_empty,eop_rd,state, sop_wr, vc_my_id, channel_dest_routed, vc_requester_from_node, channel_dest_reg, vc_allocate_from_node, pkt_re, eop_wr, vc_allocated_reg)
+ begin
+
+ vc_allocation_req <= '0';
+ vc_switch_req <= '0';
+ vc_dest <= (others => '0');
+ channel_dest <= ARB_NODECISION;
+ vc_req_id <= (others => '0');
+
+
+ case state is
+
+ when idle_st =>
+ vc_dest <= (others => '0');
+ if sop_wr = '1' then
+ nextState <= getting_vc_st;
+ else
+ nextState <= idle_st;
+ end if;
+
+ when getting_vc_st =>
+
+ channel_dest <= channel_dest_routed;
+ vc_dest <= vc_allocate_from_node;
+
+ if vc_allocate_from_node /= 0 and vc_requester_from_node = vc_my_id then
+
+ -- requesting switch signals
+ if vc_fifo_empty='0' then
+ vc_switch_req <= '1';
+ end if;
+
+ -- single word packet handling
+ if eop_rd = '1' then
+ nextState <= idle_st;
+ else
+ nextState <= sending_st;
+ end if;
+
+
+ else
+
+ -- requesting vc signals...
+ vc_allocation_req <= '1';
+ vc_req_id <= vc_my_id;
+
+ nextState <= getting_vc_st;
+ end if;
+
+
+
+
+ when sending_st =>
+
+ channel_dest <= channel_dest_routed;
+ vc_dest <= vc_allocated_reg;
+ -- requesting switch signals
+ if vc_fifo_empty = '0' then
+ vc_switch_req <= '1';
+ end if;
+
+ -- waiting for packet to be completed read
+ if eop_rd = '1' then
+ nextState <= idle_st;
+ else
+ nextState <= sending_st;
+ end if;
+
+ when others =>
+ null;
+
+
+ end case;
+ end process;
+
+
+
+
+
+-- process to determine routing based on incoming addr
+-- decision determined by topology and datain destination address
+ channel_dest_gen : process (pkt_cntrl_wr,final_dest_addr, local_addr_x, local_addr_y)
+ begin
+
+
+
+
+ -- DOUBLE TORUS: north/south have loop around, east/west have looparound....
+ if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_DTORUS then
+
+ channel_dest_routed <= ARB_NODECISION;
+
+
+
+ -- src > dst address. go east if ROWS >= 2(SRC-DST) . go west if ROWS < 2(SRC-DST)
+ if final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) < local_addr_x then
+
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(local_addr_x - final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2)) sll 1) then
+ channel_dest_routed <= ARB_EAST;
+ else
+ channel_dest_routed <= ARB_WEST;
+ end if;
+ end if;
+
+ -- dst > src address. go east if ROWS >= 2(DST-SRC) . go west if ROWS < 2(DST-SRC)
+ if final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) > local_addr_x then
+
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2)- local_addr_x) sll 1) then
+ channel_dest_routed <= ARB_EAST;
+ else
+ channel_dest_routed <= ARB_WEST;
+ end if;
+
+ end if;
+
+ -- src > dst address. go north if ROWS >= 2(SRC-DST) . go south if ROWS < 2(SRC-DST)
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) < local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(local_addr_y - final_dest_addr(NOCEM_AW/2 -1 downto 0)) sll 1) then
+ channel_dest_routed <= ARB_NORTH;
+ else
+ channel_dest_routed <= ARB_SOUTH;
+ end if;
+ end if;
+
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) > local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ -- dst > src address. go north if ROWS >= 2(DST-SRC) . go south if ROWS < 2(DST-SRC)
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(final_dest_addr(NOCEM_AW/2 -1 downto 0) - local_addr_y) sll 1) then
+ channel_dest_routed <= ARB_NORTH;
+ else
+ channel_dest_routed <= ARB_SOUTH;
+ end if;
+ end if;
+
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) = local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ channel_dest_routed <= ARB_AP;
+ end if;
+
+
+ end if; -- DTORUS
+
+
+ -- TORUS: north/south have loop around, east/west do not....
+ if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_TORUS then
+
+ channel_dest_routed <= ARB_NODECISION;
+
+
+ if final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) < local_addr_x then
+ channel_dest_routed <= ARB_WEST;
+ end if;
+
+ if final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) > local_addr_x then
+ channel_dest_routed <= ARB_EAST;
+ end if;
+
+ -- src > dst address. go north if ROWS >= 2(SRC-DST) . go south if ROWS < 2(SRC-DST)
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) < local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(local_addr_y - final_dest_addr(NOCEM_AW/2 -1 downto 0)) sll 1) then
+ channel_dest_routed <= ARB_NORTH;
+ else
+ channel_dest_routed <= ARB_SOUTH;
+ end if;
+ end if;
+
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) > local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ -- dst > src address. go north if ROWS >= 2(DST-SRC) . go south if ROWS < 2(DST-SRC)
+ if NOCEM_NUM_ROWS >= TO_STDLOGICVECTOR(TO_BITVECTOR(final_dest_addr(NOCEM_AW/2 -1 downto 0) - local_addr_y) sll 1) then
+ channel_dest_routed <= ARB_NORTH;
+ else
+ channel_dest_routed <= ARB_SOUTH;
+ end if;
+ end if;
+
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) = local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ channel_dest_routed <= ARB_AP;
+ end if;
+
+
+ end if;
+
+
+
+
+ -- MESH: simple deterministic routing....
+ if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_MESH then
+
+
+ channel_dest_routed <= ARB_NODECISION;
+
+
+ if final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) < local_addr_x then
+ channel_dest_routed <= ARB_WEST;
+ end if;
+
+ if final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) > local_addr_x then
+ channel_dest_routed <= ARB_EAST;
+ end if;
+
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) < local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ channel_dest_routed <= ARB_SOUTH;
+ end if;
+
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) > local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ channel_dest_routed <= ARB_NORTH;
+ end if;
+
+ if final_dest_addr(NOCEM_AW/2 -1 downto 0) = local_addr_y and
+ final_dest_addr(NOCEM_AW-1 downto NOCEM_AW/2) = local_addr_x then
+
+ channel_dest_routed <= ARB_AP;
+ end if;
+
+
+ end if;
+
+
+
+end process;
+
+
+
+
+
+
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/channel_fifo.vhd
===================================================================
--- nocem/trunk/VHDL/channel_fifo.vhd (nonexistent)
+++ nocem/trunk/VHDL/channel_fifo.vhd (revision 8)
@@ -0,0 +1,427 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: channel_fifo.vhd
+--
+-- Description: toplevel entity for channel fifo
+--
+
+
+--Use two channels for a bidirectional channel. This
+--will allow a node to connect to the fifo with both
+--enqueueing and dequeuing capabilities. This will
+--make connections easier as well.
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+entity channel_fifo is
+ generic (
+ P0_NODE_ADDR : integer := 0;
+ P1_NODE_ADDR : integer := 0;
+ IS_AN_ACCESS_POINT_CHANNEL : boolean := FALSE
+ );
+ port (
+
+
+ p0_datain : in data_word;
+ p0_pkt_cntrl_in : in pkt_cntrl_word;
+
+ p0_dataout : out data_word;
+ p0_pkt_cntrl_out : out pkt_cntrl_word;
+
+ p0_channel_cntrl_in : in channel_cntrl_word;
+ p0_channel_cntrl_out : out channel_cntrl_word;
+
+
+
+ p1_datain : in data_word;
+ p1_pkt_cntrl_in : in pkt_cntrl_word;
+
+ p1_dataout : out data_word;
+ p1_pkt_cntrl_out : out pkt_cntrl_word;
+
+ p1_channel_cntrl_in : in channel_cntrl_word;
+ p1_channel_cntrl_out : out channel_cntrl_word;
+
+
+
+
+
+ clk: IN std_logic;
+ rst: IN std_logic
+
+ );
+
+
+
+
+end channel_fifo;
+
+architecture Behavioral of channel_fifo is
+
+
+
+--std16,register signals
+ -- port 0 signals
+--signal p0_datain_pad, : std_logic_vector(255 downto 0);
+--signal p0_cntrl_in_pad, : std_logic_vector(255 downto 0);
+
+signal p0_data_re,p0_data_we,p0_data_full,p0_data_empty : std_logic;
+signal p0_cntrl_re,p0_cntrl_we,p0_cntrl_full,p0_cntrl_empty : std_logic;
+
+ -- port 1 signals
+--signal p1_datain_pad, : std_logic_vector(255 downto 0);
+--signal p1_cntrl_in_pad, : std_logic_vector(255 downto 0);
+--
+signal p1_data_re,p1_data_we,p1_data_full,p1_data_empty : std_logic;
+signal p1_cntrl_re,p1_cntrl_we,p1_cntrl_full,p1_cntrl_empty : std_logic;
+
+ -- for Modelsim purposes
+signal p0_addr_conv,p1_addr_conv : std_logic_vector(NOCEM_AW-1 downto 0);
+
+
+--register signals
+
+
+
+begin
+
+ -- for Modelsim purposes, do some signal re-typing here
+ p0_addr_conv <= addr_gen(P0_NODE_ADDR,NOCEM_NUM_ROWS,NOCEM_NUM_COLS,NOCEM_AW);
+ p1_addr_conv <= addr_gen(P1_NODE_ADDR,NOCEM_NUM_ROWS,NOCEM_NUM_COLS,NOCEM_AW);
+
+
+
+
+ gvc_procs: if NOCEM_TYPE = NOCEM_VC_TYPE generate
+
+
+ -- wrapping these constant assignments to make simulator actually work...
+ p0_handling_vc : process (p0_channel_cntrl_in, p0_data_full, p0_data_empty, p0_datain, p0_cntrl_full, p0_cntrl_empty, p0_pkt_cntrl_in )
+ begin
+
+ p0_data_re <= p0_channel_cntrl_in(NOCEM_CHFIFO_DATA_RE_IX);
+ p0_data_we <= p0_channel_cntrl_in(NOCEM_CHFIFO_DATA_WE_IX);
+
+ p0_channel_cntrl_out(NOCEM_CHFIFO_DATA_FULL_N_IX) <= not p0_data_full;
+ p0_channel_cntrl_out(NOCEM_CHFIFO_DATA_EMPTY_N_IX) <= not p0_data_empty;
+
+ p0_data_full <= '0';
+ p0_data_empty <= '0';
+ p0_cntrl_full <= '0';
+ p0_cntrl_empty <= '0';
+
+ p0_channel_cntrl_out(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= (others => '0');
+ p0_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_RE_IX) <= '0';
+ p0_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_WE_IX) <= '0';
+ p0_channel_cntrl_out(NOCEM_CHFIFO_DATA_RE_IX) <= '0';
+ p0_channel_cntrl_out(NOCEM_CHFIFO_DATA_WE_IX) <= '0';
+ p0_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= (others => '0');
+ p0_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= (others => '0');
+ p0_channel_cntrl_out(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= (others => '0');
+
+ p0_cntrl_re <= p0_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_RE_IX);
+ p0_cntrl_we <= p0_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_WE_IX);
+
+ p0_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_FULL_N_IX) <= not p0_cntrl_full;
+ p0_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX) <= not p0_cntrl_empty;
+
+ end process;
+
+ -- wrapping these constant assignments to make simulator actually work...
+ p1_handling_vc : process (p1_channel_cntrl_in,p1_data_full, p1_data_empty, p1_datain, p1_cntrl_full, p1_cntrl_empty, p1_pkt_cntrl_in )
+ begin
+
+ p1_data_re <= p1_channel_cntrl_in(NOCEM_CHFIFO_DATA_RE_IX);
+ p1_data_we <= p1_channel_cntrl_in(NOCEM_CHFIFO_DATA_WE_IX);
+
+ p1_channel_cntrl_out(NOCEM_CHFIFO_DATA_FULL_N_IX) <= not p1_data_full;
+ p1_channel_cntrl_out(NOCEM_CHFIFO_DATA_EMPTY_N_IX) <= not p1_data_empty;
+
+
+ p1_data_full <= '0';
+ p1_data_empty <= '0';
+ p1_cntrl_full <= '0';
+ p1_cntrl_empty <= '0';
+
+ p1_channel_cntrl_out(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= (others => '0');
+ p1_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_RE_IX) <= '0';
+ p1_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_WE_IX) <= '0';
+ p1_channel_cntrl_out(NOCEM_CHFIFO_DATA_RE_IX) <= '0';
+ p1_channel_cntrl_out(NOCEM_CHFIFO_DATA_WE_IX) <= '0';
+ p1_channel_cntrl_out(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX) <= (others => '0');
+ p1_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX) <= (others => '0');
+ p1_channel_cntrl_out(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= (others => '0');
+
+ p1_cntrl_re <= p1_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_RE_IX);
+ p1_cntrl_we <= p1_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_WE_IX);
+
+ p1_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_FULL_N_IX) <= not p1_cntrl_full;
+ p1_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX) <= not p1_cntrl_empty;
+
+ end process;
+
+ end generate; -- end VC handling processes
+
+
+ gnovc_procs: if NOCEM_TYPE /= NOCEM_VC_TYPE generate
+
+
+ -- wrapping these constant assignments to make simulator actually work...
+ p0_handling_no_vc : process (p0_channel_cntrl_in, p0_data_full, p0_data_empty, p0_datain, p0_cntrl_full, p0_cntrl_empty, p0_pkt_cntrl_in )
+ begin
+
+ p0_data_re <= p0_channel_cntrl_in(NOCEM_CHFIFO_DATA_RE_IX);
+ p0_data_we <= p0_channel_cntrl_in(NOCEM_CHFIFO_DATA_WE_IX);
+
+ p0_channel_cntrl_out(NOCEM_CHFIFO_DATA_FULL_N_IX) <= not p0_data_full;
+ p0_channel_cntrl_out(NOCEM_CHFIFO_DATA_EMPTY_N_IX) <= not p0_data_empty;
+
+ p0_cntrl_re <= p0_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_RE_IX);
+ p0_cntrl_we <= p0_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_WE_IX);
+
+ p0_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_FULL_N_IX) <= not p0_cntrl_full;
+ p0_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX) <= not p0_cntrl_empty;
+
+ end process;
+
+ -- wrapping these constant assignments to make simulator actually work...
+ p1_handling_no_vc : process (p1_channel_cntrl_in,p1_data_full, p1_data_empty, p1_datain, p1_cntrl_full, p1_cntrl_empty, p1_pkt_cntrl_in )
+ begin
+
+ p1_data_re <= p1_channel_cntrl_in(NOCEM_CHFIFO_DATA_RE_IX);
+ p1_data_we <= p1_channel_cntrl_in(NOCEM_CHFIFO_DATA_WE_IX);
+
+ p1_channel_cntrl_out(NOCEM_CHFIFO_DATA_FULL_N_IX) <= not p1_data_full;
+ p1_channel_cntrl_out(NOCEM_CHFIFO_DATA_EMPTY_N_IX) <= not p1_data_empty;
+
+ p1_cntrl_re <= p1_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_RE_IX);
+ p1_cntrl_we <= p1_channel_cntrl_in(NOCEM_CHFIFO_CNTRL_WE_IX);
+
+ p1_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_FULL_N_IX) <= not p1_cntrl_full;
+ p1_channel_cntrl_out(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX) <= not p1_cntrl_empty;
+
+ end process;
+
+ end generate; -- end no VC handling processes
+
+
+
+
+
+
+g3: if NOCEM_CHFIFO_TYPE = NOCEM_CHFIFO_VC_TYPE generate
+
+
+ p01_vc : vc_channel
+ Generic map (IS_AN_ACCESS_POINT_CHANNEL => IS_AN_ACCESS_POINT_CHANNEL)
+ PORT MAP(
+ rd_pkt_cntrl => p1_pkt_cntrl_out,
+ rd_pkt_data => p1_dataout,
+
+ node_dest_id => p1_addr_conv,
+ vc_mux_wr => p0_channel_cntrl_in(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX),
+ vc_mux_rd => p1_channel_cntrl_in(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX),
+ wr_pkt_cntrl => p0_pkt_cntrl_in,
+ wr_pkt_data => p0_datain,
+
+ rd_pkt_chdest => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_CHDEST_HIX downto NOCEM_CHFIFO_VC_CHDEST_LIX),
+ rd_pkt_vcdest => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX),
+ rd_pkt_vcsrc => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_VCSRC_HIX downto NOCEM_CHFIFO_VC_VCSRC_LIX),
+ vc_eop_rd_status => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX),
+ vc_eop_wr_status => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_EOP_WR_HIX downto NOCEM_CHFIFO_VC_EOP_WR_LIX),
+ vc_allocate_from_node => p1_channel_cntrl_in(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX),
+ vc_requester_from_node => p1_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX),
+ vc_allocate_destch_to_node => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX downto NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX),
+
+ --vc_allocate_destch_to_node--
+
+ vc_requester_to_node => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX),
+ vc_empty => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_EMPTY_HIX downto NOCEM_CHFIFO_VC_EMPTY_LIX),
+ vc_full => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX),
+ RE => p1_data_re,
+ WE => p0_data_we,
+ clk => clk,
+ rst => rst
+ );
+
+
+ g31: if IS_AN_ACCESS_POINT_CHANNEL = false generate
+
+ p10_vc_false : vc_channel
+ Generic map (IS_AN_ACCESS_POINT_CHANNEL => IS_AN_ACCESS_POINT_CHANNEL)
+ PORT MAP(
+
+ rd_pkt_cntrl => p0_pkt_cntrl_out,
+ rd_pkt_data => p0_dataout,
+
+ node_dest_id => p0_addr_conv,
+ vc_mux_wr => p1_channel_cntrl_in(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX),
+ vc_mux_rd => p0_channel_cntrl_in(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX),
+
+ wr_pkt_cntrl => p1_pkt_cntrl_in,
+ wr_pkt_data => p1_datain,
+
+ rd_pkt_chdest => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_CHDEST_HIX downto NOCEM_CHFIFO_VC_CHDEST_LIX),
+ rd_pkt_vcdest => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX),
+ rd_pkt_vcsrc => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_VCSRC_HIX downto NOCEM_CHFIFO_VC_VCSRC_LIX),
+
+ vc_eop_rd_status => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX),
+ vc_eop_wr_status => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_EOP_WR_HIX downto NOCEM_CHFIFO_VC_EOP_WR_LIX),
+ vc_allocate_from_node => p0_channel_cntrl_in(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX),
+ vc_requester_from_node => p0_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX),
+ vc_allocate_destch_to_node => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX downto NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX),
+ vc_requester_to_node => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX),
+ vc_empty => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_EMPTY_HIX downto NOCEM_CHFIFO_VC_EMPTY_LIX),
+ vc_full => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX),
+ RE => p0_data_re,
+ WE => p1_data_we,
+ clk => clk,
+ rst => rst
+ );
+
+ end generate;
+
+ g32: if IS_AN_ACCESS_POINT_CHANNEL = true generate
+
+ p10_vc_true : vc_channel_destap
+ PORT MAP(
+ node_dest_id => p0_addr_conv,
+ vc_mux_rd => p0_channel_cntrl_in(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX),
+ vc_mux_wr => p1_channel_cntrl_in(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX),
+ wr_pkt_cntrl => p1_pkt_cntrl_in,
+ wr_pkt_data => p1_datain,
+ rd_pkt_cntrl => p0_pkt_cntrl_out,
+ rd_pkt_data => p0_dataout,
+ rd_pkt_chdest => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_CHDEST_HIX downto NOCEM_CHFIFO_VC_CHDEST_LIX),
+ rd_pkt_vcdest => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_VCDEST_HIX downto NOCEM_CHFIFO_VC_VCDEST_LIX),
+ rd_pkt_vcsrc => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_VCSRC_HIX downto NOCEM_CHFIFO_VC_VCSRC_LIX),
+ vc_eop_rd_status => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX),
+ vc_eop_wr_status => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_EOP_WR_HIX downto NOCEM_CHFIFO_VC_EOP_WR_LIX),
+ vc_allocate_from_node => p0_channel_cntrl_in(NOCEM_CHFIFO_VC_ALLOC_FROMNODE_HIX downto NOCEM_CHFIFO_VC_ALLOC_FROMNODE_LIX),
+ vc_requester_from_node => p0_channel_cntrl_in(NOCEM_CHFIFO_VC_REQER_FROMNODE_HIX downto NOCEM_CHFIFO_VC_REQER_FROMNODE_LIX),
+ vc_allocate_destch_to_node => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_DEST_CH_HIX downto NOCEM_CHFIFO_VC_REQER_DEST_CH_LIX),
+ vc_requester_to_node => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_REQER_VCID_HIX downto NOCEM_CHFIFO_VC_REQER_VCID_LIX),
+ vc_empty => p0_channel_cntrl_out(NOCEM_CHFIFO_VC_EMPTY_HIX downto NOCEM_CHFIFO_VC_EMPTY_LIX),
+ vc_full => p1_channel_cntrl_out(NOCEM_CHFIFO_VC_FULL_HIX downto NOCEM_CHFIFO_VC_FULL_LIX),
+ RE => p0_data_re,
+ WE => p1_data_we,
+ clk => clk,
+ rst => rst
+ );
+
+ end generate;
+
+end generate;
+
+
+
+
+
+g2: if NOCEM_CHFIFO_TYPE = NOCEM_CHFIFO_NOVC_TYPE generate
+
+ p01_cntrl_fifo_allvhdl : fifo_allvhdl
+ generic map(
+ WIDTH => NOCEM_PKT_CNTRL_WIDTH,
+ ADDR_WIDTH => Log2(NOCEM_CHFIFO_DEPTH)
+ )
+ port map (
+ clk => clk,
+ din => p0_pkt_cntrl_in,
+ rd_en => p1_cntrl_re,
+ rst => rst,
+ wr_en => p0_cntrl_we,
+ dout => p1_pkt_cntrl_out,
+ empty => p1_cntrl_empty,
+ full => p0_cntrl_full
+ );
+
+ p01_data_fifo_allvhdl : fifo_allvhdl
+ generic map(
+ WIDTH => NOCEM_DW,
+ ADDR_WIDTH => Log2(NOCEM_CHFIFO_DEPTH)
+ )
+ port map (
+ clk => clk,
+ din => p0_datain,
+ rd_en => p1_data_re,
+ rst => rst,
+ wr_en => p0_data_we,
+ dout => p1_dataout,
+ empty => p1_data_empty,
+ full => p0_data_full
+ );
+
+ p10_cntrl_fifo_allvhdl : fifo_allvhdl
+ generic map(
+ WIDTH => NOCEM_PKT_CNTRL_WIDTH,
+ ADDR_WIDTH => Log2(NOCEM_CHFIFO_DEPTH)
+ )
+ port map (
+ clk => clk,
+ din => p1_pkt_cntrl_in,
+ rd_en => p0_cntrl_re,
+ rst => rst,
+ wr_en => p1_cntrl_we,
+ dout => p0_pkt_cntrl_out,
+ empty => p0_cntrl_empty,
+ full => p1_cntrl_full
+ );
+
+ p10_data_fifo_allvhdl : fifo_allvhdl
+ generic map(
+ WIDTH => NOCEM_DW,
+ ADDR_WIDTH => Log2(NOCEM_CHFIFO_DEPTH)
+ )
+ port map (
+ clk => clk,
+ din => p1_datain,
+ rd_en => p0_data_re,
+ rst => rst,
+ wr_en => p1_data_we,
+ dout => p0_dataout,
+ empty => p0_data_empty,
+ full => p1_data_full
+ );
+
+end generate;
+
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/simple_pkt_node.vhd
===================================================================
--- nocem/trunk/VHDL/simple_pkt_node.vhd (nonexistent)
+++ nocem/trunk/VHDL/simple_pkt_node.vhd (revision 8)
@@ -0,0 +1,190 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: simple_pkt_node.vhd
+--
+-- Description: toplevel node for nonVC designs
+--
+
+
+--
+--
+-- A node in a packet switched NoC consists of arbitration and switching logic....
+--
+--
+--
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.pkg_nocem.all;
+
+
+
+
+entity simple_pkt_node is
+
+
+
+ Port (
+ local_arb_addr : std_logic_vector(NOCEM_AW-1 downto 0);
+
+ n_datain : in data_word;
+ n_pkt_cntrl_in : in pkt_cntrl_word;
+
+ n_dataout : out data_word;
+ n_pkt_cntrl_out : out pkt_cntrl_word;
+
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+
+
+ s_datain : in data_word;
+ s_pkt_cntrl_in : in pkt_cntrl_word;
+
+ s_dataout : out data_word;
+ s_pkt_cntrl_out : out pkt_cntrl_word;
+
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+
+
+ e_datain : in data_word;
+ e_pkt_cntrl_in : in pkt_cntrl_word;
+
+ e_dataout : out data_word;
+ e_pkt_cntrl_out : out pkt_cntrl_word;
+
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+
+
+ w_datain : in data_word;
+ w_pkt_cntrl_in : in pkt_cntrl_word;
+
+ w_dataout : out data_word;
+ w_pkt_cntrl_out : out pkt_cntrl_word;
+
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+
+ ap_datain : in data_word;
+ ap_pkt_cntrl_in : in pkt_cntrl_word;
+
+ ap_dataout : out data_word;
+ ap_pkt_cntrl_out : out pkt_cntrl_word;
+
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+end simple_pkt_node;
+
+architecture Behavioral of simple_pkt_node is
+
+
+ signal arb_grant_output : arb_decision_array(4 downto 0);
+
+ -- the arbiter may be able to write the pkt_cntrl word before it gets
+ -- muxed out to the output ports, therefore need internal signal
+ signal n_pkt_cntrl_out_i : pkt_cntrl_word;
+ signal s_pkt_cntrl_out_i : pkt_cntrl_word;
+ signal e_pkt_cntrl_out_i : pkt_cntrl_word;
+ signal w_pkt_cntrl_out_i : pkt_cntrl_word;
+ signal ap_pkt_cntrl_out_i : pkt_cntrl_word;
+
+begin
+
+
+
+ I_local_arb : simple_pkt_local_arb PORT MAP(
+ local_arb_addr => local_arb_addr,
+ arb_grant_output => arb_grant_output,
+ n_pkt_cntrl_in => n_pkt_cntrl_in,
+ n_pkt_cntrl_out => n_pkt_cntrl_out_i,
+ n_channel_cntrl_in => n_channel_cntrl_in,
+ n_channel_cntrl_out => n_channel_cntrl_out,
+ s_pkt_cntrl_in => s_pkt_cntrl_in,
+ s_pkt_cntrl_out => s_pkt_cntrl_out_i,
+ s_channel_cntrl_in => s_channel_cntrl_in,
+ s_channel_cntrl_out => s_channel_cntrl_out,
+ e_pkt_cntrl_in => e_pkt_cntrl_in,
+ e_pkt_cntrl_out => e_pkt_cntrl_out_i,
+ e_channel_cntrl_in => e_channel_cntrl_in,
+ e_channel_cntrl_out => e_channel_cntrl_out,
+ w_pkt_cntrl_in => w_pkt_cntrl_in,
+ w_pkt_cntrl_out => w_pkt_cntrl_out_i,
+ w_channel_cntrl_in => w_channel_cntrl_in,
+ w_channel_cntrl_out => w_channel_cntrl_out,
+ ap_pkt_cntrl_in => ap_pkt_cntrl_in,
+ ap_pkt_cntrl_out => ap_pkt_cntrl_out_i,
+ ap_channel_cntrl_in => ap_channel_cntrl_in,
+ ap_channel_cntrl_out => ap_channel_cntrl_out,
+ clk => clk,
+ rst => rst
+ );
+
+
+ I_local_switch : simple_pkt_local_switch PORT MAP(
+ arb_grant_output => arb_grant_output,
+ ap_datain => ap_datain,
+ ap_dataout => ap_dataout,
+ n_datain => n_datain,
+ n_dataout => n_dataout,
+ s_datain => s_datain,
+ s_dataout => s_dataout,
+ e_datain => e_datain,
+ e_dataout => e_dataout,
+ w_datain => w_datain,
+ w_dataout => w_dataout,
+ n_pkt_cntrl_in => n_pkt_cntrl_out_i,
+ n_pkt_cntrl_out => n_pkt_cntrl_out,
+ s_pkt_cntrl_in => s_pkt_cntrl_out_i,
+ s_pkt_cntrl_out => s_pkt_cntrl_out,
+ e_pkt_cntrl_in => e_pkt_cntrl_out_i,
+ e_pkt_cntrl_out => e_pkt_cntrl_out,
+ w_pkt_cntrl_in => w_pkt_cntrl_out_i,
+ w_pkt_cntrl_out => w_pkt_cntrl_out,
+ ap_pkt_cntrl_in => ap_pkt_cntrl_out_i,
+ ap_pkt_cntrl_out => ap_pkt_cntrl_out,
+ clk => clk,
+ rst => rst
+ );
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/arb_simple_pkt_nocem.vhd
===================================================================
--- nocem/trunk/VHDL/arb_simple_pkt_nocem.vhd (nonexistent)
+++ nocem/trunk/VHDL/arb_simple_pkt_nocem.vhd (revision 8)
@@ -0,0 +1,82 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: arb_simple_pkt_nocem.vhd
+--
+-- Description: interconnect for packet designs
+--
+
+
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:53:27 09/12/05
+-- Design Name:
+-- Module Name: arb_simple_pkt_nocem - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity arb_simple_pkt_nocem is
+ Port ( clk : in std_logic;
+ rst : in std_logic);
+end arb_simple_pkt_nocem;
+
+architecture Behavioral of arb_simple_pkt_nocem is
+
+begin
+
+
+
+-- instantiate NUM_ACCESS_POINTS local arbitrators
+
+-- tie together the wires necessary (datain/out / channel in/out)
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/vc_node.vhd
===================================================================
--- nocem/trunk/VHDL/vc_node.vhd (nonexistent)
+++ nocem/trunk/VHDL/vc_node.vhd (revision 8)
@@ -0,0 +1,352 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: vc_node.vhd
+--
+-- Description: vc_node toplevel instantiation
+--
+
+
+
+
+--A Virtual Channel node is connected to Virtual Channels on its input and output ports.
+--This node will do normal data switching, but will also manage allocation
+--of the virtual channels themselves.
+
+library IEEE;
+
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+use work.pkg_nocem.all;
+
+entity vc_node is
+
+ Port (
+ local_arb_addr : std_logic_vector(NOCEM_AW-1 downto 0);
+
+ n_datain : in data_word;
+ n_pkt_cntrl_in : in pkt_cntrl_word;
+
+ n_dataout : out data_word;
+ n_pkt_cntrl_out : out pkt_cntrl_word;
+
+ n_channel_cntrl_in : in channel_cntrl_word;
+ n_channel_cntrl_out : out channel_cntrl_word;
+
+ s_datain : in data_word;
+ s_pkt_cntrl_in : in pkt_cntrl_word;
+
+ s_dataout : out data_word;
+ s_pkt_cntrl_out : out pkt_cntrl_word;
+
+ s_channel_cntrl_in : in channel_cntrl_word;
+ s_channel_cntrl_out : out channel_cntrl_word;
+
+
+ e_datain : in data_word;
+ e_pkt_cntrl_in : in pkt_cntrl_word;
+
+ e_dataout : out data_word;
+ e_pkt_cntrl_out : out pkt_cntrl_word;
+
+ e_channel_cntrl_in : in channel_cntrl_word;
+ e_channel_cntrl_out : out channel_cntrl_word;
+
+
+ w_datain : in data_word;
+ w_pkt_cntrl_in : in pkt_cntrl_word;
+
+ w_dataout : out data_word;
+ w_pkt_cntrl_out : out pkt_cntrl_word;
+
+ w_channel_cntrl_in : in channel_cntrl_word;
+ w_channel_cntrl_out : out channel_cntrl_word;
+
+ ap_datain : in data_word;
+ ap_pkt_cntrl_in : in pkt_cntrl_word;
+
+ ap_dataout : out data_word;
+ ap_pkt_cntrl_out : out pkt_cntrl_word;
+
+ ap_channel_cntrl_in : in channel_cntrl_word;
+ ap_channel_cntrl_out : out channel_cntrl_word;
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+end vc_node;
+
+architecture Behavioral of vc_node is
+
+-- lots of signals, but needed for the various blocks that write channel control words
+signal n_channel_cntrl_out_vcalloc_n : channel_cntrl_word;
+signal n_channel_cntrl_out_vcalloc_s : channel_cntrl_word;
+signal n_channel_cntrl_out_vcalloc_e : channel_cntrl_word;
+signal n_channel_cntrl_out_vcalloc_w : channel_cntrl_word;
+signal n_channel_cntrl_out_vcalloc_ap : channel_cntrl_word;
+
+signal s_channel_cntrl_out_vcalloc_n : channel_cntrl_word;
+signal s_channel_cntrl_out_vcalloc_s : channel_cntrl_word;
+signal s_channel_cntrl_out_vcalloc_e : channel_cntrl_word;
+signal s_channel_cntrl_out_vcalloc_w : channel_cntrl_word;
+signal s_channel_cntrl_out_vcalloc_ap : channel_cntrl_word;
+
+signal e_channel_cntrl_out_vcalloc_n : channel_cntrl_word;
+signal e_channel_cntrl_out_vcalloc_s : channel_cntrl_word;
+signal e_channel_cntrl_out_vcalloc_e : channel_cntrl_word;
+signal e_channel_cntrl_out_vcalloc_w : channel_cntrl_word;
+signal e_channel_cntrl_out_vcalloc_ap : channel_cntrl_word;
+
+signal w_channel_cntrl_out_vcalloc_n : channel_cntrl_word;
+signal w_channel_cntrl_out_vcalloc_s : channel_cntrl_word;
+signal w_channel_cntrl_out_vcalloc_e : channel_cntrl_word;
+signal w_channel_cntrl_out_vcalloc_w : channel_cntrl_word;
+signal w_channel_cntrl_out_vcalloc_ap : channel_cntrl_word;
+
+signal ap_channel_cntrl_out_vcalloc_n : channel_cntrl_word;
+signal ap_channel_cntrl_out_vcalloc_s : channel_cntrl_word;
+signal ap_channel_cntrl_out_vcalloc_e : channel_cntrl_word;
+signal ap_channel_cntrl_out_vcalloc_w : channel_cntrl_word;
+signal ap_channel_cntrl_out_vcalloc_ap : channel_cntrl_word;
+
+
+signal n_channel_cntrl_out_ch_arb : channel_cntrl_word;
+signal s_channel_cntrl_out_ch_arb : channel_cntrl_word;
+signal e_channel_cntrl_out_ch_arb : channel_cntrl_word;
+signal w_channel_cntrl_out_ch_arb : channel_cntrl_word;
+signal ap_channel_cntrl_out_ch_arb : channel_cntrl_word;
+
+
+signal arb_grant_output : arb_decision_array(4 downto 0);
+
+
+signal local_ch_addr_converted : std_logic_vector(4 downto 0);
+
+signal channel_word_z : channel_cntrl_word;
+
+
+
+begin
+
+
+channel_word_z <= (others => '0');
+
+
+
+
+ local_ch_addr_converted <= CONV_STD_LOGIC_VECTOR(2**NOCEM_NORTH_IX,5);
+
+
+ -- VC ALLOCATION BLOCKS (one per outgoing channel)
+ I_vc_alloc_n: vc_node_vc_allocator PORT MAP(
+ local_ch_addr => ARB_NORTH,
+ outoing_vc_status => n_channel_cntrl_in(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX),
+ n_channel_cntrl_in => channel_word_z, --n_channel_cntrl_in,
+ n_channel_cntrl_out => open, --n_channel_cntrl_out_vcalloc_n,
+ s_channel_cntrl_in => s_channel_cntrl_in,
+ s_channel_cntrl_out => s_channel_cntrl_out_vcalloc_n,
+ e_channel_cntrl_in => e_channel_cntrl_in,
+ e_channel_cntrl_out => e_channel_cntrl_out_vcalloc_n,
+ w_channel_cntrl_in => w_channel_cntrl_in,
+ w_channel_cntrl_out => w_channel_cntrl_out_vcalloc_n,
+ ap_channel_cntrl_in => ap_channel_cntrl_in,
+ ap_channel_cntrl_out => ap_channel_cntrl_out_vcalloc_n,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_alloc_s: vc_node_vc_allocator PORT MAP(
+ local_ch_addr => ARB_SOUTH,
+ outoing_vc_status => s_channel_cntrl_in(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX),
+ n_channel_cntrl_in => n_channel_cntrl_in,
+ n_channel_cntrl_out => n_channel_cntrl_out_vcalloc_s,
+ s_channel_cntrl_in => channel_word_z, --s_channel_cntrl_in,
+ s_channel_cntrl_out => open, --s_channel_cntrl_out_vcalloc_s,
+ e_channel_cntrl_in => e_channel_cntrl_in,
+ e_channel_cntrl_out => e_channel_cntrl_out_vcalloc_s,
+ w_channel_cntrl_in => w_channel_cntrl_in,
+ w_channel_cntrl_out => w_channel_cntrl_out_vcalloc_s,
+ ap_channel_cntrl_in => ap_channel_cntrl_in,
+ ap_channel_cntrl_out => ap_channel_cntrl_out_vcalloc_s,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_alloc_e: vc_node_vc_allocator PORT MAP(
+ local_ch_addr => ARB_EAST,
+ outoing_vc_status => e_channel_cntrl_in(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX),
+ n_channel_cntrl_in => n_channel_cntrl_in,
+ n_channel_cntrl_out => n_channel_cntrl_out_vcalloc_e,
+ s_channel_cntrl_in => s_channel_cntrl_in,
+ s_channel_cntrl_out => s_channel_cntrl_out_vcalloc_e,
+ e_channel_cntrl_in => channel_word_z, --e_channel_cntrl_in,
+ e_channel_cntrl_out => open, --e_channel_cntrl_out_vcalloc_e,
+ w_channel_cntrl_in => w_channel_cntrl_in,
+ w_channel_cntrl_out => w_channel_cntrl_out_vcalloc_e,
+ ap_channel_cntrl_in => ap_channel_cntrl_in,
+ ap_channel_cntrl_out => ap_channel_cntrl_out_vcalloc_e,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_alloc_w: vc_node_vc_allocator PORT MAP(
+ local_ch_addr => ARB_WEST,
+ outoing_vc_status => w_channel_cntrl_in(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX),
+ n_channel_cntrl_in => n_channel_cntrl_in,
+ n_channel_cntrl_out => n_channel_cntrl_out_vcalloc_w,
+ s_channel_cntrl_in => s_channel_cntrl_in,
+ s_channel_cntrl_out => s_channel_cntrl_out_vcalloc_w,
+ e_channel_cntrl_in => e_channel_cntrl_in,
+ e_channel_cntrl_out => e_channel_cntrl_out_vcalloc_w,
+ w_channel_cntrl_in => channel_word_z, --w_channel_cntrl_in,
+ w_channel_cntrl_out => open, --w_channel_cntrl_out_vcalloc_w,
+ ap_channel_cntrl_in => ap_channel_cntrl_in,
+ ap_channel_cntrl_out => ap_channel_cntrl_out_vcalloc_w,
+ clk => clk,
+ rst => rst
+ );
+
+ I_vc_alloc_ap: vc_node_vc_allocator PORT MAP(
+ local_ch_addr => ARB_AP,
+ outoing_vc_status => ap_channel_cntrl_in(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX),
+ n_channel_cntrl_in => n_channel_cntrl_in,
+ n_channel_cntrl_out => n_channel_cntrl_out_vcalloc_ap,
+ s_channel_cntrl_in => s_channel_cntrl_in,
+ s_channel_cntrl_out => s_channel_cntrl_out_vcalloc_ap,
+ e_channel_cntrl_in => e_channel_cntrl_in,
+ e_channel_cntrl_out => e_channel_cntrl_out_vcalloc_ap,
+ w_channel_cntrl_in => w_channel_cntrl_in,
+ w_channel_cntrl_out => w_channel_cntrl_out_vcalloc_ap,
+ ap_channel_cntrl_in => channel_word_z, --ap_channel_cntrl_in,
+ ap_channel_cntrl_out => open, --ap_channel_cntrl_out_vcalloc_ap,
+ clk => clk,
+ rst => rst
+ );
+
+ -- ROUTER / PHYSICAL CHANNEL ARBITER
+ I_ch_arbiter: vc_node_ch_arbiter PORT MAP(
+ arb_grant_output => arb_grant_output,
+ n_channel_cntrl_in => n_channel_cntrl_in,
+ n_channel_cntrl_out => n_channel_cntrl_out_ch_arb,
+ s_channel_cntrl_in => s_channel_cntrl_in,
+ s_channel_cntrl_out => s_channel_cntrl_out_ch_arb,
+ e_channel_cntrl_in => e_channel_cntrl_in,
+ e_channel_cntrl_out => e_channel_cntrl_out_ch_arb,
+ w_channel_cntrl_in => w_channel_cntrl_in,
+ w_channel_cntrl_out => w_channel_cntrl_out_ch_arb,
+ ap_channel_cntrl_in => ap_channel_cntrl_in,
+ ap_channel_cntrl_out => ap_channel_cntrl_out_ch_arb,
+ clk => clk,
+ rst => rst
+ );
+
+
+ -- THE SWITCH ITSELF
+ I_vc_switch : simple_pkt_local_switch PORT MAP(
+ arb_grant_output => arb_grant_output,
+ ap_datain => ap_datain,
+ ap_dataout => ap_dataout,
+ n_datain => n_datain,
+ n_dataout => n_dataout,
+ s_datain => s_datain,
+ s_dataout => s_dataout,
+ e_datain => e_datain,
+ e_dataout => e_dataout,
+ w_datain => w_datain,
+ w_dataout => w_dataout,
+ n_pkt_cntrl_in => n_pkt_cntrl_in,
+ n_pkt_cntrl_out => n_pkt_cntrl_out,
+ s_pkt_cntrl_in => s_pkt_cntrl_in,
+ s_pkt_cntrl_out => s_pkt_cntrl_out,
+ e_pkt_cntrl_in => e_pkt_cntrl_in,
+ e_pkt_cntrl_out => e_pkt_cntrl_out,
+ w_pkt_cntrl_in => w_pkt_cntrl_in,
+ w_pkt_cntrl_out => w_pkt_cntrl_out,
+ ap_pkt_cntrl_in => ap_pkt_cntrl_in,
+ ap_pkt_cntrl_out => ap_pkt_cntrl_out,
+ clk => clk,
+ rst => rst
+ );
+
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- OR TOGETHER THE CHANNEL CONTROL OUT SINGALS (JUST FOR SYNTACTICAL -----
+-- PURPOSES, "TRIM LOGIC" WILL EAT MOST IF NOT ALL OF THESE OR'D SIGNALS -----
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+ap_channel_cntrl_out <= ap_channel_cntrl_out_ch_arb or
+ ap_channel_cntrl_out_vcalloc_n or
+ ap_channel_cntrl_out_vcalloc_s or
+ ap_channel_cntrl_out_vcalloc_e or
+ ap_channel_cntrl_out_vcalloc_w;-- or
+ --ap_channel_cntrl_out_vcalloc_ap;
+
+n_channel_cntrl_out <= n_channel_cntrl_out_ch_arb or
+ --n_channel_cntrl_out_vcalloc_n or
+ n_channel_cntrl_out_vcalloc_s or
+ n_channel_cntrl_out_vcalloc_e or
+ n_channel_cntrl_out_vcalloc_w or
+ n_channel_cntrl_out_vcalloc_ap;
+
+s_channel_cntrl_out <= s_channel_cntrl_out_ch_arb or
+ s_channel_cntrl_out_vcalloc_n or
+ --s_channel_cntrl_out_vcalloc_s or
+ s_channel_cntrl_out_vcalloc_e or
+ s_channel_cntrl_out_vcalloc_w or
+ s_channel_cntrl_out_vcalloc_ap;
+
+e_channel_cntrl_out <= e_channel_cntrl_out_ch_arb or
+ e_channel_cntrl_out_vcalloc_n or
+ e_channel_cntrl_out_vcalloc_s or
+ --e_channel_cntrl_out_vcalloc_e or
+ e_channel_cntrl_out_vcalloc_w or
+ e_channel_cntrl_out_vcalloc_ap;
+
+w_channel_cntrl_out <= w_channel_cntrl_out_ch_arb or
+ w_channel_cntrl_out_vcalloc_n or
+ w_channel_cntrl_out_vcalloc_s or
+ w_channel_cntrl_out_vcalloc_e or
+ --w_channel_cntrl_out_vcalloc_w or
+ w_channel_cntrl_out_vcalloc_ap;
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/mux2to1.vhd
===================================================================
--- nocem/trunk/VHDL/mux2to1.vhd (nonexistent)
+++ nocem/trunk/VHDL/mux2to1.vhd (revision 8)
@@ -0,0 +1,109 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: mux2to1.vhd
+--
+-- Description: simple mux
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity mux2to1 is
+generic (
+ DWIDTH : integer := 16;
+ REG_OUTPUT : integer := 0
+ );
+ port (
+ din0 : in std_logic_vector( DWIDTH-1 downto 0);
+ din1 : in std_logic_vector( DWIDTH-1 downto 0);
+ sel : in std_logic_vector( 1 downto 0);
+ dout : out std_logic_vector( DWIDTH-1 downto 0);
+
+
+ clk : in std_logic;
+ rst : in std_logic
+ );
+end mux2to1;
+
+architecture Behavioral of mux2to1 is
+
+begin
+
+
+
+g_uregd: if REG_OUTPUT=0 generate
+ muxit_uregd : process (din0,din1,sel)
+ begin
+ case sel is
+ when "01" =>
+ dout <= din0;
+ when "10" =>
+ dout <= din1;
+ when others =>
+ dout <= (others => '0');
+ end case;
+
+ end process;
+
+end generate;
+
+
+g_regd: if REG_OUTPUT=1 generate
+ muxit_regd : process (rst,clk)
+ begin
+
+ if rst = '1' then
+ dout <= (others => '0');
+ elsif clk='1' and clk'event then
+ case sel is
+ when "01" =>
+ dout <= din0;
+ when "10" =>
+ dout <= din1;
+ when others =>
+ dout <= (others => '0');
+ end case;
+
+ end if;
+
+ end process;
+
+end generate;
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/fifo_reg.vhd
===================================================================
--- nocem/trunk/VHDL/fifo_reg.vhd (nonexistent)
+++ nocem/trunk/VHDL/fifo_reg.vhd (revision 8)
@@ -0,0 +1,110 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: fifo_reg.vhd
+--
+-- Description: a single register FIFO
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+
+
+entity fifo_reg is
+ generic (
+ WIDTH : integer := 16
+ );
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(WIDTH-1 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(WIDTH-1 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+
+
+end fifo_reg;
+
+architecture Behavioral of fifo_reg is
+
+signal empty_i : std_logic;
+
+
+
+
+begin
+
+
+
+ full <= not empty_i;
+ empty <= empty_i;
+
+ delay_gen : process (clk,rst)
+ begin
+ if rst='1' then
+ dout <= (others => '0');
+ empty_i <= '1';
+
+ elsif clk'event and clk='1' then
+
+
+
+ -- manage empty signal
+ if empty_i = '0' and rd_en ='1' and wr_en = '0' then
+ empty_i <= '1';
+ elsif empty_i = '1' and rd_en='0' and wr_en='1' then
+ empty_i <= '0';
+ end if;
+
+ --manage dout
+ if rd_en='1' and wr_en='0' then
+ dout <= (others => '0');
+ elsif wr_en='1' then
+ dout <= din;
+ end if;
+
+
+
+ end if;
+
+
+ end process;
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/mux4to1.vhd
===================================================================
--- nocem/trunk/VHDL/mux4to1.vhd (nonexistent)
+++ nocem/trunk/VHDL/mux4to1.vhd (revision 8)
@@ -0,0 +1,118 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: mux4to1.vhd
+--
+-- Description: simple mux
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity mux4to1 is
+generic (
+ DWIDTH : integer := 16;
+ REG_OUTPUT : integer := 0
+ );
+ port (
+ din0 : in std_logic_vector( DWIDTH-1 downto 0);
+ din1 : in std_logic_vector( DWIDTH-1 downto 0);
+ din2 : in std_logic_vector( DWIDTH-1 downto 0);
+ din3 : in std_logic_vector( DWIDTH-1 downto 0);
+ sel : in std_logic_vector( 3 downto 0);
+ dout : out std_logic_vector( DWIDTH-1 downto 0);
+
+ clk : in std_logic;
+ rst : in std_logic
+ );
+end mux4to1;
+
+architecture Behavioral of mux4to1 is
+
+begin
+
+g_uregd: if REG_OUTPUT=0 generate
+ muxit_uregd : process (din0,din1,din2,din3,sel)
+ begin
+ case sel is
+ when "0001" =>
+ dout <= din0;
+ when "0010" =>
+ dout <= din1;
+ when "0100" =>
+ dout <= din2;
+ when "1000" =>
+ dout <= din3;
+ when others =>
+ dout <= (others => '0');
+ end case;
+
+ end process;
+
+end generate;
+
+
+g_regd: if REG_OUTPUT=1 generate
+ muxit_regd : process (rst,clk)
+ begin
+
+ if rst = '1' then
+ dout <= (others => '0');
+ elsif clk='1' and clk'event then
+ case sel is
+ when "0001" =>
+ dout <= din0;
+ when "0010" =>
+ dout <= din1;
+ when "0100" =>
+ dout <= din2;
+ when "1000" =>
+ dout <= din3;
+ when others =>
+ dout <= (others => '0');
+ end case;
+
+ end if;
+
+ end process;
+
+end generate;
+
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/fifo_gfs.vhd
===================================================================
--- nocem/trunk/VHDL/fifo_gfs.vhd (nonexistent)
+++ nocem/trunk/VHDL/fifo_gfs.vhd (revision 8)
@@ -0,0 +1,329 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: fifo_gfs.vhd
+--
+-- Description: an all vhdl version of a FIFO
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity fifo_gfs is
+ generic (
+ WIDTH : integer := 16; -- FIFO word width
+ ADD_WIDTH : integer := 3 -- Address Width
+ );
+
+ PORT(
+ Data_in : IN std_logic_vector(WIDTH-1 downto 0);
+ clk : IN std_logic;
+ Reset : IN std_logic;
+ RE : IN std_logic;
+ WE : IN std_logic;
+ Data_out : OUT std_logic_vector(WIDTH-1 downto 0);
+ Full : OUT std_logic;
+ Half_full : OUT std_logic;
+ empty : OUT std_logic
+ );
+end fifo_gfs;
+
+
+
+architecture Behavioral of fifo_gfs is
+
+ signal MAX_ADDR: std_logic_vector(ADD_WIDTH downto 0);
+ signal MIN_ADDR: std_logic_vector(ADD_WIDTH downto 0);
+
+
+ signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
+ signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0);
+ signal D_ADD : std_logic_vector(ADD_WIDTH downto 0); -- notice size of ADD_WIDTH+1
+
+
+ signal rst_n : std_logic;
+
+ signal empty_datain,empty_dataout,empty_memcore : std_logic;
+ signal full_datain,full_dataout,full_memcore : std_logic;
+
+ signal dout_dataout,dout_datain,dout_memcore : std_logic_vector(WIDTH-1 downto 0);
+ signal din_dataout,din_datain,din_memcore : std_logic_vector(WIDTH-1 downto 0);
+ signal we_dataout,we_datain,we_memcore : std_logic;
+ signal re_dataout,re_datain,re_memcore : std_logic;
+
+ component dpmem
+ generic (ADD_WIDTH : integer;
+ WIDTH : integer);
+
+ port (clk : in std_logic;
+ reset : in std_logic;
+ w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
+ r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
+ data_in : in std_logic_vector(WIDTH - 1 downto 0);
+ data_out : out std_logic_vector(WIDTH - 1 downto 0 );
+ WR : in std_logic;
+ RE : in std_logic);
+ end component;
+
+ COMPONENT fifo_reg
+ generic (
+ WIDTH : integer
+ );
+ PORT(
+ clk : IN std_logic;
+ din : IN std_logic_vector(WIDTH-1 downto 0);
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_en : IN std_logic;
+ dout : OUT std_logic_vector(WIDTH-1 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic
+ );
+ END COMPONENT;
+
+
+begin
+
+
+ constant_sigs : process (empty_datain,empty_memcore, empty_dataout, full_datain, full_memcore, full_dataout, Reset)
+ begin
+ empty <= empty_datain and empty_memcore and empty_dataout;
+ full <= full_datain and full_memcore and full_dataout;
+ Half_full <= '0';
+
+ rst_n <= not reset;
+
+
+ MAX_ADDR <= (others => '0');
+ MAX_ADDR(ADD_WIDTH) <= '1';
+ MIN_ADDR <= (others => '0');
+
+ end process;
+
+
+ -----------------------------------------------------------
+ ------------------- SIGNAL GENERATION ---------------------
+ -----------------------------------------------------------
+
+ -- dataout_fifo
+ Data_out <= dout_dataout;
+
+
+ dataflow_gen : process (dout_memcore, dout_datain,full_dataout,WE, Data_in, full_memcore, full_datain, RE, empty_memcore, empty_datain)
+ begin
+
+
+ din_dataout <= (others => '0');
+ we_dataout <= '0';
+ re_dataout <= '0';
+
+ din_memcore <= (others => '0');
+ we_memcore <= '0';
+ re_memcore <= '0';
+
+ din_datain <= (others => '0');
+ we_datain <= '0';
+ re_datain <= '0';
+
+
+
+ -- where to do writing of new data
+ if full_dataout='0' and WE='1' and RE='0' then
+ din_dataout <= Data_in;
+ we_dataout <= WE;
+ elsif full_memcore='0' and WE='1' and RE='0' then
+ din_memcore <= Data_in;
+ we_memcore <= WE;
+ elsif full_datain='0' and WE='1' and RE='0' then
+ din_datain <= Data_in;
+ we_datain <= WE;
+ end if;
+
+ -- handling RE's
+ if RE='1' and WE='0' then
+ re_dataout <= RE;
+
+ if empty_memcore='0' then
+ re_memcore <= '1';
+ we_dataout <= '1';
+ din_dataout <= dout_memcore;
+ end if;
+
+ if empty_datain='0' then
+ re_datain <= '1';
+ we_memcore <= '1';
+ din_memcore <= dout_datain;
+ end if;
+ end if;
+
+
+ if RE='1' and WE='1' then
+
+ if full_dataout='1' and empty_memcore='1' then
+ re_dataout <= '1';
+ we_dataout <= '1';
+ din_dataout <= data_in;
+ elsif full_dataout='1' and empty_memcore='0' and empty_datain='1' then
+ re_dataout <= '1';
+ re_memcore <= '1';
+ we_dataout <= '1';
+ we_memcore <= '1';
+ din_dataout <= dout_memcore;
+ din_memcore <= data_in;
+ elsif full_dataout='1' and full_memcore='1' and full_datain='1' then
+ re_dataout <= '1';
+ re_memcore <= '1';
+ we_dataout <= '1';
+ we_memcore <= '1';
+ re_datain <= '1';
+ we_datain <= '1';
+ din_dataout <= dout_memcore;
+ din_memcore <= dout_datain;
+ din_datain <= data_in;
+ end if;
+ end if;
+
+
+
+ end process;
+
+
+
+
+ -- handling memcore signalling
+ memcore_sig_gen_clkd : process (clk,reset)
+ begin
+
+ if reset='1' then
+ W_ADD <= (others =>'0');
+ R_ADD <= (others =>'0');
+ D_ADD <= (others =>'0');
+ elsif clk='1' and clk'event then
+
+ if we_memcore = '1' then
+ W_ADD <= W_ADD + 1;
+ end if;
+
+ if re_memcore = '1' then
+ R_ADD <= R_ADD + 1;
+ end if;
+
+ if we_memcore='1' and re_memcore='1' then
+ null;
+ elsif we_memcore='1' then
+ D_ADD <= D_ADD + 1;
+ elsif re_memcore='1' then
+ D_ADD <= D_ADD - 1;
+ else
+ null;
+ end if;
+
+ end if;
+
+ end process;
+
+
+ -- handling memcore signalling
+ memcore_sig_gen_uclkd : process (D_ADD, MIN_ADDR, MAX_ADDR)
+ begin
+
+ if D_ADD = MIN_ADDR then
+ empty_memcore <= '1';
+ else
+ empty_memcore <= '0';
+ end if;
+
+ if D_ADD = MAX_ADDR then
+ full_memcore <= '1';
+ else
+ full_memcore <= '0';
+ end if;
+
+ end process;
+
+
+ -----------------------------------------------------------
+ ------------------- THE ACTUAL FIFOS ----------------------
+ -----------------------------------------------------------
+
+ datain_reg : fifo_reg
+ Generic map(
+ WIDTH => WIDTH
+ )
+ PORT MAP(
+ clk => clk,
+ din => din_datain,
+ rd_en => re_datain,
+ rst => Reset,
+ wr_en => we_datain,
+ dout => dout_datain,
+ empty => empty_datain,
+ full => full_datain
+ );
+
+
+ memcore: dpmem
+ generic map (
+ ADD_WIDTH =>ADD_WIDTH,
+ WIDTH => WIDTH
+ )
+ port map (clk => clk,
+ reset => rst_n,
+ w_add => W_ADD,
+ r_add => R_ADD,
+ Data_in => din_memcore,
+ data_out => dout_memcore,
+ wr => we_memcore,
+ re => re_memcore);
+
+
+ dataout_reg : fifo_reg
+ Generic map(
+ WIDTH => WIDTH
+ )
+ PORT MAP(
+ clk => clk,
+ din => din_dataout,
+ rd_en => re_dataout,
+ rst => reset,
+ wr_en => we_dataout,
+ dout => dout_dataout,
+ empty => empty_dataout,
+ full => full_dataout
+ );
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/access_point_exerciser.vhd
===================================================================
--- nocem/trunk/VHDL/access_point_exerciser.vhd (nonexistent)
+++ nocem/trunk/VHDL/access_point_exerciser.vhd (revision 8)
@@ -0,0 +1,293 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: access_point_exerciser.vhd
+--
+-- Description: access point exerciser for nonVC designs
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.pkg_nocem.all;
+
+
+
+entity access_point_exerciser is
+ Generic(
+
+ DELAY_START_COUNTER_WIDTH : integer := 32;
+ DELAY_START_CYCLES : integer := 500;
+
+
+ BURST_LENGTH : integer := 5;
+ INIT_DATA_OUT : data_word := CONV_STD_LOGIC_VECTOR(1,NOCEM_DW);
+
+ INTERVAL_COUNTER_WIDTH : integer := 8;
+ DATA_OUT_INTERVAL : integer := 16;
+
+ INIT_DEST_ADDR : integer := 2
+
+
+
+ ) ;
+ Port (
+
+ -- arbitration lines (usage depends on underlying network)
+ arb_req : out std_logic;
+ arb_cntrl_out : out arb_cntrl_word;
+
+ arb_grant : in std_logic;
+ arb_cntrl_in : in arb_cntrl_word;
+
+ datain : in data_word;
+ datain_valid : in std_logic;
+ datain_recvd : out std_logic;
+
+ dataout : out data_word;
+ dataout_valid : out std_logic;
+ dataout_recvd : in std_logic;
+
+ pkt_cntrl_in : in pkt_cntrl_word;
+ pkt_cntrl_in_valid : in std_logic;
+ pkt_cntrl_in_recvd : out std_logic;
+
+ pkt_cntrl_out : out pkt_cntrl_word;
+ pkt_cntrl_out_valid : out std_logic;
+ pkt_cntrl_out_recvd : in std_logic;
+
+ clk : in std_logic;
+ rst : in std_logic
+
+ );
+
+
+
+end access_point_exerciser;
+
+architecture Behavioral of access_point_exerciser is
+
+
+
+
+signal rst_i : std_logic;
+signal rst_counter : std_logic_vector(DELAY_START_COUNTER_WIDTH-1 downto 0);
+signal interval_counter : std_logic_vector(INTERVAL_COUNTER_WIDTH-1 downto 0);
+signal dataout_reg : std_logic_vector(NOCEM_DW-1 downto 0);
+signal pkt_cntrl_out_reg : pkt_cntrl_word;
+
+
+signal burst_counter : std_logic_vector(7 downto 0);
+
+signal datain_reg : data_word;
+signal pkt_cntrl_in_reg : pkt_cntrl_word;
+
+
+ type stateType is (init_st,sending_st,getting_arb_st);
+ signal state,nextState : stateType;
+
+
+begin
+
+rst_gen : process (clk,rst)
+begin
+ if rst='1' then
+ rst_i <= '1';
+ rst_counter <= (others => '0');
+ elsif clk'event and clk ='1' then
+ rst_counter <= rst_counter+1;
+ if rst_counter = DELAY_START_CYCLES then
+ rst_i <= '0';
+ end if;
+ end if;
+end process;
+
+
+dataout_gen_clkd : process (clk,rst_i,nextState)
+begin
+ if rst_i = '1' then
+ state <= init_st;
+ interval_counter <= (others => '0');
+ dataout_reg <= INIT_DATA_OUT;
+
+ -- setup pkt_cntrl correctly
+ pkt_cntrl_out_reg <= CONV_STD_LOGIC_VECTOR(INIT_DEST_ADDR,NOCEM_PKT_CNTRL_WIDTH);
+
+
+
+ burst_counter <= (others => '0');
+ elsif clk'event and clk='1' then
+ state <= nextState;
+ case state is
+ when init_st =>
+ interval_counter <= interval_counter+1;
+ burst_counter <= (others => '0');
+ --dataout_reg <= INIT_DATA_OUT;
+ --pkt_cntrl_out_reg <=
+ when getting_arb_st =>
+ interval_counter <= (others => '0');
+
+ if nextState = sending_st or nextState = init_st then
+ dataout_reg <= dataout_reg + 1;
+ burst_counter <= burst_counter+1;
+ end if;
+
+ if nextState = init_st then
+ pkt_cntrl_out_reg <= pkt_cntrl_out_reg + 1;
+ end if;
+
+
+ when sending_st =>
+ if arb_grant = '1' and dataout_recvd = '1' then
+ burst_counter <= burst_counter + 1;
+ end if;
+
+ if nextState = init_st then
+ pkt_cntrl_out_reg <= pkt_cntrl_out_reg + 1;
+ end if;
+
+ when others =>
+ null;
+ end case;
+ end if;
+end process;
+
+
+dataout_gen_uclkd : process (pkt_cntrl_out_reg, pkt_cntrl_out_recvd,state, interval_counter, dataout_reg, arb_grant, dataout_recvd, burst_counter)
+begin
+
+ arb_req <= '0';
+ dataout <= (others => '0');
+ dataout_valid <= '0';
+ nextState <= init_st;
+ arb_cntrl_out <= (others => '0');
+ pkt_cntrl_out <= (others => '0');
+ pkt_cntrl_out_valid <= '0';
+
+ case state is
+ when init_st =>
+ if interval_counter = CONV_STD_LOGIC_VECTOR(DATA_OUT_INTERVAL,INTERVAL_COUNTER_WIDTH) then
+ nextState <= getting_arb_st;
+ else
+ nextState <= init_st;
+ end if;
+
+ when getting_arb_st =>
+ arb_req <= '1';
+ dataout <= dataout_reg;
+ dataout_valid <= '1';
+
+ pkt_cntrl_out <= pkt_cntrl_out_reg;
+ pkt_cntrl_out_valid <= '1';
+
+
+ if arb_grant = '1' and dataout_recvd = '1' and pkt_cntrl_out_recvd = '1'and BURST_LENGTH /= 1 then
+ nextState <= sending_st;
+ elsif arb_grant = '1' and dataout_recvd = '1' and pkt_cntrl_out_recvd = '1' and BURST_LENGTH = 1 then
+ nextState <= init_st;
+ else
+ nextState <= getting_arb_st;
+ end if;
+
+
+
+
+ when sending_st =>
+ arb_req <= '1';
+ dataout <= dataout_reg;
+ dataout_valid <= '1';
+
+ if burst_counter = BURST_LENGTH then
+ nextState <= init_st;
+ else
+ nextState <= sending_st;
+ end if;
+
+ when others =>
+ null;
+ end case;
+end process;
+
+
+
+datain_gather_clkd : process (clk,rst)
+begin
+
+ if rst='1' then
+ --datain_recvd <= '0';
+ datain_reg <= (others => '0');
+ pkt_cntrl_in_reg <= (others => '0');
+ --pkt_cntrl_in_recvd <= '0';
+ elsif clk'event and clk= '1' then
+ if datain_valid = '1' then
+ datain_reg <= datain;
+ --datain_recvd <= '1';
+ --pkt_cntrl_in_recvd <= '1';
+ else
+ --datain_recvd <= '0';
+ --pkt_cntrl_in_recvd <= '0';
+ end if;
+
+ if pkt_cntrl_in_valid = '1' then
+ pkt_cntrl_in_reg <= pkt_cntrl_in;
+ --pkt_cntrl_in_recvd <= '1';
+ else
+ --pkt_cntrl_in_recvd <= '0';
+ end if;
+ end if;
+
+end process;
+
+datain_gather_uclkd : process (datain_valid,pkt_cntrl_in_valid)
+begin
+
+ datain_recvd <= '0';
+ pkt_cntrl_in_recvd <= '0';
+
+ if datain_valid = '1' then
+ datain_recvd <= '1';
+ end if;
+
+ if pkt_cntrl_in_valid = '1' then
+ pkt_cntrl_in_recvd <= '1';
+ end if;
+
+
+end process;
+
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/packetbuffer2.vhd
===================================================================
--- nocem/trunk/VHDL/packetbuffer2.vhd (nonexistent)
+++ nocem/trunk/VHDL/packetbuffer2.vhd (revision 8)
@@ -0,0 +1,141 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: packetbuffer2.vhd
+--
+-- Description: packetbuffer for noc2proc bridging
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+use work.pkg_nocem.all;
+
+
+entity packetbuffer2 is
+ generic(
+-- DATAIN_WIDTH : integer := 64;
+-- DATAOUT_WIDTH : integer := 32;
+ METADATA_WIDTH : integer := 8;
+ METADATA_LENGTH : integer := 8
+ );
+ Port (
+ din : IN std_logic_VECTOR(31 downto 0);
+
+ rd_en : IN std_logic;
+
+ wr_en : IN std_logic;
+ dout : OUT std_logic_VECTOR(31 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic;
+
+
+
+-- pkt_len : in std_logic_vector(7 downto 0);
+ pkt_metadata_din : in std_logic_vector(METADATA_WIDTH-1 downto 0);
+ pkt_metadata_re : IN std_logic;
+ pkt_metadata_we : IN std_logic;
+ pkt_metadata_dout : out std_logic_vector(METADATA_WIDTH-1 downto 0);
+ --pkt_metadata_empty : out std_logic;
+ --pkt_metadata_full : out std_logic
+ clk : in std_logic;
+ rst : in std_logic);
+end packetbuffer2;
+
+architecture Behavioral of packetbuffer2 is
+
+ COMPONENT fifo32
+ PORT(
+ din : IN std_logic_vector(31 downto 0);
+ rd_clk : IN std_logic;
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_clk : IN std_logic;
+ wr_en : IN std_logic;
+ dout : OUT std_logic_vector(31 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ signal pb_full,pkt_metadata_full,pb_empty,pkt_metadata_empty : std_logic;
+
+begin
+
+ full <= pb_full or pkt_metadata_full;
+ --empty <= pb_empty and pkt_metadata_empty;
+ empty <= pkt_metadata_empty;
+
+-- lets just wrap a 32/32 FIFO and let outside world set up reads and write appropriately.
+
+ fifo_pb : fifo32 PORT MAP(
+ din => din,
+ rd_clk => clk,
+ rd_en => rd_en,
+ rst => rst,
+ wr_clk => clk,
+ wr_en => wr_en,
+ dout => dout,
+ empty => pb_empty,
+ full => pb_full
+ );
+
+
+
+
+ I_metadata : fifo_gfs
+ Generic MAP(
+ WIDTH => METADATA_WIDTH,
+ ADD_WIDTH => Log2(METADATA_LENGTH)
+ )
+ PORT MAP(
+ Data_in => pkt_metadata_din,
+ clk => clk,
+ Reset => rst,
+ RE => pkt_metadata_re,
+ WE => pkt_metadata_we,
+ Data_out => pkt_metadata_dout,
+ Full => pkt_metadata_full,
+ Half_full => open,
+ empty => pkt_metadata_empty
+ );
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/ic_bus_nocem.vhd
===================================================================
--- nocem/trunk/VHDL/ic_bus_nocem.vhd (nonexistent)
+++ nocem/trunk/VHDL/ic_bus_nocem.vhd (revision 8)
@@ -0,0 +1,149 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: ic_bus_nocem.vhd
+--
+-- Description: interconnect for bus design
+--
+
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+
+
+entity ic_bus_nocem is
+
+
+ Port (
+
+ arb_grant : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ --data and addr incoming/outgoing line (usage depends on underlying network)
+ datain : in data_array(NOCEM_NUM_AP-1 downto 0);
+ dataout : out data_array(NOCEM_NUM_AP-1 downto 0);
+
+ dataout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ addrin : in pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ addrout : out pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ addrout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ clk : in std_logic;
+ rst : in std_logic
+
+
+
+ );
+end ic_bus_nocem;
+
+architecture Behavioral of ic_bus_nocem is
+
+
+
+begin
+
+
+ic_management : process (rst,arb_grant, datain,addrin)
+begin
+ for I in NOCEM_NUM_AP-1 downto 0 loop
+ dataout(I) <= (others => '0');
+ addrout(I) <= (others => '0');
+ dataout_valid <= (others => '0');
+ addrout_valid <= (others => '0');
+ end loop;
+
+ if rst = '1' then
+ for I in NOCEM_NUM_AP-1 downto 0 loop
+ dataout(I) <= (others => '0');
+ addrout(I) <= (others => '0');
+ dataout_valid <= (others => '0');
+ addrout_valid <= (others => '0');
+ end loop;
+ else
+ l1: for I in NOCEM_NUM_AP-1 downto 0 loop
+ if arb_grant = CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_AP) then
+-- if arb_grant(I) = '1' then
+ l2: for J in NOCEM_NUM_AP downto 1 loop
+ dataout(J) <= datain(I);
+ addrout(J) <= addrin(I);
+ end loop;
+
+ dataout_valid <= (others => '1');
+ addrout_valid <= (others => '1');
+
+
+ end if;
+ end loop;
+
+-- case arb_grant is
+-- for I in NOCEM_NUM_AP-1 downto 0 loop
+-- when CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_AP) =>
+-- l2: for J in NOCEM_NUM_AP downto 1 loop
+-- dataout(DATA_WIDTH*J-1 downto DATA_WIDTH*(J-1)) <= datain(DATA_WIDTH*(I+1)-1 downto DATA_WIDTH*I);
+-- addrout(ADDR_WIDTH*J-1 downto ADDR_WIDTH*(J-1)) <= addrin(ADDR_WIDTH*(I+1)-1 downto ADDR_WIDTH*I);
+-- end loop;
+
+-- dataout_valid <= (others => '1');
+-- addrout_valid <= (others => '1');
+-- end loop;
+
+-- when others =>
+-- dataout <= (others => '0');
+-- addrout <= (others => '0');
+-- dataout_valid <= (others => '0');
+-- addrout_valid <= (others => '0');
+
+
+-- end case;
+
+
+
+
+
+
+
+
+
+
+ end if;
+
+end process;
+
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/barrelshift4_wrapper.sch
===================================================================
--- nocem/trunk/VHDL/barrelshift4_wrapper.sch (nonexistent)
+++ nocem/trunk/VHDL/barrelshift4_wrapper.sch (revision 8)
@@ -0,0 +1,99 @@
+VERSION 6
+BEGIN SCHEMATIC
+ BEGIN ATTR DeviceFamilyName "virtex2p"
+ DELETE all:0
+ EDITNAME all:0
+ EDITTRAIT all:0
+ END ATTR
+ BEGIN NETLIST
+ SIGNAL I0
+ SIGNAL I1
+ SIGNAL I2
+ SIGNAL I3
+ SIGNAL S0
+ SIGNAL S1
+ SIGNAL O3
+ SIGNAL O2
+ SIGNAL O1
+ SIGNAL O0
+ PORT Input I0
+ PORT Input I1
+ PORT Input I2
+ PORT Input I3
+ PORT Input S0
+ PORT Input S1
+ PORT Output O3
+ PORT Output O2
+ PORT Output O1
+ PORT Output O0
+ BEGIN BLOCKDEF brlshft4
+ TIMESTAMP 2001 2 2 12 39 57
+ LINE N 0 -128 64 -128
+ LINE N 0 -192 64 -192
+ LINE N 0 -320 64 -320
+ LINE N 384 -320 320 -320
+ LINE N 384 -512 320 -512
+ LINE N 0 -448 64 -448
+ LINE N 0 -512 64 -512
+ LINE N 384 -448 320 -448
+ LINE N 0 -384 64 -384
+ LINE N 384 -384 320 -384
+ RECTANGLE N 64 -576 320 -64
+ END BLOCKDEF
+ BEGIN BLOCK XLXI_1 brlshft4
+ PIN I0 I0
+ PIN I1 I1
+ PIN I2 I2
+ PIN I3 I3
+ PIN S0 S0
+ PIN S1 S1
+ PIN O0 O0
+ PIN O1 O1
+ PIN O2 O2
+ PIN O3 O3
+ END BLOCK
+ END NETLIST
+ BEGIN SHEET 1 3520 2720
+ INSTANCE XLXI_1 1488 1520 R0
+ BEGIN BRANCH I0
+ WIRE 1456 1008 1488 1008
+ END BRANCH
+ IOMARKER 1456 1008 I0 R180 28
+ BEGIN BRANCH I1
+ WIRE 1456 1072 1488 1072
+ END BRANCH
+ IOMARKER 1456 1072 I1 R180 28
+ BEGIN BRANCH I2
+ WIRE 1456 1136 1488 1136
+ END BRANCH
+ IOMARKER 1456 1136 I2 R180 28
+ BEGIN BRANCH I3
+ WIRE 1456 1200 1488 1200
+ END BRANCH
+ IOMARKER 1456 1200 I3 R180 28
+ BEGIN BRANCH S0
+ WIRE 1456 1328 1488 1328
+ END BRANCH
+ IOMARKER 1456 1328 S0 R180 28
+ BEGIN BRANCH S1
+ WIRE 1456 1392 1488 1392
+ END BRANCH
+ IOMARKER 1456 1392 S1 R180 28
+ BEGIN BRANCH O3
+ WIRE 1872 1200 1904 1200
+ END BRANCH
+ IOMARKER 1904 1200 O3 R0 28
+ BEGIN BRANCH O2
+ WIRE 1872 1136 1904 1136
+ END BRANCH
+ IOMARKER 1904 1136 O2 R0 28
+ BEGIN BRANCH O1
+ WIRE 1872 1072 1904 1072
+ END BRANCH
+ IOMARKER 1904 1072 O1 R0 28
+ BEGIN BRANCH O0
+ WIRE 1872 1008 1904 1008
+ END BRANCH
+ IOMARKER 1904 1008 O0 R0 28
+ END SHEET
+END SCHEMATIC
Index: nocem/trunk/VHDL/fifo_allvhdl.vhd
===================================================================
--- nocem/trunk/VHDL/fifo_allvhdl.vhd (nonexistent)
+++ nocem/trunk/VHDL/fifo_allvhdl.vhd (revision 8)
@@ -0,0 +1,213 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: fifo_allvhdl.vhd
+--
+-- Description: a vhdl based FIFO implementation
+--
+
+
+-------------------------------------------------------------------------------
+--
+-- This implementation was heavily modified from
+-- http://www.geocities.com/SiliconValley/Pines/6639/ip/fifo_vhdl.html
+--
+-- and the following comment section describes the licensing and authorship
+--
+--
+-- NOTES:
+-- 1. removed buffer type ports because they are bad
+-- 2. usig FIFO_v7
+--
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Copyright Jamil Khatib 1999
+--
+--
+-- This VHDL design file is an open design; you can redistribute it and/or
+-- modify it and/or implement it under the terms of the Openip General Public
+-- License as it is going to be published by the OpenIP Organization and any
+-- coming versions of this license.
+-- You can check the draft license at
+-- http://www.openip.org/oc/license.html
+--
+--
+-- Creator : Jamil Khatib
+-- Date 10/10/99
+--
+-- version 0.19991226
+--
+-- This file was tested on the ModelSim 5.2EE
+-- The test vecors for model sim is included in vectors.do file
+-- This VHDL design file is proved through simulation but not verified on Silicon
+--
+--
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+--
+--entity listing in this file
+--
+-- 1. dpmem: used in Khatib's FIFO implementation
+-- 3. fifo_allvhdl: my wrapper to match nocem interfaces
+--
+--
+--
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+ENTITY dpmem IS
+generic ( ADD_WIDTH: integer := 8 ;
+ WIDTH : integer := 8);
+ port (
+ clk : in std_logic; -- write clock
+ reset : in std_logic; -- System Reset
+ W_add : in std_logic_vector(ADD_WIDTH -1 downto 0); -- Write Address
+ R_add : in std_logic_vector(ADD_WIDTH -1 downto 0); -- Read Address
+ Data_In : in std_logic_vector(WIDTH - 1 downto 0); -- input data
+ Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- output Data
+ WR : in std_logic; -- Write Enable
+ RE : in std_logic); -- Read Enable
+end dpmem;
+
+ARCHITECTURE dpmem_v3 OF dpmem IS
+
+ type dpmemdata_array is array (integer range <>) of std_logic_vector(WIDTH -1 downto 0); -- Memory Type
+ signal data : dpmemdata_array(0 to (2** ADD_WIDTH)-1 ); -- Local data
+
+begin -- dpmem_v3
+
+ mem_clkd : process (clk, reset,data)
+
+ begin -- PROCESS
+
+
+ -- activities triggered by asynchronous reset (active low)
+ if reset = '0' then
+
+ for i in 0 to (2** add_width)-1 loop
+ data(i) <= (others => '0');
+ end loop;
+
+ -- activities triggered by rising edge of clock
+ elsif clk'event and clk = '1' then
+ if WR = '1' then
+ data(conv_integeR(W_add)) <= Data_In;
+ end if;
+
+ end if;
+ end process;
+
+ mem_uclkd : process (RE,data,r_add)
+ begin
+ data_out <= data(conv_integer(R_add));
+ end process;
+
+
+
+
+end dpmem_v3;
+
+
+
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+
+entity fifo_allvhdl is
+ generic(
+ WIDTH : integer := 16;
+ ADDR_WIDTH : integer := 3
+ );
+ port (
+ din : in std_logic_vector(WIDTH-1 downto 0); -- Input data
+ dout : out std_logic_vector(WIDTH-1 downto 0); -- Output data
+ clk : in std_logic; -- System Clock
+ rst : in std_logic; -- System global Reset
+ rd_en : in std_logic; -- Read Enable
+ wr_en : in std_logic; -- Write Enable
+ full : out std_logic; -- Full Flag
+ empty : out std_logic -- empty Flag
+ );
+
+end fifo_allvhdl;
+
+architecture behavioral of fifo_allvhdl is
+
+begin
+
+ I_fk : fifo_gfs
+ Generic MAP(
+ WIDTH => WIDTH,
+ ADD_WIDTH => ADDR_WIDTH
+ )
+ PORT MAP(
+ Data_in => din,
+ clk => clk,
+ Reset => rst,
+ RE => rd_en,
+ WE => wr_en,
+ Data_out => dout,
+ Full => full,
+ Half_full => open,
+ empty => empty
+ );
+
+
+
+end behavioral;
\ No newline at end of file
Index: nocem/trunk/VHDL/barrelshift8_wrapper.sch
===================================================================
--- nocem/trunk/VHDL/barrelshift8_wrapper.sch (nonexistent)
+++ nocem/trunk/VHDL/barrelshift8_wrapper.sch (revision 8)
@@ -0,0 +1,171 @@
+VERSION 6
+BEGIN SCHEMATIC
+ BEGIN ATTR DeviceFamilyName "virtex2p"
+ DELETE all:0
+ EDITNAME all:0
+ EDITTRAIT all:0
+ END ATTR
+ BEGIN NETLIST
+ SIGNAL I0
+ SIGNAL I1
+ SIGNAL I2
+ SIGNAL I3
+ SIGNAL I4
+ SIGNAL I5
+ SIGNAL I6
+ SIGNAL I7
+ SIGNAL O7
+ SIGNAL O6
+ SIGNAL O5
+ SIGNAL O4
+ SIGNAL O3
+ SIGNAL O2
+ SIGNAL O1
+ SIGNAL O0
+ SIGNAL S2
+ SIGNAL S1
+ SIGNAL S0
+ PORT Input I0
+ PORT Input I1
+ PORT Input I2
+ PORT Input I3
+ PORT Input I4
+ PORT Input I5
+ PORT Input I6
+ PORT Input I7
+ PORT Output O7
+ PORT Output O6
+ PORT Output O5
+ PORT Output O4
+ PORT Output O3
+ PORT Output O2
+ PORT Output O1
+ PORT Output O0
+ PORT Input S2
+ PORT Input S1
+ PORT Input S0
+ BEGIN BLOCKDEF brlshft8
+ TIMESTAMP 2001 2 2 12 39 57
+ LINE N 0 -192 64 -192
+ RECTANGLE N 64 -896 320 -64
+ LINE N 384 -576 320 -576
+ LINE N 0 -576 64 -576
+ LINE N 0 -512 64 -512
+ LINE N 384 -512 320 -512
+ LINE N 384 -448 320 -448
+ LINE N 0 -448 64 -448
+ LINE N 0 -384 64 -384
+ LINE N 384 -384 320 -384
+ LINE N 384 -640 320 -640
+ LINE N 384 -704 320 -704
+ LINE N 384 -768 320 -768
+ LINE N 384 -832 320 -832
+ LINE N 0 -832 64 -832
+ LINE N 0 -768 64 -768
+ LINE N 0 -704 64 -704
+ LINE N 0 -640 64 -640
+ LINE N 0 -128 64 -128
+ LINE N 0 -256 64 -256
+ END BLOCKDEF
+ BEGIN BLOCK XLXI_1 brlshft8
+ PIN I0 I0
+ PIN I1 I1
+ PIN I2 I2
+ PIN I3 I3
+ PIN I4 I4
+ PIN I5 I5
+ PIN I6 I6
+ PIN I7 I7
+ PIN S0 S0
+ PIN S1 S1
+ PIN S2 S2
+ PIN O0 O0
+ PIN O1 O1
+ PIN O2 O2
+ PIN O3 O3
+ PIN O4 O4
+ PIN O5 O5
+ PIN O6 O6
+ PIN O7 O7
+ END BLOCK
+ END NETLIST
+ BEGIN SHEET 1 3520 2720
+ INSTANCE XLXI_1 1584 1744 R0
+ BEGIN BRANCH I0
+ WIRE 1552 912 1584 912
+ END BRANCH
+ IOMARKER 1552 912 I0 R180 28
+ BEGIN BRANCH I1
+ WIRE 1552 976 1584 976
+ END BRANCH
+ IOMARKER 1552 976 I1 R180 28
+ BEGIN BRANCH I2
+ WIRE 1552 1040 1584 1040
+ END BRANCH
+ IOMARKER 1552 1040 I2 R180 28
+ BEGIN BRANCH I3
+ WIRE 1552 1104 1584 1104
+ END BRANCH
+ IOMARKER 1552 1104 I3 R180 28
+ BEGIN BRANCH I4
+ WIRE 1552 1168 1584 1168
+ END BRANCH
+ IOMARKER 1552 1168 I4 R180 28
+ BEGIN BRANCH I5
+ WIRE 1552 1232 1584 1232
+ END BRANCH
+ IOMARKER 1552 1232 I5 R180 28
+ BEGIN BRANCH I6
+ WIRE 1552 1296 1584 1296
+ END BRANCH
+ IOMARKER 1552 1296 I6 R180 28
+ BEGIN BRANCH I7
+ WIRE 1552 1360 1584 1360
+ END BRANCH
+ IOMARKER 1552 1360 I7 R180 28
+ BEGIN BRANCH O7
+ WIRE 1968 1360 2000 1360
+ END BRANCH
+ IOMARKER 2000 1360 O7 R0 28
+ BEGIN BRANCH O6
+ WIRE 1968 1296 2000 1296
+ END BRANCH
+ IOMARKER 2000 1296 O6 R0 28
+ BEGIN BRANCH O5
+ WIRE 1968 1232 2000 1232
+ END BRANCH
+ IOMARKER 2000 1232 O5 R0 28
+ BEGIN BRANCH O4
+ WIRE 1968 1168 2000 1168
+ END BRANCH
+ IOMARKER 2000 1168 O4 R0 28
+ BEGIN BRANCH O3
+ WIRE 1968 1104 2000 1104
+ END BRANCH
+ IOMARKER 2000 1104 O3 R0 28
+ BEGIN BRANCH O2
+ WIRE 1968 1040 2000 1040
+ END BRANCH
+ IOMARKER 2000 1040 O2 R0 28
+ BEGIN BRANCH O1
+ WIRE 1968 976 2000 976
+ END BRANCH
+ IOMARKER 2000 976 O1 R0 28
+ BEGIN BRANCH O0
+ WIRE 1968 912 2000 912
+ END BRANCH
+ IOMARKER 2000 912 O0 R0 28
+ BEGIN BRANCH S2
+ WIRE 1552 1616 1584 1616
+ END BRANCH
+ IOMARKER 1552 1616 S2 R180 28
+ BEGIN BRANCH S1
+ WIRE 1552 1552 1584 1552
+ END BRANCH
+ IOMARKER 1552 1552 S1 R180 28
+ BEGIN BRANCH S0
+ WIRE 1552 1488 1584 1488
+ END BRANCH
+ IOMARKER 1552 1488 S0 R180 28
+ END SHEET
+END SCHEMATIC
Index: nocem/trunk/VHDL/ic_pkt_nocem.vhd
===================================================================
--- nocem/trunk/VHDL/ic_pkt_nocem.vhd (nonexistent)
+++ nocem/trunk/VHDL/ic_pkt_nocem.vhd (revision 8)
@@ -0,0 +1,710 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: ic_pkt_nocem.vhd
+--
+-- Description: the standard interconnect for pkts
+--
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+use work.pkg_nocem.all;
+
+
+
+entity ic_pkt_nocem is
+
+ Port (
+
+ -- arbitration lines (usage depends on underlying network)
+ arb_req : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_cntrl_in : in arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ arb_grant : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_cntrl_out : out arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+
+ --data and control incoming/outgoing line (usage depends on underlying network)
+ datain : in data_array(NOCEM_NUM_AP-1 downto 0);
+ datain_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ datain_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ dataout : out data_array(NOCEM_NUM_AP-1 downto 0);
+ dataout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ dataout_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ pkt_cntrl_in : in pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_in_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ pkt_cntrl_out : out pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ pkt_cntrl_out_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+
+
+ clk : in std_logic;
+ rst : in std_logic
+
+
+ );
+end ic_pkt_nocem;
+
+architecture Behavioral of ic_pkt_nocem is
+
+
+
+
+
+ -- for type conversion of x,y coordinates to std_logic_vector
+ signal local_arb_addr_converted : node_addr_array(NOCEM_NUM_AP-1 downto 0);
+
+
+ -- an aggregration of the data lines, should help in looping to create necessary signals
+ signal n_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_s_data : data_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal s_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_n_data : data_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal e_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_w_data : data_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal w_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_e_data : data_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal ap_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_node_data : data_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal node_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_ap_data : data_array(NOCEM_NUM_AP-1 downto 0);
+
+
+ -- an aggregration of the pkt_cntrls, should help in looping to create necessary signals
+ signal n_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_s_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal s_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_n_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal e_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_w_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal w_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_e_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal ap_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_node_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal node_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_to_ap_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+
+
+
+ -- an aggregration of the channel_cntrls, should help in looping to create necessary signals
+ -- naming convention is : _ fifo channel control
+ -- fifo _ channel control
+
+ -- example n_fifo_ch_cntrl: from node channel of node to fifo below
+ -- fifo_e_ch_cntrl: from fifo to east channel of node
+
+ signal n_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_n_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal s_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_s_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal e_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_e_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal w_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_w_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ signal ap_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal fifo_ap_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+ -- node: the actual PE, fifo connecting node to NoC switch
+ signal fifo_node_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal node_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+
+
+ -- signals that will be tied to (others => '0');
+ signal data_z : data_word;
+ signal pkt_cntrl_z : pkt_cntrl_word;
+ signal ch_cntrl_z : channel_cntrl_word;
+
+
+
+
+
+
+begin
+
+
+ data_z <= (others => '0');
+ pkt_cntrl_z <= (others => '0');
+ ch_cntrl_z <= (others => '0');
+
+
+
+
+
+--instantiate nodes, fifos
+g1: for I in NOCEM_NUM_AP-1 downto 0 generate
+
+ local_arb_addr_converted(I) <= addr_gen(I,NOCEM_NUM_ROWS,NOCEM_NUM_COLS,NOCEM_AW);
+
+
+
+ g11: if NOCEM_TYPE = NOCEM_VC_TYPE generate
+ I_vc_node : vc_node PORT MAP(
+ local_arb_addr => local_arb_addr_converted(I),
+
+ n_datain => fifo_to_n_data(I),
+ n_pkt_cntrl_in => fifo_to_n_pkt_cntrl(I),
+ n_dataout => n_to_fifo_data(I),
+ n_pkt_cntrl_out => n_to_fifo_pkt_cntrl(I),
+ n_channel_cntrl_in => fifo_n_ch_cntrl(I),
+ n_channel_cntrl_out => n_fifo_ch_cntrl(I),
+
+ s_datain => fifo_to_s_data(I),
+ s_pkt_cntrl_in => fifo_to_s_pkt_cntrl(I),
+ s_dataout => s_to_fifo_data(I),
+ s_pkt_cntrl_out => s_to_fifo_pkt_cntrl(I),
+ s_channel_cntrl_in => fifo_s_ch_cntrl(I),
+ s_channel_cntrl_out => s_fifo_ch_cntrl(I),
+
+ e_datain => fifo_to_e_data(I),
+ e_pkt_cntrl_in => fifo_to_e_pkt_cntrl(I),
+ e_dataout => e_to_fifo_data(I),
+ e_pkt_cntrl_out => e_to_fifo_pkt_cntrl(I),
+ e_channel_cntrl_in => fifo_e_ch_cntrl(I),
+ e_channel_cntrl_out => e_fifo_ch_cntrl(I),
+
+ w_datain => fifo_to_w_data(I),
+ w_pkt_cntrl_in => fifo_to_w_pkt_cntrl(I),
+ w_dataout => w_to_fifo_data(I),
+ w_pkt_cntrl_out => w_to_fifo_pkt_cntrl(I),
+ w_channel_cntrl_in => fifo_w_ch_cntrl(I),
+ w_channel_cntrl_out => w_fifo_ch_cntrl(I),
+
+ ap_datain => fifo_to_ap_data(I),
+ ap_pkt_cntrl_in => fifo_to_ap_pkt_cntrl(I),
+ ap_dataout => ap_to_fifo_data(I),
+ ap_pkt_cntrl_out => ap_to_fifo_pkt_cntrl(I),
+ ap_channel_cntrl_in => fifo_ap_ch_cntrl(I),
+ ap_channel_cntrl_out => ap_fifo_ch_cntrl(I),
+
+ clk => clk,
+ rst => rst
+ );
+ end generate;
+
+
+ g12: if NOCEM_TYPE = NOCEM_SIMPLE_PKT_TYPE generate
+ I_simple_pkt_node : simple_pkt_node PORT MAP(
+ local_arb_addr => local_arb_addr_converted(I),
+
+ n_datain => fifo_to_n_data(I),
+ n_pkt_cntrl_in => fifo_to_n_pkt_cntrl(I),
+ n_dataout => n_to_fifo_data(I),
+ n_pkt_cntrl_out => n_to_fifo_pkt_cntrl(I),
+ n_channel_cntrl_in => fifo_n_ch_cntrl(I),
+ n_channel_cntrl_out => n_fifo_ch_cntrl(I),
+
+ s_datain => fifo_to_s_data(I),
+ s_pkt_cntrl_in => fifo_to_s_pkt_cntrl(I),
+ s_dataout => s_to_fifo_data(I),
+ s_pkt_cntrl_out => s_to_fifo_pkt_cntrl(I),
+ s_channel_cntrl_in => fifo_s_ch_cntrl(I),
+ s_channel_cntrl_out => s_fifo_ch_cntrl(I),
+
+ e_datain => fifo_to_e_data(I),
+ e_pkt_cntrl_in => fifo_to_e_pkt_cntrl(I),
+ e_dataout => e_to_fifo_data(I),
+ e_pkt_cntrl_out => e_to_fifo_pkt_cntrl(I),
+ e_channel_cntrl_in => fifo_e_ch_cntrl(I),
+ e_channel_cntrl_out => e_fifo_ch_cntrl(I),
+
+ w_datain => fifo_to_w_data(I),
+ w_pkt_cntrl_in => fifo_to_w_pkt_cntrl(I),
+ w_dataout => w_to_fifo_data(I),
+ w_pkt_cntrl_out => w_to_fifo_pkt_cntrl(I),
+ w_channel_cntrl_in => fifo_w_ch_cntrl(I),
+ w_channel_cntrl_out => w_fifo_ch_cntrl(I),
+
+ ap_datain => fifo_to_ap_data(I),
+ ap_pkt_cntrl_in => fifo_to_ap_pkt_cntrl(I),
+ ap_dataout => ap_to_fifo_data(I),
+ ap_pkt_cntrl_out => ap_to_fifo_pkt_cntrl(I),
+ ap_channel_cntrl_in => fifo_ap_ch_cntrl(I),
+ ap_channel_cntrl_out => ap_fifo_ch_cntrl(I),
+
+ clk => clk,
+ rst => rst
+ );
+ end generate;
+
+end generate;
+
+ -- generate the fifos on outgoing paths
+ g2 : for I in NOCEM_NUM_AP-1 downto 0 generate
+
+
+---------------------------------------------------------------
+------ TOPLVEL WIRING ----
+---------------------------------------------------------------
+
+ channel_cntrl_handling : process (arb_cntrl_in,node_fifo_ch_cntrl,datain_valid, arb_req, fifo_node_ch_cntrl, pkt_cntrl_in_valid, dataout_recvd, pkt_cntrl_out_recvd)
+ begin
+
+ arb_cntrl_out(I) <= (others => '0');
+
+ -- first set control all to zeroes, let following statements overwrite values
+ node_fifo_ch_cntrl(I) <= (others => '0');
+
+ -- WE gets set when request comes in and the FIFO is not full
+ if NOCEM_TYPE = NOCEM_VC_TYPE then
+ -- with VCs, things are a little simpler....
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX) <= arb_req(I) and datain_valid(I);
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= arb_req(I) and pkt_cntrl_in_valid(I);
+
+ -- grant occurs when a write enable is allowed (see lines above)
+ arb_grant(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX) or node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX);
+
+ datain_recvd(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX);
+ pkt_cntrl_in_recvd(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX);
+
+
+ -- handling dataout valid, recvd signals
+ -- for VCs, the state of dataout is controlled by user watching for full packets
+ dataout_valid(I) <= '1';
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_RE_IX) <= dataout_recvd(I);
+
+ pkt_cntrl_out_valid(I) <= '1';
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_RE_IX) <= pkt_cntrl_out_recvd(I);
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= arb_cntrl_in(I)(NOCEM_ARB_CNTRL_VC_MUX_RD_HIX downto NOCEM_ARB_CNTRL_VC_MUX_RD_LIX);
+
+ else
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX) <= arb_req(I) and datain_valid(I) and fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_DATA_FULL_N_IX);
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= arb_req(I) and pkt_cntrl_in_valid(I) and fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_FULL_N_IX);
+
+ -- grant occurs when a write enable is allowed (see lines above)
+ arb_grant(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX) or node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX);
+
+ datain_recvd(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX);
+ pkt_cntrl_in_recvd(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX);
+
+ -- handling dataout valid, recvd signals
+ dataout_valid(I) <= fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_DATA_EMPTY_N_IX);
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_RE_IX) <= dataout_recvd(I);
+
+ pkt_cntrl_out_valid(I) <= fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX);
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_RE_IX) <= pkt_cntrl_out_recvd(I);
+
+ end if;
+
+
+
+ -- VC signalling to/from node
+ node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= arb_cntrl_in(I)(NOCEM_ARB_CNTRL_VC_MUX_WR_HIX downto NOCEM_ARB_CNTRL_VC_MUX_WR_LIX);
+ arb_cntrl_out(I)(NOCEM_ARB_CNTRL_VC_EOP_WR_HIX downto NOCEM_ARB_CNTRL_VC_EOP_WR_LIX) <= fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_VC_EOP_WR_HIX downto NOCEM_CHFIFO_VC_EOP_WR_LIX);
+ arb_cntrl_out(I)(NOCEM_ARB_CNTRL_VC_EOP_RD_HIX downto NOCEM_ARB_CNTRL_VC_EOP_RD_LIX) <= fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX);
+
+--constant NOCEM_ARB_CNTRL_VC_EOP_RD_LIX : integer := NOCEM_ARB_CNTRL_VC_MUX_RD_HIX+1; --8
+--constant NOCEM_ARB_CNTRL_VC_EOP_RD_HIX : integer := NOCEM_ARB_CNTRL_VC_EOP_RD_LIX+NOCEM_NUM_VC-1;
+--
+--constant NOCEM_ARB_CNTRL_VC_EOP_WR_LIX : integer := NOCEM_ARB_CNTRL_VC_EOP_RD_HIX+1; --12
+--constant NOCEM_ARB_CNTRL_VC_EOP_WR_HIX : integer := NOCEM_ARB_CNTRL_VC_EOP_WR_LIX+NOCEM_NUM_VC-1;
+--
+
+ end process;
+
+
+---------------------------------------------------------------
+---------------------------------------------------------------
+------ ACCESS POINT FIFOs ----
+---------------------------------------------------------------
+---------------------------------------------------------------
+
+ channel_ap_noc : channel_fifo
+ generic map(
+ P0_NODE_ADDR => I,
+ P1_NODE_ADDR => I,
+ IS_AN_ACCESS_POINT_CHANNEL => TRUE
+ )
+ PORT MAP(
+ p0_datain => datain(I),
+ p0_pkt_cntrl_in => pkt_cntrl_in(I),
+ p0_dataout => dataout(I),
+ p0_pkt_cntrl_out => pkt_cntrl_out(I),
+ p0_channel_cntrl_in => node_fifo_ch_cntrl(I),
+ p0_channel_cntrl_out => fifo_node_ch_cntrl(I),
+ p1_datain => ap_to_fifo_data(I),
+ p1_pkt_cntrl_in => ap_to_fifo_pkt_cntrl(I),
+ p1_dataout => fifo_to_ap_data(I),
+ p1_pkt_cntrl_out => fifo_to_ap_pkt_cntrl(I),
+ p1_channel_cntrl_in => ap_fifo_ch_cntrl(I),
+ p1_channel_cntrl_out => fifo_ap_ch_cntrl(I),
+ clk => clk,
+ rst => rst
+ );
+
+
+
+---------------------------------------------------------------
+---------------------------------------------------------------
+------ NORTH / SOUTH FIFOs ----
+---------------------------------------------------------------
+---------------------------------------------------------------
+
+-- top: top of chip, with ap's below it
+-- middle: middle of chip, ap's above and beloe
+-- bottom: bottom of chip, with ap's above it
+-- single row: no need for north south fifos
+
+
+ -- top of chip
+ g3: if (I+NOCEM_NUM_COLS) / NOCEM_NUM_COLS = NOCEM_NUM_ROWS and NOCEM_NUM_ROWS /= 1 generate
+
+
+
+
+
+ g33: if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_TORUS or
+ NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_DTORUS generate
+
+ channel_ns_tdt : channel_fifo
+ generic map(
+ P0_NODE_ADDR => I,
+ P1_NODE_ADDR => I mod NOCEM_NUM_COLS,
+ IS_AN_ACCESS_POINT_CHANNEL => FALSE
+ )
+ PORT MAP(
+ p0_datain => n_to_fifo_data(I),
+ p0_pkt_cntrl_in => n_to_fifo_pkt_cntrl(I),
+ p0_dataout => fifo_to_n_data(I),
+ p0_pkt_cntrl_out => fifo_to_n_pkt_cntrl(I),
+ p0_channel_cntrl_in => n_fifo_ch_cntrl(I),
+ p0_channel_cntrl_out => fifo_n_ch_cntrl(I),
+ p1_datain => s_to_fifo_data(I mod NOCEM_NUM_COLS),
+ p1_pkt_cntrl_in => s_to_fifo_pkt_cntrl(I mod NOCEM_NUM_COLS),
+ p1_dataout => fifo_to_s_data(I mod NOCEM_NUM_COLS),
+ p1_pkt_cntrl_out => fifo_to_s_pkt_cntrl(I mod NOCEM_NUM_COLS),
+ p1_channel_cntrl_in => s_fifo_ch_cntrl(I mod NOCEM_NUM_COLS),
+ p1_channel_cntrl_out => fifo_s_ch_cntrl(I mod NOCEM_NUM_COLS),
+ clk => clk,
+ rst => rst
+ );
+
+
+
+ end generate;
+
+
+ g34: if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_MESH generate
+
+
+ -- leave here just in case....
+-- channel_ns_mesh : channel_fifo PORT MAP(
+-- p0_datain => data_z,
+-- p0_pkt_cntrl_in => pkt_cntrl_z,
+-- p0_dataout => open,
+-- p0_pkt_cntrl_out => open,
+-- p0_channel_cntrl_in => ch_cntrl_z,
+-- p0_channel_cntrl_out => open,
+-- p1_datain => data_z,
+-- p1_pkt_cntrl_in => pkt_cntrl_z,
+-- p1_dataout => open,
+-- p1_pkt_cntrl_out => open,
+-- p1_channel_cntrl_in => ch_cntrl_z,
+-- p1_channel_cntrl_out => open,
+-- clk => clk,
+-- rst => rst
+-- );
+
+ end generate;
+
+
+ end generate;
+
+
+
+
+
+ -- bottom of chip
+ g4: if I / NOCEM_NUM_COLS = 0 and NOCEM_NUM_ROWS /= 1 generate
+
+
+
+ channel_ns : channel_fifo
+ generic map(
+ P0_NODE_ADDR => I,
+ P1_NODE_ADDR => I+NOCEM_NUM_COLS,
+ IS_AN_ACCESS_POINT_CHANNEL => FALSE
+ )
+ PORT MAP(
+ p0_datain => n_to_fifo_data(I),
+ p0_pkt_cntrl_in => n_to_fifo_pkt_cntrl(I),
+ p0_dataout => fifo_to_n_data(I),
+ p0_pkt_cntrl_out => fifo_to_n_pkt_cntrl(I),
+ p0_channel_cntrl_in => n_fifo_ch_cntrl(I),
+ p0_channel_cntrl_out => fifo_n_ch_cntrl(I),
+
+ p1_datain => s_to_fifo_data(I+NOCEM_NUM_COLS),
+ p1_pkt_cntrl_in => s_to_fifo_pkt_cntrl(I+NOCEM_NUM_COLS),
+ p1_dataout => fifo_to_s_data(I+NOCEM_NUM_COLS),
+ p1_pkt_cntrl_out => fifo_to_s_pkt_cntrl(I+NOCEM_NUM_COLS),
+ p1_channel_cntrl_in => s_fifo_ch_cntrl(I+NOCEM_NUM_COLS),
+ p1_channel_cntrl_out => fifo_s_ch_cntrl(I+NOCEM_NUM_COLS),
+
+ clk => clk,
+ rst => rst
+ );
+
+
+
+
+
+
+
+
+ end generate;
+
+ -- middle of chip
+ g5: if I / NOCEM_NUM_COLS /= 0 and (I+NOCEM_NUM_COLS) / NOCEM_NUM_COLS /= NOCEM_NUM_ROWS and NOCEM_NUM_ROWS /= 1 generate
+
+
+ channel_ns : channel_fifo
+ generic map(
+ P0_NODE_ADDR => I,
+ P1_NODE_ADDR => I+NOCEM_NUM_COLS,
+ IS_AN_ACCESS_POINT_CHANNEL => FALSE
+ )
+ PORT MAP(
+ p0_datain => n_to_fifo_data(I),
+ p0_pkt_cntrl_in => n_to_fifo_pkt_cntrl(I),
+ p0_dataout => fifo_to_n_data(I),
+ p0_pkt_cntrl_out => fifo_to_n_pkt_cntrl(I),
+ p0_channel_cntrl_in => n_fifo_ch_cntrl(I),
+ p0_channel_cntrl_out => fifo_n_ch_cntrl(I),
+
+ p1_datain => s_to_fifo_data(I+NOCEM_NUM_COLS),
+ p1_pkt_cntrl_in => s_to_fifo_pkt_cntrl(I+NOCEM_NUM_COLS),
+ p1_dataout => fifo_to_s_data(I+NOCEM_NUM_COLS),
+ p1_pkt_cntrl_out => fifo_to_s_pkt_cntrl(I+NOCEM_NUM_COLS),
+ p1_channel_cntrl_in => s_fifo_ch_cntrl(I+NOCEM_NUM_COLS),
+ p1_channel_cntrl_out => fifo_s_ch_cntrl(I+NOCEM_NUM_COLS),
+
+ clk => clk,
+ rst => rst
+ );
+
+
+
+
+
+
+
+ end generate;
+
+ -- single row
+ g6: if NOCEM_NUM_ROWS = 1 generate
+
+ end generate;
+
+
+
+---------------------------------------------------------------
+---------------------------------------------------------------
+------ EAST / WEST FIFOs ----
+---------------------------------------------------------------
+---------------------------------------------------------------
+
+
+ -- left side of chip
+ g7: if I mod NOCEM_NUM_COLS = 0 and NOCEM_NUM_COLS /= 1 generate
+
+
+
+
+
+
+
+
+ channel_ew : channel_fifo
+ generic map(
+ P0_NODE_ADDR => I,
+ P1_NODE_ADDR => I+1,
+ IS_AN_ACCESS_POINT_CHANNEL => FALSE
+ )
+ PORT MAP(
+ p0_datain => e_to_fifo_data(I),
+ p0_pkt_cntrl_in => e_to_fifo_pkt_cntrl(I),
+ p0_dataout => fifo_to_e_data(I),
+ p0_pkt_cntrl_out => fifo_to_e_pkt_cntrl(I),
+ p0_channel_cntrl_in => e_fifo_ch_cntrl(I),
+ p0_channel_cntrl_out => fifo_e_ch_cntrl(I),
+
+ p1_datain => w_to_fifo_data(I+1),
+ p1_pkt_cntrl_in => w_to_fifo_pkt_cntrl(I+1),
+ p1_dataout => fifo_to_w_data(I+1),
+ p1_pkt_cntrl_out => fifo_to_w_pkt_cntrl(I+1),
+ p1_channel_cntrl_in => w_fifo_ch_cntrl(I+1),
+ p1_channel_cntrl_out => fifo_w_ch_cntrl(I+1),
+
+ clk => clk,
+ rst => rst
+ );
+
+
+
+
+
+
+
+
+ end generate;
+
+
+ -- right side of chip
+ g8: if I mod NOCEM_NUM_COLS = NOCEM_NUM_COLS-1 and NOCEM_NUM_COLS /= 1 generate
+
+ -- only do this on double torus
+ g81: if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_DTORUS generate
+
+ channel_ew_dt : channel_fifo
+ generic map(
+ P0_NODE_ADDR => I,
+ P1_NODE_ADDR => I-NOCEM_NUM_COLS+1,
+ IS_AN_ACCESS_POINT_CHANNEL => FALSE
+ )
+ PORT MAP(
+ p0_datain => e_to_fifo_data(I),
+ p0_pkt_cntrl_in => e_to_fifo_pkt_cntrl(I),
+ p0_dataout => fifo_to_e_data(I),
+ p0_pkt_cntrl_out => fifo_to_e_pkt_cntrl(I),
+ p0_channel_cntrl_in => e_fifo_ch_cntrl(I),
+ p0_channel_cntrl_out => fifo_e_ch_cntrl(I),
+
+ p1_datain => w_to_fifo_data(I-NOCEM_NUM_COLS+1),
+ p1_pkt_cntrl_in => w_to_fifo_pkt_cntrl(I-NOCEM_NUM_COLS+1),
+ p1_dataout => fifo_to_w_data(I-NOCEM_NUM_COLS+1),
+ p1_pkt_cntrl_out => fifo_to_w_pkt_cntrl(I-NOCEM_NUM_COLS+1),
+ p1_channel_cntrl_in => w_fifo_ch_cntrl(I-NOCEM_NUM_COLS+1),
+ p1_channel_cntrl_out => fifo_w_ch_cntrl(I-NOCEM_NUM_COLS+1),
+
+ clk => clk,
+ rst => rst
+ );
+
+ end generate;
+
+
+ g82: if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_MESH generate
+
+-- channel_ew_mesht : channel_fifo PORT MAP(
+-- p0_datain => data_z,
+-- p0_pkt_cntrl_in => pkt_cntrl_z,
+-- p0_dataout => open,
+-- p0_pkt_cntrl_out => open,
+-- p0_channel_cntrl_in => ch_cntrl_z,
+-- p0_channel_cntrl_out => open,
+-- p1_datain => data_z,
+-- p1_pkt_cntrl_in => pkt_cntrl_z,
+-- p1_dataout => open,
+-- p1_pkt_cntrl_out => open,
+-- p1_channel_cntrl_in => ch_cntrl_z,
+-- p1_channel_cntrl_out => open,
+-- clk => clk,
+-- rst => rst
+-- );
+--
+ end generate;
+
+ end generate;
+
+
+ -- middle of chip (in terms of columns)
+ g9: if I mod NOCEM_NUM_COLS /= NOCEM_NUM_COLS-1 and I mod NOCEM_NUM_COLS /= 0 and NOCEM_NUM_COLS /= 1 generate
+
+
+ channel_ew : channel_fifo
+ generic map(
+ P0_NODE_ADDR => I,
+ P1_NODE_ADDR => I+1,
+ IS_AN_ACCESS_POINT_CHANNEL => FALSE
+ )
+
+ PORT MAP(
+ p0_datain => e_to_fifo_data(I),
+ p0_pkt_cntrl_in => e_to_fifo_pkt_cntrl(I),
+ p0_dataout => fifo_to_e_data(I),
+ p0_pkt_cntrl_out => fifo_to_e_pkt_cntrl(I),
+ p0_channel_cntrl_in => e_fifo_ch_cntrl(I),
+ p0_channel_cntrl_out => fifo_e_ch_cntrl(I),
+
+ p1_datain => w_to_fifo_data(I+1),
+ p1_pkt_cntrl_in => w_to_fifo_pkt_cntrl(I+1),
+ p1_dataout => fifo_to_w_data(I+1),
+ p1_pkt_cntrl_out => fifo_to_w_pkt_cntrl(I+1),
+ p1_channel_cntrl_in => w_fifo_ch_cntrl(I+1),
+ p1_channel_cntrl_out => fifo_w_ch_cntrl(I+1),
+
+ clk => clk,
+ rst => rst
+ );
+
+
+
+
+ end generate;
+
+
+ -- single column
+ g10: if NOCEM_NUM_COLS = 1 generate
+
+
+
+ end generate;
+
+
+
+ end generate;
+
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/arb_bus_nocem.vhd
===================================================================
--- nocem/trunk/VHDL/arb_bus_nocem.vhd (nonexistent)
+++ nocem/trunk/VHDL/arb_bus_nocem.vhd (revision 8)
@@ -0,0 +1,109 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: arb_bus_nocem.vhd
+--
+-- Description: legacy bus implementation
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+
+
+entity arb_bus_nocem is
+ Port(
+ -- arbitration lines (usage depends on underlying network)
+ arb_req : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ arb_grant : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+
+ clk : in std_logic;
+ rst : in std_logic
+ );
+
+end arb_bus_nocem;
+
+architecture Behavioral of arb_bus_nocem is
+
+signal idle : std_logic;
+signal arb_grant_i : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+begin
+
+
+--need internal signal so that I can read from arb_grant internally
+arb_grant <= arb_grant_i;
+
+
+arb_proc : process (clk,rst)
+begin
+ if rst='1' then
+ idle <= '1';
+ arb_grant_i <= (others => '0');
+ elsif clk'event and clk='1' then
+
+ -- if not granting arbitration to anyone, then bus idle
+ if arb_grant_i = 0 then
+ idle <= '1';
+ else
+ idle <= '0';
+ end if;
+
+ --grant arbitration to a single access point
+ for I in NOCEM_NUM_AP-1 downto 1 loop
+
+ if idle = '1' and arb_req(I) = '1' and arb_req(I-1 downto 0) = 0 then
+ arb_grant_i(I) <= '1';
+ else
+ arb_grant_i(I) <= '0';
+ end if;
+
+ end loop;
+
+ --base case
+ if idle = '1' and arb_req(0) = '1' then
+ arb_grant_i(0) <= '1';
+ else
+ arb_grant_i(0) <= '0';
+
+ end if;
+
+ end if;
+
+
+end process;
+
+
+end Behavioral;
Index: nocem/trunk/VHDL/vc_vc_alloc_arb.vhd
===================================================================
--- nocem/trunk/VHDL/vc_vc_alloc_arb.vhd (nonexistent)
+++ nocem/trunk/VHDL/vc_vc_alloc_arb.vhd (revision 8)
@@ -0,0 +1,76 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: vc_vc_alloc_arb.vhd
+--
+-- Description: vc allocation arbiter
+--
+
+
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:18:42 03/14/06
+-- Design Name:
+-- Module Name: vc_vc_alloc_arb - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity vc_vc_alloc_arb is
+ Port ( clk : in std_logic;
+ rst : in std_logic);
+end vc_vc_alloc_arb;
+
+architecture Behavioral of vc_vc_alloc_arb is
+
+begin
+
+
+end Behavioral;
Index: nocem/trunk/bridge/noc2proc_bridge2.vhd
===================================================================
--- nocem/trunk/bridge/noc2proc_bridge2.vhd (nonexistent)
+++ nocem/trunk/bridge/noc2proc_bridge2.vhd (revision 8)
@@ -0,0 +1,1602 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: noc2proc_bridge2.vhd
+--
+-- Description: the bridge for proc2noc communication
+--
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_textio.all;
+
+
+use work.pkg_nocem.all;
+--use work.pkg_snocem.all;
+
+library std;
+use std.textio.all;
+
+
+entity noc2proc_bridge2 is
+ generic
+ (
+
+ -- DO NOT EDIT BELOW THIS LINE ---------------------
+ -- Bus protocol parameters, do not add to or delete
+ C_AWIDTH : integer := 32;
+ C_DWIDTH : integer := 64;
+ C_NUM_CS : integer := 1;
+ C_NUM_CE : integer := 2;
+ C_IP_INTR_NUM : integer := 1
+ -- DO NOT EDIT ABOVE THIS LINE ---------------------
+ );
+ port
+ (
+ -- ADD USER PORTS BELOW THIS LINE ------------------
+
+
+ noc_arb_req : out std_logic;
+ noc_arb_cntrl_out : out arb_cntrl_word;
+
+ noc_arb_grant : in std_logic;
+ noc_arb_cntrl_in : in arb_cntrl_word;
+
+ noc_datain : in std_logic_vector(NOCEM_DW-1 downto 0);
+ noc_datain_valid : in std_logic;
+ noc_datain_recvd : out std_logic;
+
+ noc_dataout : out std_logic_vector(NOCEM_DW-1 downto 0);
+ noc_dataout_valid : out std_logic;
+ noc_dataout_recvd : in std_logic;
+
+ noc_pkt_cntrl_in : in pkt_cntrl_word;
+ noc_pkt_cntrl_in_valid : in std_logic;
+ noc_pkt_cntrl_in_recvd : out std_logic;
+
+ noc_pkt_cntrl_out : out pkt_cntrl_word;
+ noc_pkt_cntrl_out_valid : out std_logic;
+ noc_pkt_cntrl_out_recvd : in std_logic;
+
+
+
+
+
+ -- ADD USER PORTS ABOVE THIS LINE ------------------
+
+ -- DO NOT EDIT BELOW THIS LINE ---------------------
+ -- Bus protocol ports, do not add to or delete
+ Bus2IP_Clk : in std_logic;
+ Bus2IP_Reset : in std_logic;
+ IP2Bus_IntrEvent : out std_logic_vector(0 to C_IP_INTR_NUM-1);
+ Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
+ Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
+ Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
+ Bus2IP_Burst : in std_logic;
+ Bus2IP_CS : in std_logic_vector(0 to C_NUM_CS-1);
+ Bus2IP_CE : in std_logic_vector(0 to C_NUM_CE-1);
+ Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
+ Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
+ Bus2IP_RdReq : in std_logic;
+ Bus2IP_WrReq : in std_logic;
+ IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
+ IP2Bus_Retry : out std_logic;
+ IP2Bus_Error : out std_logic;
+ IP2Bus_ToutSup : out std_logic;
+ IP2Bus_RdAck : out std_logic;
+ IP2Bus_WrAck : out std_logic
+ -- DO NOT EDIT ABOVE THIS LINE ---------------------
+ );
+end noc2proc_bridge2;
+
+architecture Behavioral of noc2proc_bridge2 is
+
+ COMPONENT packetbuffer2
+ generic(
+ METADATA_WIDTH : integer;
+ METADATA_LENGTH : integer
+ );
+ Port (
+ din : IN std_logic_VECTOR(31 downto 0);
+ rd_en : IN std_logic;
+ wr_en : IN std_logic;
+ dout : OUT std_logic_VECTOR(31 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic;
+ pkt_metadata_din : in std_logic_vector(METADATA_WIDTH-1 downto 0);
+ pkt_metadata_re : IN std_logic;
+ pkt_metadata_we : IN std_logic;
+ pkt_metadata_dout : out std_logic_vector(METADATA_WIDTH-1 downto 0);
+ clk : in std_logic;
+ rst : in std_logic);
+ END COMPONENT;
+
+
+
+ ------------------ GLOBAL SIGNALS ----------------------------------
+ signal clk,rst : std_logic;
+ signal arb_sending_word,arb_receiving_word : arb_cntrl_word;
+ signal allones_vcwidth : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+
+
+ ------------------ PB 2 NoC Signals ----------------------------------
+ signal pb2noc_word1,pb2noc_word2,pb2noc_word3,pb2noc_word4 : std_logic_vector(31 downto 0);
+ signal outgoing_next_free_vc : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal outgoing_vc_state : std_logic_Vector(NOCEM_NUM_VC-1 downto 0); -- 0: free, 1: allocated --
+ signal pb2noc_vc_alloc : std_logic;
+ signal outgoing_free_this_vc : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal vc_mux_wr_reg : std_logic_vector(NOCEM_VC_ID_WIDTH-1 downto 0);
+ signal pb2noc_byte_counter : std_logic_vector(7 downto 0);
+ signal pb2noc_pkt_dest_addr : std_logic_vector(NOCEM_AW-1 downto 0);
+ signal pb2noc_pkt_len : std_logic_vector(7 downto 0);
+
+ signal pb2noc_amI_os : std_logic;
+
+ type pb2noc_st is (init_st,getting_vc_st,sending_word1_st,sending_word2_st,sending_word3_st,sending_word4_st) ;
+ signal pb2noc_state,pb2noc_nextState : pb2noc_st;
+
+ ------------------ PB 2 Processor Signals ----------------------------
+ signal pb2proc_interrupt : std_logic_vector(0 to C_IP_INTR_NUM-1);
+ signal pb2proc_byte_counter : std_logic_vector(7 downto 0);
+ signal pb2proc_dest_addr_i : std_logic_vector(NOCEM_AW-1 downto 0);
+ signal pb2proc_pkt_len_i : std_logic_vector(7 downto 0);
+ signal pb2proc_len_addr_aggr : std_logic_vector(0 to C_DWIDTH-1);
+
+
+
+ type pb2proc_st is (IDLE_ST, SENDING_META_ST,SENDING_ST) ;
+ signal pb2proc_state,pb2proc_nextState : pb2proc_st;
+
+
+ ------------------ NoC 2 PB Signals ----------------------------------
+ signal noc2pb_next_vc_with_pkt,noc2pb_finished_pkt,noc2pb_eop_wr_sig,noc2pb_pkt_rdy : std_logic_vector(NOCEM_NUM_VC-1 downto 0);
+ signal noc2pb_recv_idle : std_logic;
+ signal noc2pb_din_pad : std_logic_vector(31 downto 0);
+ signal noc2pb_din_reg : std_logic_vector(31 downto 0);
+ signal noc2pb_byte_counter : std_logic_vector(7 downto 0);
+ signal noc2pb_we_delay, noc2pb_mwe_delay : std_logic;
+ signal noc2pb_we_b1,noc2pb_we_b2,noc2pb_we_b3,noc2pb_we_b4 : std_logic;
+ signal noc2pb_din_rotated : std_logic_vector(31 downto 0);
+
+
+ type noc2pb_st is (init_st,recving_word1_st,recving_word2_st,recving_word3_st,recving_word4_st) ;
+ signal noc2pb_state,noc2pb_nextState : noc2pb_st;
+
+
+
+
+
+ ------------------ Processor 2 PB Signals ----------------------------
+ signal proc2pb_dest_addr_i : std_logic_vector(NOCEM_AW-1 downto 0);
+ signal proc2pb_pkt_len_i : std_logic_vector(7 downto 0);
+ signal proc2pb_byte_counter : std_logic_vector(7 downto 0);
+
+ type proc2pb_st is (IDLE_ST, SENDING_ST) ;
+ signal proc2pb_state,proc2pb_nextState : proc2pb_st;
+
+
+ ------------------ PKT BUFFER SIGNALS ----------------------------------
+ constant METADATA_WIDTH : integer := NOCEM_AW+8 ;
+ constant METADATA_LENGTH : integer := 16 ;
+
+
+ signal din_n2p,dout_n2p : std_logic_vector(31 downto 0);
+ signal re_n2p,we_n2p,empty_n2p,full_n2p,mre_n2p,mwe_n2p : std_logic;
+ signal mdin_n2p,mdout_n2p : std_logic_vector(METADATA_WIDTH-1 downto 0);
+
+
+ signal din_p2n,dout_p2n : std_logic_vector(31 downto 0);
+ signal re_p2n,we_p2n,empty_p2n,full_p2n,mre_p2n,mwe_p2n : std_logic;
+ signal mdin_p2n,mdout_p2n : std_logic_vector(METADATA_WIDTH-1 downto 0);
+ -------------------------------------------------------------------------
+
+
+
+
+ ------------------------ DEBUG SIGNALLING
+ signal debug_p2n_addr1,debug_p2n_addr2 : std_logic_vector (0 to 11);
+ signal debug_p2n_boolean_test1,debug_p2n_boolean_test2,debug_p2n_boolean_test3 : std_logic;
+ signal tl_debug : std_logic_vector(4 downto 0);
+
+
+begin
+
+---------------------------------------------------------------------
+--------------------- GLOBAL RENAMING, ETC --------------------------
+---------------------------------------------------------------------
+
+clk <= Bus2IP_Clk;
+rst <= Bus2IP_Reset;
+noc_arb_cntrl_out <= arb_sending_word or arb_receiving_word;
+
+IP2Bus_Error <= '0';
+IP2Bus_Retry <= '0';
+IP2Bus_ToutSup <= '0';
+
+
+
+
+
+---------------------------------------------------------------------
+------------ PROCESSSOR TO PKT BUFFER PROCESSES ---------------------
+---------------------------------------------------------------------
+
+
+----------------------------------------------------------------------------
+-- Processor to noc packet flow
+
+-- the Processor wants to write a packet to the NoC. It must first write and address
+-- into the noc_addr_reg and packet length and then begin writing the packet.
+-- This is accomplished by using the following register locations:
+--
+-- C_BASE_ADDR + 0x000: NOC_ADDR_REG,NOC_PACKET_LENGTH
+-- C_BASE_ADDR + 0x004: IP2NOC_PACKET_DATA
+-- ...
+-- ...
+-- the PPC will write to successive locations (in burst mode) so once a write starts
+-- this process will just accept the successive writes and hand it off to the NoC
+----------------------------------------------------------------------------
+
+
+
+proc2pb_clkd : process (clk,rst)
+
+variable L : line;
+
+begin
+ if rst='1' then
+ proc2pb_dest_addr_i <= (others => '0');
+ proc2pb_pkt_len_i <= (others => '0');
+ proc2pb_byte_counter <= (others => '0');
+ proc2pb_state <= IDLE_ST;
+
+ elsif clk='1' and clk'event then
+ proc2pb_state <= proc2pb_nextState;
+ case proc2pb_state is
+ when IDLE_ST =>
+
+
+ -----------------------------------------------------------
+ -- THIS IS FOR TASKLIST EXERCISER WORK --
+ -----------------------------------------------------------
+ --224 0E0 11100000 SIMULATION ONLY an entire tasklist has begun being allocated
+ --228 0E4 11100100 SIMULATION ONLY an entire tasklist has finished -- all CE's are deallocated
+ --232 0E8 11101000 SIMULATION ONLY an allocation attempt has been successful
+ --236 0EC 11101100 SIMULATION ONLY an allocation attempt has NOT been successful
+ --240 0F0 11110000 SIMULATION ONLY a deallocation occurred
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0E0" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" tasklist started: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+
+-- tl_debug(4) <= '1';
+--
+-- IP2Bus_WrAck <= '1';
+-- proc2pb_nextState <= IDLE_ST;
+ end if;
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0E4" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" tasklist ended: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+
+-- tl_debug(3) <= '1';
+--
+-- IP2Bus_WrAck <= '1';
+-- proc2pb_nextState <= IDLE_ST;
+ end if;
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0E8" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" task allocated SUCCESS: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+
+-- tl_debug(2) <= '1';
+--
+-- IP2Bus_WrAck <= '1';
+-- proc2pb_nextState <= IDLE_ST;
+ end if;
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0EC" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" task alloacted FAILURE: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+
+-- tl_debug(1) <= '1';
+--
+-- IP2Bus_WrAck <= '1';
+-- proc2pb_nextState <= IDLE_ST;
+--
+ end if;
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0F0" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" CE Deallocated: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+---- writeline(OUTPUT, L);
+--
+-- write(L, string'(" "));
+-- writeline(OUTPUT, L);
+
+-- tl_debug(0) <= '1';
+--
+-- IP2Bus_WrAck <= '1';
+-- proc2pb_nextState <= IDLE_ST;
+--
+ end if;
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0F4" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" BAD SYSCALL PACKET: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+
+-- --tl_debug(0) <= '1';
+--
+-- IP2Bus_WrAck <= '1';
+-- proc2pb_nextState <= IDLE_ST;
+--
+ end if;
+
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0D8" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" STATISTICS COLLECTED: "));
+-- write(L, string'(" with runtime: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+
+-- --tl_debug(0) <= '1';
+--
+-- IP2Bus_WrAck <= '1';
+-- proc2pb_nextState <= IDLE_ST;
+--
+ end if;
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0DC" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" STATISTICS COLLECTED: "));
+-- write(L, string'(" with packets sent: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+
+-- --tl_debug(0) <= '1';
+--
+-- IP2Bus_WrAck <= '1';
+-- proc2pb_nextState <= IDLE_ST;
+--
+ end if;
+
+
+ -----------------------------------------------------------
+ -- END TASKLIST EXERCISER WORK --
+ -----------------------------------------------------------
+
+
+
+
+
+
+
+
+
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"000" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+ proc2pb_dest_addr_i <= Bus2IP_Data(32-NOCEM_AW to 31);
+ proc2pb_pkt_len_i <= Bus2IP_Data(16 to 23);
+ else
+ proc2pb_dest_addr_i <= (others => '0');
+ proc2pb_pkt_len_i <= (others => '0');
+ proc2pb_byte_counter <= (others => '0');
+ end if;
+
+ when SENDING_ST =>
+
+
+ -- to send data, must have data coming from PLB and also ready on Noc side
+ if full_p2n = '0' and
+ Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) >= X"004" and
+ Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) < X"080" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+ -- may have to decode BE signal coming in
+ proc2pb_byte_counter <= proc2pb_byte_counter+4;
+ else
+ null;
+ end if;
+
+ when others =>
+ null;
+ end case;
+
+ end if;
+
+
+end process;
+
+
+
+proc2pb_uclkd : process (full_p2n,proc2pb_dest_addr_i,Bus2IP_Data, Bus2IP_BE,proc2pb_state, Bus2IP_Addr, Bus2IP_WrReq, Bus2IP_CS, Bus2IP_CE, proc2pb_byte_counter, proc2pb_pkt_len_i)
+
+
+begin
+
+
+ proc2pb_nextState <= IDLE_ST;
+-- proc2pb_packet <= (others => '0');
+ --proc2pb_packet_we <= '0';
+
+ IP2Bus_WrAck <= '0';
+
+ din_p2n <= (others => '0');
+ mdin_p2n <= (others => '0');
+ we_p2n <= '0';
+ mwe_p2n <= '0';
+
+ tl_debug <= (others => '0');
+
+ case proc2pb_state is
+ when IDLE_ST =>
+
+
+ -----------------------------------------------------------
+ -- THIS IS FOR TASKLIST EXERCISER WORK --
+ -----------------------------------------------------------
+ --224 0E0 11100000 SIMULATION ONLY an entire tasklist has begun being allocated
+ --228 0E4 11100100 SIMULATION ONLY an entire tasklist has finished -- all CE's are deallocated
+ --232 0E8 11101000 SIMULATION ONLY an allocation attempt has been successful
+ --236 0EC 11101100 SIMULATION ONLY an allocation attempt has NOT been successful
+ --240 0F0 11110000 SIMULATION ONLY a deallocation occurred
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0E0" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" tasklist started: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+--
+ tl_debug(4) <= '1';
+
+ IP2Bus_WrAck <= '1';
+ proc2pb_nextState <= IDLE_ST;
+ end if;
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0E4" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" tasklist ended: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+--
+ tl_debug(3) <= '1';
+
+ IP2Bus_WrAck <= '1';
+ proc2pb_nextState <= IDLE_ST;
+ end if;
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0E8" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" task allocated SUCCESS: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+--
+ tl_debug(2) <= '1';
+
+ IP2Bus_WrAck <= '1';
+ proc2pb_nextState <= IDLE_ST;
+ end if;
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0EC" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" task alloacted FAILURE: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+--
+ tl_debug(1) <= '1';
+
+ IP2Bus_WrAck <= '1';
+ proc2pb_nextState <= IDLE_ST;
+
+ end if;
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0F0" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" CE Deallocated: "));
+-- write(L, string'(" with OS Data: "));
+-- hhwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+--
+ tl_debug(0) <= '1';
+
+ IP2Bus_WrAck <= '1';
+ proc2pb_nextState <= IDLE_ST;
+
+ end if;
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"0F4" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+-- write(L, string'("OS checkpoint: "));
+-- write(L,time'image(NOW));
+-- write(L, string'(" BAD SYSCALL PACKET: "));
+-- write(L, string'(" with OS Data: "));
+-- hwrite(L, Bus2IP_data);
+-- writeline(OUTPUT, L);
+
+ --tl_debug(0) <= '1';
+
+ IP2Bus_WrAck <= '1';
+ proc2pb_nextState <= IDLE_ST;
+
+ end if;
+
+
+ -----------------------------------------------------------
+ -- END TASKLIST EXERCISER WORK --
+ -----------------------------------------------------------
+
+
+
+
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"000" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+ IP2Bus_WrAck <= '1';
+ proc2pb_nextState <= SENDING_ST;
+
+ else
+ proc2pb_nextState <= IDLE_ST;
+ end if;
+
+ when SENDING_ST =>
+
+ if full_p2n = '0' and
+ Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) >= X"004" and
+ Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) < X"080" and
+ Bus2IP_WrReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+ din_p2n <= Bus2IP_data(0 to 31);
+ we_p2n <= '1';
+ IP2Bus_WrAck <= '1';
+ end if;
+
+
+
+ mdin_p2n(NOCEM_AW-1 downto 0) <= proc2pb_dest_addr_i;
+ mdin_p2n(NOCEM_AW+7 downto NOCEM_AW) <= proc2pb_pkt_len_i;
+ -- when am done sending packet
+ if proc2pb_byte_counter >= proc2pb_pkt_len_i then
+ proc2pb_nextState <= IDLE_ST;
+ mwe_p2n <= '1';
+ else
+ proc2pb_nextState <= SENDING_ST;
+ end if;
+ when others =>
+ null;
+ end case;
+
+end process;
+
+
+
+
+
+
+
+
+
+---------------------------------------------------------------------
+------------ PKT BUFFER TO PROCESSOR PROCESSES -----------------
+---------------------------------------------------------------------
+
+
+----------------------------------------------------------------------------
+-- PKT BUFFER to Processor packet flow
+--
+-- the noc has pb2proc_interrupted the processor and now is being requested to send a packet
+-- up to the Processor for handling. This is accomplished by the processor reading from
+-- the memory locations that are specifically used for this.
+--
+-- C_BASE_ADDR + 0x080: NOC_ADDR_REG,NOC_PACKET_LENGTH
+-- C_BASE_ADDR + 0x084: NOC2IP_PACKET_DATA
+-- ...
+-- ...
+-- The PPC will read the addr and length values and then do reads of the packet. The
+-- packet will eventually be consumed directly or buffered elsewhere. The Processor cannot
+-- will not attempt to read the packet twice from this bridge as it is not supported ;)
+--
+----------------------------------------------------------------------------
+
+
+----------------------------------------------------------------------------
+-- when a packet arrives, pb2proc_interrupt the processor and let the processor
+-- do normal plb reads to get the packet into a packetbuffer for processing
+--
+-- need to make sure the packet is read and copied somewhere, as this block
+-- is not going to handle holding the packet and manage random access to contents
+----------------------------------------------------------------------------
+
+
+
+
+pb2proc_clkd : process (clk,rst)
+begin
+
+ if rst='1' then
+
+ pb2proc_byte_counter <= (others => '0');
+ pb2proc_state <= IDLE_ST;
+
+ elsif clk='1' and clk'event then
+ pb2proc_state <= pb2proc_nextState;
+ case pb2proc_state is
+ when IDLE_ST =>
+ pb2proc_byte_counter <= (others => '0');
+ when SENDING_META_ST =>
+ pb2proc_byte_counter <= (others => '0');
+ when SENDING_ST =>
+
+ -- increment this counter as 4B get read each time
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) >= X"084" and
+ Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) < X"100" and
+ Bus2IP_RdReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+ pb2proc_byte_counter <= pb2proc_byte_counter+4;
+ end if;
+ when others => null;
+ end case;
+ end if;
+
+
+end process;
+
+
+
+
+
+
+
+
+pb2proc_uclkd : process (mdout_n2p,pb2proc_interrupt, pb2proc_state, empty_n2p, Bus2IP_Addr, Bus2IP_RdReq, Bus2IP_CS, Bus2IP_CE, dout_n2p, pb2proc_byte_counter)
+begin
+
+ -- currently, straight translation from NoC inputs (addr,len)
+ pb2proc_dest_addr_i <= mdout_n2p(NOCEM_AW-1 downto 0);
+ pb2proc_pkt_len_i <= mdout_n2p(NOCEM_AW+7 downto NOCEM_AW);
+
+
+ -- aggregate the length and addr into one 64b word for the PLB to read
+ pb2proc_len_addr_aggr <= (others => '0');
+ pb2proc_len_addr_aggr(16 to 23) <= pb2proc_pkt_len_i;
+ --pb2proc_len_addr_aggr(47 downto 40) <= pb2proc_pkt_len_i;
+ --pb2proc_len_addr_aggr(NOCEM_AW+7 downto 8) <= pb2proc_dest_addr_i;
+
+
+ -- zero out outgoing signals
+ IP2Bus_RdAck <= '0';
+ IP2Bus_Data <= (others => '0');
+ IP2Bus_IntrEvent <= pb2proc_interrupt;
+
+ re_n2p <= '0';
+ mre_n2p <= '0';
+ pb2proc_interrupt <= (others => '0');
+
+
+ case pb2proc_state is
+ when IDLE_ST =>
+
+ --------------------------------------
+ ------POLLING BASED DESIGN------------
+ --------------------------------------
+ pb2proc_nextState <= SENDING_META_ST;
+
+ --------------------------------------
+ ------INTERRUPT BASED DESIGN----------
+ --------------------------------------
+-- if empty_n2p = '0' then
+-- pb2proc_interrupt <= (others => '1');
+-- pb2proc_nextState <= SENDING_META_ST;
+-- else
+-- pb2proc_nextState <= IDLE_ST;
+-- pb2proc_interrupt <= (others => '0');
+-- end if;
+--
+
+
+
+
+
+
+
+
+
+ when SENDING_META_ST =>
+
+ -- the processor has been pb2proc_interrupted and now is requesting len,addr register
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"080" and
+ Bus2IP_RdReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+
+ --------------------------------------
+ ------INTERRUPT BASED DESIGN----------
+ --------------------------------------
+-- IP2Bus_RdAck <= '1';
+-- IP2Bus_Data <= pb2proc_len_addr_aggr;
+-- pb2proc_nextState <= SENDING_ST;
+--
+ --------------------------------------
+ ------POLLING BASED DESIGN------------
+ --------------------------------------
+ if empty_n2p = '0' then
+ IP2Bus_RdAck <= '1';
+ IP2Bus_Data <= pb2proc_len_addr_aggr;
+ pb2proc_nextState <= SENDING_ST;
+ else
+ IP2Bus_RdAck <= '1';
+ IP2Bus_Data <= (others => '0');
+ pb2proc_nextState <= SENDING_META_ST;
+ end if;
+ else
+ pb2proc_nextState <= SENDING_META_ST;
+ end if;
+
+
+ -----------------------------------------------------------
+ -- THIS IS SOME DEBUG CODE TO CHECK NOCEM --
+ -----------------------------------------------------------
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"088" and
+ Bus2IP_RdReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+ IP2Bus_RdAck <= '1';
+ IP2Bus_Data <= X"DEADBEEF";
+ pb2proc_nextState <= SENDING_META_ST;
+
+ end if;
+
+
+
+ -----------------------------------------------------------
+ -- THIS IS SOME DEBUG CODE TO CHECK NOCEM --
+ -----------------------------------------------------------
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) = X"088" and
+ Bus2IP_RdReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+
+ IP2Bus_RdAck <= '1';
+ IP2Bus_Data <= X"DEADBEEF";
+ pb2proc_nextState <= SENDING_META_ST;
+
+ end if;
+
+
+
+
+
+
+
+
+
+
+ when SENDING_ST =>
+
+ -- the processor should be now requesting the packet
+ if Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) >= X"084" and
+ Bus2IP_Addr(C_AWIDTH-12 to C_AWIDTH-1) < X"100" and
+ Bus2IP_RdReq = '1' and
+ Bus2IP_CS /= 0 and
+ Bus2IP_CE /= 0 then
+ IP2Bus_RdAck <= '1';
+ IP2Bus_Data(0 to 31) <= dout_n2p;
+ re_n2p <= '1';
+
+ end if;
+
+ -- data is read in 4B words, so possible to go over packet length
+ -- will be handled in software
+ if pb2proc_byte_counter >= pb2proc_pkt_len_i then
+ pb2proc_nextState <= IDLE_ST;
+ --re_n2p <= '1';
+ mre_n2p <= '1';
+ else
+ pb2proc_nextState <= SENDING_ST;
+ end if;
+
+
+ when others =>
+ null;
+ end case;
+
+end process;
+
+
+
+
+
+---------------------------------------------------------------------
+------------ NOCEM TO PKT BUFFER PROCESSES ---------------------
+---------------------------------------------------------------------
+
+
+-- type noc2pb_st is (init_st,recving_word1_st,recving_word2_st,recving_word3_st,recving_word4_st) ;
+-- signal noc2pb_state,noc2pb_nextState : noc2pb_st;
+
+
+noc2pb_clkd : process (clk,rst)
+begin
+
+
+ if rst='1' then
+ noc2pb_pkt_rdy <= (others => '0');
+ noc2pb_next_vc_with_pkt <= (others => '0');
+ noc2pb_recv_idle <= '1';
+ noc2pb_state <= init_st;
+ noc2pb_byte_counter <= (others => '0');
+ noc2pb_mwe_delay <= '0';
+ noc2pb_we_delay <= '0';
+ noc2pb_din_reg <= (others => '0');
+ elsif clk'event and clk='1' then
+
+ -- doing some width conversion we's here.
+ if noc2pb_we_b1='1' then
+ noc2pb_din_reg(7 downto 0) <= noc2pb_din_rotated(7 downto 0);
+ end if;
+ if noc2pb_we_b2='1' then
+ noc2pb_din_reg(15 downto 8) <= noc2pb_din_rotated(15 downto 8);
+
+ end if;
+ if noc2pb_we_b3='1' then
+ noc2pb_din_reg(23 downto 16) <= noc2pb_din_rotated(23 downto 16);
+
+ end if;
+ if noc2pb_we_b4='1' then
+ noc2pb_din_reg(31 downto 24) <= noc2pb_din_rotated(31 downto 24);
+ noc2pb_we_delay <= '1';
+ end if;
+
+ -- need to force a we to the pkt buffer when the EOP is seen from NoC
+ if (noc2pb_we_b1='1' or noc2pb_we_b2='1' or noc2pb_we_b3='1' or noc2pb_we_b4='1') and noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+
+ noc2pb_mwe_delay <= '1';
+ noc2pb_we_delay <= '1';
+ elsif noc2pb_we_b4='1' then
+ noc2pb_we_delay <= '1';
+ noc2pb_mwe_delay <= '0';
+ else
+ noc2pb_mwe_delay <= '0';
+ noc2pb_we_delay <= '0';
+
+ end if;
+
+
+
+
+
+ noc2pb_state <= noc2pb_nextState;
+ case noc2pb_state is
+ when init_st =>
+ noc2pb_byte_counter <= (others => '0');
+ noc2pb_din_reg <= (others => '0');
+ when recving_word1_st =>
+ noc2pb_byte_counter <= noc2pb_byte_counter + NOCEM_DW/8;
+ when recving_word2_st =>
+ noc2pb_byte_counter <= noc2pb_byte_counter + NOCEM_DW/8;
+ when recving_word3_st =>
+ noc2pb_byte_counter <= noc2pb_byte_counter + NOCEM_DW/8;
+ when recving_word4_st =>
+ noc2pb_byte_counter <= noc2pb_byte_counter + NOCEM_DW/8;
+ when others => null;
+ end case;
+
+
+
+ -------------------------------------------------------------------------------------
+ ---------------------------- FINDING NEXT VC WITH A PACKET --------------------------
+ -------------------------------------------------------------------------------------
+ l1: for I in NOCEM_NUM_VC-1 downto 0 loop
+
+ -- is the pkt rdy for reading?
+ if noc2pb_eop_wr_sig(I) = '1' then
+ noc2pb_pkt_rdy(I) <= '1';
+ elsif noc2pb_finished_pkt(I) = '1' then
+ noc2pb_pkt_rdy(I) <= '0';
+ end if;
+
+ -- what is the next pkt to read from VCs?
+ if noc2pb_pkt_rdy(I) = '1' and noc2pb_recv_idle = '1' then
+ noc2pb_next_vc_with_pkt <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_VC);
+ noc2pb_recv_idle <= '0';
+ elsif noc2pb_finished_pkt /= 0 then
+ noc2pb_recv_idle <= '1';
+ end if;
+
+ end loop;
+
+ -- if no packets OR just finished a packet's handling, show that no packet is ready
+ if noc2pb_pkt_rdy = 0 or noc2pb_finished_pkt /= 0 then
+ noc2pb_next_vc_with_pkt <= (others => '0');
+ end if;
+ -------------------------------------------------------------------------------------
+
+ end if;
+
+
+end process;
+
+noc2pb_uclkd : process (noc2pb_din_pad,noc2pb_next_vc_with_pkt,noc_arb_cntrl_in, noc_pkt_cntrl_in,noc2pb_mwe_delay, noc2pb_we_delay, noc2pb_din_reg, noc2pb_byte_counter, noc_datain, noc2pb_state, full_n2p)
+begin
+
+
+
+ mwe_n2p <= noc2pb_mwe_delay;
+ we_n2p <= noc2pb_we_delay;
+
+ -- a quick network to processor byte endian change
+ din_n2p(7 downto 0) <= noc2pb_din_reg(31 downto 24);
+ din_n2p(15 downto 8) <= noc2pb_din_reg(23 downto 16);
+ din_n2p(23 downto 16) <= noc2pb_din_reg(15 downto 8);
+ din_n2p(31 downto 24) <= noc2pb_din_reg(7 downto 0);
+
+ mdin_n2p <= noc2pb_byte_counter & CONV_STD_LOGIC_VECTOR(0,NOCEM_AW);
+
+ noc_datain_recvd <= '0';
+ noc_pkt_cntrl_in_recvd <= '0';
+ noc2pb_finished_pkt <= (others => '0');
+ arb_receiving_word <= (others => '0');
+ noc2pb_eop_wr_sig <= noc_arb_cntrl_in(NOCEM_ARB_CNTRL_VC_EOP_WR_HIX downto NOCEM_ARB_CNTRL_VC_EOP_WR_LIX);
+
+ -- setting up the padded register for width conversion
+ noc2pb_din_pad <= (others => '0');
+ noc2pb_din_pad(NOCEM_DW-1 downto 0) <= noc_datain;
+ noc2pb_din_rotated <= (others => '0');
+
+ noc2pb_we_b1 <= '0';
+ noc2pb_we_b2 <= '0';
+ noc2pb_we_b3 <= '0';
+ noc2pb_we_b4 <= '0';
+
+
+
+
+ case noc2pb_state is
+ when init_st =>
+ if noc2pb_next_vc_with_pkt /= 0 and full_n2p = '0' then
+ noc2pb_nextState <= recving_word1_st;
+ else
+ noc2pb_nextState <= init_st;
+ end if;
+
+ when recving_word1_st =>
+
+
+
+ arb_receiving_word(NOCEM_ARB_CNTRL_VC_MUX_RD_HIX downto NOCEM_ARB_CNTRL_VC_MUX_RD_LIX) <= noc2pb_next_vc_with_pkt;
+ noc_datain_recvd <= '1';
+ noc_pkt_cntrl_in_recvd <= '1';
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_finished_pkt <= noc2pb_next_vc_with_pkt;
+ end if;
+
+
+
+ -- setup the width conversion correctly....
+ noc2pb_din_rotated(NOCEM_DW-1 downto 0) <= noc2pb_din_pad(NOCEM_DW-1 downto 0);
+ if NOCEM_DW = 32 then
+ noc2pb_we_b1 <= '1';
+ noc2pb_we_b2 <= '1';
+ noc2pb_we_b3 <= '1';
+ noc2pb_we_b4 <= '1';
+
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_nextState <= init_st;
+ else
+ noc2pb_nextState <= recving_word1_st;
+ end if;
+ elsif NOCEM_DW = 16 then
+ noc2pb_we_b1 <= '1';
+ noc2pb_we_b2 <= '1';
+
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_nextState <= init_st;
+ else
+ noc2pb_nextState <= recving_word2_st;
+ end if;
+
+ elsif NOCEM_DW = 8 then
+ noc2pb_we_b1 <= '1';
+
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_nextState <= init_st;
+ else
+ noc2pb_nextState <= recving_word2_st;
+ end if;
+
+
+ end if;
+
+
+ when recving_word2_st =>
+
+ arb_receiving_word(NOCEM_ARB_CNTRL_VC_MUX_RD_HIX downto NOCEM_ARB_CNTRL_VC_MUX_RD_LIX) <= noc2pb_next_vc_with_pkt;
+ noc_datain_recvd <= '1';
+ noc_pkt_cntrl_in_recvd <= '1';
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_finished_pkt <= noc2pb_next_vc_with_pkt;
+ end if;
+
+
+
+
+
+ -- setup the width conversion correctly....
+ if NOCEM_DW = 16 then
+ noc2pb_din_rotated(31 downto 16) <= noc2pb_din_pad(15 downto 0);
+ noc2pb_we_b3 <= '1';
+ noc2pb_we_b4 <= '1';
+
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_nextState <= init_st;
+ else
+ noc2pb_nextState <= recving_word1_st;
+ end if;
+
+ elsif NOCEM_DW = 8 then
+ noc2pb_din_rotated(15 downto 8) <= noc2pb_din_pad(7 downto 0);
+ noc2pb_we_b2 <= '1';
+
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_nextState <= init_st;
+ else
+ noc2pb_nextState <= recving_word3_st;
+ end if;
+
+ end if;
+
+
+
+ when recving_word3_st =>
+
+
+ arb_receiving_word(NOCEM_ARB_CNTRL_VC_MUX_RD_HIX downto NOCEM_ARB_CNTRL_VC_MUX_RD_LIX) <= noc2pb_next_vc_with_pkt;
+ noc_datain_recvd <= '1';
+ noc_pkt_cntrl_in_recvd <= '1';
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_finished_pkt <= noc2pb_next_vc_with_pkt;
+ end if;
+
+ -- setup the width conversion correctly....
+ noc2pb_din_rotated(23 downto 16) <= noc2pb_din_pad(7 downto 0);
+ noc2pb_we_b3 <= '1';
+
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_nextState <= init_st;
+ else
+ noc2pb_nextState <= recving_word4_st;
+ end if;
+
+ when recving_word4_st =>
+
+ arb_receiving_word(NOCEM_ARB_CNTRL_VC_MUX_RD_HIX downto NOCEM_ARB_CNTRL_VC_MUX_RD_LIX) <= noc2pb_next_vc_with_pkt;
+ noc_datain_recvd <= '1';
+ noc_pkt_cntrl_in_recvd <= '1';
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_finished_pkt <= noc2pb_next_vc_with_pkt;
+ end if;
+
+ -- setup the width conversion correctly....
+ noc2pb_din_rotated(31 downto 24) <= noc2pb_din_pad(7 downto 0);
+ noc2pb_we_b4 <= '1';
+
+ if noc_pkt_cntrl_in(NOCEM_PKTCNTRL_EOP_IX) = '1' then
+ noc2pb_nextState <= init_st;
+ else
+ noc2pb_nextState <= recving_word1_st;
+ end if;
+
+ when others => null;
+ end case;
+
+
+
+
+
+
+
+
+
+end process;
+
+
+---------------------------------------------------------------------
+------------ PKT BUFFER TO NOCEM PROCESSES ---------------------
+---------------------------------------------------------------------
+
+
+g_dw32: if NOCEM_DW = 32 generate
+
+ pb2noc_word1 <= dout_p2n;
+ pb2noc_word2 <= (others => '0');
+ pb2noc_word3 <= (others => '0');
+ pb2noc_word4 <= (others => '0');
+
+end generate;
+
+g_dw16: if NOCEM_DW = 16 generate
+
+ pb2noc_word1(31 downto 16) <= (others => '0');
+ pb2noc_word2(31 downto 16) <= (others => '0');
+ pb2noc_word1(15 downto 0) <= dout_p2n(31 downto 16);
+ pb2noc_word2(15 downto 0) <= dout_p2n(15 downto 0);
+ pb2noc_word3(15 downto 0) <= (others => '0');
+ pb2noc_word4(15 downto 0) <= (others => '0');
+
+end generate;
+
+g_dw8: if NOCEM_DW = 8 generate
+
+ pb2noc_word1(31 downto 8) <= (others => '0');
+ pb2noc_word2(31 downto 8) <= (others => '0');
+ pb2noc_word3(31 downto 8) <= (others => '0');
+ pb2noc_word4(31 downto 8) <= (others => '0');
+
+ pb2noc_word1(7 downto 0) <= dout_p2n(31 downto 24);
+ pb2noc_word2(7 downto 0) <= dout_p2n(23 downto 16);
+ pb2noc_word3(7 downto 0) <= dout_p2n(15 downto 8);
+ pb2noc_word4(7 downto 0) <= dout_p2n(7 downto 0);
+
+end generate;
+
+
+
+
+gen_outgoing_vc_status_clkd : process (clk,rst)
+begin
+
+
+ if rst='1' then
+ outgoing_vc_state <= (others => '0');
+ outgoing_free_this_vc <= (others => '0');
+ outgoing_next_free_vc <= (others => '0');
+ elsif clk'event and clk='1' then
+
+
+ l2: for I in NOCEM_NUM_VC-1 downto 0 loop
+ if outgoing_vc_state(I) = '0' then
+ outgoing_next_free_vc <= CONV_STD_LOGIC_VECTOR(2**I,NOCEM_NUM_VC);
+ end if;
+ end loop;
+
+ if outgoing_vc_state = allones_vcwidth then
+ outgoing_next_free_vc <= (others => '0');
+ end if;
+
+
+ outgoing_free_this_vc <= noc_arb_cntrl_in(NOCEM_ARB_CNTRL_VC_EOP_RD_HIX downto NOCEM_ARB_CNTRL_VC_EOP_RD_LIX);
+
+ -- 0: free, 1: allocated --
+ l1: for I in NOCEM_NUM_VC-1 downto 0 loop
+ if outgoing_vc_state(I) = '0' and outgoing_next_free_vc(I) = '1' and pb2noc_vc_alloc = '1' then -- free going to allocated
+ outgoing_vc_state(I) <= '1';
+ elsif outgoing_vc_state(I) = '1' and outgoing_free_this_vc(I) = '1' then -- allocated going to free
+ outgoing_vc_state(I) <= '0';
+ end if;
+ end loop;
+
+ end if;
+end process;
+
+
+
+-- see a packet is ready in pkt_buffer
+-- then attempt to get a VC
+-- then send the packet correctly
+-- breaking up the 4B buffer word into appropriate chunks
+pb2noc_clkd : process (clk,rst)
+begin
+ if rst = '1' then
+ pb2noc_state <= init_st;
+ pb2noc_byte_counter <= CONV_STD_LOGIC_VECTOR(NOCEM_DW/8,8);
+ vc_mux_wr_reg <= (others => '0');
+ elsif clk'event and clk='1' then
+ pb2noc_state <= pb2noc_nextState;
+ case pb2noc_state is
+ when init_st =>
+ pb2noc_byte_counter <= CONV_STD_LOGIC_VECTOR(NOCEM_DW/8,8);
+ when getting_vc_st =>
+ vc_mux_wr_reg <= outgoing_next_free_vc;
+ when sending_word1_st =>
+ pb2noc_byte_counter <= pb2noc_byte_counter + NOCEM_DW/8;
+ when sending_word2_st =>
+ pb2noc_byte_counter <= pb2noc_byte_counter + NOCEM_DW/8;
+ when sending_word3_st =>
+ pb2noc_byte_counter <= pb2noc_byte_counter + NOCEM_DW/8;
+ when sending_word4_st =>
+ pb2noc_byte_counter <= pb2noc_byte_counter + NOCEM_DW/8;
+ when others => null;
+ end case;
+ end if;
+
+end process;
+
+pb2noc_uclkd : process (empty_p2n,pb2noc_state,mdout_p2n, outgoing_next_free_vc, pb2noc_word1, vc_mux_wr_reg, pb2noc_byte_counter, pb2noc_word2, pb2noc_word3, pb2noc_word4)
+begin
+
+ pb2noc_amI_os <= '1';
+
+ noc_pkt_cntrl_out <= (others => '0');
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_OS_PKT_IX) <= pb2noc_amI_os;
+
+
+ noc_dataout_valid <= '0';
+ noc_dataout <= (others => '0');
+ noc_pkt_cntrl_out_valid <= '0';
+ noc_arb_req <= '0';
+
+ allones_vcwidth <= (others => '1');
+ arb_sending_word <= (others => '0');
+ pb2noc_pkt_dest_addr <= mdout_p2n(NOCEM_AW-1 downto 0);
+ pb2noc_pkt_len <= mdout_p2n(NOCEM_AW+7 downto NOCEM_AW);
+ pb2noc_vc_alloc <= '0';
+ re_p2n <= '0';
+ mre_p2n <= '0';
+
+ case pb2noc_state is
+ when init_st =>
+ if empty_p2n='0' then
+ pb2noc_nextstate <= getting_vc_st;
+ else
+ pb2noc_nextstate <= init_st;
+ end if;
+
+
+ when getting_vc_st =>
+ if outgoing_next_free_vc /= 0 then
+ pb2noc_vc_alloc <= '1';
+ pb2noc_nextState <= sending_word1_st;
+ else
+ pb2noc_nextState <= getting_vc_st;
+ end if;
+
+ when sending_word1_st =>
+ noc_dataout <= pb2noc_word1(NOCEM_DW-1 downto 0);
+ noc_dataout_valid <= '1';
+
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) <= pb2noc_pkt_dest_addr;
+ noc_pkt_cntrl_out_valid <= '1';
+
+ noc_arb_req <= '1';
+ arb_sending_word(NOCEM_ARB_CNTRL_VC_MUX_WR_HIX downto NOCEM_ARB_CNTRL_VC_MUX_WR_LIX) <= vc_mux_wr_reg;
+
+ -- do correct SOP/EOP signalling
+ if pb2noc_byte_counter = CONV_STD_LOGIC_VECTOR(NOCEM_DW/8,8) then
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_SOP_IX) <= '1';
+ end if;
+ if pb2noc_byte_counter >= pb2noc_pkt_len then
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_EOP_IX) <= '1';
+ end if;
+
+
+ -- state change logic (depends on noc datawidth)
+ if pb2noc_byte_counter = pb2noc_pkt_len then
+ re_p2n <= '1';
+ mre_p2n <= '1';
+ pb2noc_nextState <= init_st;
+ elsif NOCEM_DW = 32 then
+ pb2noc_nextState <= sending_word1_st;
+ re_p2n <= '1';
+ else
+ pb2noc_nextState <= sending_word2_st;
+ end if;
+
+
+
+ when sending_word2_st =>
+ noc_dataout <= pb2noc_word2(NOCEM_DW-1 downto 0);
+ noc_dataout_valid <= '1';
+
+
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) <= pb2noc_pkt_dest_addr;
+ noc_pkt_cntrl_out_valid <= '1';
+
+ noc_arb_req <= '1';
+ arb_sending_word(NOCEM_ARB_CNTRL_VC_MUX_WR_HIX downto NOCEM_ARB_CNTRL_VC_MUX_WR_LIX) <= vc_mux_wr_reg;
+
+ -- do correct SOP/EOP signalling
+-- if pb2noc_byte_counter = 0 then
+-- noc_pkt_cntrl_out(NOCEM_PKTCNTRL_SOP_IX) <= '1';
+-- end if;
+ if pb2noc_byte_counter >= pb2noc_pkt_len then
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_EOP_IX) <= '1';
+ end if;
+
+
+ -- state change logic (depends on noc datawidth)
+ if pb2noc_byte_counter = pb2noc_pkt_len then
+ re_p2n <= '1';
+ mre_p2n <= '1';
+ pb2noc_nextState <= init_st;
+ elsif NOCEM_DW = 16 then
+ pb2noc_nextState <= sending_word1_st;
+ re_p2n <= '1';
+ else
+ pb2noc_nextState <= sending_word3_st;
+ end if;
+
+
+
+
+
+ when sending_word3_st =>
+ noc_dataout <= pb2noc_word3(NOCEM_DW-1 downto 0);
+ noc_dataout_valid <= '1';
+
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) <= pb2noc_pkt_dest_addr;
+ noc_pkt_cntrl_out_valid <= '1';
+
+ noc_arb_req <= '1';
+ arb_sending_word(NOCEM_ARB_CNTRL_VC_MUX_WR_HIX downto NOCEM_ARB_CNTRL_VC_MUX_WR_LIX) <= vc_mux_wr_reg;
+
+ -- do correct SOP/EOP signalling
+-- if pb2noc_byte_counter = 0 then
+-- noc_pkt_cntrl_out(NOCEM_PKTCNTRL_SOP_IX) <= '1';
+-- end if;
+ if pb2noc_byte_counter >= pb2noc_pkt_len then
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_EOP_IX) <= '1';
+ end if;
+
+
+ -- state change logic (depends on noc datawidth)
+ if pb2noc_byte_counter = pb2noc_pkt_len then
+ re_p2n <= '1';
+ mre_p2n <= '1';
+ pb2noc_nextState <= init_st;
+ else
+ pb2noc_nextState <= sending_word4_st;
+ end if;
+
+
+ when sending_word4_st =>
+ noc_dataout <= pb2noc_word4(NOCEM_DW-1 downto 0);
+ noc_dataout_valid <= '1';
+
+
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_DEST_ADDR_HIX downto NOCEM_PKTCNTRL_DEST_ADDR_LIX) <= pb2noc_pkt_dest_addr;
+ noc_pkt_cntrl_out_valid <= '1';
+
+ noc_arb_req <= '1';
+ arb_sending_word(NOCEM_ARB_CNTRL_VC_MUX_WR_HIX downto NOCEM_ARB_CNTRL_VC_MUX_WR_LIX) <= vc_mux_wr_reg;
+
+ -- do correct SOP/EOP signalling
+-- if pb2noc_byte_counter = 0 then
+-- noc_pkt_cntrl_out(NOCEM_PKTCNTRL_SOP_IX) <= '1';
+-- end if;
+ if pb2noc_byte_counter >= pb2noc_pkt_len then
+ noc_pkt_cntrl_out(NOCEM_PKTCNTRL_EOP_IX) <= '1';
+ end if;
+
+
+ -- state change logic (depends on noc datawidth)
+ if pb2noc_byte_counter = pb2noc_pkt_len then
+ re_p2n <= '1';
+ mre_p2n <= '1';
+ pb2noc_nextState <= init_st;
+ else
+ re_p2n <= '1';
+ pb2noc_nextState <= sending_word1_st;
+ end if;
+
+
+ when others => null;
+ end case;
+
+end process;
+
+
+
+
+
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+
+
+
+
+--------------------------------------------------------------------------------
+------------ THE PACKET BUFFER INSTANTIATIONS ---------------
+--------------------------------------------------------------------------------
+
+
+---------------------------------------------------------
+--metadata(NOCEM_AW-1 downto 0) : dest_addr ---
+--metadata(NOCEM_AW+7 downto NOCEM_AW) : pkt_len ---
+---------------------------------------------------------
+
+
+ pb_noc2proc : packetbuffer2
+
+ generic map
+ (
+ METADATA_WIDTH => METADATA_WIDTH,
+ METADATA_LENGTH => METADATA_LENGTH
+ )
+ PORT MAP(
+ din => din_n2p,
+ rd_en => re_n2p,
+ wr_en => we_n2p,
+ dout => dout_n2p,
+ empty => empty_n2p,
+ full => full_n2p,
+ pkt_metadata_din => mdin_n2p,
+ pkt_metadata_re => mre_n2p,
+ pkt_metadata_we => mwe_n2p,
+ pkt_metadata_dout => mdout_n2p,
+ clk => clk,
+ rst => rst
+ );
+
+
+ pb_proc2noc: packetbuffer2
+ generic map
+ (
+ METADATA_WIDTH => METADATA_WIDTH,
+ METADATA_LENGTH => METADATA_LENGTH
+ )
+ PORT MAP(
+ din => din_p2n,
+ rd_en => re_p2n,
+ wr_en => we_p2n,
+ dout => dout_p2n,
+ empty => empty_p2n,
+ full => full_p2n,
+ pkt_metadata_din => mdin_p2n,
+ pkt_metadata_re => mre_p2n,
+ pkt_metadata_we => mwe_p2n,
+ pkt_metadata_dout => mdout_p2n,
+ clk => clk,
+ rst => rst
+ );
+
+
+
+
+
+
+end Behavioral;
Index: nocem/trunk/doc/gpl.txt
===================================================================
--- nocem/trunk/doc/gpl.txt (nonexistent)
+++ nocem/trunk/doc/gpl.txt (revision 8)
@@ -0,0 +1,340 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Lesser General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+ Finally, any free program is threatened constantly by software
+patents. We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary. To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License. The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language. (Hereinafter, translation is included without limitation in
+the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+ 1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+ 2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) year name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ , 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.
nocem/trunk/doc/gpl.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: nocem/trunk/doc/userguide_nocem.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: nocem/trunk/doc/userguide_nocem.pdf
===================================================================
--- nocem/trunk/doc/userguide_nocem.pdf (nonexistent)
+++ nocem/trunk/doc/userguide_nocem.pdf (revision 8)
nocem/trunk/doc/userguide_nocem.pdf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: nocem/trunk/doc/WARFP.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: nocem/trunk/doc/WARFP.pdf
===================================================================
--- nocem/trunk/doc/WARFP.pdf (nonexistent)
+++ nocem/trunk/doc/WARFP.pdf (revision 8)
nocem/trunk/doc/WARFP.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: nocem/trunk/sim/testbench.vhd
===================================================================
--- nocem/trunk/sim/testbench.vhd (nonexistent)
+++ nocem/trunk/sim/testbench.vhd (revision 8)
@@ -0,0 +1,221 @@
+
+-----------------------------------------------------------------------------
+-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
+-- and Implementations
+--
+-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License
+-- as published by the Free Software Foundation; either version 2
+-- of the License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+-- 02110-1301, USA.
+--
+-- The authors can be contacted by email: @cs.colorado.edu
+--
+-- or by mail: Campus Box 430, Department of Computer Science,
+-- University of Colorado at Boulder, Boulder, Colorado 80309
+--------------------------------------------------------------------------------
+
+
+--
+-- Filename: testbench.vhd
+--
+-- Description:
+--
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.pkg_nocem.all;
+
+
+
+entity testbench is
+end testbench;
+
+architecture Behavioral of testbench is
+
+
+ signal clk,rst : std_logic;
+
+
+ -- arbitration lines (usage depends on underlying network)
+ signal arb_req : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ signal arb_cntrl_noc2proc : arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal arb_grant : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ signal arb_cntrl_proc2noc : arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal noc_node_data : data_array(NOCEM_NUM_AP-1 downto 0);
+ signal noc_node_data_valid : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ signal noc_node_data_recvd : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ signal node_noc_data : data_array(NOCEM_NUM_AP-1 downto 0);
+ signal node_noc_data_valid : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ signal node_noc_data_recvd : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ signal noc_node_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal noc_node_pkt_cntrl_valid : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ signal noc_node_pkt_cntrl_recvd : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ signal node_noc_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
+ signal node_noc_pkt_cntrl_valid : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+ signal node_noc_pkt_cntrl_recvd : std_logic_vector(NOCEM_NUM_AP-1 downto 0);
+
+ signal test_val0,test_val1,test_val2,test_val3 : integer;
+
+
+ type int_array is array(natural range <>) of integer;
+ --constant DATAOUT_INTERVAL : int_array(NOCEM_NUM_AP-1 downto 0) := (60000,60000,32,16);
+ constant DATAOUT_INTERVAL : int_array(NOCEM_NUM_AP-1 downto 0) := (48,16,32,16);
+
+begin
+
+
+
+
+ test_val0 <= DATAOUT_INTERVAL(0);
+ test_val1 <= DATAOUT_INTERVAL(1);
+ test_val2 <= DATAOUT_INTERVAL(2);
+ test_val3 <= DATAOUT_INTERVAL(3);
+
+
+ I_noc: nocem PORT MAP(
+ arb_req => arb_req,
+ arb_cntrl_in => arb_cntrl_proc2noc,
+ arb_grant => arb_grant,
+ arb_cntrl_out => arb_cntrl_noc2proc,
+ datain => node_noc_data,
+ datain_valid => node_noc_data_valid,
+ datain_recvd => noc_node_data_recvd,
+ dataout => noc_node_data,
+ dataout_valid => noc_node_data_valid,
+ dataout_recvd => node_noc_data_recvd,
+ pkt_cntrl_in => node_noc_pkt_cntrl,
+ pkt_cntrl_in_valid => node_noc_pkt_cntrl_valid,
+ pkt_cntrl_in_recvd => noc_node_pkt_cntrl_recvd,
+ pkt_cntrl_out => noc_node_pkt_cntrl,
+ pkt_cntrl_out_valid => noc_node_pkt_cntrl_valid,
+ pkt_cntrl_out_recvd => node_noc_pkt_cntrl_recvd,
+ clk => clk,
+ rst => rst
+ );
+
+
+
+
+
+
+ g1: for I in NOCEM_NUM_AP-1 downto 0 generate
+
+
+
+ g11: if NOCEM_TYPE = NOCEM_VC_TYPE generate
+ I_ap_ex: ap_exerciser_vc
+
+ Generic map(
+ DELAY_START_COUNTER_WIDTH => 8,
+ DELAY_START_CYCLES => 10+I*8,
+ INTERVAL_COUNTER_WIDTH => 16,
+ PKT_LENGTH => 4+I,
+ INIT_DEST_ADDR => (I+1) mod NOCEM_NUM_AP,
+ MY_ADDR => I,
+ DATA_OUT_INTERVAL => DATAOUT_INTERVAL(I)
+ )
+
+ PORT MAP(
+ arb_req => arb_req(I),
+ arb_cntrl_in => arb_cntrl_noc2proc(I),
+ arb_grant => arb_grant(I),
+ arb_cntrl_out => arb_cntrl_proc2noc(I),
+ dataout => node_noc_data(I),
+ dataout_valid => node_noc_data_valid(I),
+ dataout_recvd => noc_node_data_recvd(I),
+ datain => noc_node_data(I),
+ datain_valid => noc_node_data_valid(I),
+ datain_recvd => node_noc_data_recvd(I),
+ pkt_cntrl_out => node_noc_pkt_cntrl(I),
+ pkt_cntrl_out_valid => node_noc_pkt_cntrl_valid(I),
+ pkt_cntrl_out_recvd => noc_node_pkt_cntrl_recvd(I),
+ pkt_cntrl_in => noc_node_pkt_cntrl(I),
+ pkt_cntrl_in_valid => noc_node_pkt_cntrl_valid(I),
+ pkt_cntrl_in_recvd => node_noc_pkt_cntrl_recvd(I),
+ clk => clk,
+ rst => rst
+ );
+ end generate;
+
+ g12: if NOCEM_TYPE = NOCEM_SIMPLE_PKT_TYPE generate
+
+ I_ap_ex: access_point_exerciser
+
+ Generic map(
+ DELAY_START_COUNTER_WIDTH => 8,
+ DELAY_START_CYCLES => 10+I*8,
+ INIT_DATA_OUT => CONV_STD_LOGIC_VECTOR(I+1+2**I,NOCEM_DW),
+ INTERVAL_COUNTER_WIDTH => 16,
+ BURST_LENGTH => 1,
+ INIT_DEST_ADDR => (I+1) mod NOCEM_NUM_AP,
+
+ DATA_OUT_INTERVAL => 15
+ )
+
+ PORT MAP(
+ arb_req => arb_req(I),
+ arb_cntrl_in => arb_cntrl_noc2proc(I),
+ arb_grant => arb_grant(I),
+ arb_cntrl_out => arb_cntrl_proc2noc(I),
+ dataout => node_noc_data(I),
+ dataout_valid => node_noc_data_valid(I),
+ dataout_recvd => noc_node_data_recvd(I),
+ datain => noc_node_data(I),
+ datain_valid => noc_node_data_valid(I),
+ datain_recvd => node_noc_data_recvd(I),
+ pkt_cntrl_out => node_noc_pkt_cntrl(I),
+ pkt_cntrl_out_valid => node_noc_pkt_cntrl_valid(I),
+ pkt_cntrl_out_recvd => noc_node_pkt_cntrl_recvd(I),
+ pkt_cntrl_in => noc_node_pkt_cntrl(I),
+ pkt_cntrl_in_valid => noc_node_pkt_cntrl_valid(I),
+ pkt_cntrl_in_recvd => node_noc_pkt_cntrl_recvd(I),
+ clk => clk,
+ rst => rst
+ );
+ end generate;
+ end generate;
+
+
+
+
+ P_STIMULUS: process
+ begin -- process P_STIMULUS
+ rst <= '1';
+ wait for 250 ns;
+ rst <= '0';
+ wait for 1000 ms; -- forever!
+ end process P_STIMULUS;
+
+p_clk : process -- drives clk
+ begin
+ clk <= '0';
+ wait for 2 ns;
+ loop
+ wait for 4 ns;
+ clk <= '1';
+ wait for 4 ns;
+ clk <= '0';
+ end loop;
+ end process p_clk;
+
+
+
+end Behavioral;
Index: nocem/trunk
===================================================================
--- nocem/trunk (nonexistent)
+++ nocem/trunk (revision 8)
nocem/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: nocem/web_uploads
===================================================================
--- nocem/web_uploads (nonexistent)
+++ nocem/web_uploads (revision 8)
nocem/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: nocem/branches
===================================================================
--- nocem/branches (nonexistent)
+++ nocem/branches (revision 8)
nocem/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: nocem/tags
===================================================================
--- nocem/tags (nonexistent)
+++ nocem/tags (revision 8)
nocem/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##