URL
https://opencores.org/ocsvn/pcie_vera_tb/pcie_vera_tb/trunk
Subversion Repositories pcie_vera_tb
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/tags/gutzlogic_v_0/docs/PCI_Express_VERA_testbench.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
tags/gutzlogic_v_0/docs/PCI_Express_VERA_testbench.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: tags/gutzlogic_v_0/InitFC1.vri
===================================================================
--- tags/gutzlogic_v_0/InitFC1.vri (revision 7)
+++ tags/gutzlogic_v_0/InitFC1.vri (nonexistent)
@@ -1,363 +0,0 @@
-// ===========================================================================
-// File : InitFC1.vri
-// Author : cwinward
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: InitFC1.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file performs the initial flow control sequence.
-//
-// ===========================================================================
-// ===========================================================================
-
-#include
-
-task InitFC1(var bit [7:0] ph_cl, var bit [11:0] pd_cl, var bit [7:0] cplh_cl,var bit [11:0] cpld_cl,var bit [7:0] nph_cl,var bit [11:0] npd_cl,var bit INITFC_DONE){
- integer index;
- string dllp_type;
- bit fc1_p_rcvd = 1'b0;
- bit fc1_np_rcvd = 1'b0;
- bit fc1_cpl_rcvd = 1'b0;
- bit fc2_p_rcvd = 1'b0;
- bit fc2_np_rcvd = 1'b0;
- bit fc2_cpl_rcvd = 1'b0;
-
- bit fc1_completed = 1'b0;
- bit fc2_completed = 1'b0;
-
- //****************************************************************************************
- //new task to read out the dllp's
- //
-
- while(fc1_completed == 1'b0){
- fc1_completed = fc1_p_rcvd & fc1_np_rcvd & fc1_cpl_rcvd;
- printf("FC1_completed <= %d.\n",fc1_completed);
- receive_fc1_dllp(fc1_p_rcvd,fc1_np_rcvd,fc1_cpl_rcvd,ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl);
- dllp_type = "initfc1_p";
- printf("Sending out an InitFC1_P packet.\n");
- flowcntrl_1 = new(*,*,*,*);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
-
- dllp_type = "initfc1_np";
- printf("Sending out an InitFC1_NP packet.\n");
- flowcntrl_1 = new(8'h00,8'h00,8'h01,8'b01010000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
-
- dllp_type = "initfc1_cpl";
- printf("Sending out an InitFC1_NP packet.\n");
- flowcntrl_1 = new(8'h40,8'h00,8'h01,8'b01100000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
- }
-
- while(fc2_completed == 1'b0){
- fc2_completed = fc2_p_rcvd | fc2_np_rcvd | fc2_cpl_rcvd;
- printf("FC2_completed <= %d.\n",fc2_completed);
- receive_fc2_dllp(fc2_p_rcvd,fc2_np_rcvd,fc2_cpl_rcvd);
- dllp_type = "initfc1_p";
- printf("Sending out an InitFC2_P packet.\n");
- flowcntrl_1 = new(*,*,*,8'b11000000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
-
- dllp_type = "initfc1_np";
- printf("Sending out an InitFC2_NP packet.\n");
- flowcntrl_1 = new(8'h00,8'h00,8'h01,8'b11010000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
-
- dllp_type = "initfc1_cpl";
- printf("Sending out an InitFC2_NP packet.\n");
- flowcntrl_1 = new(8'h40,8'h00,8'h01,8'b11100000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- INITFC_DONE = fc1_completed & fc2_completed;
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
- }
-
-}
-
-task receive_fc1_dllp (var bit fc1_p_rcvd, var bit fc1_np_rcvd, var bit fc1_cpl_rcvd,var bit [7:0] ph_cl, var bit [11:0] pd_cl, var bit [7:0] cplh_cl,var bit [11:0] cpld_cl,var bit [7:0] nph_cl,var bit [11:0] npd_cl) {
- integer ret;
- bit [47:0] receive_dll_packet;
-
- while (~(fc1_p_rcvd & fc1_np_rcvd & fc1_cpl_rcvd)) {
- ret = mailbox_get (WAIT,dllp_mailbox,receive_dll_packet,CHECK);
- if(receive_dll_packet[7:0] == 8'h40){
- fc1_p_rcvd = 1'b1;
- ph_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
- pd_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
- }
- else if(receive_dll_packet[7:0] == 8'h50){
- fc1_np_rcvd = 1'b1;
- nph_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
- npd_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
- }
- else if(receive_dll_packet[7:0] == 8'h60){
- fc1_cpl_rcvd = 1'b1;
- cplh_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
- cpld_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
- }
- printf ("InitFC1 DLL PACKET (%0h) taken out of dll mailbox\n",receive_dll_packet);
- }
-}
-
-task receive_fc2_dllp (var bit fc2_p_rcvd, var bit fc2_np_rcvd, var bit fc2_cpl_rcvd) {
- integer ret;
- bit [47:0] receive_dll_packet;
-
- while (~(fc2_p_rcvd | fc2_np_rcvd | fc2_cpl_rcvd)) {
- ret = mailbox_get (WAIT,dllp_mailbox,receive_dll_packet,CHECK);
- if(receive_dll_packet[7:0] == 8'hC0){
- fc2_p_rcvd = 1'b1;
- }
- else if(receive_dll_packet[7:0] == 8'hD0){
- fc2_np_rcvd = 1'b1;
- }
- else if(receive_dll_packet[7:0] == 8'hE0){
- fc2_cpl_rcvd = 1'b1;
- }
- printf ("InitFC2 DLL PACKET (%0h) taken out of dll mailbox\n",receive_dll_packet);
- }
-}
-
Index: tags/gutzlogic_v_0/ti_phy_top.vr
===================================================================
--- tags/gutzlogic_v_0/ti_phy_top.vr (revision 7)
+++ tags/gutzlogic_v_0/ti_phy_top.vr (nonexistent)
@@ -1,209 +0,0 @@
-// ===========================================================================
-// File : ti_phy_top.vr
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-// Please contact www.gutzlogic.com for details.
-// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
-// ===========================================================================
-//
-// $Id: ti_phy_top.vr,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This is the top level VERA file. It call all tasks and brings
-// up the PHY.
-// ===========================================================================
-// ===========================================================================
-
-#define OUTPUT_EDGE PHOLD
-#define OUTPUT_SKEW #1
-#define INPUT_SKEW #-1
-#define INPUT_EDGE PSAMPLE
-#include
-
-// define interfaces, and verilog_node here if necessary
-
-#include "ti_phy_top.if.vrh"
-#include "receive_packet.vri"
-#include "send_packet.vri"
-#include "pcie_phy_packet.vri"
-#include "link_training.vri"
-#include "skip_order_set.vri"
-#include "pcie_dllp_packet.vri"
-#include "InitFC1.vri"
-#include "pcie_tlp_packet.vri"
-#include "tlp_gen.vri"
-
-//kcode symbols
-#define COM_s 8'hbc
-#define SKP_s 8'h1c
-#define IDLE_s 8'h7c
-#define FTS_s 8'h3c
-#define STP_s 8'hfb
-#define SDP_s 8'h5c
-#define EDB 8'hfe
-#define END_s 8'hfd
-program ti_phy_top_test {
-
- pcie_phy_packet training_set;
- pcie_phy_packet skip_set;
- //********************************
- //link training gobal variables
- integer send_ts1 = 1;
- integer send_ts2 = 0;
- bit [11:0] sequence_id;
- bit [31:0] packet_array [1040];
- bit [7:0] link = 8'hf7;
- bit [7:0] lane = 8'hf7;
- integer ts1_cycle_cnt = 1;
- integer ts2_cycle_cnt = 1;
- integer LINK_UP = 0;
- bit [7:0] ph_cl = 8'b0;
- bit [11:0] pd_cl = 12'b0;
- bit [7:0] cplh_cl = 8'b0;
- bit [11:0] cpld_cl = 12'b0;
- bit [7:0] nph_cl = 8'b0;
- bit [11:0] npd_cl = 12'b0;
- bit INITFC_DONE = 1'b0;
- //********************************
- pcie_dllp_packet flowcntrl_1;
- pcie_dllp_packet ack_seq_num;
- pcie_tlp_packet tlp_packet;
- integer phy_rdy = 0;
- integer my_semaphore;
- bit [8:0] tx_data_mailbox;
- bit [15:0] tlp_header_mailbox;
- bit [31:0] tlp_data_mailbox;
- bit [47:0] dllp_mailbox;
- bit [127:0] phy_mailbox;
- bit [17:0] rx_data_mailbox;
-
- //create mailboxes for transmit and receive packets
- tx_data_mailbox = alloc(MAILBOX,0,1);
- rx_data_mailbox = alloc(MAILBOX,0,1);
-
- tlp_header_mailbox = alloc(MAILBOX,0,1);
- tlp_data_mailbox = alloc(MAILBOX,0,1);
- dllp_mailbox = alloc(MAILBOX,0,1);
- phy_mailbox = alloc(MAILBOX,0,1);
-
- //create a packet arbiter for packet going out on the rx line.
- my_semaphore = alloc(SEMAPHORE, 0, 1, 1);
- if (!my_semaphore) error ("Semaphore could not be allocated\n");
-
- fork
- clk_50mhz_gen();
- phy_status();
- skip_order_set();
- receive_packet();
- send_packet();
- wait_var(phy_rdy);
- link_training();
- join none
-
- init_ports ();
- reset_sequence();
- wait_var(LINK_UP);
- fork
- zero_fill();
- join none
- InitFC1(ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl,INITFC_DONE);
-
- printf("Posted Header credit %h\n",ph_cl);
- printf("Posted Data credit %h\n",pd_cl);
-
- printf("NonPosted Header credit %h\n",nph_cl);
- printf("NonPosted Data credit %h\n",npd_cl);
-
- printf("Completion Header credit %h\n",cplh_cl);
- printf("Completion Data credit %h\n",cpld_cl);
-
- printf("INITFC_DONE=%d\n.",INITFC_DONE);
- tlp_gen();
- repeat (10000) @(posedge CLOCK);
-} // end of program ti_phy_top_test
-
-// define tasks/classes/functions here if necessary
-
-task clk_50mhz_gen () {
- ti_phy_top.clk_50mhz = 0;
- @(posedge ti_phy_top.rxclk);
- while(1) {
- @10 ti_phy_top.clk_50mhz = 1;
- @10 ti_phy_top.clk_50mhz = 0;
- }
-}
-
-task init_ports () {
- printf("Task init_ports\n");
- @(posedge ti_phy_top.rxclk);
- ti_phy_top.FPGA_RESET_n = 1'b0;
- ti_phy_top.rxdata16 = 16'b0;
- ti_phy_top.rxdatak16 = 2'b0;
- ti_phy_top.rxvalid16 = 1'b0;
- ti_phy_top.rxidle16 = 1'b0;
- ti_phy_top.rxstatus = 1'b1;
- ti_phy_top.phystatus = 1'b1;
-}
-
-task reset_sequence() {
- printf("Task phy bring up\n");
-
- @5 ti_phy_top.FPGA_RESET_n = 1'b0;
- @1 ti_phy_top.FPGA_RESET_n = 1'b1;
-}
-
-
-task phy_status () {
- bit [1:0] prev_pwrdwn = 0;
- integer loop_back_high;
- integer phy_status_arb;
- phy_status_arb = alloc(SEMAPHORE,0,1,1);
- if (!phy_status_arb) error ("Semaphore could not be allocated\n");
- printf("Look for power changes\n");
- @50 ti_phy_top.rxidle16 = 1'b0;
- @100 ti_phy_top.phystatus = 1'b0;
- while (1){
- prev_pwrdwn = ti_phy_top.pwrdwn;
- @(posedge CLOCK);
- //receiver detect
- if (ti_phy_top.rxdet_loopb == 1'b1 && ti_phy_top.pwrdwn == 2'b10) {
- loop_back_high = 1;
- if (!semaphore_get(WAIT,phy_status_arb,1))
- error ("Semaphore_get returned 0\n");
- //printf("GOT PHY ARB1 /n");
- @10 ti_phy_top.rxstatus = 3'b11;
- @10 ti_phy_top.phystatus = 1'b1;
- while(loop_back_high) {
- @(posedge CLOCK);
- if (ti_phy_top.rxdet_loopb == 1'b0) {
- loop_back_high = 1'b0;
- }
- }
- @4 ti_phy_top.phystatus = 1'b0;
- ti_phy_top.rxstatus = 3'b0;
- semaphore_put (phy_status_arb, 1);
- }
- if (ti_phy_top.pwrdwn != prev_pwrdwn){
- if (!semaphore_get(WAIT,phy_status_arb,1))
- error ("Semaphore_get returned 0\n");
- //printf("GOT PHY ARB2 /n");
- @1 ti_phy_top.rxstatus = 3'b100;
- ti_phy_top.phystatus = 1'b1;
- @1 ti_phy_top.phystatus = 1'b0;
- if (ti_phy_top.pwrdwn == 2'b00) phy_rdy = 1;
- semaphore_put (phy_status_arb, 1);
-
- }
- }
-}
-
-
-
Index: tags/gutzlogic_v_0/receive_packet.vri
===================================================================
--- tags/gutzlogic_v_0/receive_packet.vri (revision 7)
+++ tags/gutzlogic_v_0/receive_packet.vri (nonexistent)
@@ -1,305 +0,0 @@
-// ===========================================================================
-// File : receive_packet.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: receive_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file processes all packets received from the 16 tx interface
-//
-// ===========================================================================
-// ===========================================================================
-#include
-#include "scramble8.vri"
-#define COM_s 8'hbc
-#define SKP_s 8'h1c
-#define IDLE_s 8'h7c
-#define FTS_s 8'h3c
-#define STP_s 8'hfb
-#define SDP_s 8'h5c
-#define EDB 8'hfe
-#define END_s 8'hfd
-
-task receive_packet () {
- bit [7:0] tx_data[];
- bit tx_datak[];
- integer ret,ret1,ret2,ret3,ret4;
- integer i = 0;
- integer m = 0;
- bit[8:0] tx_pkt;
- event phy_start, phy_done, tlp_start, tlp_done, dllp_start, dllp_done;
- bit [7:0] phy_pkt[];
- bit [7:0] dll_pkt[];
- bit [7:0] tlp_pkt[];
- integer j,k,l;
- bit [127:0] build_phy_pkt;
- bit [47:0] build_dll_pkt;
- bit [127:0] build_tlp_header;
- bit [31:0] build_tlp_data;
- bit [15:0] expected_seq_id = 0;
- bit [15:0] recv_seq_id = 0;
- bit [9:0] recv_length = 0;
- bit [31:0] recv_lcrc = 0;
- bit td = 0;
- integer kstart = 0;
- integer debug = 1;
- bit [15:0] lfsr = 16'hFFFF;
- bit [7:0] scramble_data[];
- bit skp_detect = 1'b0;
- bit com_detect = 1'b0;
- bit scram_bypass = 1'b0;
- bit [3:0] bypass_count = 4'b0;
-
- printf("Look for transmit packets\n");
- wait_var(phy_rdy);
- @ (posedge CLOCK);
- fork
- while (1) {
- @ (posedge CLOCK);
- tx_data[0] = ti_phy_top.txdata16[7:0];
- tx_data[1] = ti_phy_top.txdata16[15:8];
- tx_datak[0] = ti_phy_top.txdatak16[0];
- tx_datak[1] = ti_phy_top.txdatak16[1];
- for (i=0; i<2; i++) {
-
- if(com_detect == 1'b1){
- scram_bypass = 1'b1;
- }
- else if(((bypass_count == 4'b0011) & tx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
- scram_bypass = 1'b0;
- }
-
- if((com_detect == 1'b1) | scram_bypass){
- bypass_count = bypass_count + 1'b1;
- }
- else if(((bypass_count == 4'b0011) & tx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
- bypass_count = 4'b0000;
- }
-
-
- if({tx_datak[i],tx_data[i]} == {1'b1,SKP_s}){
- skp_detect = 1'b1;
- }
- else{
- skp_detect = 1'b0;
- }
- if({tx_datak[i],tx_data[i]} == {1'b1,COM_s}){
- com_detect = 1'b1;
- }
- else{
- com_detect = 1'b0;
- }
-
-
- //printf("K-Code = %h DATA = %h COM = %h SKP = %h bypass_count = %d scram_bypass = %h\n",tx_datak[i],tx_data[i],com_detect,skp_detect,bypass_count,scram_bypass);
-
- //if({tx_datak[i],tx_data[i]} == {1'b1,STP_s}){
- // printf("Start of TLP packet.\n");
- //}
-
- scramble8(tx_data[i],skp_detect,com_detect,(scram_bypass | tx_datak[i]),lfsr,scramble_data[i],lfsr);
- //printf("K-Code = %h COM = %h SKP = %h bypass = %h scramble_data = %h unscramble_data = %h lfsr = %h bypass_cnt = %d\n",tx_datak[i],com_detect,skp_detect,scram_bypass,tx_data[i],scramble_data[i],lfsr,bypass_count);
-
- mailbox_put (tx_data_mailbox, {tx_datak[i],scramble_data[i]});
- //printf("Add packet to tx_mailbox %0h\n",tx_data[i]);
-
- }
- }
- while (1) {
- ret = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- if (ret <= 0)
- error ("mailbox_get returned %0d\n",ret);
- //printf ("got tx_pkt %0h\n",tx_pkt);
- if (tx_pkt == {1'b1,COM_s}) {
- trigger (ONE_BLAST,phy_start);
- sync (ALL,phy_done);
- }
- if (tx_pkt == {1'b1,STP_s}) {
- trigger (ONE_BLAST,tlp_start);
- sync (ALL,tlp_done);
- }
- if (tx_pkt == {1'b1,SDP_s}) {
- trigger (ONE_BLAST,dllp_start);
- sync (ALL,dllp_done);
- }
- }
- //phy layer packets
- while (1) {
- sync(ALL,phy_start);
- //printf ("got past sync %0h\n",tx_pkt);
- phy_pkt[0] = COM_s;
- phy_pkt[4] = 0;
- phy_pkt[5] = 0;
- phy_pkt[6] = 0;
- phy_pkt[7] = 0;
- phy_pkt[8] = 0;
- phy_pkt[9] = 0;
- phy_pkt[10] = 0;
- phy_pkt[11] = 0;
- phy_pkt[12] = 0;
- phy_pkt[13] = 0;
- phy_pkt[14] = 0;
- phy_pkt[15] = 0;
- ret2 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- //printf ("got past mailbox get %0h\n",tx_pkt);
- phy_pkt[1] = tx_pkt;
- //training set
- if ((tx_pkt == 'h1f7) || ~tx_pkt[8]) {
- for (j = 2; j <16; j++) {
- ret2 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- phy_pkt[j] = tx_pkt;
- }
- }
- //skip fst idle
- else {
- for (j=2;j<4;j++) {
- ret1 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- phy_pkt[j] = tx_pkt;
- //printf ("skip loop got past %0h\n",tx_pkt);
- }
- }
- build_phy_pkt = {phy_pkt[15],phy_pkt[14],phy_pkt[13],phy_pkt[12],phy_pkt[11],
- phy_pkt[10],phy_pkt[9],phy_pkt[8],phy_pkt[7],phy_pkt[6],
- phy_pkt[5],phy_pkt[4],phy_pkt[3],phy_pkt[2],phy_pkt[1],phy_pkt[0]};
- mailbox_put (phy_mailbox, build_phy_pkt);
- printf ("Recieved PHY PACKET (%0h) added to phy mailbox\n",build_phy_pkt);
- trigger (ONE_BLAST,phy_done);
- }
- //dll layer packets
- while (1) {
- sync (ALL,dllp_start);
- //printf ("sync into dllp packet\n");
- for (k = 0; k < 6; k++) {
- ret3 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- dll_pkt[k] = tx_pkt;
- //printf ("dll_pkt(%0h)\n",dll_pkt[k]);
- }
- ret3 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- //printf ("dll this should be end(%0h)\n",tx_pkt);
- if (tx_pkt == {1'b1,END_s}) {
- build_dll_pkt = {dll_pkt[6],dll_pkt[5],dll_pkt[4],dll_pkt[3],
- dll_pkt[2],dll_pkt[1],dll_pkt[0]};
- mailbox_put (dllp_mailbox, build_dll_pkt);
- printf ("Recieved DLL PACKET (%0h) added to dllp mailbox\n",build_dll_pkt);
- }
- else
- printf ("ERROR ->>>>>>> DLL malformed no END\n");
-
- trigger (ONE_BLAST,dllp_done);
- }
- //tlp layer packets
- while (1) {
- sync (ALL,tlp_start);
- printf ("sync into tlp packet\n");
- @(posedge CLOCK);
- //4 dw header + seq.
- for (k = 0; k < 18; k++) {
- //printf("debug1 %0d\n",debug++);
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- tlp_pkt[k] = tx_pkt;
- }
- recv_seq_id = {tlp_pkt[0],tlp_pkt[1]};
- if (recv_seq_id != expected_seq_id) printf ("ERROR ->>>>>>> TLP BAD SEQUENCE ID of %0h\n",recv_seq_id);
- //ack packet
- else {
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- ack_seq_num = new(recv_seq_id[7:0],{4'b0,recv_seq_id[11:8]},8'b0,8'b0);
- ack_seq_num.build_packet("ack");
- for(m=0; m <= 3; m ++) {
- @ (posedge CLOCK);
- printf("ACK PACKET Sequence Number (%0h)\n",recv_seq_id);
- if(m==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,ack_seq_num.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",ack_seq_num.temp_packet[0][7:0],8'h5C);
- }
- else if(m==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {ack_packet.temp_packet[0][23:16],ack_packet.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,ack_seq_num.temp_packet[0][23:16],ack_seq_num.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",ack_seq_num.temp_packet[0][23:16],ack_seq_num.temp_packet[0][15:8]);
- }
- else if(m==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {ack_packet.temp_packet[1][7:0],ack_packet.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,ack_seq_num.temp_packet[1][7:0],ack_seq_num.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",ack_seq_num.temp_packet[1][7:0],ack_seq_num.temp_packet[0][31:24]);
- }
- else if(m==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,ack_packet.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,ack_seq_num.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,ack_seq_num.temp_packet[1][15:8]);
- }
- }
- semaphore_put (my_semaphore, 1);
- }
- expected_seq_id++;
- build_tlp_header = {tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14],
- tlp_pkt[13],tlp_pkt[12],tlp_pkt[11],tlp_pkt[10],
- tlp_pkt[9],tlp_pkt[8],tlp_pkt[7],tlp_pkt[6],
- tlp_pkt[5],tlp_pkt[4],tlp_pkt[3],tlp_pkt[2]};
- if (build_tlp_header[5] == 1'b0) {
- if (build_tlp_header[6] == 0) recv_lcrc = {tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14]};
- build_tlp_header[127:96] = 32'b0;
- }
- mailbox_put (tlp_header_mailbox, build_tlp_header);
- printf ("Recieved TLP PACKET (%0h) added to tlp header mailbox\n",build_tlp_header);
- if (build_tlp_header[6] == 1) {
- td = build_tlp_header[23];
- recv_length = {build_tlp_header[17:16],build_tlp_header[31:24]};
- kstart = 0;
- if (build_tlp_header[5] == 1'b0) {
- mailbox_put (tlp_data_mailbox, {tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14]});
- printf ("Recieved TLP DATA (%0h) added to tlp data mailbox\n",{tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14]});
- kstart = 5;
- }
-
- for (k=kstart;k<=((recv_length*4)+(td*4));k++) {
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- //printf("debug2 %0d\n",debug++);
- tlp_pkt[k] = tx_pkt;
- if (k%4) {
- mailbox_put (tlp_data_mailbox, {tlp_pkt[k],tlp_pkt[k-1],tlp_pkt[k-2],tlp_pkt[k-3]});
- printf ("Recieved TLP DATA (%0h) added to tlp data mailbox\n",{tlp_pkt[k],tlp_pkt[k-1],tlp_pkt[k-2],tlp_pkt[k-3]});
- }
-
- }
- }
- if (build_tlp_header[5] == 0 & build_tlp_header[6] == 0) printf ("tlp lcrc value = %0h \n",recv_lcrc);
- else {
- for (k=0;k<=3;k++) {
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- //printf("debug3 %0d\n",debug++);
- tlp_pkt[k] = tx_pkt;
- }
- printf ("tlp lcrc value = %0h \n",{tlp_pkt[3],tlp_pkt[2],tlp_pkt[1],tlp_pkt[0]});
- }
-
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- //printf("debug4 %0d\n",debug++);
- if (tx_pkt != {1'b1,END_s}) printf ("ERROR ->>>>>>> TLP malformed no END(%0h)\n",tx_pkt);
-
-
- trigger (ONE_BLAST,tlp_done);
- }
- join none
-}
-
Index: tags/gutzlogic_v_0/ti_phy_top.if.vrh
===================================================================
--- tags/gutzlogic_v_0/ti_phy_top.if.vrh (revision 7)
+++ tags/gutzlogic_v_0/ti_phy_top.if.vrh (nonexistent)
@@ -1,64 +0,0 @@
-// ===========================================================================
-// File : ti_phy_top.if.vrh
-// Author : cwinward
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: ti_phy_top.if.vrh,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : .This is the interface file linking verilog with VERA
-//
-// ===========================================================================
-// ===========================================================================
-#ifndef INC_TI_PHY_TOP_IF_VRH
-#define INC_TI_PHY_TOP_IF_VRH
-
- interface ti_phy_top {
- input rxclk CLOCK;
- //input [9:0] t1_count PSAMPLE #-1 verilog_node "dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count";
- output clk_50mhz OUTPUT_EDGE OUTPUT_SKEW;
- output [1:0] PUSH_BUTTON OUTPUT_EDGE OUTPUT_SKEW;
- output FPGA_RESET_n OUTPUT_EDGE OUTPUT_SKEW;
- output [15:0] rxdata16 OUTPUT_EDGE OUTPUT_SKEW;
- output [1:0] rxdatak16 OUTPUT_EDGE OUTPUT_SKEW;
- output rxvalid16 OUTPUT_EDGE OUTPUT_SKEW;
- output rxidle16 OUTPUT_EDGE OUTPUT_SKEW;
- output rxidle OUTPUT_EDGE OUTPUT_SKEW;
- output [2:0] rxstatus OUTPUT_EDGE OUTPUT_SKEW;
- output phystatus OUTPUT_EDGE OUTPUT_SKEW;
- input [7:0] LED INPUT_EDGE INPUT_SKEW;
- input txclk INPUT_EDGE INPUT_SKEW;
- input [15:0] txdata16 INPUT_EDGE INPUT_SKEW;
- input [1:0] txdatak16 INPUT_EDGE INPUT_SKEW;
- input txidle16 INPUT_EDGE INPUT_SKEW;
- input rxdet_loopb INPUT_EDGE INPUT_SKEW;
- input txcomp INPUT_EDGE INPUT_SKEW;
- input rxpol INPUT_EDGE INPUT_SKEW;
- input phy_reset_n INPUT_EDGE INPUT_SKEW;
- input [1:0] pwrdwn INPUT_EDGE INPUT_SKEW;
- input [16:0] sram_addr INPUT_EDGE INPUT_SKEW;
- input sram_adscn INPUT_EDGE INPUT_SKEW;
- input sram_adspn INPUT_EDGE INPUT_SKEW;
- input sram_advn INPUT_EDGE INPUT_SKEW;
- input [3:0] sram_ben INPUT_EDGE INPUT_SKEW;
- input [2:0] sram_ce INPUT_EDGE INPUT_SKEW;
- input sram_clk INPUT_EDGE INPUT_SKEW;
- input sram_gwn INPUT_EDGE INPUT_SKEW;
- input sram_mode INPUT_EDGE INPUT_SKEW;
- input sram_oen INPUT_EDGE INPUT_SKEW;
- input sram_wen INPUT_EDGE INPUT_SKEW;
- input sram_zz INPUT_EDGE INPUT_SKEW;
- inout [35:0] sram_data INPUT_EDGE INPUT_SKEW OUTPUT_EDGE OUTPUT_SKEW;
- } // end of interface ti_phy_top
-
-#endif
Index: tags/gutzlogic_v_0/skip_order_set.vri
===================================================================
--- tags/gutzlogic_v_0/skip_order_set.vri (revision 7)
+++ tags/gutzlogic_v_0/skip_order_set.vri (nonexistent)
@@ -1,64 +0,0 @@
-// ===========================================================================
-// File : skip_order_set.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: skip_order_set.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : this file generates skip order sets when the timer expires
-//
-// ===========================================================================
-// ===========================================================================
-#include
-
-//task to send in skip order sets on a regular basis.
-task skip_order_set() {
- integer time_limit_expire = 0;
- integer index = 0;
- wait_var(phy_rdy);
- while(1) {
- time_limit_expire++;
- @ (posedge CLOCK);
- ti_phy_top.rxdatak16 = 2'b00;
- ti_phy_top.rxdata16 = 1'b0;
- //1180 symbols clk is 2 symbols
- if (time_limit_expire == 1180/2) {
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- skip_set = new(*,*,*,*,*,*);
- skip_set.build_packet("skip");
- for (index = 0; index < skip_set.length; index ++) {
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = skip_set.temp_packet[index][17:16];
- //ti_phy_top.rxdata16 = skip_set.temp_packet[index][15:0];
- //adding mailbox
- mailbox_put (rx_data_mailbox, {skip_set.temp_packet[index][17:16],skip_set.temp_packet[index][15:0]});
- time_limit_expire = 0;
- }
- semaphore_put (my_semaphore, 1);
- }
- }
-}
-
-
-task zero_fill(){
-
- while(1) {
- @ (posedge CLOCK);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- mailbox_put (rx_data_mailbox,18'b0);
- semaphore_put(my_semaphore, 1);
- }
-}
Index: tags/gutzlogic_v_0/send_packet.vri
===================================================================
--- tags/gutzlogic_v_0/send_packet.vri (revision 7)
+++ tags/gutzlogic_v_0/send_packet.vri (nonexistent)
@@ -1,109 +0,0 @@
-// ===========================================================================
-// File : send_packet.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: send_packet.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file sends all packets on the rx 16 bit data lines
-//
-// ===========================================================================
-// ===========================================================================
-#include
-//#include "scramble8.vri"
-#define COM_s 8'hbc
-#define SKP_s 8'h1c
-#define IDLE_s 8'h7c
-#define FTS_s 8'h3c
-#define STP_s 8'hfb
-#define SDP_s 8'h5c
-#define EDB 8'hfe
-#define END_s 8'hfd
-
-task send_packet () {
- bit [7:0] rx_data[];
- bit rx_datak[];
-
- bit [17:0] rx_pkt;
- bit [15:0] rx_data_out;
- bit [1:0] rx_datak_out;
- integer ret;
- integer i;
-
- bit [15:0] lfsr = 16'hFFFF;
- bit [7:0] scramble_data[];
- bit skp_detect = 1'b0;
- bit com_detect = 1'b0;
- bit scram_bypass = 1'b0;
- bit [3:0] bypass_count = 4'b0;
-
-
- ti_phy_top.rxdatak16 = 2'b0;
- ti_phy_top.rxdata16 = 16'b0;
- while (1) {
- @ (posedge CLOCK);
- ti_phy_top.rxdatak16 = 2'b0;
- ti_phy_top.rxdata16 = 16'b0;
-
- ret = mailbox_get (WAIT,rx_data_mailbox,rx_pkt,CHECK);
- if (ret <= 0)
- error ("mailbox_get returned %0d\n",ret);
-
- rx_datak[1] = rx_pkt[17];
- rx_datak[0] = rx_pkt[16];
- rx_data[1] = rx_pkt[15:8];
- rx_data[0] = rx_pkt[7:0];
-
-
- for (i=0; i<2; i++) {
-
- if(com_detect == 1'b1){
- scram_bypass = 1'b1;
- }
- else if(((bypass_count == 4'b0011) & rx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
- scram_bypass = 1'b0;
- }
-
- if((com_detect == 1'b1) | scram_bypass){
- bypass_count = bypass_count + 1'b1;
- }
- else if(((bypass_count == 4'b0011) & rx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
- bypass_count = 4'b0000;
- }
-
-
- if({rx_datak[i],rx_data[i]} == {1'b1,SKP_s}){
- skp_detect = 1'b1;
- }
- else{
- skp_detect = 1'b0;
- }
- if({rx_datak[i],rx_data[i]} == {1'b1,COM_s}){
- com_detect = 1'b1;
- }
- else{
- com_detect = 1'b0;
- }
-
- scramble8(rx_data[i],skp_detect,com_detect,(scram_bypass | rx_datak[i]),lfsr,scramble_data[i],lfsr);
- //printf("K-Code = %h COM = %h SKP = %h bypass = %h unscramble_data = %h scramble_data = %h lfsr = %h bypass_cnt = %d\n",rx_datak[i],com_detect,skp_detect,scram_bypass,rx_data[i],scramble_data[i],lfsr,bypass_count);
- }
-
-
- //printf("RX MAILBOX OUT datak(%0h) data(%0h) to be sent\n",rx_pkt[17:16],rx_pkt[15:0]);
- ti_phy_top.rxdatak16 = {rx_datak[1],rx_datak[0]};
- ti_phy_top.rxdata16 = {scramble_data[1],scramble_data[0]};
- }
-
-}
Index: tags/gutzlogic_v_0/scramble8.vri
===================================================================
--- tags/gutzlogic_v_0/scramble8.vri (revision 7)
+++ tags/gutzlogic_v_0/scramble8.vri (nonexistent)
@@ -1,70 +0,0 @@
-// ===========================================================================
-// File : scramble8.vri
-// Author : cwinward
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: scramble8.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file scrambles the rx lines and descrambles the tx lines.
-//
-// ===========================================================================
-// ===========================================================================
-#include
-
-
-
-task scramble8(bit [7:0] data_in, bit skp_detect, bit com_detect, bit sram_bypass, bit [15:0] lfsr_old, var bit [7:0] scramble_data, var bit [15:0] lfsr) {
-
-
- if((sram_bypass == 1'b1) | (com_detect == 1'b1)) {
- scramble_data = data_in;
- }
- else {
- scramble_data[0] = lfsr_old[15] ^ data_in[0];
- scramble_data[1] = lfsr_old[14] ^ data_in[1];
- scramble_data[2] = lfsr_old[13] ^ data_in[2];
- scramble_data[3] = lfsr_old[12] ^ data_in[3];
- scramble_data[4] = lfsr_old[11] ^ data_in[4];
- scramble_data[5] = lfsr_old[10] ^ data_in[5];
- scramble_data[6] = lfsr_old[9] ^ data_in[6];
- scramble_data[7] = lfsr_old[8] ^ data_in[7];
- }
-
-
- if(com_detect == 1'b1) {
- lfsr = 16'hFFFF;
- }
- else if(skp_detect == 1'b0) {
- lfsr[0] = lfsr_old[8];
- lfsr[1] = lfsr_old[9];
- lfsr[2] = lfsr_old[10];
- lfsr[3] = lfsr_old[8] ^ lfsr_old[11];
- lfsr[4] = lfsr_old[8] ^ lfsr_old[9] ^ lfsr_old[12];
- lfsr[5] = lfsr_old[8] ^ lfsr_old[9] ^ lfsr_old[10] ^ lfsr_old[13];
- lfsr[6] = lfsr_old[9] ^ lfsr_old[10] ^ lfsr_old[11] ^ lfsr_old[14];
- lfsr[7] = lfsr_old[10] ^ lfsr_old[11] ^ lfsr_old[12] ^ lfsr_old[15];
- lfsr[8] = lfsr_old[0] ^ lfsr_old[11] ^ lfsr_old[12] ^ lfsr_old[13];
- lfsr[9] = lfsr_old[1] ^ lfsr_old[12] ^ lfsr_old[13] ^ lfsr_old[14];
- lfsr[10] = lfsr_old[2] ^ lfsr_old[13] ^ lfsr_old[14] ^ lfsr_old[15];
- lfsr[11] = lfsr_old[3] ^ lfsr_old[14] ^ lfsr_old[15];
- lfsr[12] = lfsr_old[4] ^ lfsr_old[15];
- lfsr[13] = lfsr_old[5];
- lfsr[14] = lfsr_old[6];
- lfsr[15] = lfsr_old[7];
- }
- else {
- lfsr = lfsr_old;
- }
-
-}
Index: tags/gutzlogic_v_0/pcie_dllp_packet.vri
===================================================================
--- tags/gutzlogic_v_0/pcie_dllp_packet.vri (revision 7)
+++ tags/gutzlogic_v_0/pcie_dllp_packet.vri (nonexistent)
@@ -1,150 +0,0 @@
-// ===========================================================================
-// File : pcie_dllp_packet.vri
-// Author : cwinward
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: pcie_dllp_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file is a class of pcie packet can be used for all DLLP
-// packet types.
-//
-// ===========================================================================
-// ===========================================================================
-#include
-
-class pcie_dllp_packet {
- bit [7:0] byte3;
- bit [7:0] byte2;
- bit [7:0] byte1;
- bit [7:0] dllp_type;
- bit [31:0] temp_packet[];
-
- task new(
- bit [7:0] init_byte3 = 8'h40,
- bit [7:0] init_byte2 = 8'h00,
- bit [7:0] init_byte1 = 8'h01,
- bit [7:0] init_dllp_type = 8'b01000000) {
-
- dllp_type = init_dllp_type;
- byte1 = init_byte1;
- byte2 = init_byte2;
- byte3 = init_byte3;
- }
-
- task build_packet (string pkt_type = "initfc1_p") {
- if(pkt_type == "initfc1_p") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc1_np") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc1_cpl") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc2_p") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc2_np") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc1_cpl") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if (pkt_type == "ack") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
-
- }
-
- function bit[15:0] crc16d32(bit[31:0] d) {
-
- bit [15:0] crc;
- bit [15:0] C = 32'hFFFF;
-
- crc[0] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[8] ^ d[10] ^ d[11] ^ d[16] ^ d[18] ^
- d[19] ^ d[23] ^ d[27] ^ d[31] ^ C[4] ^ C[5] ^ C[7] ^ C[10] ^ C[12]
- ^ C[13] ^ C[15];
- crc[1] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[5] ^ d[7] ^ d[8] ^ d[9] ^ d[11] ^ d[15]
- ^ d[16] ^ d[17] ^ d[19] ^ d[22] ^ d[23] ^ d[26] ^ d[27] ^ d[30] ^
- d[31] ^ C[0] ^ C[4] ^ C[6] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ C[12] ^
- C[14] ^ C[15];
- crc[2] = d[0] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[14] ^ d[15]
- ^ d[16] ^ d[18] ^ d[21] ^ d[22] ^ d[25] ^ d[26] ^ d[29] ^ d[30] ^
- C[0] ^ C[1] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^
- C[15];
- crc[3] = d[0] ^ d[1] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[13] ^
- d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[23]
- ^ d[24] ^ d[25] ^ d[27] ^ d[28] ^ d[29] ^ d[31] ^ C[0] ^ C[1] ^ C[2]
- ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[14] ^ C[15];
- crc[4] = d[0] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[12] ^ d[13] ^
- d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[23]
- ^ d[24] ^ d[26] ^ d[27] ^ d[28] ^ d[30] ^ C[0] ^ C[1] ^ C[2] ^ C[3]
- ^ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[15];
- crc[5] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[11] ^ d[12] ^ d[13] ^
- d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[21] ^ d[22] ^ d[23]
- ^ d[25] ^ d[26] ^ d[27] ^ d[29] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4]
- ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[11];
- crc[6] = d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[11] ^ d[12] ^
- d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[22]
- ^ d[24] ^ d[25] ^ d[26] ^ d[28] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4]
- ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ C[12];
- crc[7] = d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[9] ^ d[10] ^ d[11] ^ d[12]
- ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[19] ^ d[20] ^ d[21] ^
- d[23] ^ d[24] ^ d[25] ^ d[27] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
- C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ C[12] ^ C[13];
- crc[8] = d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[8] ^ d[9] ^ d[10] ^ d[11]
- ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^
- d[22] ^ d[23] ^ d[24] ^ d[26] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
- C[5] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[12] ^ C[13] ^ C[14];
- crc[9] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
- ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[17] ^ d[18] ^ d[19] ^
- d[21] ^ d[22] ^ d[23] ^ d[25] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
- C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ C[12] ^ C[13] ^ C[14]
- ^ C[15];
- crc[10] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
- ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^
- d[21] ^ d[22] ^ d[24] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^
- C[7] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[14] ^ C[15];
- crc[11] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
- ^ d[11] ^ d[12] ^ d[13] ^ d[15] ^ d[16] ^ d[17] ^ d[19] ^ d[20] ^
- d[21] ^ d[23] ^ C[0] ^ C[2] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ C[8]
- ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[14] ^ C[15];
- crc[12] = d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[9] ^ d[12] ^ d[14] ^ d[15] ^
- d[20] ^ d[22] ^ d[23] ^ d[27] ^ d[31] ^ C[0] ^ C[1] ^ C[3] ^ C[6]
- ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[14];
- crc[13] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[8] ^ d[11] ^ d[13] ^ d[14] ^
- d[19] ^ d[21] ^ d[22] ^ d[26] ^ d[30] ^ C[1] ^ C[2] ^ C[4] ^ C[7]
- ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15];
- crc[14] = d[1] ^ d[2] ^ d[4] ^ d[5] ^ d[7] ^ d[10] ^ d[12] ^ d[13] ^ d[18] ^
- d[20] ^ d[21] ^ d[25] ^ d[29] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10]
- ^ C[11] ^ C[13] ^ C[14];
- crc[15] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[9] ^ d[11] ^ d[12] ^ d[17] ^
- d[19] ^ d[20] ^ d[24] ^ d[28] ^ C[3] ^ C[4] ^ C[6] ^ C[9] ^ C[11]
- ^ C[12] ^ C[14] ^ C[15];
-
- crc16d32 = {~crc[0],~crc[1],~crc[2],~crc[3],~crc[4],~crc[5],~crc[6],~crc[7],
- ~crc[8],~crc[9],~crc[10],~crc[11],~crc[12],~crc[13],~crc[14],~crc[15]};
-
- return;
- }
-
-
- }
Index: tags/gutzlogic_v_0/run_vera
===================================================================
--- tags/gutzlogic_v_0/run_vera (revision 7)
+++ tags/gutzlogic_v_0/run_vera (nonexistent)
@@ -1,10 +0,0 @@
-#!/bin/csh -f
-
-\rm -rf simv csrc simv.daidir comp.log sim.log
-
- vcs -ntb ti_phy_top.test_top.v ti_phy_top.v ti_phy_top.vr \
- -P /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/debussy.tab \
- /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/pli.a \
- -Mupdate -l vcs_compile.log +vcs+lic+wait +define+SYNOPSYS_NTB -l comp.log $*
-
- ./simv -l sim.log $*
tags/gutzlogic_v_0/run_vera
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/gutzlogic_v_0/ti_phy_top.test_top.v
===================================================================
--- tags/gutzlogic_v_0/ti_phy_top.test_top.v (revision 7)
+++ tags/gutzlogic_v_0/ti_phy_top.test_top.v (nonexistent)
@@ -1,231 +0,0 @@
-// ===========================================================================
-// File : ti_phy_top.test_top.v
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-// Please contact www.gutzlogic.com for details.
-// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
-// ===========================================================================
-//
-// $Id: ti_phy_top.test_top.v,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This is the top level testbench file.
-//
-// ===========================================================================
-// ===========================================================================
-module ti_phy_top_test_top;
- parameter simulation_cycle = 100;
-
- reg SystemClock;
- wire clk_50mhz;
- wire [1:0] PUSH_BUTTON;
- wire FPGA_RESET_n;
- wire rxclk;
- wire [15:0] rxdata16;
- wire [1:0] rxdatak16;
- wire rxvalid16;
- wire rxidle16;
- wire rxidle;
- wire [2:0] rxstatus;
- wire phystatus;
- wire [7:0] LED;
- wire txclk;
- wire [15:0] txdata16;
- wire [1:0] txdatak16;
- wire txidle16;
- wire rxdet_loopb;
- wire txcomp;
- wire rxpol;
- wire phy_reset_n;
- wire [1:0] pwrdwn;
- wire [16:0] sram_addr;
- wire sram_adscn;
- wire sram_adspn;
- wire sram_advn;
- wire [3:0] sram_ben;
- wire [2:0] sram_ce;
- wire sram_clk;
- wire sram_gwn;
- wire sram_mode;
- wire sram_oen;
- wire sram_wen;
- wire sram_zz;
- wire [35:0] sram_data;
- assign rxclk = SystemClock;
-
-`ifdef SYNOPSYS_NTB
- ti_phy_top_test vshell(
- .SystemClock (SystemClock),
- .\ti_phy_top.clk_50mhz (clk_50mhz),
- .\ti_phy_top.PUSH_BUTTON (PUSH_BUTTON),
- .\ti_phy_top.FPGA_RESET_n (FPGA_RESET_n),
- .\ti_phy_top.rxclk (rxclk),
- .\ti_phy_top.rxdata16 (rxdata16),
- .\ti_phy_top.rxdatak16 (rxdatak16),
- .\ti_phy_top.rxvalid16 (rxvalid16),
- .\ti_phy_top.rxidle16 (rxidle16),
- .\ti_phy_top.rxidle (rxidle),
- .\ti_phy_top.rxstatus (rxstatus),
- .\ti_phy_top.phystatus (phystatus),
- .\ti_phy_top.sram_data (sram_data),
- .\ti_phy_top.LED (LED),
- .\ti_phy_top.txclk (txclk),
- .\ti_phy_top.txdata16 (txdata16),
- .\ti_phy_top.txdatak16 (txdatak16),
- .\ti_phy_top.txidle16 (txidle16),
- .\ti_phy_top.rxdet_loopb (rxdet_loopb),
- .\ti_phy_top.txcomp (txcomp),
- .\ti_phy_top.rxpol (rxpol),
- .\ti_phy_top.phy_reset_n (phy_reset_n),
- .\ti_phy_top.pwrdwn (pwrdwn),
- .\ti_phy_top.sram_addr (sram_addr),
- .\ti_phy_top.sram_adscn (sram_adscn),
- .\ti_phy_top.sram_adspn (sram_adspn),
- .\ti_phy_top.sram_advn (sram_advn),
- .\ti_phy_top.sram_ben (sram_ben),
- .\ti_phy_top.sram_ce (sram_ce),
- .\ti_phy_top.sram_clk (sram_clk),
- .\ti_phy_top.sram_gwn (sram_gwn),
- .\ti_phy_top.sram_mode (sram_mode),
- .\ti_phy_top.sram_oen (sram_oen),
- .\ti_phy_top.sram_wen (sram_wen),
- .\ti_phy_top.sram_zz (sram_zz)
- );
-`else
-
- vera_shell vshell(
- .SystemClock (SystemClock),
- .ti_phy_top_clk_50mhz (clk_50mhz),
- .ti_phy_top_PUSH_BUTTON (PUSH_BUTTON),
- .ti_phy_top_FPGA_RESET_n (FPGA_RESET_n),
- .ti_phy_top_rxclk (rxclk),
- .ti_phy_top_rxdata16 (rxdata16),
- .ti_phy_top_rxdatak16 (rxdatak16),
- .ti_phy_top_rxvalid16 (rxvalid16),
- .ti_phy_top_rxidle16 (rxidle16),
- .ti_phy_top_rxidle (rxidle),
- .ti_phy_top_rxstatus (rxstatus),
- .ti_phy_top_phystatus (phystatus),
- .ti_phy_top_sram_data (sram_data),
- .ti_phy_top_LED (LED),
- .ti_phy_top_txclk (txclk),
- .ti_phy_top_txdata16 (txdata16),
- .ti_phy_top_txdatak16 (txdatak16),
- .ti_phy_top_txidle16 (txidle16),
- .ti_phy_top_rxdet_loopb (rxdet_loopb),
- .ti_phy_top_txcomp (txcomp),
- .ti_phy_top_rxpol (rxpol),
- .ti_phy_top_phy_reset_n (phy_reset_n),
- .ti_phy_top_pwrdwn (pwrdwn),
- .ti_phy_top_sram_addr (sram_addr),
- .ti_phy_top_sram_adscn (sram_adscn),
- .ti_phy_top_sram_adspn (sram_adspn),
- .ti_phy_top_sram_advn (sram_advn),
- .ti_phy_top_sram_ben (sram_ben),
- .ti_phy_top_sram_ce (sram_ce),
- .ti_phy_top_sram_clk (sram_clk),
- .ti_phy_top_sram_gwn (sram_gwn),
- .ti_phy_top_sram_mode (sram_mode),
- .ti_phy_top_sram_oen (sram_oen),
- .ti_phy_top_sram_wen (sram_wen),
- .ti_phy_top_sram_zz (sram_zz)
- );
-`endif
-
-
-
-`ifdef emu
- /* DUT is in emulator, so not instantiated here */
-`else
- ti_phy_top dut(
- .clk_50mhz (clk_50mhz),
- .PUSH_BUTTON (PUSH_BUTTON),
- .FPGA_RESET_n (FPGA_RESET_n),
- .rxclk (rxclk),
- .rxdata16 (rxdata16),
- .rxdatak16 (rxdatak16),
- .rxvalid16 (rxvalid16),
- .rxidle16 (rxidle16),
- .rxidle (rxidle),
- .rxstatus (rxstatus),
- .phystatus (phystatus),
- .sram_data (sram_data),
- .LED (LED),
- .txclk (txclk),
- .txdata16 (txdata16),
- .txdatak16 (txdatak16),
- .txidle16 (txidle16),
- .rxdet_loopb (rxdet_loopb),
- .txcomp (txcomp),
- .rxpol (rxpol),
- .phy_reset_n (phy_reset_n),
- .pwrdwn (pwrdwn),
- .sram_addr (sram_addr),
- .sram_adscn (sram_adscn),
- .sram_adspn (sram_adspn),
- .sram_advn (sram_advn),
- .sram_ben (sram_ben),
- .sram_ce (sram_ce),
- .sram_clk (sram_clk),
- .sram_gwn (sram_gwn),
- .sram_mode (sram_mode),
- .sram_oen (sram_oen),
- .sram_wen (sram_wen),
- .sram_zz (sram_zz)
- );
-`endif
-
- always @ (posedge SystemClock) begin
- if (|rxdatak16)
- $display($time,":datak symbol");
- end
-
- reg set_once;
- //simulation short ts1 sets
-`ifdef REAL_RTL
- always @ (posedge SystemClock) begin
- if (dut.phy_layer_top_inst.send_ts1 & ~set_once) begin
- force dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count = 10'b1111000000;
- set_once <= #1 1'b1;
-
- end
- else begin
- release dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count;
- if (dut.phy_layer_top_inst.ltssm_32bit_inst.start_link_training_pm) begin
- set_once <= #1 1'b0;
- end
- end
- end // always @ (posedge ti_phy_top_inst.clk_125mhz)
-`endif
-
- initial begin
- //****************************************************************************************
- //force scramble bypass until the tb can scramble and de-scramble data.
- //force dut.phy_layer_top_inst.make_rxdata_path16.scramble16_inst.scram_bypass = 2'b11;
- //force dut.phy_layer_top_inst.make_tx_data_path16.scramble16_inst.scram_bypass = 2'b11;
- //****************************************************************************************
- set_once = 0;
- SystemClock = 0;
- forever begin
- #(simulation_cycle/2)
- SystemClock = ~SystemClock;
- end
-
- end
-
- initial begin
- $fsdbDumpfile("vera_test.fsdb");
- $fsdbDumpvars(dut);
- end
-
-
-
-endmodule
Index: tags/gutzlogic_v_0/ti_phy_top.v
===================================================================
--- tags/gutzlogic_v_0/ti_phy_top.v (revision 7)
+++ tags/gutzlogic_v_0/ti_phy_top.v (nonexistent)
@@ -1,200 +0,0 @@
-// ===========================================================================
-// File : ti_phy_top.v
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-// Please contact www.gutzlogic.com for details.
-// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
-//
-// ===========================================================================
-//
-// $Id: ti_phy_top.v,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file is non-synthesizable rtl file to demonstrate TS1's.
-// Insert your own RTL design here. It has dummy signals for a sram if that
-// can be ignored.
-// ===========================================================================
-// ===========================================================================
-
-module ti_phy_top (/*AUTOARG*/
- // Outputs
- LED, txclk, txdata16, txdatak16, txidle16, rxdet_loopb, txcomp,
- rxpol, phy_reset_n, pwrdwn, sram_addr, sram_adscn, sram_adspn,
- sram_advn, sram_ben, sram_ce, sram_clk, sram_gwn, sram_mode,
- sram_oen, sram_wen, sram_zz,
- // Inouts
- sram_data,
- // Inputs
- clk_50mhz, PUSH_BUTTON, FPGA_RESET_n, rxclk, rxdata16, rxdatak16,
- rxvalid16, rxidle16, rxidle, rxstatus, phystatus
- );
- //****************************************************************************************
- //TI PHY interface
- //****************************************************************************************
- //debug ports
- input clk_50mhz;
- input [1:0] PUSH_BUTTON;
- output [7:0] LED;
- reg [7:0] LED;
- input FPGA_RESET_n;
- //****************************************************************************************
- //Phillips PHY interface
- output txclk; //source synch 250 Mhz transmit clock from MAC.
- wire txclk;
-
- output [15:0] txdata16;
- reg [15:0] txdata16;
- output [1:0] txdatak16;
- reg [1:0] txdatak16;
- output txidle16; //forces tx output to electrical idle. txidle should be asserted while in power states p0 and p1.
- reg txidle16;
- input rxclk; //source synch 250 clk for received data.
- input [15:0] rxdata16;
- input [1:0] rxdatak16;
- input rxvalid16;
- output rxdet_loopb; //used to tell the phy to begin
- reg rxdet_loopb;
- input rxidle16;
- input rxidle; //indicates receiver detection of an electrical idle; This is a synchronous signal.
- input [2:0] rxstatus; //encodes receiver status and error codes.
-
- input phystatus; //used to communicate completion of several phy functions.
- output txcomp; //used when transmitting the compliance pattern; high-level sets the running disparity to negative.
- reg txcomp;
- output rxpol; //signals the phy to perform a polarity inversion on the receive data; low = no polarity inversion; high = polarity inversion.
- reg rxpol;
- output phy_reset_n; //phy reset active low
- reg phy_reset_n;
- output [1:0] pwrdwn;
- reg [1:0] pwrdwn;
-
- //****************************************************************************************
- //SRAM Interface
- output [16:0] sram_addr;
- reg [16:0] sram_addr;
- output sram_adscn;
- reg sram_adscn;
- output sram_adspn;
- reg sram_adspn;
- output sram_advn;
- reg sram_advn;
- output [3:0] sram_ben;
- reg [3:0] sram_ben;
- output [2:0] sram_ce;
- reg [2:0] sram_ce;
- output sram_clk;
- reg sram_clk;
- output sram_gwn;
- reg sram_gwn;
- output sram_mode;
- reg sram_mode;
- output sram_oen;
- reg sram_oen;
- output sram_wen;
- reg sram_wen;
- output sram_zz;
- reg sram_zz;
- inout [35:0] sram_data;
-
-
- assign txclk = rxclk;
- reg continue;
-
- initial begin
- LED <= 'b0;
- txdata16 <= 15'b0;
- txdatak16 <= 2'b0;
- txidle16 <= 1'b0;
- pwrdwn <= 2'b0;
- phy_reset_n <= 1'b0;
- rxpol <= 1'b0;
- txcomp <= 1'b0;
- rxdet_loopb <= 1'b0;
- phy_reset_n <= 1'b0;
- //ignore these signals
- sram_addr <= 'b0;
- sram_adscn <= 'b0;
- sram_adspn <= 'b0;
- sram_advn <= 'b0;
- sram_ben <= 'b0;
- sram_ce <= 'b0;
- sram_clk <= 'b0;
- sram_gwn <= 'b0;
- sram_mode <= 'b0;
- sram_oen <= 'b0;
- sram_wen <= 'b0;
- sram_zz <= 'b0;
- //sram_data <= 'b0;
- continue <= 1'b1;
- #100;
- phy_reset_n <= 1'b1;
- sample_ts1();
- end
-
- task sample_ts1;
- begin
- pwrdwn <= 2'b10;
- @ (negedge rxclk);
- wait (phystatus == 0); //indicate that the pll is locked.
- repeat (20) @ (negedge rxclk);
- rxdet_loopb <= 1'b1;
- wait (phystatus == 1'b1 && rxstatus == 3'b11); //receiver detect
- repeat (5) @ (negedge rxclk);
- rxdet_loopb <= 1'b0;
- repeat (2) @ (negedge rxclk);
- pwrdwn <= 2'b0;
- wait (phystatus == 1'b0);
- wait (phystatus == 1'b1 && rxstatus == 4'b100); //power change accept
- repeat (100) @ (negedge rxclk);
-
- while (continue == 1) begin
- //start sending ts1;
- @ (negedge rxclk);
- txdatak16 <= 2'b11;
- txdata16 <= 16'hf7bc; //PAD LINK,COM
- @ (negedge rxclk);
- txdatak16 <= 2'b01;
- txdata16 <= 16'hf0f7; //NFST,PAD LANE
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h02; //training control Rate ID
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- //add sending ts2;
- //add link and lane
- end // while (continue == 1)
- end
- endtask // sample_ts1
-
-
-
-
-
-
-endmodule
-
-
-// Local Variables:
-// verilog-library-directories:("." "./dcm" "./ddr_div2" "./single_dcm" "./dll" "./tl")
-// End:
\ No newline at end of file
Index: tags/gutzlogic_v_0/pcie_tlp_packet.vri
===================================================================
--- tags/gutzlogic_v_0/pcie_tlp_packet.vri (revision 7)
+++ tags/gutzlogic_v_0/pcie_tlp_packet.vri (nonexistent)
@@ -1,465 +0,0 @@
-// ===========================================================================
-// File : pcie_tlp_packet.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: pcie_tlp_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file is a class of pcie packet can be used for all TLP
-// packet types.
-//
-// ===========================================================================
-// ===========================================================================
-#include
-
-class pcie_tlp_packet {
- bit [15:0] sequence_num;
- bit [4:0] type;
- bit [1:0] fmt;
- bit [9:0] length;
- bit [2:0] tc;
- bit [1:0] attr;
- bit ep;
- bit td;
- bit [63:0] address; //used for multiple purposes.
- bit [15:0] req_id;
- bit [7:0] tag;
- bit [3:0] first_be;
- bit [3:0] last_be;
- //completion fields
- bit [15:0] completer_id;
- bit [11:0] byte_count;
- bit bcm;
- bit [2:0] cmp_status;
- bit [127:0] header;
- bit [31:0] lcrc;
- bit [31:0] data [];
-
- //methods
- task new(
- bit [11:0] ic_sequence_num = 12'b0,
- bit [4:0] ic_type = 5'h0,
- bit [1:0] ic_fmt = 2'h0,
- bit [9:0] ic_length = 10'h0,
- bit [2:0] ic_tc = 3'h0,
- bit [1:0] ic_attr = 2'h0,
- bit ic_ep = 1'h0,
- bit ic_td = 1'h0,
- bit [63:0] ic_address = 64'h0,
- bit [15:0] ic_req_id = 16'h0,
- bit [7:0] ic_tag = 8'h0,
- bit [3:0] ic_first_be = 4'hf,
- bit [3:0] ic_last_be = 4'hf,
- //completion fields
- bit [15:0] ic_completer_id = 16'h0,
- bit [11:0] ic_byte_count = 12'h0,
- bit ic_bcm = 1'h0,
- bit [2:0] ic_cmp_status = 3'h0,
- bit [31:0] ic_config_data = 32'b0) {
-
- sequence_num = {4'b0,ic_sequence_num};
- type = ic_type;
- fmt = ic_fmt;
- length = ic_length;
- tc = ic_tc;
- attr = ic_attr;
- ep = ic_ep;
- td = ic_td;
- address = ic_address;
- req_id = ic_req_id;
- tag = ic_tag;
- first_be = ic_first_be;
- last_be = ic_last_be;
- completer_id = ic_completer_id;
- byte_count = ic_byte_count;
- bcm = ic_bcm;
- cmp_status = ic_cmp_status;
- data[0] = ic_config_data;
- printf ("new seq(%0h),type(%0h),fmt(%0h),length(%0h),tc(%0h),attr(%0h),ep(%0h),td(%0h),addr(%0h),req_id(%0h),tag(%0h),fbe(%0h),lbe(%0h),cmp_id(%0h),bc(%0h),bcm(%0h),cmp_stat(%0h),cfgwr data(%0h)\n",
- ic_sequence_num,
- ic_type,
- ic_fmt,
- ic_length,
- ic_tc,
- ic_attr,
- ic_ep,
- ic_td,
- ic_address,
- ic_req_id,
- ic_tag,
- ic_first_be,
- ic_last_be,
- ic_completer_id,
- ic_byte_count,
- ic_bcm,
- ic_cmp_status,
- ic_config_data
- );
- }
-
- task build_packet (string pkt_type = "posted") {
- integer reserved = 0;
- integer i;
- bit [5:0] register_num;
- bit [3:0] ext_register_num;
- bit [2:0] function_number;
- bit [4:0] device_number;
- bit [7:0] bus_number;
- bit [6:0] lower_addr = address[6:0];
-
- bus_number = address[31:24];
- function_number = address[23:19];
- device_number = address[18:16];
- ext_register_num = address[11:8];
- register_num = address[7:2];
-
- if (pkt_type == "posted" || pkt_type == "nonposted") {
- //dw1
- header[4:0] = type;
- header[6:5] = fmt;
- header[7] = reserved;
- header[11:8] = reserved;
- header[14:12] = tc;
- header[15] = reserved;
- header[17:16] = length[9:8];
- header[19:18] = reserved;
- header[21:20] = attr;
- header[22] = ep;
- header[23] = td;
- header[31:24] = length[7:0];
- //dw2
- header[39:32] = req_id[15:8];
- header[47:40] = req_id[7:0];
- header[55:48] = tag;
- header[59:56] = first_be;
- header[63:60] = last_be;
- //dw3&4
- //configurations
- if (type == 5'b00100 || type == 5'b00101) {
- header[127:64] = {32'b0,
- register_num[5:0],2'b0,
- 4'b0,ext_register_num[3:0],
- device_number[4:0],function_number[2:0],
- bus_number[7:0]};
- }
- else if (fmt[0] == 1'b1) {
- header[127:64] = {address[7:2],2'b0,address[15:8],
- address[23:16],address[31:24],
- address[39:32],address[47:40],
- address[55:48],address[63:56]};
- }
- else {
- header[127:64] = {32'b0,address[7:2],2'b0,address[15:8],
- address[23:16],address[31:24]};
- }
- }
- else if (pkt_type == "completion") {
- //dw1
- header[4:0] = type;
- header[6:5] = fmt;
- header[7] = reserved;
- header[11:8] = reserved;
- header[14:12] = tc;
- header[15] = reserved;
- header[17:16] = length[9:8];
- header[19:18] = reserved;
- header[21:20] = attr;
- header[22] = ep;
- header[23] = td;
- header[31:24] = length[7:0];
- //dw 2
- header[39:32] = completer_id[15:8];
- header[47:40] = completer_id[7:0];
- header[51:48] = byte_count[11:8];
- header[52] = bcm;
- header[55:53] = cmp_status;
- header[63:56] = byte_count[7:0];
- //dw3
- header[71:64] = req_id[15:8];
- header[79:72] = req_id[7:0];
- header[87:80] = tag;
- header[95:88] = {1'b0,lower_addr};
- //dw4
- header[127:96] = 32'b0;
- }
- if (type[4:1] != 5'b0010 && fmt[1]) {
- for (i=0;i
-
-class pcie_phy_packet {
- bit [7:0] com;
- bit [7:0] link;
- bit [7:0] lane;
- bit [7:0] n_fts;
- bit [7:0] rateid;
- bit [7:0] train_cntrl;
- bit [7:0] ts_id;
- bit [7:0] idle;
- bit [7:0] skp;
- bit [7:0] fts;
- integer length;
- bit [17:0] temp_packet[];
-
-
- //methods
- task new(
- bit [7:0] ic_link = 8'hf7,
- bit [7:0] ic_lane = 8'hf7,
- bit [7:0] ic_nfts = 8'hff,
- bit [7:0] ic_rateid = 8'h2,
- bit [7:0] ic_train_cntrl = 8'h0,
- bit [7:0] ic_ts_id = 8'h4a) {
-
- link = ic_link;
- lane = ic_lane;
- n_fts = ic_nfts;
- rateid = ic_rateid;
- train_cntrl = ic_train_cntrl;
- ts_id = ic_ts_id;
- com = 8'hbc;
- idle = 8'h7c;
- skp = 8'h1c;
- fts = 8'h3c;
- }
-
- task build_packet (string pkt_type = "ts") {
- if (pkt_type == "ts") {
- length = 8;
- if (link == 8'hf7) temp_packet[0] = {2'b11,link,com};
- else temp_packet[0] = {2'b01,link,com};
- if (lane == 8'hf7) temp_packet[1] = {2'b1,n_fts,lane};
- else temp_packet[1] = {2'b0,n_fts,lane};
- temp_packet[2] = {2'b0,train_cntrl,rateid};
- temp_packet[3] = {2'b0,ts_id,ts_id};
- temp_packet[4] = {2'b0,ts_id,ts_id};
- temp_packet[5] = {2'b0,ts_id,ts_id};
- temp_packet[6] = {2'b0,ts_id,ts_id};
- temp_packet[7] = {2'b0,ts_id,ts_id};
- printf ("building training set packet (%0h)\n",
- {temp_packet[7][15:0],temp_packet[6][15:0],
- temp_packet[5][15:0],temp_packet[4][15:0],
- temp_packet[3][15:0],temp_packet[2][15:0],
- temp_packet[1][15:0],temp_packet[0][15:0]});
- }
- else if (pkt_type == "eidle") {
- length = 2;
- temp_packet[0] = {2'b11,idle,com};
- temp_packet[1] = {2'b11,idle,idle};
- printf ("building eidle packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
- }
- else if (pkt_type == "skip"){
- length = 2;
- temp_packet[0] = {2'b11,skp,com};
- temp_packet[1] = {2'b11,skp,skp};
- printf ("building skip packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
- }
- else if (pkt_type == "fast_ts"){
- length = 2;
- temp_packet[0] = {2'b11,fts,com};
- temp_packet[1] = {2'b11,fts,fts};
- printf ("building fts packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
- }
-
- }
-}
Index: tags/gutzlogic_v_0/tlp_gen.vri
===================================================================
--- tags/gutzlogic_v_0/tlp_gen.vri (revision 7)
+++ tags/gutzlogic_v_0/tlp_gen.vri (nonexistent)
@@ -1,186 +0,0 @@
-// ===========================================================================
-// File : tlp_gen.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-// Please contact www.gutzlogic.com for details.
-// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
-// ===========================================================================
-//
-// $Id: tlp_gen.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file generates cfgrd/wr memrd/wr.
-//
-// ===========================================================================
-// ===========================================================================
-#include
-#define STP_s 8'hfb
-#define EDB 8'hfe
-task tlp_gen() {
-
- bit [15:0] req_id;
- bit [7:0] busnum;
- bit [7:0] reg_num;
- bit [3:0] first_be;
- bit [3:0] last_be;
- bit [63:0] address;
- bit [9:0] length;
- bit [31:0] data;
- bit [7:0] tag;
-
- //cfgwr(reg_num,first_be,req_id,tag,data);
- sequence_id = 0; reg_num=0;first_be=4'hf;req_id=0101;tag=1;busnum=1;
- printf ("read vendor id\n");
- cfgrd(reg_num,first_be,req_id,tag,busnum);
- sequence_id++; reg_num='h5;first_be=4'hf;req_id=0101;tag++;busnum=1;
- printf ("write base address 1 register\n");
- cfgwr(reg_num,first_be,req_id,tag,busnum,32'hba120000);
- sequence_id++;address = 64'hba120000;length=10'h5;first_be=4'hf;last_be=4'hf;req_id=16'h0100;tag++;
- memwr(address,length,first_be,last_be,req_id,tag);
- //memrd(address,length,first_be,last_be,req_id,tag);
-}
-
-task cfgrd (bit [7:0] reg_num,
- bit [3:0] first_be,
- bit [15:0] req_id,
- bit [7:0] tag,
- bit [7:0] busnum) {
-
- integer index;
- bit [63:0] address = {32'b0,busnum,5'b1,3'b0,8'b0,reg_num,2'b0};
-
- tlp_packet = new(sequence_id,5'b00100,2'b0,10'h1,*,*,*,*,
- address,req_id,tag,first_be,4'b0,*,*,*,*,*);
- tlp_packet.build_packet("nonposted");
- printf ("header %0h \n",tlp_packet.header);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- //sequence id
- printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
- mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
- printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
- mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
- //loop for sending out packet
- for (index=1;index<3;index++) {
- printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
- printf("%0h put into mailbox index+1 = %0d\n",{2'b00,packet_array[index+1][7:0],packet_array[index][31:24]},index+1);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index+1][7:0],packet_array[index][31:24]});
- }
- printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
- printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]},index);
- mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]});
- printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[23:8]});
- printf("%0h put into mailbox\n",{2'b10,END_s,tlp_packet.lcrc[31:24]});
- mailbox_put(rx_data_mailbox, {2'b10,END_s,tlp_packet.lcrc[31:24]});
- semaphore_put (my_semaphore, 1);
-}
-
-task cfgwr (bit [7:0] reg_num,
- bit [3:0] first_be,
- bit [15:0] req_id,
- bit [7:0] tag,
- bit [7:0] busnum,
- bit [31:0] data) {
-
- integer index;
- //bus num,device num,function num,ext reg reg_num;
- bit [63:0] address = {32'b0,busnum,5'b1,3'b0,8'b0,reg_num,2'b0};
- printf ("cfgwr data = %0h\n",data);
- tlp_packet = new(sequence_id,5'b00100,2'b10,10'h1,*,*,*,*,
- address,req_id,tag,first_be,4'b0,*,*,*,*,data);
- tlp_packet.build_packet("nonposted");
- printf ("header %0h \n",tlp_packet.header);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- //sequence id
- printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
- mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
- printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
- mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
- //loop for sending out packet
- for (index=1;index<4;index++) {
- printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
- printf("%0h put into mailbox index+1 = %0d\n",{2'b00,packet_array[index+1][7:0],packet_array[index][31:24]},index+1);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index+1][7:0],packet_array[index][31:24]});
- }
- printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
- printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]},index);
- mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]});
- printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[23:8]});
- printf("%0h put into mailbox\n",{2'b10,END_s,tlp_packet.lcrc[31:24]});
- mailbox_put(rx_data_mailbox, {2'b10,END_s,tlp_packet.lcrc[31:24]});
- semaphore_put (my_semaphore, 1);
-}
-
-
-task memwr (bit [63:0] address,
- bit [9:0] length,
- bit [3:0] first_be,
- bit [3:0] last_be,
- bit [15:0] req_id,
- bit [7:0] tag){
- integer index;
- bit seq_header;
- integer total_length;
- bit[1:0] fmt;
- integer hdr_dw;
- fmt = |address[63:32] == 1 ? 2'b11 : 2'b10;
- hdr_dw = |address[63:32] == 1 ? 4 : 3;
- total_length = hdr_dw + length; //add td when ready
- //bus num,device num,function num,ext reg reg_num;
- tlp_packet = new(sequence_id,5'b00000,fmt,length,*,*,*,*,
- address,req_id,tag,first_be,last_be,*,*,*,*,*);
- tlp_packet.build_packet("nonposted");
- printf ("header %0h \n",tlp_packet.header);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- //sequence id
- printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
- mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
- printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
- mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
- //loop for sending out packet
- for (index=1;index
-#define COM_s 8'hbc
-#define SKP_s 8'h1c
-#define IDLE_s 8'h7c
-#define FTS_s 8'h3c
-#define STP_s 8'hfb
-#define SDP_s 8'h5c
-#define EDB 8'hfe
-#define END_s 8'hfd
-
-task link_training () {
-
- fork
- send_ts();
- receive_ts();
- join none
-}
-
-
-task send_ts( ) {
- integer index;
- string pkt_type;
- pkt_type = "ts";
- //ti_phy_top.t1_count == 9'hff;
- ti_phy_top.rxvalid16 = 1'b1;
- wait_var(phy_rdy);
-
- printf ("send_ts1 = %d \n",send_ts1);
- while (LINK_UP == 0) {
- if (send_ts1 == 1) {
- ts2_cycle_cnt = 1;
- //printf ("number of ts dut sent %d \n",ti_phy_top.t1_count);
- printf ("ts #%0d ts 1's ",ts1_cycle_cnt++);
- pkt_type = "ts";
- training_set = new(link,lane,*,*,*,*);
- training_set.build_packet(pkt_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for (index = 0; index < training_set.length; index ++) {
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = training_set.temp_packet[index][17:16];
- //ti_phy_top.rxdata16 = training_set.temp_packet[index][15:0];
- //adding mailbox
- mailbox_put (rx_data_mailbox, {training_set.temp_packet[index][17:16],training_set.temp_packet[index][15:0]});
- }
- semaphore_put (my_semaphore, 1);
- }
- else if (send_ts2 == 1){
- ts1_cycle_cnt = 1;
- printf ("ts #%0d ts 2's ",ts2_cycle_cnt++);
- pkt_type = "ts";
- training_set = new(lane,link,*,*,*,'h45);
- training_set.build_packet(pkt_type);
- for (index = 0; index < training_set.length; index ++) {
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = training_set.temp_packet[index][17:16];
- //ti_phy_top.rxdata16 = training_set.temp_packet[index][15:0];
- //adding mailbox
- mailbox_put (rx_data_mailbox, {training_set.temp_packet[index][17:16],training_set.temp_packet[index][15:0]});
- }
- }
- }
-
- printf ("LINK UP(%0d) !!!!!!!!!!!\n",LINK_UP);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
-}
-
-task receive_ts () {
- integer ret;
- integer ts1_count=0;
- integer ts2_count=0;
- integer ts1_link_count = 0;
- integer ts1_lane_count = 0;
- integer ts2_lane_link_count = 0;
- integer send_ts1_with_link, send_ts1_with_link_lane, send_ts2_with_link_lane;
- bit [127:0] receive_phy_packet;
-
- send_ts1 = 1;
- send_ts2 = 0;
- send_ts1_with_link = 0;
- send_ts1_with_link_lane = 0;
- send_ts2_with_link_lane = 0;
- while (1) {
- ret = mailbox_get (WAIT,phy_mailbox,receive_phy_packet,CHECK);
- //printf ("Recieved PHY PACKET (%0h) added to phy mailbox\n",receive_phy_packet);
- if (receive_phy_packet == 127'h454545454545454545450002f0f7f7bc) {
- printf ("Recieved TS 2 PHY PACKET\n");
- ts2_count++;
- }
- if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f0f7f7bc){
- printf ("Recieved TS 1 PHY PACKET\n");
- ts1_count++;
- }
- if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f0f701bc) {
- printf ("Recieved TS 1 link accept PHY PACKET\n");
- ts1_link_count++;
- }
- if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f00101bc) {
- printf ("Recieved TS 1 lane and link accept PHY PACKET\n");
- ts1_lane_count++;
- }
- if (receive_phy_packet == 127'h454545454545454545450002f00101bc) {
- printf ("Recieved TS 1 lane and link accept PHY PACKET\n");
- ts2_lane_link_count++;
- }
-
- //printf ("send_ts2_with_link_lane(%0d)send_ts1_with_link_lane(%0d)send_ts1_with_link(%0d)send_ts2(%0d)send_ts1(%0d)\n",
- // send_ts2_with_link_lane,send_ts1_with_link_lane,send_ts1_with_link,send_ts2,send_ts1 );
- //printf ("ts2_lane_link_count(%0d)ts1_lane_count(%0d)ts1_link_count(%0d)ts1_count(%0d)ts2_count(%0d)\n",
- // ts2_lane_link_count,ts1_lane_count,ts1_link_count,ts1_count,ts2_count);
-
- if (send_ts2_with_link_lane && ts2_cycle_cnt > 16 && ts2_lane_link_count > 15) {
- //clear all signals if we get a ts1 with pad
- if (ts1_count > 0) {
- send_ts1 = 1;
- send_ts2 = 0;
- send_ts2_with_link_lane = 0;
- send_ts1_with_link_lane = 0;
- send_ts1_with_link = 0;
- LINK_UP = 0;
- ts2_lane_link_count = 0;
- ts1_lane_count = 0;
- ts1_link_count = 0;
- ts1_count = 0;
- ts2_count = 0;
- }
- else {
- send_ts1 = 0;
- send_ts2 = 0;
- LINK_UP = 1;
- ts1_lane_count = 0;
- ts1_link_count = 0;
- ts1_count = 0;
- ts2_count = 0;
-
- }
-
- }
- else if (send_ts1_with_link_lane){
- if (ts1_cycle_cnt > 16 && ts1_lane_count >16 ) {
- send_ts1 = 0;
- send_ts2 = 1;
- link = 8'b1;
- lane = 8'b1;
- send_ts2_with_link_lane = 1;
- ts1_lane_count = 0;
- ts1_link_count = 0;
- ts1_count = 0;
- ts2_count = 0;
- }
- }
- else if (send_ts1_with_link) {
- if (ts1_cycle_cnt > 16 && ts1_link_count > 16) {
- send_ts1 = 1;
- send_ts2 = 0;
- link = 8'b1;
- lane = 8'b1;
- send_ts1_with_link_lane = 1;
- }
- }
- //send at least 16 ts 2
- else if (send_ts2) {
- if (ts2_count > 16 && ts2_cycle_cnt > 16) {
- send_ts1 = 1;
- send_ts2 = 0;
- send_ts1_with_link = 1;
- link = 8'b1;
- lane = 8'hf7;
- }
- }
- //send at least 100 ts 1's
- else if (ts2_count > 16 && ts1_cycle_cnt > 100) {
- send_ts1 = 0;
- send_ts2 = 1;
- link = 'hf7;
- lane = 'hf7;
- }
- else {
- send_ts1 = 1;
- send_ts2 = 0;
- link = 'hf7;
- lane = 'hf7;
- }
- }
-}
-
Index: trunk/ti_phy_top.test_top.v
===================================================================
--- trunk/ti_phy_top.test_top.v (revision 7)
+++ trunk/ti_phy_top.test_top.v (nonexistent)
@@ -1,285 +0,0 @@
-// ===========================================================================
-// File : ti_phy_top.test_top.v
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-// Please contact www.gutzlogic.com for details.
-// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
-// ===========================================================================
-//
-// $Id: ti_phy_top.test_top.v,v 1.3 2008-01-15 03:25:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.2 2007/12/05 23:00:33 cmagleby
-// add sram for real rtl
-//
-// Revision 1.1.1.1 2007/12/05 18:37:07 cmagleby
-// importing tb files
-//
-//
-// ===========================================================================
-// Function : This is the top level testbench file.
-//
-// ===========================================================================
-// ===========================================================================
-`timescale 1 ns/100 ps
-module ti_phy_top_test_top;
- parameter simulation_cycle = 8;
-
- reg SystemClock;
- wire clk_50mhz;
- wire [1:0] PUSH_BUTTON;
- wire FPGA_RESET_n;
- wire PERST_n;
- wire rxclk;
- wire [15:0] rxdata16;
- wire [1:0] rxdatak16;
- wire rxvalid16;
- wire rxidle16;
- wire [2:0] rxstatus;
- wire phystatus;
- wire [7:0] LED;
- wire txclk;
- wire [15:0] txdata16;
- wire [1:0] txdatak16;
- wire txidle16;
- wire rxdet_loopb;
- wire txcomp;
- wire rxpol;
- wire phy_reset_n;
- wire [1:0] pwrdwn;
- wire [16:0] sram_addr;
- wire sram_adscn;
- wire sram_adspn;
- wire sram_advn;
- wire [3:0] sram_ben;
- wire [2:0] sram_ce;
- wire sram_clk;
- wire sram_gwn;
- wire sram_mode;
- wire sram_oen;
- wire sram_wen;
- wire sram_zz;
- wire [35:0] sram_data;
- assign rxclk = SystemClock;
- assign PERST_n = FPGA_RESET_n;
-
-`ifdef SYNOPSYS_NTB
- ti_phy_top_test vshell(
- .SystemClock (SystemClock),
- .\ti_phy_top.clk_50mhz (clk_50mhz),
- .\ti_phy_top.PUSH_BUTTON (PUSH_BUTTON),
- .\ti_phy_top.FPGA_RESET_n (FPGA_RESET_n),
- .\ti_phy_top.PERST_n (PERST_n),
- .\ti_phy_top.rxclk (rxclk),
- .\ti_phy_top.rxdata16 (rxdata16),
- .\ti_phy_top.rxdatak16 (rxdatak16),
- .\ti_phy_top.rxvalid16 (rxvalid16),
- .\ti_phy_top.rxidle16 (rxidle16),
- .\ti_phy_top.rxstatus (rxstatus),
- .\ti_phy_top.phystatus (phystatus),
- .\ti_phy_top.sram_data (sram_data),
- .\ti_phy_top.LED (LED),
- .\ti_phy_top.txclk (txclk),
- .\ti_phy_top.txdata16 (txdata16),
- .\ti_phy_top.txdatak16 (txdatak16),
- .\ti_phy_top.txidle16 (txidle16),
- .\ti_phy_top.rxdet_loopb (rxdet_loopb),
- .\ti_phy_top.txcomp (txcomp),
- .\ti_phy_top.rxpol (rxpol),
- .\ti_phy_top.phy_reset_n (phy_reset_n),
- .\ti_phy_top.pwrdwn (pwrdwn),
- .\ti_phy_top.sram_addr (sram_addr),
- .\ti_phy_top.sram_adscn (sram_adscn),
- .\ti_phy_top.sram_adspn (sram_adspn),
- .\ti_phy_top.sram_advn (sram_advn),
- .\ti_phy_top.sram_ben (sram_ben),
- .\ti_phy_top.sram_ce (sram_ce),
- .\ti_phy_top.sram_clk (sram_clk),
- .\ti_phy_top.sram_gwn (sram_gwn),
- .\ti_phy_top.sram_mode (sram_mode),
- .\ti_phy_top.sram_oen (sram_oen),
- .\ti_phy_top.sram_wen (sram_wen),
- .\ti_phy_top.sram_zz (sram_zz)
- );
-`else
-
- vera_shell vshell(
- .SystemClock (SystemClock),
- .ti_phy_top_clk_50mhz (clk_50mhz),
- .ti_phy_top_PUSH_BUTTON (PUSH_BUTTON),
- .ti_phy_top_FPGA_RESET_n (FPGA_RESET_),
- .ti_phy_top_rxclk (rxclk),
- .ti_phy_top_rxdata16 (rxdata16),
- .ti_phy_top_rxdatak16 (rxdatak16),
- .ti_phy_top_rxvalid16 (rxvalid16),
- .ti_phy_top_rxidle16 (rxidle16),
- .ti_phy_top_rxstatus (rxstatus),
- .ti_phy_top_phystatus (phystatus),
- .ti_phy_top_sram_data (sram_data),
- .ti_phy_top_LED (LED),
- .ti_phy_top_txclk (txclk),
- .ti_phy_top_txdata16 (txdata16),
- .ti_phy_top_txdatak16 (txdatak16),
- .ti_phy_top_txidle16 (txidle16),
- .ti_phy_top_rxdet_loopb (rxdet_loopb),
- .ti_phy_top_txcomp (txcomp),
- .ti_phy_top_rxpol (rxpol),
- .ti_phy_top_phy_reset_n (phy_reset_n),
- .ti_phy_top_pwrdwn (pwrdwn),
- .ti_phy_top_sram_addr (sram_addr),
- .ti_phy_top_sram_adscn (sram_adscn),
- .ti_phy_top_sram_adspn (sram_adspn),
- .ti_phy_top_sram_advn (sram_advn),
- .ti_phy_top_sram_ben (sram_ben),
- .ti_phy_top_sram_ce (sram_ce),
- .ti_phy_top_sram_clk (sram_clk),
- .ti_phy_top_sram_gwn (sram_gwn),
- .ti_phy_top_sram_mode (sram_mode),
- .ti_phy_top_sram_oen (sram_oen),
- .ti_phy_top_sram_wen (sram_wen),
- .ti_phy_top_sram_zz (sram_zz)
- );
-`endif
-
-
-
-`ifdef emu
- /* DUT is in emulator, so not instantiated here */
-`else
- ti_phy_top dut(
- .clk_50mhz (clk_50mhz),
- .PUSH_BUTTON (PUSH_BUTTON),
- .FPGA_RESET_n (FPGA_RESET_n),
- .PERST_n (PERST_n),
- .rxclk (rxclk),
- .rxdata16 (rxdata16),
- .rxdatak16 (rxdatak16),
- .rxvalid16 (rxvalid16),
- .rxidle16 (rxidle16),
- .rxstatus (rxstatus),
- .phystatus (phystatus),
- .sram_data (sram_data),
- .LED (LED),
- .txclk (txclk),
- .txdata16 (txdata16),
- .txdatak16 (txdatak16),
- .txidle16 (txidle16),
- .rxdet_loopb (rxdet_loopb),
- .txcomp (txcomp),
- .rxpol (rxpol),
- .phy_reset_n (phy_reset_n),
- .pwrdwn (pwrdwn),
- .sram_addr (sram_addr),
- .sram_adscn (sram_adscn),
- .sram_adspn (sram_adspn),
- .sram_advn (sram_advn),
- .sram_ben (sram_ben),
- .sram_ce (sram_ce),
- .sram_clk (sram_clk),
- .sram_gwn (sram_gwn),
- .sram_mode (sram_mode),
- .sram_oen (sram_oen),
- .sram_wen (sram_wen),
- .sram_zz (sram_zz)
- );
-`endif
-
- always @ (posedge SystemClock) begin
- if (|rxdatak16)
- $display($time,":datak symbol");
- end
-
- reg set_once;
- //simulation short ts1 sets
-`ifdef REAL_RTL
- always @ (posedge SystemClock) begin
- if (dut.phy_layer_top_inst.send_ts1 & ~set_once) begin
- force dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count = 10'b1111000000;
- set_once <= #1 1'b1;
-
- end
- else begin
- release dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count;
- if (dut.phy_layer_top_inst.ltssm_32bit_inst.start_link_training_pm) begin
- set_once <= #1 1'b0;
- end
- end
- end // always @ (posedge ti_phy_top_inst.clk_125mhz)
-
- /* -----\/----- EXCLUDED -----\/-----
- idt71v25761s200 AUTO_TEMPLATE (
- .D (sram_data[31:0]),
- .DP (sram_data[35:32]),
- // Inputs
- .A (sram_addr),
- .oe_ (sram_oen),
- .ce_ (sram_ce[0]),
- .cs0 (sram_ce[1]),
- .cs1_ (sram_ce[2]),
- .lbo_ (sram_mode),
- .gw_ (sram_gwn),
- .bwe_ (sram_wen),
- .bw4_ (sram_ben[3]),
- .bw3_ (sram_ben[2]),
- .bw2_ (sram_ben[1]),
- .bw1_ (sram_ben[0]),
- .adsp_(sram_adspn),
- .adsc_(sram_adscn),
- .adv_ (sram_advn),
- .clk (sram_clk));
- -----/\----- EXCLUDED -----/\----- */
-
- idt71v25761s200 SRAM_MODEL_inst (/*AUTOINST*/
- // Inouts
- .D (sram_data[31:0]), // Templated
- .DP (sram_data[35:32]), // Templated
- // Inputs
- .A (sram_addr), // Templated
- .oe_ (sram_oen), // Templated
- .ce_ (sram_ce[0]), // Templated
- .cs0 (sram_ce[1]), // Templated
- .cs1_ (sram_ce[2]), // Templated
- .lbo_ (sram_mode), // Templated
- .gw_ (sram_gwn), // Templated
- .bwe_ (sram_wen), // Templated
- .bw4_ (sram_ben[3]), // Templated
- .bw3_ (sram_ben[2]), // Templated
- .bw2_ (sram_ben[1]), // Templated
- .bw1_ (sram_ben[0]), // Templated
- .adsp_(sram_adspn), // Templated
- .adsc_(sram_adscn), // Templated
- .adv_ (sram_advn), // Templated
- .clk (sram_clk)); // Templated
-
-`endif
-
- initial begin
- //****************************************************************************************
- //force scramble bypass until the tb can scramble and de-scramble data.
- //force dut.phy_layer_top_inst.make_rxdata_path16.scramble16_inst.scram_bypass = 2'b11;
- //force dut.phy_layer_top_inst.make_tx_data_path16.scramble16_inst.scram_bypass = 2'b11;
- //****************************************************************************************
- set_once = 0;
- SystemClock = 0;
- forever begin
- #(simulation_cycle/2)
- SystemClock = ~SystemClock;
- end
-
- end // initial begin
-
-`ifdef REAL_RTL
- initial begin
- $fsdbDumpfile("vera_test.fsdb");
- $fsdbDumpvars(dut);
- end
-`endif
-
-
-endmodule
Index: trunk/ti_phy_top.v
===================================================================
--- trunk/ti_phy_top.v (revision 7)
+++ trunk/ti_phy_top.v (nonexistent)
@@ -1,204 +0,0 @@
-// ===========================================================================
-// File : ti_phy_top.v
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-// Please contact www.gutzlogic.com for details.
-// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
-//
-// ===========================================================================
-//
-// $Id: ti_phy_top.v,v 1.2 2008-01-15 03:25:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.1.1.1 2007/12/05 18:37:06 cmagleby
-// importing tb files
-//
-//
-// ===========================================================================
-// Function : This file is non-synthesizable rtl file to demonstrate TS1's.
-// Insert your own RTL design here. It has dummy signals for a sram if that
-// can be ignored.
-// ===========================================================================
-// ===========================================================================
-
-module ti_phy_top (/*AUTOARG*/
- // Outputs
- LED, txclk, txdata16, txdatak16, txidle16, rxdet_loopb, txcomp,
- rxpol, phy_reset_n, pwrdwn, sram_addr, sram_adscn, sram_adspn,
- sram_advn, sram_ben, sram_ce, sram_clk, sram_gwn, sram_mode,
- sram_oen, sram_wen, sram_zz,
- // Inouts
- sram_data,
- // Inputs
- clk_50mhz, PUSH_BUTTON, FPGA_RESET_n, PERST_n, rxclk, rxdata16,
- rxdatak16, rxvalid16, rxidle16, rxidle, rxstatus, phystatus
- );
- //****************************************************************************************
- //TI PHY interface
- //****************************************************************************************
- //debug ports
- input clk_50mhz;
- input [1:0] PUSH_BUTTON;
- output [7:0] LED;
- reg [7:0] LED;
- input FPGA_RESET_n;
- input PERST_n;
- //****************************************************************************************
- //Phillips PHY interface
- output txclk; //source synch 250 Mhz transmit clock from MAC.
- wire txclk;
-
- output [15:0] txdata16;
- reg [15:0] txdata16;
- output [1:0] txdatak16;
- reg [1:0] txdatak16;
- output txidle16; //forces tx output to electrical idle. txidle should be asserted while in power states p0 and p1.
- reg txidle16;
- input rxclk; //source synch 250 clk for received data.
- input [15:0] rxdata16;
- input [1:0] rxdatak16;
- input rxvalid16;
- output rxdet_loopb; //used to tell the phy to begin
- reg rxdet_loopb;
- input rxidle16;
- input rxidle; //indicates receiver detection of an electrical idle; This is a synchronous signal.
- input [2:0] rxstatus; //encodes receiver status and error codes.
-
- input phystatus; //used to communicate completion of several phy functions.
- output txcomp; //used when transmitting the compliance pattern; high-level sets the running disparity to negative.
- reg txcomp;
- output rxpol; //signals the phy to perform a polarity inversion on the receive data; low = no polarity inversion; high = polarity inversion.
- reg rxpol;
- output phy_reset_n; //phy reset active low
- reg phy_reset_n;
- output [1:0] pwrdwn;
- reg [1:0] pwrdwn;
-
- //****************************************************************************************
- //SRAM Interface
- output [16:0] sram_addr;
- reg [16:0] sram_addr;
- output sram_adscn;
- reg sram_adscn;
- output sram_adspn;
- reg sram_adspn;
- output sram_advn;
- reg sram_advn;
- output [3:0] sram_ben;
- reg [3:0] sram_ben;
- output [2:0] sram_ce;
- reg [2:0] sram_ce;
- output sram_clk;
- reg sram_clk;
- output sram_gwn;
- reg sram_gwn;
- output sram_mode;
- reg sram_mode;
- output sram_oen;
- reg sram_oen;
- output sram_wen;
- reg sram_wen;
- output sram_zz;
- reg sram_zz;
- inout [35:0] sram_data;
-
-
- assign txclk = rxclk;
- reg continue;
-
- initial begin
- LED <= 'b0;
- txdata16 <= 15'b0;
- txdatak16 <= 2'b0;
- txidle16 <= 1'b0;
- pwrdwn <= 2'b0;
- phy_reset_n <= 1'b0;
- rxpol <= 1'b0;
- txcomp <= 1'b0;
- rxdet_loopb <= 1'b0;
- phy_reset_n <= 1'b0;
- //ignore these signals
- sram_addr <= 'b0;
- sram_adscn <= 'b0;
- sram_adspn <= 'b0;
- sram_advn <= 'b0;
- sram_ben <= 'b0;
- sram_ce <= 'b0;
- sram_clk <= 'b0;
- sram_gwn <= 'b0;
- sram_mode <= 'b0;
- sram_oen <= 'b0;
- sram_wen <= 'b0;
- sram_zz <= 'b0;
- //sram_data <= 'b0;
- continue <= 1'b1;
- #100;
- phy_reset_n <= 1'b1;
- sample_ts1();
- end
-
- task sample_ts1;
- begin
- pwrdwn <= 2'b10;
- @ (negedge rxclk);
- wait (phystatus == 0); //indicate that the pll is locked.
- repeat (20) @ (negedge rxclk);
- rxdet_loopb <= 1'b1;
- wait (phystatus == 1'b1 && rxstatus == 3'b11); //receiver detect
- repeat (5) @ (negedge rxclk);
- rxdet_loopb <= 1'b0;
- repeat (2) @ (negedge rxclk);
- pwrdwn <= 2'b0;
- wait (phystatus == 1'b0);
- wait (phystatus == 1'b1 && rxstatus == 4'b100); //power change accept
- repeat (100) @ (negedge rxclk);
-
- while (continue == 1) begin
- //start sending ts1;
- @ (negedge rxclk);
- txdatak16 <= 2'b11;
- txdata16 <= 16'hf7bc; //PAD LINK,COM
- @ (negedge rxclk);
- txdatak16 <= 2'b01;
- txdata16 <= 16'hf0f7; //NFST,PAD LANE
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h02; //training control Rate ID
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- @ (negedge rxclk);
- txdatak16 <= 2'b0;
- txdata16 <= 16'h4a4a; //ts id
- //add sending ts2;
- //add link and lane
- end // while (continue == 1)
- end
- endtask // sample_ts1
-
-
-
-
-
-
-endmodule
-
-
-// Local Variables:
-// verilog-library-directories:("." "./dcm" "./ddr_div2" "./single_dcm" "./dll" "./tl")
-// End:
\ No newline at end of file
Index: trunk/pcie_tlp_packet.vri
===================================================================
--- trunk/pcie_tlp_packet.vri (revision 7)
+++ trunk/pcie_tlp_packet.vri (nonexistent)
@@ -1,465 +0,0 @@
-// ===========================================================================
-// File : pcie_tlp_packet.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: pcie_tlp_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file is a class of pcie packet can be used for all TLP
-// packet types.
-//
-// ===========================================================================
-// ===========================================================================
-#include
-
-class pcie_tlp_packet {
- bit [15:0] sequence_num;
- bit [4:0] type;
- bit [1:0] fmt;
- bit [9:0] length;
- bit [2:0] tc;
- bit [1:0] attr;
- bit ep;
- bit td;
- bit [63:0] address; //used for multiple purposes.
- bit [15:0] req_id;
- bit [7:0] tag;
- bit [3:0] first_be;
- bit [3:0] last_be;
- //completion fields
- bit [15:0] completer_id;
- bit [11:0] byte_count;
- bit bcm;
- bit [2:0] cmp_status;
- bit [127:0] header;
- bit [31:0] lcrc;
- bit [31:0] data [];
-
- //methods
- task new(
- bit [11:0] ic_sequence_num = 12'b0,
- bit [4:0] ic_type = 5'h0,
- bit [1:0] ic_fmt = 2'h0,
- bit [9:0] ic_length = 10'h0,
- bit [2:0] ic_tc = 3'h0,
- bit [1:0] ic_attr = 2'h0,
- bit ic_ep = 1'h0,
- bit ic_td = 1'h0,
- bit [63:0] ic_address = 64'h0,
- bit [15:0] ic_req_id = 16'h0,
- bit [7:0] ic_tag = 8'h0,
- bit [3:0] ic_first_be = 4'hf,
- bit [3:0] ic_last_be = 4'hf,
- //completion fields
- bit [15:0] ic_completer_id = 16'h0,
- bit [11:0] ic_byte_count = 12'h0,
- bit ic_bcm = 1'h0,
- bit [2:0] ic_cmp_status = 3'h0,
- bit [31:0] ic_config_data = 32'b0) {
-
- sequence_num = {4'b0,ic_sequence_num};
- type = ic_type;
- fmt = ic_fmt;
- length = ic_length;
- tc = ic_tc;
- attr = ic_attr;
- ep = ic_ep;
- td = ic_td;
- address = ic_address;
- req_id = ic_req_id;
- tag = ic_tag;
- first_be = ic_first_be;
- last_be = ic_last_be;
- completer_id = ic_completer_id;
- byte_count = ic_byte_count;
- bcm = ic_bcm;
- cmp_status = ic_cmp_status;
- data[0] = ic_config_data;
- printf ("new seq(%0h),type(%0h),fmt(%0h),length(%0h),tc(%0h),attr(%0h),ep(%0h),td(%0h),addr(%0h),req_id(%0h),tag(%0h),fbe(%0h),lbe(%0h),cmp_id(%0h),bc(%0h),bcm(%0h),cmp_stat(%0h),cfgwr data(%0h)\n",
- ic_sequence_num,
- ic_type,
- ic_fmt,
- ic_length,
- ic_tc,
- ic_attr,
- ic_ep,
- ic_td,
- ic_address,
- ic_req_id,
- ic_tag,
- ic_first_be,
- ic_last_be,
- ic_completer_id,
- ic_byte_count,
- ic_bcm,
- ic_cmp_status,
- ic_config_data
- );
- }
-
- task build_packet (string pkt_type = "posted") {
- integer reserved = 0;
- integer i;
- bit [5:0] register_num;
- bit [3:0] ext_register_num;
- bit [2:0] function_number;
- bit [4:0] device_number;
- bit [7:0] bus_number;
- bit [6:0] lower_addr = address[6:0];
-
- bus_number = address[31:24];
- function_number = address[23:19];
- device_number = address[18:16];
- ext_register_num = address[11:8];
- register_num = address[7:2];
-
- if (pkt_type == "posted" || pkt_type == "nonposted") {
- //dw1
- header[4:0] = type;
- header[6:5] = fmt;
- header[7] = reserved;
- header[11:8] = reserved;
- header[14:12] = tc;
- header[15] = reserved;
- header[17:16] = length[9:8];
- header[19:18] = reserved;
- header[21:20] = attr;
- header[22] = ep;
- header[23] = td;
- header[31:24] = length[7:0];
- //dw2
- header[39:32] = req_id[15:8];
- header[47:40] = req_id[7:0];
- header[55:48] = tag;
- header[59:56] = first_be;
- header[63:60] = last_be;
- //dw3&4
- //configurations
- if (type == 5'b00100 || type == 5'b00101) {
- header[127:64] = {32'b0,
- register_num[5:0],2'b0,
- 4'b0,ext_register_num[3:0],
- device_number[4:0],function_number[2:0],
- bus_number[7:0]};
- }
- else if (fmt[0] == 1'b1) {
- header[127:64] = {address[7:2],2'b0,address[15:8],
- address[23:16],address[31:24],
- address[39:32],address[47:40],
- address[55:48],address[63:56]};
- }
- else {
- header[127:64] = {32'b0,address[7:2],2'b0,address[15:8],
- address[23:16],address[31:24]};
- }
- }
- else if (pkt_type == "completion") {
- //dw1
- header[4:0] = type;
- header[6:5] = fmt;
- header[7] = reserved;
- header[11:8] = reserved;
- header[14:12] = tc;
- header[15] = reserved;
- header[17:16] = length[9:8];
- header[19:18] = reserved;
- header[21:20] = attr;
- header[22] = ep;
- header[23] = td;
- header[31:24] = length[7:0];
- //dw 2
- header[39:32] = completer_id[15:8];
- header[47:40] = completer_id[7:0];
- header[51:48] = byte_count[11:8];
- header[52] = bcm;
- header[55:53] = cmp_status;
- header[63:56] = byte_count[7:0];
- //dw3
- header[71:64] = req_id[15:8];
- header[79:72] = req_id[7:0];
- header[87:80] = tag;
- header[95:88] = {1'b0,lower_addr};
- //dw4
- header[127:96] = 32'b0;
- }
- if (type[4:1] != 5'b0010 && fmt[1]) {
- for (i=0;i
-
-class pcie_phy_packet {
- bit [7:0] com;
- bit [7:0] link;
- bit [7:0] lane;
- bit [7:0] n_fts;
- bit [7:0] rateid;
- bit [7:0] train_cntrl;
- bit [7:0] ts_id;
- bit [7:0] idle;
- bit [7:0] skp;
- bit [7:0] fts;
- integer length;
- bit [17:0] temp_packet[];
-
-
- //methods
- task new(
- bit [7:0] ic_link = 8'hf7,
- bit [7:0] ic_lane = 8'hf7,
- bit [7:0] ic_nfts = 8'hff,
- bit [7:0] ic_rateid = 8'h2,
- bit [7:0] ic_train_cntrl = 8'h0,
- bit [7:0] ic_ts_id = 8'h4a) {
-
- link = ic_link;
- lane = ic_lane;
- n_fts = ic_nfts;
- rateid = ic_rateid;
- train_cntrl = ic_train_cntrl;
- ts_id = ic_ts_id;
- com = 8'hbc;
- idle = 8'h7c;
- skp = 8'h1c;
- fts = 8'h3c;
- }
-
- task build_packet (string pkt_type = "ts") {
- if (pkt_type == "ts") {
- length = 8;
- if (link == 8'hf7) temp_packet[0] = {2'b11,link,com};
- else temp_packet[0] = {2'b01,link,com};
- if (lane == 8'hf7) temp_packet[1] = {2'b1,n_fts,lane};
- else temp_packet[1] = {2'b0,n_fts,lane};
- temp_packet[2] = {2'b0,train_cntrl,rateid};
- temp_packet[3] = {2'b0,ts_id,ts_id};
- temp_packet[4] = {2'b0,ts_id,ts_id};
- temp_packet[5] = {2'b0,ts_id,ts_id};
- temp_packet[6] = {2'b0,ts_id,ts_id};
- temp_packet[7] = {2'b0,ts_id,ts_id};
- printf ("building training set packet (%0h)\n",
- {temp_packet[7][15:0],temp_packet[6][15:0],
- temp_packet[5][15:0],temp_packet[4][15:0],
- temp_packet[3][15:0],temp_packet[2][15:0],
- temp_packet[1][15:0],temp_packet[0][15:0]});
- }
- else if (pkt_type == "eidle") {
- length = 2;
- temp_packet[0] = {2'b11,idle,com};
- temp_packet[1] = {2'b11,idle,idle};
- printf ("building eidle packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
- }
- else if (pkt_type == "skip"){
- length = 2;
- temp_packet[0] = {2'b11,skp,com};
- temp_packet[1] = {2'b11,skp,skp};
- printf ("building skip packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
- }
- else if (pkt_type == "fast_ts"){
- length = 2;
- temp_packet[0] = {2'b11,fts,com};
- temp_packet[1] = {2'b11,fts,fts};
- printf ("building fts packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
- }
-
- }
-}
Index: trunk/tlp_gen.vri
===================================================================
--- trunk/tlp_gen.vri (revision 7)
+++ trunk/tlp_gen.vri (nonexistent)
@@ -1,277 +0,0 @@
-// ===========================================================================
-// File : tlp_gen.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-// Please contact www.gutzlogic.com for details.
-// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
-// ===========================================================================
-//
-// $Id: tlp_gen.vri,v 1.2 2007-12-05 23:01:11 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.1.1.1 2007/12/05 18:37:07 cmagleby
-// importing tb files
-//
-//
-// ===========================================================================
-// Function : This file generates cfgrd/wr memrd/wr.
-//
-// ===========================================================================
-// ===========================================================================
-#include
-#define STP_s 8'hfb
-#define EDB 8'hfe
-task tlp_gen() {
-
- bit [15:0] req_id;
- bit [7:0] busnum;
- bit [7:0] reg_num;
- bit [3:0] first_be;
- bit [3:0] last_be;
- bit [63:0] address;
- bit [9:0] length;
- bit [31:0] data;
- bit [7:0] tag;
-
- sequence_id = 0; reg_num=0;first_be=4'hf;req_id=0101;tag=1;busnum=1;
- printf ("read vendor id\n");
- cfgrd(reg_num,first_be,req_id,tag,busnum);
-
- sequence_id++; reg_num='h5;first_be=4'hf;req_id=0101;tag++;busnum=1;
- printf ("write base address 1 register\n");
- cfgwr(reg_num,first_be,req_id,tag,busnum,32'hba120000);
- sequence_id++;address = 64'hba120000;length=10'h5;first_be=4'hf;last_be=4'hf;req_id=16'h0100;tag++;
- memwr(address,length,first_be,last_be,req_id,tag);
- sequence_id++;
- memrd(address,length,first_be,last_be,req_id,tag);
-}
-
-task cfgrd (bit [7:0] reg_num,
- bit [3:0] first_be,
- bit [15:0] req_id,
- bit [7:0] tag,
- bit [7:0] busnum) {
-
- integer index;
- integer ret;
- bit [127:0] return_pkt;
- bit [31:0] return_data;
- bit [63:0] address = {32'b0,busnum,5'b1,3'b0,8'b0,reg_num,2'b0};
-
- tlp_packet = new(sequence_id,5'b00100,2'b0,10'h1,*,*,*,*,
- address,req_id,tag,first_be,4'b0,*,*,*,*,*);
- tlp_packet.build_packet("nonposted");
- printf ("header %0h \n",tlp_packet.header);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- //sequence id
- printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
- mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
- printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
- mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
- //loop for sending out packet
- for (index=1;index<3;index++) {
- printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
- printf("%0h put into mailbox index+1 = %0d\n",{2'b00,packet_array[index+1][7:0],packet_array[index][31:24]},index+1);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index+1][7:0],packet_array[index][31:24]});
- }
- printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
- printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]},index);
- mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]});
- printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[23:8]});
- printf("%0h put into mailbox\n",{2'b10,END_s,tlp_packet.lcrc[31:24]});
- mailbox_put(rx_data_mailbox, {2'b10,END_s,tlp_packet.lcrc[31:24]});
- semaphore_put (my_semaphore, 1);
-
- ret = mailbox_get (WAIT,tlp_header_mailbox,return_pkt,CHECK);
- if (ret <= 0)
- error ("mailbox_get returned %0d\n",ret);
- if (return_pkt[4:0] == 4'ha) {
- if (return_pkt[6] == 1'b1) {
- ret = mailbox_get (WAIT,tlp_data_mailbox,return_data,CHECK);
- if (ret <= 0)
- error ("mailbox_get returned %0d\n",ret);
- printf("returned header %0h and data %0h for tag %0h\n",return_pkt,return_data,tag);
- }
- }
- else if ((return_pkt[4:0] == 4'ha) && (return_pkt[5] == 1'b0)) {
- printf("comp without data returned header %0h and comp_stat of %0b\n",return_pkt,return_pkt[55:53]);
- }
-}
-
-
-
-task cfgwr (bit [7:0] reg_num,
- bit [3:0] first_be,
- bit [15:0] req_id,
- bit [7:0] tag,
- bit [7:0] busnum,
- bit [31:0] data) {
-
- integer index;
- integer ret;
- bit [127:0] return_pkt;
- //bus num,device num,function num,ext reg reg_num;
- bit [63:0] address = {32'b0,busnum,5'b1,3'b0,8'b0,reg_num,2'b0};
- printf ("cfgwr data = %0h\n",data);
- tlp_packet = new(sequence_id,5'b00100,2'b10,10'h1,*,*,*,*,
- address,req_id,tag,first_be,4'b0,*,*,*,*,data);
- tlp_packet.build_packet("nonposted");
- printf ("header %0h \n",tlp_packet.header);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- //sequence id
- printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
- mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
- printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
- mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
- //loop for sending out packet
- for (index=1;index<4;index++) {
- printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
- printf("%0h put into mailbox index+1 = %0d\n",{2'b00,packet_array[index+1][7:0],packet_array[index][31:24]},index+1);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index+1][7:0],packet_array[index][31:24]});
- }
- printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
- printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]},index);
- mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]});
- printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[23:8]},index);
- mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[23:8]});
- printf("%0h put into mailbox\n",{2'b10,END_s,tlp_packet.lcrc[31:24]});
- mailbox_put(rx_data_mailbox, {2'b10,END_s,tlp_packet.lcrc[31:24]});
- semaphore_put (my_semaphore, 1);
- ret = mailbox_get (WAIT,tlp_header_mailbox,return_pkt,CHECK);
- if (ret <= 0)
- error ("mailbox_get returned %0d\n",ret);
-
- if ((return_pkt[4:0] == 4'ha) && (return_pkt[5] == 1'b0)) {
- if (return_pkt[55:53] == 3'b000) printf("comp without data returned header %0h tag %0h and comp_stat of successful completion\n",return_pkt,tag);
- else if (return_pkt[55:53] == 3'b001) printf("comp without data returned header %0h tag %0hand comp_stat of unsupported response\n",return_pkt,tag);
- else if (return_pkt[55:53] == 3'b010) printf("comp without data returned header %0h tag %0hand comp_stat of completer abort\n",return_pkt,tag);
- }
-}
-
-
-task memwr (bit [63:0] address,
- bit [9:0] length,
- bit [3:0] first_be,
- bit [3:0] last_be,
- bit [15:0] req_id,
- bit [7:0] tag){
- integer index;
- bit seq_header;
- integer total_length;
- bit[1:0] fmt;
- integer hdr_dw;
- fmt = |address[63:32] == 1 ? 2'b11 : 2'b10;
- hdr_dw = |address[63:32] == 1 ? 4 : 3;
- total_length = hdr_dw + length; //add td when ready
- //bus num,device num,function num,ext reg reg_num;
- tlp_packet = new(sequence_id,5'b00000,fmt,length,*,*,*,*,
- address,req_id,tag,first_be,last_be,*,*,*,*,*);
- tlp_packet.build_packet("nonposted");
- printf ("header %0h \n",tlp_packet.header);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- //sequence id
- printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
- mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
- printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
- mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
- //loop for sending out packet
- for (index=1;index
-#define COM_s 8'hbc
-#define SKP_s 8'h1c
-#define IDLE_s 8'h7c
-#define FTS_s 8'h3c
-#define STP_s 8'hfb
-#define SDP_s 8'h5c
-#define EDB 8'hfe
-#define END_s 8'hfd
-
-task link_training () {
-
- fork
- send_ts();
- receive_ts();
- join none
-}
-
-
-task send_ts( ) {
- integer index;
- string pkt_type;
- pkt_type = "ts";
- //ti_phy_top.t1_count == 9'hff;
- ti_phy_top.rxvalid16 = 1'b1;
- wait_var(phy_rdy);
-
- printf ("send_ts1 = %d \n",send_ts1);
- while (LINK_UP == 0) {
- if (send_ts1 == 1) {
- ts2_cycle_cnt = 1;
- //printf ("number of ts dut sent %d \n",ti_phy_top.t1_count);
- printf ("ts #%0d ts 1's ",ts1_cycle_cnt++);
- pkt_type = "ts";
- training_set = new(link,lane,*,*,*,*);
- training_set.build_packet(pkt_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for (index = 0; index < training_set.length; index ++) {
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = training_set.temp_packet[index][17:16];
- //ti_phy_top.rxdata16 = training_set.temp_packet[index][15:0];
- //adding mailbox
- mailbox_put (rx_data_mailbox, {training_set.temp_packet[index][17:16],training_set.temp_packet[index][15:0]});
- }
- semaphore_put (my_semaphore, 1);
- }
- else if (send_ts2 == 1){
- ts1_cycle_cnt = 1;
- printf ("ts #%0d ts 2's ",ts2_cycle_cnt++);
- pkt_type = "ts";
- training_set = new(lane,link,*,*,*,'h45);
- training_set.build_packet(pkt_type);
- for (index = 0; index < training_set.length; index ++) {
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = training_set.temp_packet[index][17:16];
- //ti_phy_top.rxdata16 = training_set.temp_packet[index][15:0];
- //adding mailbox
- mailbox_put (rx_data_mailbox, {training_set.temp_packet[index][17:16],training_set.temp_packet[index][15:0]});
- }
- }
- }
-
- printf ("LINK UP(%0d) !!!!!!!!!!!\n",LINK_UP);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
-}
-
-task receive_ts () {
- integer ret;
- integer ts1_count=0;
- integer ts2_count=0;
- integer ts1_link_count = 0;
- integer ts1_lane_count = 0;
- integer ts2_lane_link_count = 0;
- integer send_ts1_with_link, send_ts1_with_link_lane, send_ts2_with_link_lane;
- bit [127:0] receive_phy_packet;
-
- send_ts1 = 1;
- send_ts2 = 0;
- send_ts1_with_link = 0;
- send_ts1_with_link_lane = 0;
- send_ts2_with_link_lane = 0;
- while (1) {
- ret = mailbox_get (WAIT,phy_mailbox,receive_phy_packet,CHECK);
- //printf ("Recieved PHY PACKET (%0h) added to phy mailbox\n",receive_phy_packet);
- if (receive_phy_packet == 127'h454545454545454545450002f0f7f7bc) {
- printf ("Recieved TS 2 PHY PACKET\n");
- ts2_count++;
- }
- if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f0f7f7bc){
- printf ("Recieved TS 1 PHY PACKET\n");
- ts1_count++;
- }
- if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f0f701bc) {
- printf ("Recieved TS 1 link accept PHY PACKET\n");
- ts1_link_count++;
- }
- if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f00101bc) {
- printf ("Recieved TS 1 lane and link accept PHY PACKET\n");
- ts1_lane_count++;
- }
- if (receive_phy_packet == 127'h454545454545454545450002f00101bc) {
- printf ("Recieved TS 1 lane and link accept PHY PACKET\n");
- ts2_lane_link_count++;
- }
-
- //printf ("send_ts2_with_link_lane(%0d)send_ts1_with_link_lane(%0d)send_ts1_with_link(%0d)send_ts2(%0d)send_ts1(%0d)\n",
- // send_ts2_with_link_lane,send_ts1_with_link_lane,send_ts1_with_link,send_ts2,send_ts1 );
- //printf ("ts2_lane_link_count(%0d)ts1_lane_count(%0d)ts1_link_count(%0d)ts1_count(%0d)ts2_count(%0d)\n",
- // ts2_lane_link_count,ts1_lane_count,ts1_link_count,ts1_count,ts2_count);
-
- if (send_ts2_with_link_lane && ts2_cycle_cnt > 16 && ts2_lane_link_count > 15) {
- //clear all signals if we get a ts1 with pad
- if (ts1_count > 0) {
- send_ts1 = 1;
- send_ts2 = 0;
- send_ts2_with_link_lane = 0;
- send_ts1_with_link_lane = 0;
- send_ts1_with_link = 0;
- LINK_UP = 0;
- ts2_lane_link_count = 0;
- ts1_lane_count = 0;
- ts1_link_count = 0;
- ts1_count = 0;
- ts2_count = 0;
- }
- else {
- send_ts1 = 0;
- send_ts2 = 0;
- LINK_UP = 1;
- ts1_lane_count = 0;
- ts1_link_count = 0;
- ts1_count = 0;
- ts2_count = 0;
-
- }
-
- }
- else if (send_ts1_with_link_lane){
- if (ts1_cycle_cnt > 16 && ts1_lane_count >16 ) {
- send_ts1 = 0;
- send_ts2 = 1;
- link = 8'b1;
- lane = 8'b1;
- send_ts2_with_link_lane = 1;
- ts1_lane_count = 0;
- ts1_link_count = 0;
- ts1_count = 0;
- ts2_count = 0;
- }
- }
- else if (send_ts1_with_link) {
- if (ts1_cycle_cnt > 16 && ts1_link_count > 16) {
- send_ts1 = 1;
- send_ts2 = 0;
- link = 8'b1;
- lane = 8'b1;
- send_ts1_with_link_lane = 1;
- }
- }
- //send at least 16 ts 2
- else if (send_ts2) {
- if (ts2_count > 16 && ts2_cycle_cnt > 16) {
- send_ts1 = 1;
- send_ts2 = 0;
- send_ts1_with_link = 1;
- link = 8'b1;
- lane = 8'hf7;
- }
- }
- //send at least 100 ts 1's
- else if (ts2_count > 16 && ts1_cycle_cnt > 100) {
- send_ts1 = 0;
- send_ts2 = 1;
- link = 'hf7;
- lane = 'hf7;
- }
- else {
- send_ts1 = 1;
- send_ts2 = 0;
- link = 'hf7;
- lane = 'hf7;
- }
- }
-}
-
Index: trunk/docs/PCI_Express_VERA_testbench.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/docs/PCI_Express_VERA_testbench.pdf
===================================================================
--- trunk/docs/PCI_Express_VERA_testbench.pdf (revision 7)
+++ trunk/docs/PCI_Express_VERA_testbench.pdf (nonexistent)
trunk/docs/PCI_Express_VERA_testbench.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/InitFC1.vri
===================================================================
--- trunk/InitFC1.vri (revision 7)
+++ trunk/InitFC1.vri (nonexistent)
@@ -1,363 +0,0 @@
-// ===========================================================================
-// File : InitFC1.vri
-// Author : cwinward
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: InitFC1.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file performs the initial flow control sequence.
-//
-// ===========================================================================
-// ===========================================================================
-
-#include
-
-task InitFC1(var bit [7:0] ph_cl, var bit [11:0] pd_cl, var bit [7:0] cplh_cl,var bit [11:0] cpld_cl,var bit [7:0] nph_cl,var bit [11:0] npd_cl,var bit INITFC_DONE){
- integer index;
- string dllp_type;
- bit fc1_p_rcvd = 1'b0;
- bit fc1_np_rcvd = 1'b0;
- bit fc1_cpl_rcvd = 1'b0;
- bit fc2_p_rcvd = 1'b0;
- bit fc2_np_rcvd = 1'b0;
- bit fc2_cpl_rcvd = 1'b0;
-
- bit fc1_completed = 1'b0;
- bit fc2_completed = 1'b0;
-
- //****************************************************************************************
- //new task to read out the dllp's
- //
-
- while(fc1_completed == 1'b0){
- fc1_completed = fc1_p_rcvd & fc1_np_rcvd & fc1_cpl_rcvd;
- printf("FC1_completed <= %d.\n",fc1_completed);
- receive_fc1_dllp(fc1_p_rcvd,fc1_np_rcvd,fc1_cpl_rcvd,ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl);
- dllp_type = "initfc1_p";
- printf("Sending out an InitFC1_P packet.\n");
- flowcntrl_1 = new(*,*,*,*);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
-
- dllp_type = "initfc1_np";
- printf("Sending out an InitFC1_NP packet.\n");
- flowcntrl_1 = new(8'h00,8'h00,8'h01,8'b01010000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
-
- dllp_type = "initfc1_cpl";
- printf("Sending out an InitFC1_NP packet.\n");
- flowcntrl_1 = new(8'h40,8'h00,8'h01,8'b01100000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
- }
-
- while(fc2_completed == 1'b0){
- fc2_completed = fc2_p_rcvd | fc2_np_rcvd | fc2_cpl_rcvd;
- printf("FC2_completed <= %d.\n",fc2_completed);
- receive_fc2_dllp(fc2_p_rcvd,fc2_np_rcvd,fc2_cpl_rcvd);
- dllp_type = "initfc1_p";
- printf("Sending out an InitFC2_P packet.\n");
- flowcntrl_1 = new(*,*,*,8'b11000000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
-
- dllp_type = "initfc1_np";
- printf("Sending out an InitFC2_NP packet.\n");
- flowcntrl_1 = new(8'h00,8'h00,8'h01,8'b11010000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
-
- dllp_type = "initfc1_cpl";
- printf("Sending out an InitFC2_NP packet.\n");
- flowcntrl_1 = new(8'h40,8'h00,8'h01,8'b11100000);
- flowcntrl_1.build_packet(dllp_type);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- for(index=0; index <= 3; index ++)
- {
- @ (posedge CLOCK);
- if(index==0){
- //ti_phy_top.rxdatak16 = 2'b01;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
- }
- else if(index==1){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
- }
- else if(index==2){
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
- }
- else if(index==3){
- //ti_phy_top.rxdatak16 = 2'b10;
- //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
- //adding mailbox
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
- }
- }
-
- @ (posedge CLOCK);
- INITFC_DONE = fc1_completed & fc2_completed;
- //ti_phy_top.rxdatak16 = 2'b00;
- //ti_phy_top.rxdata16 = 1'b0;
- semaphore_put (my_semaphore, 1);
- }
-
-}
-
-task receive_fc1_dllp (var bit fc1_p_rcvd, var bit fc1_np_rcvd, var bit fc1_cpl_rcvd,var bit [7:0] ph_cl, var bit [11:0] pd_cl, var bit [7:0] cplh_cl,var bit [11:0] cpld_cl,var bit [7:0] nph_cl,var bit [11:0] npd_cl) {
- integer ret;
- bit [47:0] receive_dll_packet;
-
- while (~(fc1_p_rcvd & fc1_np_rcvd & fc1_cpl_rcvd)) {
- ret = mailbox_get (WAIT,dllp_mailbox,receive_dll_packet,CHECK);
- if(receive_dll_packet[7:0] == 8'h40){
- fc1_p_rcvd = 1'b1;
- ph_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
- pd_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
- }
- else if(receive_dll_packet[7:0] == 8'h50){
- fc1_np_rcvd = 1'b1;
- nph_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
- npd_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
- }
- else if(receive_dll_packet[7:0] == 8'h60){
- fc1_cpl_rcvd = 1'b1;
- cplh_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
- cpld_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
- }
- printf ("InitFC1 DLL PACKET (%0h) taken out of dll mailbox\n",receive_dll_packet);
- }
-}
-
-task receive_fc2_dllp (var bit fc2_p_rcvd, var bit fc2_np_rcvd, var bit fc2_cpl_rcvd) {
- integer ret;
- bit [47:0] receive_dll_packet;
-
- while (~(fc2_p_rcvd | fc2_np_rcvd | fc2_cpl_rcvd)) {
- ret = mailbox_get (WAIT,dllp_mailbox,receive_dll_packet,CHECK);
- if(receive_dll_packet[7:0] == 8'hC0){
- fc2_p_rcvd = 1'b1;
- }
- else if(receive_dll_packet[7:0] == 8'hD0){
- fc2_np_rcvd = 1'b1;
- }
- else if(receive_dll_packet[7:0] == 8'hE0){
- fc2_cpl_rcvd = 1'b1;
- }
- printf ("InitFC2 DLL PACKET (%0h) taken out of dll mailbox\n",receive_dll_packet);
- }
-}
-
Index: trunk/ti_phy_top.vr
===================================================================
--- trunk/ti_phy_top.vr (revision 7)
+++ trunk/ti_phy_top.vr (nonexistent)
@@ -1,209 +0,0 @@
-// ===========================================================================
-// File : ti_phy_top.vr
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-// Please contact www.gutzlogic.com for details.
-// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
-// ===========================================================================
-//
-// $Id: ti_phy_top.vr,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This is the top level VERA file. It call all tasks and brings
-// up the PHY.
-// ===========================================================================
-// ===========================================================================
-
-#define OUTPUT_EDGE PHOLD
-#define OUTPUT_SKEW #1
-#define INPUT_SKEW #-1
-#define INPUT_EDGE PSAMPLE
-#include
-
-// define interfaces, and verilog_node here if necessary
-
-#include "ti_phy_top.if.vrh"
-#include "receive_packet.vri"
-#include "send_packet.vri"
-#include "pcie_phy_packet.vri"
-#include "link_training.vri"
-#include "skip_order_set.vri"
-#include "pcie_dllp_packet.vri"
-#include "InitFC1.vri"
-#include "pcie_tlp_packet.vri"
-#include "tlp_gen.vri"
-
-//kcode symbols
-#define COM_s 8'hbc
-#define SKP_s 8'h1c
-#define IDLE_s 8'h7c
-#define FTS_s 8'h3c
-#define STP_s 8'hfb
-#define SDP_s 8'h5c
-#define EDB 8'hfe
-#define END_s 8'hfd
-program ti_phy_top_test {
-
- pcie_phy_packet training_set;
- pcie_phy_packet skip_set;
- //********************************
- //link training gobal variables
- integer send_ts1 = 1;
- integer send_ts2 = 0;
- bit [11:0] sequence_id;
- bit [31:0] packet_array [1040];
- bit [7:0] link = 8'hf7;
- bit [7:0] lane = 8'hf7;
- integer ts1_cycle_cnt = 1;
- integer ts2_cycle_cnt = 1;
- integer LINK_UP = 0;
- bit [7:0] ph_cl = 8'b0;
- bit [11:0] pd_cl = 12'b0;
- bit [7:0] cplh_cl = 8'b0;
- bit [11:0] cpld_cl = 12'b0;
- bit [7:0] nph_cl = 8'b0;
- bit [11:0] npd_cl = 12'b0;
- bit INITFC_DONE = 1'b0;
- //********************************
- pcie_dllp_packet flowcntrl_1;
- pcie_dllp_packet ack_seq_num;
- pcie_tlp_packet tlp_packet;
- integer phy_rdy = 0;
- integer my_semaphore;
- bit [8:0] tx_data_mailbox;
- bit [15:0] tlp_header_mailbox;
- bit [31:0] tlp_data_mailbox;
- bit [47:0] dllp_mailbox;
- bit [127:0] phy_mailbox;
- bit [17:0] rx_data_mailbox;
-
- //create mailboxes for transmit and receive packets
- tx_data_mailbox = alloc(MAILBOX,0,1);
- rx_data_mailbox = alloc(MAILBOX,0,1);
-
- tlp_header_mailbox = alloc(MAILBOX,0,1);
- tlp_data_mailbox = alloc(MAILBOX,0,1);
- dllp_mailbox = alloc(MAILBOX,0,1);
- phy_mailbox = alloc(MAILBOX,0,1);
-
- //create a packet arbiter for packet going out on the rx line.
- my_semaphore = alloc(SEMAPHORE, 0, 1, 1);
- if (!my_semaphore) error ("Semaphore could not be allocated\n");
-
- fork
- clk_50mhz_gen();
- phy_status();
- skip_order_set();
- receive_packet();
- send_packet();
- wait_var(phy_rdy);
- link_training();
- join none
-
- init_ports ();
- reset_sequence();
- wait_var(LINK_UP);
- fork
- zero_fill();
- join none
- InitFC1(ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl,INITFC_DONE);
-
- printf("Posted Header credit %h\n",ph_cl);
- printf("Posted Data credit %h\n",pd_cl);
-
- printf("NonPosted Header credit %h\n",nph_cl);
- printf("NonPosted Data credit %h\n",npd_cl);
-
- printf("Completion Header credit %h\n",cplh_cl);
- printf("Completion Data credit %h\n",cpld_cl);
-
- printf("INITFC_DONE=%d\n.",INITFC_DONE);
- tlp_gen();
- repeat (10000) @(posedge CLOCK);
-} // end of program ti_phy_top_test
-
-// define tasks/classes/functions here if necessary
-
-task clk_50mhz_gen () {
- ti_phy_top.clk_50mhz = 0;
- @(posedge ti_phy_top.rxclk);
- while(1) {
- @10 ti_phy_top.clk_50mhz = 1;
- @10 ti_phy_top.clk_50mhz = 0;
- }
-}
-
-task init_ports () {
- printf("Task init_ports\n");
- @(posedge ti_phy_top.rxclk);
- ti_phy_top.FPGA_RESET_n = 1'b0;
- ti_phy_top.rxdata16 = 16'b0;
- ti_phy_top.rxdatak16 = 2'b0;
- ti_phy_top.rxvalid16 = 1'b0;
- ti_phy_top.rxidle16 = 1'b0;
- ti_phy_top.rxstatus = 1'b1;
- ti_phy_top.phystatus = 1'b1;
-}
-
-task reset_sequence() {
- printf("Task phy bring up\n");
-
- @5 ti_phy_top.FPGA_RESET_n = 1'b0;
- @1 ti_phy_top.FPGA_RESET_n = 1'b1;
-}
-
-
-task phy_status () {
- bit [1:0] prev_pwrdwn = 0;
- integer loop_back_high;
- integer phy_status_arb;
- phy_status_arb = alloc(SEMAPHORE,0,1,1);
- if (!phy_status_arb) error ("Semaphore could not be allocated\n");
- printf("Look for power changes\n");
- @50 ti_phy_top.rxidle16 = 1'b0;
- @100 ti_phy_top.phystatus = 1'b0;
- while (1){
- prev_pwrdwn = ti_phy_top.pwrdwn;
- @(posedge CLOCK);
- //receiver detect
- if (ti_phy_top.rxdet_loopb == 1'b1 && ti_phy_top.pwrdwn == 2'b10) {
- loop_back_high = 1;
- if (!semaphore_get(WAIT,phy_status_arb,1))
- error ("Semaphore_get returned 0\n");
- //printf("GOT PHY ARB1 /n");
- @10 ti_phy_top.rxstatus = 3'b11;
- @10 ti_phy_top.phystatus = 1'b1;
- while(loop_back_high) {
- @(posedge CLOCK);
- if (ti_phy_top.rxdet_loopb == 1'b0) {
- loop_back_high = 1'b0;
- }
- }
- @4 ti_phy_top.phystatus = 1'b0;
- ti_phy_top.rxstatus = 3'b0;
- semaphore_put (phy_status_arb, 1);
- }
- if (ti_phy_top.pwrdwn != prev_pwrdwn){
- if (!semaphore_get(WAIT,phy_status_arb,1))
- error ("Semaphore_get returned 0\n");
- //printf("GOT PHY ARB2 /n");
- @1 ti_phy_top.rxstatus = 3'b100;
- ti_phy_top.phystatus = 1'b1;
- @1 ti_phy_top.phystatus = 1'b0;
- if (ti_phy_top.pwrdwn == 2'b00) phy_rdy = 1;
- semaphore_put (phy_status_arb, 1);
-
- }
- }
-}
-
-
-
Index: trunk/receive_packet.vri
===================================================================
--- trunk/receive_packet.vri (revision 7)
+++ trunk/receive_packet.vri (nonexistent)
@@ -1,306 +0,0 @@
-// ===========================================================================
-// File : receive_packet.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: receive_packet.vri,v 1.2 2007-12-07 20:16:29 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.1.1.1 2007/12/05 18:37:06 cmagleby
-// importing tb files
-//
-//
-// ===========================================================================
-// Function : This file processes all packets received from the 16 tx interface
-//
-// ===========================================================================
-// ===========================================================================
-#include
-#include "scramble8.vri"
-#define COM_s 8'hbc
-#define SKP_s 8'h1c
-#define IDLE_s 8'h7c
-#define FTS_s 8'h3c
-#define STP_s 8'hfb
-#define SDP_s 8'h5c
-#define EDB 8'hfe
-#define END_s 8'hfd
-
-task receive_packet () {
- bit [7:0] tx_data[];
- bit tx_datak[];
- integer ret,ret1,ret2,ret3,ret4;
- integer i = 0;
- integer m = 0;
- bit[8:0] tx_pkt;
- event phy_start, phy_done, tlp_start, tlp_done, dllp_start, dllp_done;
- bit [7:0] phy_pkt[];
- bit [7:0] dll_pkt[];
- bit [7:0] tlp_pkt[];
- integer j,k,l;
- bit [127:0] build_phy_pkt;
- bit [47:0] build_dll_pkt;
- bit [127:0] build_tlp_header;
- bit [31:0] build_tlp_data;
- bit [15:0] expected_seq_id = 0;
- bit [15:0] recv_seq_id = 0;
- bit [9:0] recv_length = 0;
- bit [11:0] byte_length = 0;
- bit [31:0] recv_lcrc = 0;
- bit td = 0;
- integer kstart = 0;
- integer debug = 1;
- bit [15:0] lfsr = 16'hFFFF;
- bit [7:0] scramble_data[];
- bit skp_detect = 1'b0;
- bit com_detect = 1'b0;
- bit scram_bypass = 1'b0;
- bit [3:0] bypass_count = 4'b0;
-
- printf("Look for transmit packets\n");
- wait_var(phy_rdy);
- @ (posedge CLOCK);
- fork
- while (1) {
- @ (posedge CLOCK);
- tx_data[0] = ti_phy_top.txdata16[7:0];
- tx_data[1] = ti_phy_top.txdata16[15:8];
- tx_datak[0] = ti_phy_top.txdatak16[0];
- tx_datak[1] = ti_phy_top.txdatak16[1];
- for (i=0; i<2; i++) {
-
- if(com_detect == 1'b1){
- scram_bypass = 1'b1;
- }
- else if(((bypass_count == 4'b0011) & tx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
- scram_bypass = 1'b0;
- }
-
- if((com_detect == 1'b1) | scram_bypass){
- bypass_count = bypass_count + 1'b1;
- }
- else if(((bypass_count == 4'b0011) & tx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
- bypass_count = 4'b0000;
- }
-
-
- if({tx_datak[i],tx_data[i]} == {1'b1,SKP_s}){
- skp_detect = 1'b1;
- }
- else{
- skp_detect = 1'b0;
- }
- if({tx_datak[i],tx_data[i]} == {1'b1,COM_s}){
- com_detect = 1'b1;
- }
- else{
- com_detect = 1'b0;
- }
-
-
- //printf("K-Code = %h DATA = %h COM = %h SKP = %h bypass_count = %d scram_bypass = %h\n",tx_datak[i],tx_data[i],com_detect,skp_detect,bypass_count,scram_bypass);
-
- //if({tx_datak[i],tx_data[i]} == {1'b1,STP_s}){
- // printf("Start of TLP packet.\n");
- //}
-
- scramble8(tx_data[i],skp_detect,com_detect,(scram_bypass | tx_datak[i]),lfsr,scramble_data[i],lfsr);
- //printf("K-Code = %h COM = %h SKP = %h bypass = %h scramble_data = %h unscramble_data = %h lfsr = %h bypass_cnt = %d\n",tx_datak[i],com_detect,skp_detect,scram_bypass,tx_data[i],scramble_data[i],lfsr,bypass_count);
-
- mailbox_put (tx_data_mailbox, {tx_datak[i],scramble_data[i]});
- //printf("Add packet to tx_mailbox %0h\n",tx_data[i]);
-
- }
- }
- while (1) {
- ret = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- if (ret <= 0)
- error ("mailbox_get returned %0d\n",ret);
- //printf ("got tx_pkt %0h\n",tx_pkt);
- if (tx_pkt == {1'b1,COM_s}) {
- trigger (ONE_BLAST,phy_start);
- sync (ALL,phy_done);
- }
- if (tx_pkt == {1'b1,STP_s}) {
- trigger (ONE_BLAST,tlp_start);
- sync (ALL,tlp_done);
- }
- if (tx_pkt == {1'b1,SDP_s}) {
- trigger (ONE_BLAST,dllp_start);
- sync (ALL,dllp_done);
- }
- }
- //phy layer packets
- while (1) {
- sync(ALL,phy_start);
- //printf ("got past sync %0h\n",tx_pkt);
- phy_pkt[0] = COM_s;
- phy_pkt[4] = 0;
- phy_pkt[5] = 0;
- phy_pkt[6] = 0;
- phy_pkt[7] = 0;
- phy_pkt[8] = 0;
- phy_pkt[9] = 0;
- phy_pkt[10] = 0;
- phy_pkt[11] = 0;
- phy_pkt[12] = 0;
- phy_pkt[13] = 0;
- phy_pkt[14] = 0;
- phy_pkt[15] = 0;
- ret2 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- //printf ("got past mailbox get %0h\n",tx_pkt);
- phy_pkt[1] = tx_pkt;
- //training set
- if ((tx_pkt == 'h1f7) || ~tx_pkt[8]) {
- for (j = 2; j <16; j++) {
- ret2 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- phy_pkt[j] = tx_pkt;
- }
- }
- //skip fst idle
- else {
- for (j=2;j<4;j++) {
- ret1 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- phy_pkt[j] = tx_pkt;
- //printf ("skip loop got past %0h\n",tx_pkt);
- }
- }
- build_phy_pkt = {phy_pkt[15],phy_pkt[14],phy_pkt[13],phy_pkt[12],phy_pkt[11],
- phy_pkt[10],phy_pkt[9],phy_pkt[8],phy_pkt[7],phy_pkt[6],
- phy_pkt[5],phy_pkt[4],phy_pkt[3],phy_pkt[2],phy_pkt[1],phy_pkt[0]};
- mailbox_put (phy_mailbox, build_phy_pkt);
- printf ("Recieved PHY PACKET (%0h) added to phy mailbox\n",build_phy_pkt);
- trigger (ONE_BLAST,phy_done);
- }
- //dll layer packets
- while (1) {
- sync (ALL,dllp_start);
- //printf ("sync into dllp packet\n");
- for (k = 0; k < 6; k++) {
- ret3 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- dll_pkt[k] = tx_pkt;
- //printf ("dll_pkt(%0h)\n",dll_pkt[k]);
- }
- ret3 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- //printf ("dll this should be end(%0h)\n",tx_pkt);
- if (tx_pkt == {1'b1,END_s}) {
- build_dll_pkt = {dll_pkt[6],dll_pkt[5],dll_pkt[4],dll_pkt[3],
- dll_pkt[2],dll_pkt[1],dll_pkt[0]};
- mailbox_put (dllp_mailbox, build_dll_pkt);
- printf ("Recieved DLL PACKET (%0h) added to dllp mailbox\n",build_dll_pkt);
- }
- else
- printf ("ERROR ->>>>>>> DLL malformed no END\n");
-
- trigger (ONE_BLAST,dllp_done);
- }
- //tlp layer packets
- while (1) {
- sync (ALL,tlp_start);
- printf ("sync into tlp packet\n");
- @(posedge CLOCK);
- //3 dw header + seq.
- for (k = 0; k < 14; k++) {
- //printf("debug1 %0d\n",debug++);
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- tlp_pkt[k] = tx_pkt;
- }
- //dword 4
- if (tlp_pkt[2][5] == 1'b1) {
- for (k=14;k<18;k++) {
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- tlp_pkt[k] = tx_pkt;
- }
- }
-
- //****************************************************************************************
- //Check sequence ID and send ACK
- recv_seq_id = {tlp_pkt[0],tlp_pkt[1]};
- if (recv_seq_id != expected_seq_id) printf ("ERROR ->>>>>>> TLP BAD SEQUENCE ID of %0h\n",recv_seq_id);
- else {
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- ack_seq_num = new(recv_seq_id[7:0],{4'b0,recv_seq_id[11:8]},8'b0,8'b0);
- ack_seq_num.build_packet("ack");
- printf("ACK PACKET Sequence Number (%0h)\n",recv_seq_id);
- for(m=0; m <= 3; m ++) {
- if(m==0){
- mailbox_put (rx_data_mailbox, {2'b01,ack_seq_num.temp_packet[0][7:0],8'h5C});
- printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",ack_seq_num.temp_packet[0][7:0],8'h5C);
- }
- else if(m==1){
- mailbox_put (rx_data_mailbox, {2'b00,ack_seq_num.temp_packet[0][23:16],ack_seq_num.temp_packet[0][15:8]});
- printf("DLLP bytes 2 & 1 %h%h.\n",ack_seq_num.temp_packet[0][23:16],ack_seq_num.temp_packet[0][15:8]);
- }
- else if(m==2){
- mailbox_put (rx_data_mailbox, {2'b00,ack_seq_num.temp_packet[1][7:0],ack_seq_num.temp_packet[0][31:24]});
- printf("DLLP CRC and byte 3 %h%h.\n",ack_seq_num.temp_packet[1][7:0],ack_seq_num.temp_packet[0][31:24]);
- }
- else if(m==3){
- mailbox_put (rx_data_mailbox, {2'b10,8'hFD,ack_seq_num.temp_packet[1][15:8]});
- printf("DLLP STP and CRC %h%h.\n",8'hFD,ack_seq_num.temp_packet[1][15:8]);
- }
- }
- semaphore_put (my_semaphore, 1);
- }
- expected_seq_id++;
- //****************************************************************************************
- //build tlp get all header information
- build_tlp_header = {tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14],
- tlp_pkt[13],tlp_pkt[12],tlp_pkt[11],tlp_pkt[10],
- tlp_pkt[9],tlp_pkt[8],tlp_pkt[7],tlp_pkt[6],
- tlp_pkt[5],tlp_pkt[4],tlp_pkt[3],tlp_pkt[2]};
-
- if (build_tlp_header[5] == 1'b0) {
- build_tlp_header[127:96] = 32'b0;
- }
- //****************************************************************************************
- //put header in mailbox
- mailbox_put (tlp_header_mailbox, build_tlp_header);
- printf ("Recieved TLP PACKET (%0h) added to tlp header mailbox\n",build_tlp_header);
- //****************************************************************************************
- //check for data and put into mailbox
- if (build_tlp_header[6] == 1) {
- td = build_tlp_header[23];
- recv_length = {build_tlp_header[17:16],build_tlp_header[31:24]};
- byte_length = (recv_length*4) + (td*4);
- printf ("TLP PACKET Receive Length dw(%0d) byte(%0d)\n",recv_length,byte_length);
- for (k=1;k<=byte_length;k++) {
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- tlp_pkt[k] = tx_pkt;
- if (k%4 ==0) {
- mailbox_put (tlp_data_mailbox, {tlp_pkt[k],tlp_pkt[k-1],tlp_pkt[k-2],tlp_pkt[k-3]});
- printf ("k = (%0d)\n",k);
- printf ("Recieved TLP DATA (%0h) added to tlp data mailbox\n",{tlp_pkt[k],tlp_pkt[k-1],tlp_pkt[k-2],tlp_pkt[k-3]});
- }
-
- }
- }
- //****************************************************************************************
- //Read out the LCRC
- for (k=0;k<=3;k++) {
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- //printf("debug3 %0d\n",debug++);
- tlp_pkt[k] = tx_pkt;
- }
- printf ("tlp lcrc value = %0h \n",{tlp_pkt[3],tlp_pkt[2],tlp_pkt[1],tlp_pkt[0]});
-
- //****************************************************************************************
- //READ out the END VALUE
- ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
- if (tx_pkt != {1'b1,END_s}) printf ("ERROR ->>>>>>> TLP malformed no END(%0h)\n",tx_pkt);
-
-
- trigger (ONE_BLAST,tlp_done);
- }
- join none
-}
-
Index: trunk/ti_phy_top.if.vrh
===================================================================
--- trunk/ti_phy_top.if.vrh (revision 7)
+++ trunk/ti_phy_top.if.vrh (nonexistent)
@@ -1,67 +0,0 @@
-// ===========================================================================
-// File : ti_phy_top.if.vrh
-// Author : cwinward
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: ti_phy_top.if.vrh,v 1.2 2008-01-15 03:25:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.1.1.1 2007/12/05 18:37:07 cmagleby
-// importing tb files
-//
-//
-// ===========================================================================
-// Function : .This is the interface file linking verilog with VERA
-//
-// ===========================================================================
-// ===========================================================================
-#ifndef INC_TI_PHY_TOP_IF_VRH
-#define INC_TI_PHY_TOP_IF_VRH
-
- interface ti_phy_top {
- input rxclk CLOCK;
- //input [9:0] t1_count PSAMPLE #-1 verilog_node "dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count";
- output clk_50mhz OUTPUT_EDGE OUTPUT_SKEW;
- output [1:0] PUSH_BUTTON OUTPUT_EDGE OUTPUT_SKEW;
- output FPGA_RESET_n OUTPUT_EDGE OUTPUT_SKEW;
- output PERST_n OUTPUT_EDGE OUTPUT_SKEW;
- output [15:0] rxdata16 OUTPUT_EDGE OUTPUT_SKEW;
- output [1:0] rxdatak16 OUTPUT_EDGE OUTPUT_SKEW;
- output rxvalid16 OUTPUT_EDGE OUTPUT_SKEW;
- output rxidle16 OUTPUT_EDGE OUTPUT_SKEW;
- output [2:0] rxstatus OUTPUT_EDGE OUTPUT_SKEW;
- output phystatus OUTPUT_EDGE OUTPUT_SKEW;
- input [7:0] LED INPUT_EDGE INPUT_SKEW;
- input txclk INPUT_EDGE INPUT_SKEW;
- input [15:0] txdata16 INPUT_EDGE INPUT_SKEW;
- input [1:0] txdatak16 INPUT_EDGE INPUT_SKEW;
- input txidle16 INPUT_EDGE INPUT_SKEW;
- input rxdet_loopb INPUT_EDGE INPUT_SKEW;
- input txcomp INPUT_EDGE INPUT_SKEW;
- input rxpol INPUT_EDGE INPUT_SKEW;
- input phy_reset_n INPUT_EDGE INPUT_SKEW;
- input [1:0] pwrdwn INPUT_EDGE INPUT_SKEW;
- input [16:0] sram_addr INPUT_EDGE INPUT_SKEW;
- input sram_adscn INPUT_EDGE INPUT_SKEW;
- input sram_adspn INPUT_EDGE INPUT_SKEW;
- input sram_advn INPUT_EDGE INPUT_SKEW;
- input [3:0] sram_ben INPUT_EDGE INPUT_SKEW;
- input [2:0] sram_ce INPUT_EDGE INPUT_SKEW;
- input sram_clk INPUT_EDGE INPUT_SKEW;
- input sram_gwn INPUT_EDGE INPUT_SKEW;
- input sram_mode INPUT_EDGE INPUT_SKEW;
- input sram_oen INPUT_EDGE INPUT_SKEW;
- input sram_wen INPUT_EDGE INPUT_SKEW;
- input sram_zz INPUT_EDGE INPUT_SKEW;
- inout [35:0] sram_data INPUT_EDGE INPUT_SKEW OUTPUT_EDGE OUTPUT_SKEW;
- } // end of interface ti_phy_top
-
-#endif
Index: trunk/skip_order_set.vri
===================================================================
--- trunk/skip_order_set.vri (revision 7)
+++ trunk/skip_order_set.vri (nonexistent)
@@ -1,64 +0,0 @@
-// ===========================================================================
-// File : skip_order_set.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: skip_order_set.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : this file generates skip order sets when the timer expires
-//
-// ===========================================================================
-// ===========================================================================
-#include
-
-//task to send in skip order sets on a regular basis.
-task skip_order_set() {
- integer time_limit_expire = 0;
- integer index = 0;
- wait_var(phy_rdy);
- while(1) {
- time_limit_expire++;
- @ (posedge CLOCK);
- ti_phy_top.rxdatak16 = 2'b00;
- ti_phy_top.rxdata16 = 1'b0;
- //1180 symbols clk is 2 symbols
- if (time_limit_expire == 1180/2) {
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- skip_set = new(*,*,*,*,*,*);
- skip_set.build_packet("skip");
- for (index = 0; index < skip_set.length; index ++) {
- @ (posedge CLOCK);
- //ti_phy_top.rxdatak16 = skip_set.temp_packet[index][17:16];
- //ti_phy_top.rxdata16 = skip_set.temp_packet[index][15:0];
- //adding mailbox
- mailbox_put (rx_data_mailbox, {skip_set.temp_packet[index][17:16],skip_set.temp_packet[index][15:0]});
- time_limit_expire = 0;
- }
- semaphore_put (my_semaphore, 1);
- }
- }
-}
-
-
-task zero_fill(){
-
- while(1) {
- @ (posedge CLOCK);
- if (!semaphore_get(WAIT,my_semaphore,1))
- error ("Semaphore_get returned 0\n");
- mailbox_put (rx_data_mailbox,18'b0);
- semaphore_put(my_semaphore, 1);
- }
-}
Index: trunk/send_packet.vri
===================================================================
--- trunk/send_packet.vri (revision 7)
+++ trunk/send_packet.vri (nonexistent)
@@ -1,109 +0,0 @@
-// ===========================================================================
-// File : send_packet.vri
-// Author : cmagleby
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: send_packet.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file sends all packets on the rx 16 bit data lines
-//
-// ===========================================================================
-// ===========================================================================
-#include
-//#include "scramble8.vri"
-#define COM_s 8'hbc
-#define SKP_s 8'h1c
-#define IDLE_s 8'h7c
-#define FTS_s 8'h3c
-#define STP_s 8'hfb
-#define SDP_s 8'h5c
-#define EDB 8'hfe
-#define END_s 8'hfd
-
-task send_packet () {
- bit [7:0] rx_data[];
- bit rx_datak[];
-
- bit [17:0] rx_pkt;
- bit [15:0] rx_data_out;
- bit [1:0] rx_datak_out;
- integer ret;
- integer i;
-
- bit [15:0] lfsr = 16'hFFFF;
- bit [7:0] scramble_data[];
- bit skp_detect = 1'b0;
- bit com_detect = 1'b0;
- bit scram_bypass = 1'b0;
- bit [3:0] bypass_count = 4'b0;
-
-
- ti_phy_top.rxdatak16 = 2'b0;
- ti_phy_top.rxdata16 = 16'b0;
- while (1) {
- @ (posedge CLOCK);
- ti_phy_top.rxdatak16 = 2'b0;
- ti_phy_top.rxdata16 = 16'b0;
-
- ret = mailbox_get (WAIT,rx_data_mailbox,rx_pkt,CHECK);
- if (ret <= 0)
- error ("mailbox_get returned %0d\n",ret);
-
- rx_datak[1] = rx_pkt[17];
- rx_datak[0] = rx_pkt[16];
- rx_data[1] = rx_pkt[15:8];
- rx_data[0] = rx_pkt[7:0];
-
-
- for (i=0; i<2; i++) {
-
- if(com_detect == 1'b1){
- scram_bypass = 1'b1;
- }
- else if(((bypass_count == 4'b0011) & rx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
- scram_bypass = 1'b0;
- }
-
- if((com_detect == 1'b1) | scram_bypass){
- bypass_count = bypass_count + 1'b1;
- }
- else if(((bypass_count == 4'b0011) & rx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
- bypass_count = 4'b0000;
- }
-
-
- if({rx_datak[i],rx_data[i]} == {1'b1,SKP_s}){
- skp_detect = 1'b1;
- }
- else{
- skp_detect = 1'b0;
- }
- if({rx_datak[i],rx_data[i]} == {1'b1,COM_s}){
- com_detect = 1'b1;
- }
- else{
- com_detect = 1'b0;
- }
-
- scramble8(rx_data[i],skp_detect,com_detect,(scram_bypass | rx_datak[i]),lfsr,scramble_data[i],lfsr);
- //printf("K-Code = %h COM = %h SKP = %h bypass = %h unscramble_data = %h scramble_data = %h lfsr = %h bypass_cnt = %d\n",rx_datak[i],com_detect,skp_detect,scram_bypass,rx_data[i],scramble_data[i],lfsr,bypass_count);
- }
-
-
- //printf("RX MAILBOX OUT datak(%0h) data(%0h) to be sent\n",rx_pkt[17:16],rx_pkt[15:0]);
- ti_phy_top.rxdatak16 = {rx_datak[1],rx_datak[0]};
- ti_phy_top.rxdata16 = {scramble_data[1],scramble_data[0]};
- }
-
-}
Index: trunk/scramble8.vri
===================================================================
--- trunk/scramble8.vri (revision 7)
+++ trunk/scramble8.vri (nonexistent)
@@ -1,70 +0,0 @@
-// ===========================================================================
-// File : scramble8.vri
-// Author : cwinward
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: scramble8.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file scrambles the rx lines and descrambles the tx lines.
-//
-// ===========================================================================
-// ===========================================================================
-#include
-
-
-
-task scramble8(bit [7:0] data_in, bit skp_detect, bit com_detect, bit sram_bypass, bit [15:0] lfsr_old, var bit [7:0] scramble_data, var bit [15:0] lfsr) {
-
-
- if((sram_bypass == 1'b1) | (com_detect == 1'b1)) {
- scramble_data = data_in;
- }
- else {
- scramble_data[0] = lfsr_old[15] ^ data_in[0];
- scramble_data[1] = lfsr_old[14] ^ data_in[1];
- scramble_data[2] = lfsr_old[13] ^ data_in[2];
- scramble_data[3] = lfsr_old[12] ^ data_in[3];
- scramble_data[4] = lfsr_old[11] ^ data_in[4];
- scramble_data[5] = lfsr_old[10] ^ data_in[5];
- scramble_data[6] = lfsr_old[9] ^ data_in[6];
- scramble_data[7] = lfsr_old[8] ^ data_in[7];
- }
-
-
- if(com_detect == 1'b1) {
- lfsr = 16'hFFFF;
- }
- else if(skp_detect == 1'b0) {
- lfsr[0] = lfsr_old[8];
- lfsr[1] = lfsr_old[9];
- lfsr[2] = lfsr_old[10];
- lfsr[3] = lfsr_old[8] ^ lfsr_old[11];
- lfsr[4] = lfsr_old[8] ^ lfsr_old[9] ^ lfsr_old[12];
- lfsr[5] = lfsr_old[8] ^ lfsr_old[9] ^ lfsr_old[10] ^ lfsr_old[13];
- lfsr[6] = lfsr_old[9] ^ lfsr_old[10] ^ lfsr_old[11] ^ lfsr_old[14];
- lfsr[7] = lfsr_old[10] ^ lfsr_old[11] ^ lfsr_old[12] ^ lfsr_old[15];
- lfsr[8] = lfsr_old[0] ^ lfsr_old[11] ^ lfsr_old[12] ^ lfsr_old[13];
- lfsr[9] = lfsr_old[1] ^ lfsr_old[12] ^ lfsr_old[13] ^ lfsr_old[14];
- lfsr[10] = lfsr_old[2] ^ lfsr_old[13] ^ lfsr_old[14] ^ lfsr_old[15];
- lfsr[11] = lfsr_old[3] ^ lfsr_old[14] ^ lfsr_old[15];
- lfsr[12] = lfsr_old[4] ^ lfsr_old[15];
- lfsr[13] = lfsr_old[5];
- lfsr[14] = lfsr_old[6];
- lfsr[15] = lfsr_old[7];
- }
- else {
- lfsr = lfsr_old;
- }
-
-}
Index: trunk/pcie_dllp_packet.vri
===================================================================
--- trunk/pcie_dllp_packet.vri (revision 7)
+++ trunk/pcie_dllp_packet.vri (nonexistent)
@@ -1,150 +0,0 @@
-// ===========================================================================
-// File : pcie_dllp_packet.vri
-// Author : cwinward
-// Date : Mon Dec 3 11:03:46 MST 2007
-// Project : TI PHY design
-//
-// Copyright (c) notice
-// This code adheres to the GNU public license
-//
-// ===========================================================================
-//
-// $Id: pcie_dllp_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
-//
-// ===========================================================================
-//
-// $Log: not supported by cvs2svn $
-//
-// ===========================================================================
-// Function : This file is a class of pcie packet can be used for all DLLP
-// packet types.
-//
-// ===========================================================================
-// ===========================================================================
-#include
-
-class pcie_dllp_packet {
- bit [7:0] byte3;
- bit [7:0] byte2;
- bit [7:0] byte1;
- bit [7:0] dllp_type;
- bit [31:0] temp_packet[];
-
- task new(
- bit [7:0] init_byte3 = 8'h40,
- bit [7:0] init_byte2 = 8'h00,
- bit [7:0] init_byte1 = 8'h01,
- bit [7:0] init_dllp_type = 8'b01000000) {
-
- dllp_type = init_dllp_type;
- byte1 = init_byte1;
- byte2 = init_byte2;
- byte3 = init_byte3;
- }
-
- task build_packet (string pkt_type = "initfc1_p") {
- if(pkt_type == "initfc1_p") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc1_np") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc1_cpl") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc2_p") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc2_np") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if(pkt_type == "initfc1_cpl") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
- else if (pkt_type == "ack") {
- temp_packet[0] = {byte3,byte2,byte1,dllp_type};
- temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
- }
-
- }
-
- function bit[15:0] crc16d32(bit[31:0] d) {
-
- bit [15:0] crc;
- bit [15:0] C = 32'hFFFF;
-
- crc[0] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[8] ^ d[10] ^ d[11] ^ d[16] ^ d[18] ^
- d[19] ^ d[23] ^ d[27] ^ d[31] ^ C[4] ^ C[5] ^ C[7] ^ C[10] ^ C[12]
- ^ C[13] ^ C[15];
- crc[1] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[5] ^ d[7] ^ d[8] ^ d[9] ^ d[11] ^ d[15]
- ^ d[16] ^ d[17] ^ d[19] ^ d[22] ^ d[23] ^ d[26] ^ d[27] ^ d[30] ^
- d[31] ^ C[0] ^ C[4] ^ C[6] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ C[12] ^
- C[14] ^ C[15];
- crc[2] = d[0] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[14] ^ d[15]
- ^ d[16] ^ d[18] ^ d[21] ^ d[22] ^ d[25] ^ d[26] ^ d[29] ^ d[30] ^
- C[0] ^ C[1] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^
- C[15];
- crc[3] = d[0] ^ d[1] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[13] ^
- d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[23]
- ^ d[24] ^ d[25] ^ d[27] ^ d[28] ^ d[29] ^ d[31] ^ C[0] ^ C[1] ^ C[2]
- ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[14] ^ C[15];
- crc[4] = d[0] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[12] ^ d[13] ^
- d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[23]
- ^ d[24] ^ d[26] ^ d[27] ^ d[28] ^ d[30] ^ C[0] ^ C[1] ^ C[2] ^ C[3]
- ^ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[15];
- crc[5] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[11] ^ d[12] ^ d[13] ^
- d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[21] ^ d[22] ^ d[23]
- ^ d[25] ^ d[26] ^ d[27] ^ d[29] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4]
- ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[11];
- crc[6] = d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[11] ^ d[12] ^
- d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[22]
- ^ d[24] ^ d[25] ^ d[26] ^ d[28] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4]
- ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ C[12];
- crc[7] = d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[9] ^ d[10] ^ d[11] ^ d[12]
- ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[19] ^ d[20] ^ d[21] ^
- d[23] ^ d[24] ^ d[25] ^ d[27] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
- C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ C[12] ^ C[13];
- crc[8] = d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[8] ^ d[9] ^ d[10] ^ d[11]
- ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^
- d[22] ^ d[23] ^ d[24] ^ d[26] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
- C[5] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[12] ^ C[13] ^ C[14];
- crc[9] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
- ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[17] ^ d[18] ^ d[19] ^
- d[21] ^ d[22] ^ d[23] ^ d[25] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
- C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ C[12] ^ C[13] ^ C[14]
- ^ C[15];
- crc[10] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
- ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^
- d[21] ^ d[22] ^ d[24] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^
- C[7] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[14] ^ C[15];
- crc[11] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
- ^ d[11] ^ d[12] ^ d[13] ^ d[15] ^ d[16] ^ d[17] ^ d[19] ^ d[20] ^
- d[21] ^ d[23] ^ C[0] ^ C[2] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ C[8]
- ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[14] ^ C[15];
- crc[12] = d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[9] ^ d[12] ^ d[14] ^ d[15] ^
- d[20] ^ d[22] ^ d[23] ^ d[27] ^ d[31] ^ C[0] ^ C[1] ^ C[3] ^ C[6]
- ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[14];
- crc[13] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[8] ^ d[11] ^ d[13] ^ d[14] ^
- d[19] ^ d[21] ^ d[22] ^ d[26] ^ d[30] ^ C[1] ^ C[2] ^ C[4] ^ C[7]
- ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15];
- crc[14] = d[1] ^ d[2] ^ d[4] ^ d[5] ^ d[7] ^ d[10] ^ d[12] ^ d[13] ^ d[18] ^
- d[20] ^ d[21] ^ d[25] ^ d[29] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10]
- ^ C[11] ^ C[13] ^ C[14];
- crc[15] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[9] ^ d[11] ^ d[12] ^ d[17] ^
- d[19] ^ d[20] ^ d[24] ^ d[28] ^ C[3] ^ C[4] ^ C[6] ^ C[9] ^ C[11]
- ^ C[12] ^ C[14] ^ C[15];
-
- crc16d32 = {~crc[0],~crc[1],~crc[2],~crc[3],~crc[4],~crc[5],~crc[6],~crc[7],
- ~crc[8],~crc[9],~crc[10],~crc[11],~crc[12],~crc[13],~crc[14],~crc[15]};
-
- return;
- }
-
-
- }
Index: trunk/run_vera
===================================================================
--- trunk/run_vera (revision 7)
+++ trunk/run_vera (nonexistent)
@@ -1,10 +0,0 @@
-#!/bin/csh -f
-
-\rm -rf simv csrc simv.daidir comp.log sim.log
-
- vcs -ntb ti_phy_top.test_top.v ti_phy_top.v ti_phy_top.vr \
- -P /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/debussy.tab \
- /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/pli.a \
- -Mupdate -l vcs_compile.log +vcs+lic+wait +define+SYNOPSYS_NTB -l comp.log $*
-
- ./simv -l sim.log $*
trunk/run_vera
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: pcie_vera_tb/trunk/ti_phy_top.test_top.v
===================================================================
--- pcie_vera_tb/trunk/ti_phy_top.test_top.v (nonexistent)
+++ pcie_vera_tb/trunk/ti_phy_top.test_top.v (revision 8)
@@ -0,0 +1,285 @@
+// ===========================================================================
+// File : ti_phy_top.test_top.v
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+// Please contact www.gutzlogic.com for details.
+// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
+// ===========================================================================
+//
+// $Id: ti_phy_top.test_top.v,v 1.3 2008-01-15 03:25:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2 2007/12/05 23:00:33 cmagleby
+// add sram for real rtl
+//
+// Revision 1.1.1.1 2007/12/05 18:37:07 cmagleby
+// importing tb files
+//
+//
+// ===========================================================================
+// Function : This is the top level testbench file.
+//
+// ===========================================================================
+// ===========================================================================
+`timescale 1 ns/100 ps
+module ti_phy_top_test_top;
+ parameter simulation_cycle = 8;
+
+ reg SystemClock;
+ wire clk_50mhz;
+ wire [1:0] PUSH_BUTTON;
+ wire FPGA_RESET_n;
+ wire PERST_n;
+ wire rxclk;
+ wire [15:0] rxdata16;
+ wire [1:0] rxdatak16;
+ wire rxvalid16;
+ wire rxidle16;
+ wire [2:0] rxstatus;
+ wire phystatus;
+ wire [7:0] LED;
+ wire txclk;
+ wire [15:0] txdata16;
+ wire [1:0] txdatak16;
+ wire txidle16;
+ wire rxdet_loopb;
+ wire txcomp;
+ wire rxpol;
+ wire phy_reset_n;
+ wire [1:0] pwrdwn;
+ wire [16:0] sram_addr;
+ wire sram_adscn;
+ wire sram_adspn;
+ wire sram_advn;
+ wire [3:0] sram_ben;
+ wire [2:0] sram_ce;
+ wire sram_clk;
+ wire sram_gwn;
+ wire sram_mode;
+ wire sram_oen;
+ wire sram_wen;
+ wire sram_zz;
+ wire [35:0] sram_data;
+ assign rxclk = SystemClock;
+ assign PERST_n = FPGA_RESET_n;
+
+`ifdef SYNOPSYS_NTB
+ ti_phy_top_test vshell(
+ .SystemClock (SystemClock),
+ .\ti_phy_top.clk_50mhz (clk_50mhz),
+ .\ti_phy_top.PUSH_BUTTON (PUSH_BUTTON),
+ .\ti_phy_top.FPGA_RESET_n (FPGA_RESET_n),
+ .\ti_phy_top.PERST_n (PERST_n),
+ .\ti_phy_top.rxclk (rxclk),
+ .\ti_phy_top.rxdata16 (rxdata16),
+ .\ti_phy_top.rxdatak16 (rxdatak16),
+ .\ti_phy_top.rxvalid16 (rxvalid16),
+ .\ti_phy_top.rxidle16 (rxidle16),
+ .\ti_phy_top.rxstatus (rxstatus),
+ .\ti_phy_top.phystatus (phystatus),
+ .\ti_phy_top.sram_data (sram_data),
+ .\ti_phy_top.LED (LED),
+ .\ti_phy_top.txclk (txclk),
+ .\ti_phy_top.txdata16 (txdata16),
+ .\ti_phy_top.txdatak16 (txdatak16),
+ .\ti_phy_top.txidle16 (txidle16),
+ .\ti_phy_top.rxdet_loopb (rxdet_loopb),
+ .\ti_phy_top.txcomp (txcomp),
+ .\ti_phy_top.rxpol (rxpol),
+ .\ti_phy_top.phy_reset_n (phy_reset_n),
+ .\ti_phy_top.pwrdwn (pwrdwn),
+ .\ti_phy_top.sram_addr (sram_addr),
+ .\ti_phy_top.sram_adscn (sram_adscn),
+ .\ti_phy_top.sram_adspn (sram_adspn),
+ .\ti_phy_top.sram_advn (sram_advn),
+ .\ti_phy_top.sram_ben (sram_ben),
+ .\ti_phy_top.sram_ce (sram_ce),
+ .\ti_phy_top.sram_clk (sram_clk),
+ .\ti_phy_top.sram_gwn (sram_gwn),
+ .\ti_phy_top.sram_mode (sram_mode),
+ .\ti_phy_top.sram_oen (sram_oen),
+ .\ti_phy_top.sram_wen (sram_wen),
+ .\ti_phy_top.sram_zz (sram_zz)
+ );
+`else
+
+ vera_shell vshell(
+ .SystemClock (SystemClock),
+ .ti_phy_top_clk_50mhz (clk_50mhz),
+ .ti_phy_top_PUSH_BUTTON (PUSH_BUTTON),
+ .ti_phy_top_FPGA_RESET_n (FPGA_RESET_),
+ .ti_phy_top_rxclk (rxclk),
+ .ti_phy_top_rxdata16 (rxdata16),
+ .ti_phy_top_rxdatak16 (rxdatak16),
+ .ti_phy_top_rxvalid16 (rxvalid16),
+ .ti_phy_top_rxidle16 (rxidle16),
+ .ti_phy_top_rxstatus (rxstatus),
+ .ti_phy_top_phystatus (phystatus),
+ .ti_phy_top_sram_data (sram_data),
+ .ti_phy_top_LED (LED),
+ .ti_phy_top_txclk (txclk),
+ .ti_phy_top_txdata16 (txdata16),
+ .ti_phy_top_txdatak16 (txdatak16),
+ .ti_phy_top_txidle16 (txidle16),
+ .ti_phy_top_rxdet_loopb (rxdet_loopb),
+ .ti_phy_top_txcomp (txcomp),
+ .ti_phy_top_rxpol (rxpol),
+ .ti_phy_top_phy_reset_n (phy_reset_n),
+ .ti_phy_top_pwrdwn (pwrdwn),
+ .ti_phy_top_sram_addr (sram_addr),
+ .ti_phy_top_sram_adscn (sram_adscn),
+ .ti_phy_top_sram_adspn (sram_adspn),
+ .ti_phy_top_sram_advn (sram_advn),
+ .ti_phy_top_sram_ben (sram_ben),
+ .ti_phy_top_sram_ce (sram_ce),
+ .ti_phy_top_sram_clk (sram_clk),
+ .ti_phy_top_sram_gwn (sram_gwn),
+ .ti_phy_top_sram_mode (sram_mode),
+ .ti_phy_top_sram_oen (sram_oen),
+ .ti_phy_top_sram_wen (sram_wen),
+ .ti_phy_top_sram_zz (sram_zz)
+ );
+`endif
+
+
+
+`ifdef emu
+ /* DUT is in emulator, so not instantiated here */
+`else
+ ti_phy_top dut(
+ .clk_50mhz (clk_50mhz),
+ .PUSH_BUTTON (PUSH_BUTTON),
+ .FPGA_RESET_n (FPGA_RESET_n),
+ .PERST_n (PERST_n),
+ .rxclk (rxclk),
+ .rxdata16 (rxdata16),
+ .rxdatak16 (rxdatak16),
+ .rxvalid16 (rxvalid16),
+ .rxidle16 (rxidle16),
+ .rxstatus (rxstatus),
+ .phystatus (phystatus),
+ .sram_data (sram_data),
+ .LED (LED),
+ .txclk (txclk),
+ .txdata16 (txdata16),
+ .txdatak16 (txdatak16),
+ .txidle16 (txidle16),
+ .rxdet_loopb (rxdet_loopb),
+ .txcomp (txcomp),
+ .rxpol (rxpol),
+ .phy_reset_n (phy_reset_n),
+ .pwrdwn (pwrdwn),
+ .sram_addr (sram_addr),
+ .sram_adscn (sram_adscn),
+ .sram_adspn (sram_adspn),
+ .sram_advn (sram_advn),
+ .sram_ben (sram_ben),
+ .sram_ce (sram_ce),
+ .sram_clk (sram_clk),
+ .sram_gwn (sram_gwn),
+ .sram_mode (sram_mode),
+ .sram_oen (sram_oen),
+ .sram_wen (sram_wen),
+ .sram_zz (sram_zz)
+ );
+`endif
+
+ always @ (posedge SystemClock) begin
+ if (|rxdatak16)
+ $display($time,":datak symbol");
+ end
+
+ reg set_once;
+ //simulation short ts1 sets
+`ifdef REAL_RTL
+ always @ (posedge SystemClock) begin
+ if (dut.phy_layer_top_inst.send_ts1 & ~set_once) begin
+ force dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count = 10'b1111000000;
+ set_once <= #1 1'b1;
+
+ end
+ else begin
+ release dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count;
+ if (dut.phy_layer_top_inst.ltssm_32bit_inst.start_link_training_pm) begin
+ set_once <= #1 1'b0;
+ end
+ end
+ end // always @ (posedge ti_phy_top_inst.clk_125mhz)
+
+ /* -----\/----- EXCLUDED -----\/-----
+ idt71v25761s200 AUTO_TEMPLATE (
+ .D (sram_data[31:0]),
+ .DP (sram_data[35:32]),
+ // Inputs
+ .A (sram_addr),
+ .oe_ (sram_oen),
+ .ce_ (sram_ce[0]),
+ .cs0 (sram_ce[1]),
+ .cs1_ (sram_ce[2]),
+ .lbo_ (sram_mode),
+ .gw_ (sram_gwn),
+ .bwe_ (sram_wen),
+ .bw4_ (sram_ben[3]),
+ .bw3_ (sram_ben[2]),
+ .bw2_ (sram_ben[1]),
+ .bw1_ (sram_ben[0]),
+ .adsp_(sram_adspn),
+ .adsc_(sram_adscn),
+ .adv_ (sram_advn),
+ .clk (sram_clk));
+ -----/\----- EXCLUDED -----/\----- */
+
+ idt71v25761s200 SRAM_MODEL_inst (/*AUTOINST*/
+ // Inouts
+ .D (sram_data[31:0]), // Templated
+ .DP (sram_data[35:32]), // Templated
+ // Inputs
+ .A (sram_addr), // Templated
+ .oe_ (sram_oen), // Templated
+ .ce_ (sram_ce[0]), // Templated
+ .cs0 (sram_ce[1]), // Templated
+ .cs1_ (sram_ce[2]), // Templated
+ .lbo_ (sram_mode), // Templated
+ .gw_ (sram_gwn), // Templated
+ .bwe_ (sram_wen), // Templated
+ .bw4_ (sram_ben[3]), // Templated
+ .bw3_ (sram_ben[2]), // Templated
+ .bw2_ (sram_ben[1]), // Templated
+ .bw1_ (sram_ben[0]), // Templated
+ .adsp_(sram_adspn), // Templated
+ .adsc_(sram_adscn), // Templated
+ .adv_ (sram_advn), // Templated
+ .clk (sram_clk)); // Templated
+
+`endif
+
+ initial begin
+ //****************************************************************************************
+ //force scramble bypass until the tb can scramble and de-scramble data.
+ //force dut.phy_layer_top_inst.make_rxdata_path16.scramble16_inst.scram_bypass = 2'b11;
+ //force dut.phy_layer_top_inst.make_tx_data_path16.scramble16_inst.scram_bypass = 2'b11;
+ //****************************************************************************************
+ set_once = 0;
+ SystemClock = 0;
+ forever begin
+ #(simulation_cycle/2)
+ SystemClock = ~SystemClock;
+ end
+
+ end // initial begin
+
+`ifdef REAL_RTL
+ initial begin
+ $fsdbDumpfile("vera_test.fsdb");
+ $fsdbDumpvars(dut);
+ end
+`endif
+
+
+endmodule
Index: pcie_vera_tb/trunk/ti_phy_top.v
===================================================================
--- pcie_vera_tb/trunk/ti_phy_top.v (nonexistent)
+++ pcie_vera_tb/trunk/ti_phy_top.v (revision 8)
@@ -0,0 +1,204 @@
+// ===========================================================================
+// File : ti_phy_top.v
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+// Please contact www.gutzlogic.com for details.
+// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
+//
+// ===========================================================================
+//
+// $Id: ti_phy_top.v,v 1.2 2008-01-15 03:25:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2007/12/05 18:37:06 cmagleby
+// importing tb files
+//
+//
+// ===========================================================================
+// Function : This file is non-synthesizable rtl file to demonstrate TS1's.
+// Insert your own RTL design here. It has dummy signals for a sram if that
+// can be ignored.
+// ===========================================================================
+// ===========================================================================
+
+module ti_phy_top (/*AUTOARG*/
+ // Outputs
+ LED, txclk, txdata16, txdatak16, txidle16, rxdet_loopb, txcomp,
+ rxpol, phy_reset_n, pwrdwn, sram_addr, sram_adscn, sram_adspn,
+ sram_advn, sram_ben, sram_ce, sram_clk, sram_gwn, sram_mode,
+ sram_oen, sram_wen, sram_zz,
+ // Inouts
+ sram_data,
+ // Inputs
+ clk_50mhz, PUSH_BUTTON, FPGA_RESET_n, PERST_n, rxclk, rxdata16,
+ rxdatak16, rxvalid16, rxidle16, rxidle, rxstatus, phystatus
+ );
+ //****************************************************************************************
+ //TI PHY interface
+ //****************************************************************************************
+ //debug ports
+ input clk_50mhz;
+ input [1:0] PUSH_BUTTON;
+ output [7:0] LED;
+ reg [7:0] LED;
+ input FPGA_RESET_n;
+ input PERST_n;
+ //****************************************************************************************
+ //Phillips PHY interface
+ output txclk; //source synch 250 Mhz transmit clock from MAC.
+ wire txclk;
+
+ output [15:0] txdata16;
+ reg [15:0] txdata16;
+ output [1:0] txdatak16;
+ reg [1:0] txdatak16;
+ output txidle16; //forces tx output to electrical idle. txidle should be asserted while in power states p0 and p1.
+ reg txidle16;
+ input rxclk; //source synch 250 clk for received data.
+ input [15:0] rxdata16;
+ input [1:0] rxdatak16;
+ input rxvalid16;
+ output rxdet_loopb; //used to tell the phy to begin
+ reg rxdet_loopb;
+ input rxidle16;
+ input rxidle; //indicates receiver detection of an electrical idle; This is a synchronous signal.
+ input [2:0] rxstatus; //encodes receiver status and error codes.
+
+ input phystatus; //used to communicate completion of several phy functions.
+ output txcomp; //used when transmitting the compliance pattern; high-level sets the running disparity to negative.
+ reg txcomp;
+ output rxpol; //signals the phy to perform a polarity inversion on the receive data; low = no polarity inversion; high = polarity inversion.
+ reg rxpol;
+ output phy_reset_n; //phy reset active low
+ reg phy_reset_n;
+ output [1:0] pwrdwn;
+ reg [1:0] pwrdwn;
+
+ //****************************************************************************************
+ //SRAM Interface
+ output [16:0] sram_addr;
+ reg [16:0] sram_addr;
+ output sram_adscn;
+ reg sram_adscn;
+ output sram_adspn;
+ reg sram_adspn;
+ output sram_advn;
+ reg sram_advn;
+ output [3:0] sram_ben;
+ reg [3:0] sram_ben;
+ output [2:0] sram_ce;
+ reg [2:0] sram_ce;
+ output sram_clk;
+ reg sram_clk;
+ output sram_gwn;
+ reg sram_gwn;
+ output sram_mode;
+ reg sram_mode;
+ output sram_oen;
+ reg sram_oen;
+ output sram_wen;
+ reg sram_wen;
+ output sram_zz;
+ reg sram_zz;
+ inout [35:0] sram_data;
+
+
+ assign txclk = rxclk;
+ reg continue;
+
+ initial begin
+ LED <= 'b0;
+ txdata16 <= 15'b0;
+ txdatak16 <= 2'b0;
+ txidle16 <= 1'b0;
+ pwrdwn <= 2'b0;
+ phy_reset_n <= 1'b0;
+ rxpol <= 1'b0;
+ txcomp <= 1'b0;
+ rxdet_loopb <= 1'b0;
+ phy_reset_n <= 1'b0;
+ //ignore these signals
+ sram_addr <= 'b0;
+ sram_adscn <= 'b0;
+ sram_adspn <= 'b0;
+ sram_advn <= 'b0;
+ sram_ben <= 'b0;
+ sram_ce <= 'b0;
+ sram_clk <= 'b0;
+ sram_gwn <= 'b0;
+ sram_mode <= 'b0;
+ sram_oen <= 'b0;
+ sram_wen <= 'b0;
+ sram_zz <= 'b0;
+ //sram_data <= 'b0;
+ continue <= 1'b1;
+ #100;
+ phy_reset_n <= 1'b1;
+ sample_ts1();
+ end
+
+ task sample_ts1;
+ begin
+ pwrdwn <= 2'b10;
+ @ (negedge rxclk);
+ wait (phystatus == 0); //indicate that the pll is locked.
+ repeat (20) @ (negedge rxclk);
+ rxdet_loopb <= 1'b1;
+ wait (phystatus == 1'b1 && rxstatus == 3'b11); //receiver detect
+ repeat (5) @ (negedge rxclk);
+ rxdet_loopb <= 1'b0;
+ repeat (2) @ (negedge rxclk);
+ pwrdwn <= 2'b0;
+ wait (phystatus == 1'b0);
+ wait (phystatus == 1'b1 && rxstatus == 4'b100); //power change accept
+ repeat (100) @ (negedge rxclk);
+
+ while (continue == 1) begin
+ //start sending ts1;
+ @ (negedge rxclk);
+ txdatak16 <= 2'b11;
+ txdata16 <= 16'hf7bc; //PAD LINK,COM
+ @ (negedge rxclk);
+ txdatak16 <= 2'b01;
+ txdata16 <= 16'hf0f7; //NFST,PAD LANE
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h02; //training control Rate ID
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ //add sending ts2;
+ //add link and lane
+ end // while (continue == 1)
+ end
+ endtask // sample_ts1
+
+
+
+
+
+
+endmodule
+
+
+// Local Variables:
+// verilog-library-directories:("." "./dcm" "./ddr_div2" "./single_dcm" "./dll" "./tl")
+// End:
\ No newline at end of file
Index: pcie_vera_tb/trunk/ti_phy_top.if.vrh
===================================================================
--- pcie_vera_tb/trunk/ti_phy_top.if.vrh (nonexistent)
+++ pcie_vera_tb/trunk/ti_phy_top.if.vrh (revision 8)
@@ -0,0 +1,67 @@
+// ===========================================================================
+// File : ti_phy_top.if.vrh
+// Author : cwinward
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: ti_phy_top.if.vrh,v 1.2 2008-01-15 03:25:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2007/12/05 18:37:07 cmagleby
+// importing tb files
+//
+//
+// ===========================================================================
+// Function : .This is the interface file linking verilog with VERA
+//
+// ===========================================================================
+// ===========================================================================
+#ifndef INC_TI_PHY_TOP_IF_VRH
+#define INC_TI_PHY_TOP_IF_VRH
+
+ interface ti_phy_top {
+ input rxclk CLOCK;
+ //input [9:0] t1_count PSAMPLE #-1 verilog_node "dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count";
+ output clk_50mhz OUTPUT_EDGE OUTPUT_SKEW;
+ output [1:0] PUSH_BUTTON OUTPUT_EDGE OUTPUT_SKEW;
+ output FPGA_RESET_n OUTPUT_EDGE OUTPUT_SKEW;
+ output PERST_n OUTPUT_EDGE OUTPUT_SKEW;
+ output [15:0] rxdata16 OUTPUT_EDGE OUTPUT_SKEW;
+ output [1:0] rxdatak16 OUTPUT_EDGE OUTPUT_SKEW;
+ output rxvalid16 OUTPUT_EDGE OUTPUT_SKEW;
+ output rxidle16 OUTPUT_EDGE OUTPUT_SKEW;
+ output [2:0] rxstatus OUTPUT_EDGE OUTPUT_SKEW;
+ output phystatus OUTPUT_EDGE OUTPUT_SKEW;
+ input [7:0] LED INPUT_EDGE INPUT_SKEW;
+ input txclk INPUT_EDGE INPUT_SKEW;
+ input [15:0] txdata16 INPUT_EDGE INPUT_SKEW;
+ input [1:0] txdatak16 INPUT_EDGE INPUT_SKEW;
+ input txidle16 INPUT_EDGE INPUT_SKEW;
+ input rxdet_loopb INPUT_EDGE INPUT_SKEW;
+ input txcomp INPUT_EDGE INPUT_SKEW;
+ input rxpol INPUT_EDGE INPUT_SKEW;
+ input phy_reset_n INPUT_EDGE INPUT_SKEW;
+ input [1:0] pwrdwn INPUT_EDGE INPUT_SKEW;
+ input [16:0] sram_addr INPUT_EDGE INPUT_SKEW;
+ input sram_adscn INPUT_EDGE INPUT_SKEW;
+ input sram_adspn INPUT_EDGE INPUT_SKEW;
+ input sram_advn INPUT_EDGE INPUT_SKEW;
+ input [3:0] sram_ben INPUT_EDGE INPUT_SKEW;
+ input [2:0] sram_ce INPUT_EDGE INPUT_SKEW;
+ input sram_clk INPUT_EDGE INPUT_SKEW;
+ input sram_gwn INPUT_EDGE INPUT_SKEW;
+ input sram_mode INPUT_EDGE INPUT_SKEW;
+ input sram_oen INPUT_EDGE INPUT_SKEW;
+ input sram_wen INPUT_EDGE INPUT_SKEW;
+ input sram_zz INPUT_EDGE INPUT_SKEW;
+ inout [35:0] sram_data INPUT_EDGE INPUT_SKEW OUTPUT_EDGE OUTPUT_SKEW;
+ } // end of interface ti_phy_top
+
+#endif
Index: pcie_vera_tb/trunk/receive_packet.vri
===================================================================
--- pcie_vera_tb/trunk/receive_packet.vri (nonexistent)
+++ pcie_vera_tb/trunk/receive_packet.vri (revision 8)
@@ -0,0 +1,306 @@
+// ===========================================================================
+// File : receive_packet.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: receive_packet.vri,v 1.2 2007-12-07 20:16:29 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2007/12/05 18:37:06 cmagleby
+// importing tb files
+//
+//
+// ===========================================================================
+// Function : This file processes all packets received from the 16 tx interface
+//
+// ===========================================================================
+// ===========================================================================
+#include
+#include "scramble8.vri"
+#define COM_s 8'hbc
+#define SKP_s 8'h1c
+#define IDLE_s 8'h7c
+#define FTS_s 8'h3c
+#define STP_s 8'hfb
+#define SDP_s 8'h5c
+#define EDB 8'hfe
+#define END_s 8'hfd
+
+task receive_packet () {
+ bit [7:0] tx_data[];
+ bit tx_datak[];
+ integer ret,ret1,ret2,ret3,ret4;
+ integer i = 0;
+ integer m = 0;
+ bit[8:0] tx_pkt;
+ event phy_start, phy_done, tlp_start, tlp_done, dllp_start, dllp_done;
+ bit [7:0] phy_pkt[];
+ bit [7:0] dll_pkt[];
+ bit [7:0] tlp_pkt[];
+ integer j,k,l;
+ bit [127:0] build_phy_pkt;
+ bit [47:0] build_dll_pkt;
+ bit [127:0] build_tlp_header;
+ bit [31:0] build_tlp_data;
+ bit [15:0] expected_seq_id = 0;
+ bit [15:0] recv_seq_id = 0;
+ bit [9:0] recv_length = 0;
+ bit [11:0] byte_length = 0;
+ bit [31:0] recv_lcrc = 0;
+ bit td = 0;
+ integer kstart = 0;
+ integer debug = 1;
+ bit [15:0] lfsr = 16'hFFFF;
+ bit [7:0] scramble_data[];
+ bit skp_detect = 1'b0;
+ bit com_detect = 1'b0;
+ bit scram_bypass = 1'b0;
+ bit [3:0] bypass_count = 4'b0;
+
+ printf("Look for transmit packets\n");
+ wait_var(phy_rdy);
+ @ (posedge CLOCK);
+ fork
+ while (1) {
+ @ (posedge CLOCK);
+ tx_data[0] = ti_phy_top.txdata16[7:0];
+ tx_data[1] = ti_phy_top.txdata16[15:8];
+ tx_datak[0] = ti_phy_top.txdatak16[0];
+ tx_datak[1] = ti_phy_top.txdatak16[1];
+ for (i=0; i<2; i++) {
+
+ if(com_detect == 1'b1){
+ scram_bypass = 1'b1;
+ }
+ else if(((bypass_count == 4'b0011) & tx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
+ scram_bypass = 1'b0;
+ }
+
+ if((com_detect == 1'b1) | scram_bypass){
+ bypass_count = bypass_count + 1'b1;
+ }
+ else if(((bypass_count == 4'b0011) & tx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
+ bypass_count = 4'b0000;
+ }
+
+
+ if({tx_datak[i],tx_data[i]} == {1'b1,SKP_s}){
+ skp_detect = 1'b1;
+ }
+ else{
+ skp_detect = 1'b0;
+ }
+ if({tx_datak[i],tx_data[i]} == {1'b1,COM_s}){
+ com_detect = 1'b1;
+ }
+ else{
+ com_detect = 1'b0;
+ }
+
+
+ //printf("K-Code = %h DATA = %h COM = %h SKP = %h bypass_count = %d scram_bypass = %h\n",tx_datak[i],tx_data[i],com_detect,skp_detect,bypass_count,scram_bypass);
+
+ //if({tx_datak[i],tx_data[i]} == {1'b1,STP_s}){
+ // printf("Start of TLP packet.\n");
+ //}
+
+ scramble8(tx_data[i],skp_detect,com_detect,(scram_bypass | tx_datak[i]),lfsr,scramble_data[i],lfsr);
+ //printf("K-Code = %h COM = %h SKP = %h bypass = %h scramble_data = %h unscramble_data = %h lfsr = %h bypass_cnt = %d\n",tx_datak[i],com_detect,skp_detect,scram_bypass,tx_data[i],scramble_data[i],lfsr,bypass_count);
+
+ mailbox_put (tx_data_mailbox, {tx_datak[i],scramble_data[i]});
+ //printf("Add packet to tx_mailbox %0h\n",tx_data[i]);
+
+ }
+ }
+ while (1) {
+ ret = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ if (ret <= 0)
+ error ("mailbox_get returned %0d\n",ret);
+ //printf ("got tx_pkt %0h\n",tx_pkt);
+ if (tx_pkt == {1'b1,COM_s}) {
+ trigger (ONE_BLAST,phy_start);
+ sync (ALL,phy_done);
+ }
+ if (tx_pkt == {1'b1,STP_s}) {
+ trigger (ONE_BLAST,tlp_start);
+ sync (ALL,tlp_done);
+ }
+ if (tx_pkt == {1'b1,SDP_s}) {
+ trigger (ONE_BLAST,dllp_start);
+ sync (ALL,dllp_done);
+ }
+ }
+ //phy layer packets
+ while (1) {
+ sync(ALL,phy_start);
+ //printf ("got past sync %0h\n",tx_pkt);
+ phy_pkt[0] = COM_s;
+ phy_pkt[4] = 0;
+ phy_pkt[5] = 0;
+ phy_pkt[6] = 0;
+ phy_pkt[7] = 0;
+ phy_pkt[8] = 0;
+ phy_pkt[9] = 0;
+ phy_pkt[10] = 0;
+ phy_pkt[11] = 0;
+ phy_pkt[12] = 0;
+ phy_pkt[13] = 0;
+ phy_pkt[14] = 0;
+ phy_pkt[15] = 0;
+ ret2 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ //printf ("got past mailbox get %0h\n",tx_pkt);
+ phy_pkt[1] = tx_pkt;
+ //training set
+ if ((tx_pkt == 'h1f7) || ~tx_pkt[8]) {
+ for (j = 2; j <16; j++) {
+ ret2 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ phy_pkt[j] = tx_pkt;
+ }
+ }
+ //skip fst idle
+ else {
+ for (j=2;j<4;j++) {
+ ret1 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ phy_pkt[j] = tx_pkt;
+ //printf ("skip loop got past %0h\n",tx_pkt);
+ }
+ }
+ build_phy_pkt = {phy_pkt[15],phy_pkt[14],phy_pkt[13],phy_pkt[12],phy_pkt[11],
+ phy_pkt[10],phy_pkt[9],phy_pkt[8],phy_pkt[7],phy_pkt[6],
+ phy_pkt[5],phy_pkt[4],phy_pkt[3],phy_pkt[2],phy_pkt[1],phy_pkt[0]};
+ mailbox_put (phy_mailbox, build_phy_pkt);
+ printf ("Recieved PHY PACKET (%0h) added to phy mailbox\n",build_phy_pkt);
+ trigger (ONE_BLAST,phy_done);
+ }
+ //dll layer packets
+ while (1) {
+ sync (ALL,dllp_start);
+ //printf ("sync into dllp packet\n");
+ for (k = 0; k < 6; k++) {
+ ret3 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ dll_pkt[k] = tx_pkt;
+ //printf ("dll_pkt(%0h)\n",dll_pkt[k]);
+ }
+ ret3 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ //printf ("dll this should be end(%0h)\n",tx_pkt);
+ if (tx_pkt == {1'b1,END_s}) {
+ build_dll_pkt = {dll_pkt[6],dll_pkt[5],dll_pkt[4],dll_pkt[3],
+ dll_pkt[2],dll_pkt[1],dll_pkt[0]};
+ mailbox_put (dllp_mailbox, build_dll_pkt);
+ printf ("Recieved DLL PACKET (%0h) added to dllp mailbox\n",build_dll_pkt);
+ }
+ else
+ printf ("ERROR ->>>>>>> DLL malformed no END\n");
+
+ trigger (ONE_BLAST,dllp_done);
+ }
+ //tlp layer packets
+ while (1) {
+ sync (ALL,tlp_start);
+ printf ("sync into tlp packet\n");
+ @(posedge CLOCK);
+ //3 dw header + seq.
+ for (k = 0; k < 14; k++) {
+ //printf("debug1 %0d\n",debug++);
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ tlp_pkt[k] = tx_pkt;
+ }
+ //dword 4
+ if (tlp_pkt[2][5] == 1'b1) {
+ for (k=14;k<18;k++) {
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ tlp_pkt[k] = tx_pkt;
+ }
+ }
+
+ //****************************************************************************************
+ //Check sequence ID and send ACK
+ recv_seq_id = {tlp_pkt[0],tlp_pkt[1]};
+ if (recv_seq_id != expected_seq_id) printf ("ERROR ->>>>>>> TLP BAD SEQUENCE ID of %0h\n",recv_seq_id);
+ else {
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ ack_seq_num = new(recv_seq_id[7:0],{4'b0,recv_seq_id[11:8]},8'b0,8'b0);
+ ack_seq_num.build_packet("ack");
+ printf("ACK PACKET Sequence Number (%0h)\n",recv_seq_id);
+ for(m=0; m <= 3; m ++) {
+ if(m==0){
+ mailbox_put (rx_data_mailbox, {2'b01,ack_seq_num.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",ack_seq_num.temp_packet[0][7:0],8'h5C);
+ }
+ else if(m==1){
+ mailbox_put (rx_data_mailbox, {2'b00,ack_seq_num.temp_packet[0][23:16],ack_seq_num.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",ack_seq_num.temp_packet[0][23:16],ack_seq_num.temp_packet[0][15:8]);
+ }
+ else if(m==2){
+ mailbox_put (rx_data_mailbox, {2'b00,ack_seq_num.temp_packet[1][7:0],ack_seq_num.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",ack_seq_num.temp_packet[1][7:0],ack_seq_num.temp_packet[0][31:24]);
+ }
+ else if(m==3){
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,ack_seq_num.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,ack_seq_num.temp_packet[1][15:8]);
+ }
+ }
+ semaphore_put (my_semaphore, 1);
+ }
+ expected_seq_id++;
+ //****************************************************************************************
+ //build tlp get all header information
+ build_tlp_header = {tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14],
+ tlp_pkt[13],tlp_pkt[12],tlp_pkt[11],tlp_pkt[10],
+ tlp_pkt[9],tlp_pkt[8],tlp_pkt[7],tlp_pkt[6],
+ tlp_pkt[5],tlp_pkt[4],tlp_pkt[3],tlp_pkt[2]};
+
+ if (build_tlp_header[5] == 1'b0) {
+ build_tlp_header[127:96] = 32'b0;
+ }
+ //****************************************************************************************
+ //put header in mailbox
+ mailbox_put (tlp_header_mailbox, build_tlp_header);
+ printf ("Recieved TLP PACKET (%0h) added to tlp header mailbox\n",build_tlp_header);
+ //****************************************************************************************
+ //check for data and put into mailbox
+ if (build_tlp_header[6] == 1) {
+ td = build_tlp_header[23];
+ recv_length = {build_tlp_header[17:16],build_tlp_header[31:24]};
+ byte_length = (recv_length*4) + (td*4);
+ printf ("TLP PACKET Receive Length dw(%0d) byte(%0d)\n",recv_length,byte_length);
+ for (k=1;k<=byte_length;k++) {
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ tlp_pkt[k] = tx_pkt;
+ if (k%4 ==0) {
+ mailbox_put (tlp_data_mailbox, {tlp_pkt[k],tlp_pkt[k-1],tlp_pkt[k-2],tlp_pkt[k-3]});
+ printf ("k = (%0d)\n",k);
+ printf ("Recieved TLP DATA (%0h) added to tlp data mailbox\n",{tlp_pkt[k],tlp_pkt[k-1],tlp_pkt[k-2],tlp_pkt[k-3]});
+ }
+
+ }
+ }
+ //****************************************************************************************
+ //Read out the LCRC
+ for (k=0;k<=3;k++) {
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ //printf("debug3 %0d\n",debug++);
+ tlp_pkt[k] = tx_pkt;
+ }
+ printf ("tlp lcrc value = %0h \n",{tlp_pkt[3],tlp_pkt[2],tlp_pkt[1],tlp_pkt[0]});
+
+ //****************************************************************************************
+ //READ out the END VALUE
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ if (tx_pkt != {1'b1,END_s}) printf ("ERROR ->>>>>>> TLP malformed no END(%0h)\n",tx_pkt);
+
+
+ trigger (ONE_BLAST,tlp_done);
+ }
+ join none
+}
+
Index: pcie_vera_tb/trunk/tlp_gen.vri
===================================================================
--- pcie_vera_tb/trunk/tlp_gen.vri (nonexistent)
+++ pcie_vera_tb/trunk/tlp_gen.vri (revision 8)
@@ -0,0 +1,277 @@
+// ===========================================================================
+// File : tlp_gen.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+// Please contact www.gutzlogic.com for details.
+// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
+// ===========================================================================
+//
+// $Id: tlp_gen.vri,v 1.2 2007-12-05 23:01:11 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2007/12/05 18:37:07 cmagleby
+// importing tb files
+//
+//
+// ===========================================================================
+// Function : This file generates cfgrd/wr memrd/wr.
+//
+// ===========================================================================
+// ===========================================================================
+#include
+#define STP_s 8'hfb
+#define EDB 8'hfe
+task tlp_gen() {
+
+ bit [15:0] req_id;
+ bit [7:0] busnum;
+ bit [7:0] reg_num;
+ bit [3:0] first_be;
+ bit [3:0] last_be;
+ bit [63:0] address;
+ bit [9:0] length;
+ bit [31:0] data;
+ bit [7:0] tag;
+
+ sequence_id = 0; reg_num=0;first_be=4'hf;req_id=0101;tag=1;busnum=1;
+ printf ("read vendor id\n");
+ cfgrd(reg_num,first_be,req_id,tag,busnum);
+
+ sequence_id++; reg_num='h5;first_be=4'hf;req_id=0101;tag++;busnum=1;
+ printf ("write base address 1 register\n");
+ cfgwr(reg_num,first_be,req_id,tag,busnum,32'hba120000);
+ sequence_id++;address = 64'hba120000;length=10'h5;first_be=4'hf;last_be=4'hf;req_id=16'h0100;tag++;
+ memwr(address,length,first_be,last_be,req_id,tag);
+ sequence_id++;
+ memrd(address,length,first_be,last_be,req_id,tag);
+}
+
+task cfgrd (bit [7:0] reg_num,
+ bit [3:0] first_be,
+ bit [15:0] req_id,
+ bit [7:0] tag,
+ bit [7:0] busnum) {
+
+ integer index;
+ integer ret;
+ bit [127:0] return_pkt;
+ bit [31:0] return_data;
+ bit [63:0] address = {32'b0,busnum,5'b1,3'b0,8'b0,reg_num,2'b0};
+
+ tlp_packet = new(sequence_id,5'b00100,2'b0,10'h1,*,*,*,*,
+ address,req_id,tag,first_be,4'b0,*,*,*,*,*);
+ tlp_packet.build_packet("nonposted");
+ printf ("header %0h \n",tlp_packet.header);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ //sequence id
+ printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
+ mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
+ printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
+ mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
+ //loop for sending out packet
+ for (index=1;index<3;index++) {
+ printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
+ printf("%0h put into mailbox index+1 = %0d\n",{2'b00,packet_array[index+1][7:0],packet_array[index][31:24]},index+1);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index+1][7:0],packet_array[index][31:24]});
+ }
+ printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
+ printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]});
+ printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[23:8]});
+ printf("%0h put into mailbox\n",{2'b10,END_s,tlp_packet.lcrc[31:24]});
+ mailbox_put(rx_data_mailbox, {2'b10,END_s,tlp_packet.lcrc[31:24]});
+ semaphore_put (my_semaphore, 1);
+
+ ret = mailbox_get (WAIT,tlp_header_mailbox,return_pkt,CHECK);
+ if (ret <= 0)
+ error ("mailbox_get returned %0d\n",ret);
+ if (return_pkt[4:0] == 4'ha) {
+ if (return_pkt[6] == 1'b1) {
+ ret = mailbox_get (WAIT,tlp_data_mailbox,return_data,CHECK);
+ if (ret <= 0)
+ error ("mailbox_get returned %0d\n",ret);
+ printf("returned header %0h and data %0h for tag %0h\n",return_pkt,return_data,tag);
+ }
+ }
+ else if ((return_pkt[4:0] == 4'ha) && (return_pkt[5] == 1'b0)) {
+ printf("comp without data returned header %0h and comp_stat of %0b\n",return_pkt,return_pkt[55:53]);
+ }
+}
+
+
+
+task cfgwr (bit [7:0] reg_num,
+ bit [3:0] first_be,
+ bit [15:0] req_id,
+ bit [7:0] tag,
+ bit [7:0] busnum,
+ bit [31:0] data) {
+
+ integer index;
+ integer ret;
+ bit [127:0] return_pkt;
+ //bus num,device num,function num,ext reg reg_num;
+ bit [63:0] address = {32'b0,busnum,5'b1,3'b0,8'b0,reg_num,2'b0};
+ printf ("cfgwr data = %0h\n",data);
+ tlp_packet = new(sequence_id,5'b00100,2'b10,10'h1,*,*,*,*,
+ address,req_id,tag,first_be,4'b0,*,*,*,*,data);
+ tlp_packet.build_packet("nonposted");
+ printf ("header %0h \n",tlp_packet.header);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ //sequence id
+ printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
+ mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
+ printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
+ mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
+ //loop for sending out packet
+ for (index=1;index<4;index++) {
+ printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
+ printf("%0h put into mailbox index+1 = %0d\n",{2'b00,packet_array[index+1][7:0],packet_array[index][31:24]},index+1);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index+1][7:0],packet_array[index][31:24]});
+ }
+ printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
+ printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]});
+ printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[23:8]});
+ printf("%0h put into mailbox\n",{2'b10,END_s,tlp_packet.lcrc[31:24]});
+ mailbox_put(rx_data_mailbox, {2'b10,END_s,tlp_packet.lcrc[31:24]});
+ semaphore_put (my_semaphore, 1);
+ ret = mailbox_get (WAIT,tlp_header_mailbox,return_pkt,CHECK);
+ if (ret <= 0)
+ error ("mailbox_get returned %0d\n",ret);
+
+ if ((return_pkt[4:0] == 4'ha) && (return_pkt[5] == 1'b0)) {
+ if (return_pkt[55:53] == 3'b000) printf("comp without data returned header %0h tag %0h and comp_stat of successful completion\n",return_pkt,tag);
+ else if (return_pkt[55:53] == 3'b001) printf("comp without data returned header %0h tag %0hand comp_stat of unsupported response\n",return_pkt,tag);
+ else if (return_pkt[55:53] == 3'b010) printf("comp without data returned header %0h tag %0hand comp_stat of completer abort\n",return_pkt,tag);
+ }
+}
+
+
+task memwr (bit [63:0] address,
+ bit [9:0] length,
+ bit [3:0] first_be,
+ bit [3:0] last_be,
+ bit [15:0] req_id,
+ bit [7:0] tag){
+ integer index;
+ bit seq_header;
+ integer total_length;
+ bit[1:0] fmt;
+ integer hdr_dw;
+ fmt = |address[63:32] == 1 ? 2'b11 : 2'b10;
+ hdr_dw = |address[63:32] == 1 ? 4 : 3;
+ total_length = hdr_dw + length; //add td when ready
+ //bus num,device num,function num,ext reg reg_num;
+ tlp_packet = new(sequence_id,5'b00000,fmt,length,*,*,*,*,
+ address,req_id,tag,first_be,last_be,*,*,*,*,*);
+ tlp_packet.build_packet("nonposted");
+ printf ("header %0h \n",tlp_packet.header);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ //sequence id
+ printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
+ mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
+ printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
+ mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
+ //loop for sending out packet
+ for (index=1;index
+
+
+
+task scramble8(bit [7:0] data_in, bit skp_detect, bit com_detect, bit sram_bypass, bit [15:0] lfsr_old, var bit [7:0] scramble_data, var bit [15:0] lfsr) {
+
+
+ if((sram_bypass == 1'b1) | (com_detect == 1'b1)) {
+ scramble_data = data_in;
+ }
+ else {
+ scramble_data[0] = lfsr_old[15] ^ data_in[0];
+ scramble_data[1] = lfsr_old[14] ^ data_in[1];
+ scramble_data[2] = lfsr_old[13] ^ data_in[2];
+ scramble_data[3] = lfsr_old[12] ^ data_in[3];
+ scramble_data[4] = lfsr_old[11] ^ data_in[4];
+ scramble_data[5] = lfsr_old[10] ^ data_in[5];
+ scramble_data[6] = lfsr_old[9] ^ data_in[6];
+ scramble_data[7] = lfsr_old[8] ^ data_in[7];
+ }
+
+
+ if(com_detect == 1'b1) {
+ lfsr = 16'hFFFF;
+ }
+ else if(skp_detect == 1'b0) {
+ lfsr[0] = lfsr_old[8];
+ lfsr[1] = lfsr_old[9];
+ lfsr[2] = lfsr_old[10];
+ lfsr[3] = lfsr_old[8] ^ lfsr_old[11];
+ lfsr[4] = lfsr_old[8] ^ lfsr_old[9] ^ lfsr_old[12];
+ lfsr[5] = lfsr_old[8] ^ lfsr_old[9] ^ lfsr_old[10] ^ lfsr_old[13];
+ lfsr[6] = lfsr_old[9] ^ lfsr_old[10] ^ lfsr_old[11] ^ lfsr_old[14];
+ lfsr[7] = lfsr_old[10] ^ lfsr_old[11] ^ lfsr_old[12] ^ lfsr_old[15];
+ lfsr[8] = lfsr_old[0] ^ lfsr_old[11] ^ lfsr_old[12] ^ lfsr_old[13];
+ lfsr[9] = lfsr_old[1] ^ lfsr_old[12] ^ lfsr_old[13] ^ lfsr_old[14];
+ lfsr[10] = lfsr_old[2] ^ lfsr_old[13] ^ lfsr_old[14] ^ lfsr_old[15];
+ lfsr[11] = lfsr_old[3] ^ lfsr_old[14] ^ lfsr_old[15];
+ lfsr[12] = lfsr_old[4] ^ lfsr_old[15];
+ lfsr[13] = lfsr_old[5];
+ lfsr[14] = lfsr_old[6];
+ lfsr[15] = lfsr_old[7];
+ }
+ else {
+ lfsr = lfsr_old;
+ }
+
+}
Index: pcie_vera_tb/trunk/send_packet.vri
===================================================================
--- pcie_vera_tb/trunk/send_packet.vri (nonexistent)
+++ pcie_vera_tb/trunk/send_packet.vri (revision 8)
@@ -0,0 +1,109 @@
+// ===========================================================================
+// File : send_packet.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: send_packet.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file sends all packets on the rx 16 bit data lines
+//
+// ===========================================================================
+// ===========================================================================
+#include
+//#include "scramble8.vri"
+#define COM_s 8'hbc
+#define SKP_s 8'h1c
+#define IDLE_s 8'h7c
+#define FTS_s 8'h3c
+#define STP_s 8'hfb
+#define SDP_s 8'h5c
+#define EDB 8'hfe
+#define END_s 8'hfd
+
+task send_packet () {
+ bit [7:0] rx_data[];
+ bit rx_datak[];
+
+ bit [17:0] rx_pkt;
+ bit [15:0] rx_data_out;
+ bit [1:0] rx_datak_out;
+ integer ret;
+ integer i;
+
+ bit [15:0] lfsr = 16'hFFFF;
+ bit [7:0] scramble_data[];
+ bit skp_detect = 1'b0;
+ bit com_detect = 1'b0;
+ bit scram_bypass = 1'b0;
+ bit [3:0] bypass_count = 4'b0;
+
+
+ ti_phy_top.rxdatak16 = 2'b0;
+ ti_phy_top.rxdata16 = 16'b0;
+ while (1) {
+ @ (posedge CLOCK);
+ ti_phy_top.rxdatak16 = 2'b0;
+ ti_phy_top.rxdata16 = 16'b0;
+
+ ret = mailbox_get (WAIT,rx_data_mailbox,rx_pkt,CHECK);
+ if (ret <= 0)
+ error ("mailbox_get returned %0d\n",ret);
+
+ rx_datak[1] = rx_pkt[17];
+ rx_datak[0] = rx_pkt[16];
+ rx_data[1] = rx_pkt[15:8];
+ rx_data[0] = rx_pkt[7:0];
+
+
+ for (i=0; i<2; i++) {
+
+ if(com_detect == 1'b1){
+ scram_bypass = 1'b1;
+ }
+ else if(((bypass_count == 4'b0011) & rx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
+ scram_bypass = 1'b0;
+ }
+
+ if((com_detect == 1'b1) | scram_bypass){
+ bypass_count = bypass_count + 1'b1;
+ }
+ else if(((bypass_count == 4'b0011) & rx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
+ bypass_count = 4'b0000;
+ }
+
+
+ if({rx_datak[i],rx_data[i]} == {1'b1,SKP_s}){
+ skp_detect = 1'b1;
+ }
+ else{
+ skp_detect = 1'b0;
+ }
+ if({rx_datak[i],rx_data[i]} == {1'b1,COM_s}){
+ com_detect = 1'b1;
+ }
+ else{
+ com_detect = 1'b0;
+ }
+
+ scramble8(rx_data[i],skp_detect,com_detect,(scram_bypass | rx_datak[i]),lfsr,scramble_data[i],lfsr);
+ //printf("K-Code = %h COM = %h SKP = %h bypass = %h unscramble_data = %h scramble_data = %h lfsr = %h bypass_cnt = %d\n",rx_datak[i],com_detect,skp_detect,scram_bypass,rx_data[i],scramble_data[i],lfsr,bypass_count);
+ }
+
+
+ //printf("RX MAILBOX OUT datak(%0h) data(%0h) to be sent\n",rx_pkt[17:16],rx_pkt[15:0]);
+ ti_phy_top.rxdatak16 = {rx_datak[1],rx_datak[0]};
+ ti_phy_top.rxdata16 = {scramble_data[1],scramble_data[0]};
+ }
+
+}
Index: pcie_vera_tb/trunk/pcie_dllp_packet.vri
===================================================================
--- pcie_vera_tb/trunk/pcie_dllp_packet.vri (nonexistent)
+++ pcie_vera_tb/trunk/pcie_dllp_packet.vri (revision 8)
@@ -0,0 +1,150 @@
+// ===========================================================================
+// File : pcie_dllp_packet.vri
+// Author : cwinward
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: pcie_dllp_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file is a class of pcie packet can be used for all DLLP
+// packet types.
+//
+// ===========================================================================
+// ===========================================================================
+#include
+
+class pcie_dllp_packet {
+ bit [7:0] byte3;
+ bit [7:0] byte2;
+ bit [7:0] byte1;
+ bit [7:0] dllp_type;
+ bit [31:0] temp_packet[];
+
+ task new(
+ bit [7:0] init_byte3 = 8'h40,
+ bit [7:0] init_byte2 = 8'h00,
+ bit [7:0] init_byte1 = 8'h01,
+ bit [7:0] init_dllp_type = 8'b01000000) {
+
+ dllp_type = init_dllp_type;
+ byte1 = init_byte1;
+ byte2 = init_byte2;
+ byte3 = init_byte3;
+ }
+
+ task build_packet (string pkt_type = "initfc1_p") {
+ if(pkt_type == "initfc1_p") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc1_np") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc1_cpl") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc2_p") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc2_np") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc1_cpl") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if (pkt_type == "ack") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+
+ }
+
+ function bit[15:0] crc16d32(bit[31:0] d) {
+
+ bit [15:0] crc;
+ bit [15:0] C = 32'hFFFF;
+
+ crc[0] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[8] ^ d[10] ^ d[11] ^ d[16] ^ d[18] ^
+ d[19] ^ d[23] ^ d[27] ^ d[31] ^ C[4] ^ C[5] ^ C[7] ^ C[10] ^ C[12]
+ ^ C[13] ^ C[15];
+ crc[1] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[5] ^ d[7] ^ d[8] ^ d[9] ^ d[11] ^ d[15]
+ ^ d[16] ^ d[17] ^ d[19] ^ d[22] ^ d[23] ^ d[26] ^ d[27] ^ d[30] ^
+ d[31] ^ C[0] ^ C[4] ^ C[6] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ C[12] ^
+ C[14] ^ C[15];
+ crc[2] = d[0] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[14] ^ d[15]
+ ^ d[16] ^ d[18] ^ d[21] ^ d[22] ^ d[25] ^ d[26] ^ d[29] ^ d[30] ^
+ C[0] ^ C[1] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^
+ C[15];
+ crc[3] = d[0] ^ d[1] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[13] ^
+ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[23]
+ ^ d[24] ^ d[25] ^ d[27] ^ d[28] ^ d[29] ^ d[31] ^ C[0] ^ C[1] ^ C[2]
+ ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[14] ^ C[15];
+ crc[4] = d[0] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[12] ^ d[13] ^
+ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[23]
+ ^ d[24] ^ d[26] ^ d[27] ^ d[28] ^ d[30] ^ C[0] ^ C[1] ^ C[2] ^ C[3]
+ ^ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[15];
+ crc[5] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[11] ^ d[12] ^ d[13] ^
+ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[21] ^ d[22] ^ d[23]
+ ^ d[25] ^ d[26] ^ d[27] ^ d[29] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4]
+ ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[11];
+ crc[6] = d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[11] ^ d[12] ^
+ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[22]
+ ^ d[24] ^ d[25] ^ d[26] ^ d[28] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4]
+ ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ C[12];
+ crc[7] = d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[9] ^ d[10] ^ d[11] ^ d[12]
+ ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[19] ^ d[20] ^ d[21] ^
+ d[23] ^ d[24] ^ d[25] ^ d[27] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
+ C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ C[12] ^ C[13];
+ crc[8] = d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[8] ^ d[9] ^ d[10] ^ d[11]
+ ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^
+ d[22] ^ d[23] ^ d[24] ^ d[26] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
+ C[5] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[12] ^ C[13] ^ C[14];
+ crc[9] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
+ ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[17] ^ d[18] ^ d[19] ^
+ d[21] ^ d[22] ^ d[23] ^ d[25] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
+ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ C[12] ^ C[13] ^ C[14]
+ ^ C[15];
+ crc[10] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
+ ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^
+ d[21] ^ d[22] ^ d[24] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^
+ C[7] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[14] ^ C[15];
+ crc[11] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
+ ^ d[11] ^ d[12] ^ d[13] ^ d[15] ^ d[16] ^ d[17] ^ d[19] ^ d[20] ^
+ d[21] ^ d[23] ^ C[0] ^ C[2] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ C[8]
+ ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[14] ^ C[15];
+ crc[12] = d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[9] ^ d[12] ^ d[14] ^ d[15] ^
+ d[20] ^ d[22] ^ d[23] ^ d[27] ^ d[31] ^ C[0] ^ C[1] ^ C[3] ^ C[6]
+ ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[14];
+ crc[13] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[8] ^ d[11] ^ d[13] ^ d[14] ^
+ d[19] ^ d[21] ^ d[22] ^ d[26] ^ d[30] ^ C[1] ^ C[2] ^ C[4] ^ C[7]
+ ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15];
+ crc[14] = d[1] ^ d[2] ^ d[4] ^ d[5] ^ d[7] ^ d[10] ^ d[12] ^ d[13] ^ d[18] ^
+ d[20] ^ d[21] ^ d[25] ^ d[29] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10]
+ ^ C[11] ^ C[13] ^ C[14];
+ crc[15] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[9] ^ d[11] ^ d[12] ^ d[17] ^
+ d[19] ^ d[20] ^ d[24] ^ d[28] ^ C[3] ^ C[4] ^ C[6] ^ C[9] ^ C[11]
+ ^ C[12] ^ C[14] ^ C[15];
+
+ crc16d32 = {~crc[0],~crc[1],~crc[2],~crc[3],~crc[4],~crc[5],~crc[6],~crc[7],
+ ~crc[8],~crc[9],~crc[10],~crc[11],~crc[12],~crc[13],~crc[14],~crc[15]};
+
+ return;
+ }
+
+
+ }
Index: pcie_vera_tb/trunk/run_vera
===================================================================
--- pcie_vera_tb/trunk/run_vera (nonexistent)
+++ pcie_vera_tb/trunk/run_vera (revision 8)
@@ -0,0 +1,10 @@
+#!/bin/csh -f
+
+\rm -rf simv csrc simv.daidir comp.log sim.log
+
+ vcs -ntb ti_phy_top.test_top.v ti_phy_top.v ti_phy_top.vr \
+ -P /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/debussy.tab \
+ /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/pli.a \
+ -Mupdate -l vcs_compile.log +vcs+lic+wait +define+SYNOPSYS_NTB -l comp.log $*
+
+ ./simv -l sim.log $*
pcie_vera_tb/trunk/run_vera
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: pcie_vera_tb/trunk/pcie_tlp_packet.vri
===================================================================
--- pcie_vera_tb/trunk/pcie_tlp_packet.vri (nonexistent)
+++ pcie_vera_tb/trunk/pcie_tlp_packet.vri (revision 8)
@@ -0,0 +1,465 @@
+// ===========================================================================
+// File : pcie_tlp_packet.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: pcie_tlp_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file is a class of pcie packet can be used for all TLP
+// packet types.
+//
+// ===========================================================================
+// ===========================================================================
+#include
+
+class pcie_tlp_packet {
+ bit [15:0] sequence_num;
+ bit [4:0] type;
+ bit [1:0] fmt;
+ bit [9:0] length;
+ bit [2:0] tc;
+ bit [1:0] attr;
+ bit ep;
+ bit td;
+ bit [63:0] address; //used for multiple purposes.
+ bit [15:0] req_id;
+ bit [7:0] tag;
+ bit [3:0] first_be;
+ bit [3:0] last_be;
+ //completion fields
+ bit [15:0] completer_id;
+ bit [11:0] byte_count;
+ bit bcm;
+ bit [2:0] cmp_status;
+ bit [127:0] header;
+ bit [31:0] lcrc;
+ bit [31:0] data [];
+
+ //methods
+ task new(
+ bit [11:0] ic_sequence_num = 12'b0,
+ bit [4:0] ic_type = 5'h0,
+ bit [1:0] ic_fmt = 2'h0,
+ bit [9:0] ic_length = 10'h0,
+ bit [2:0] ic_tc = 3'h0,
+ bit [1:0] ic_attr = 2'h0,
+ bit ic_ep = 1'h0,
+ bit ic_td = 1'h0,
+ bit [63:0] ic_address = 64'h0,
+ bit [15:0] ic_req_id = 16'h0,
+ bit [7:0] ic_tag = 8'h0,
+ bit [3:0] ic_first_be = 4'hf,
+ bit [3:0] ic_last_be = 4'hf,
+ //completion fields
+ bit [15:0] ic_completer_id = 16'h0,
+ bit [11:0] ic_byte_count = 12'h0,
+ bit ic_bcm = 1'h0,
+ bit [2:0] ic_cmp_status = 3'h0,
+ bit [31:0] ic_config_data = 32'b0) {
+
+ sequence_num = {4'b0,ic_sequence_num};
+ type = ic_type;
+ fmt = ic_fmt;
+ length = ic_length;
+ tc = ic_tc;
+ attr = ic_attr;
+ ep = ic_ep;
+ td = ic_td;
+ address = ic_address;
+ req_id = ic_req_id;
+ tag = ic_tag;
+ first_be = ic_first_be;
+ last_be = ic_last_be;
+ completer_id = ic_completer_id;
+ byte_count = ic_byte_count;
+ bcm = ic_bcm;
+ cmp_status = ic_cmp_status;
+ data[0] = ic_config_data;
+ printf ("new seq(%0h),type(%0h),fmt(%0h),length(%0h),tc(%0h),attr(%0h),ep(%0h),td(%0h),addr(%0h),req_id(%0h),tag(%0h),fbe(%0h),lbe(%0h),cmp_id(%0h),bc(%0h),bcm(%0h),cmp_stat(%0h),cfgwr data(%0h)\n",
+ ic_sequence_num,
+ ic_type,
+ ic_fmt,
+ ic_length,
+ ic_tc,
+ ic_attr,
+ ic_ep,
+ ic_td,
+ ic_address,
+ ic_req_id,
+ ic_tag,
+ ic_first_be,
+ ic_last_be,
+ ic_completer_id,
+ ic_byte_count,
+ ic_bcm,
+ ic_cmp_status,
+ ic_config_data
+ );
+ }
+
+ task build_packet (string pkt_type = "posted") {
+ integer reserved = 0;
+ integer i;
+ bit [5:0] register_num;
+ bit [3:0] ext_register_num;
+ bit [2:0] function_number;
+ bit [4:0] device_number;
+ bit [7:0] bus_number;
+ bit [6:0] lower_addr = address[6:0];
+
+ bus_number = address[31:24];
+ function_number = address[23:19];
+ device_number = address[18:16];
+ ext_register_num = address[11:8];
+ register_num = address[7:2];
+
+ if (pkt_type == "posted" || pkt_type == "nonposted") {
+ //dw1
+ header[4:0] = type;
+ header[6:5] = fmt;
+ header[7] = reserved;
+ header[11:8] = reserved;
+ header[14:12] = tc;
+ header[15] = reserved;
+ header[17:16] = length[9:8];
+ header[19:18] = reserved;
+ header[21:20] = attr;
+ header[22] = ep;
+ header[23] = td;
+ header[31:24] = length[7:0];
+ //dw2
+ header[39:32] = req_id[15:8];
+ header[47:40] = req_id[7:0];
+ header[55:48] = tag;
+ header[59:56] = first_be;
+ header[63:60] = last_be;
+ //dw3&4
+ //configurations
+ if (type == 5'b00100 || type == 5'b00101) {
+ header[127:64] = {32'b0,
+ register_num[5:0],2'b0,
+ 4'b0,ext_register_num[3:0],
+ device_number[4:0],function_number[2:0],
+ bus_number[7:0]};
+ }
+ else if (fmt[0] == 1'b1) {
+ header[127:64] = {address[7:2],2'b0,address[15:8],
+ address[23:16],address[31:24],
+ address[39:32],address[47:40],
+ address[55:48],address[63:56]};
+ }
+ else {
+ header[127:64] = {32'b0,address[7:2],2'b0,address[15:8],
+ address[23:16],address[31:24]};
+ }
+ }
+ else if (pkt_type == "completion") {
+ //dw1
+ header[4:0] = type;
+ header[6:5] = fmt;
+ header[7] = reserved;
+ header[11:8] = reserved;
+ header[14:12] = tc;
+ header[15] = reserved;
+ header[17:16] = length[9:8];
+ header[19:18] = reserved;
+ header[21:20] = attr;
+ header[22] = ep;
+ header[23] = td;
+ header[31:24] = length[7:0];
+ //dw 2
+ header[39:32] = completer_id[15:8];
+ header[47:40] = completer_id[7:0];
+ header[51:48] = byte_count[11:8];
+ header[52] = bcm;
+ header[55:53] = cmp_status;
+ header[63:56] = byte_count[7:0];
+ //dw3
+ header[71:64] = req_id[15:8];
+ header[79:72] = req_id[7:0];
+ header[87:80] = tag;
+ header[95:88] = {1'b0,lower_addr};
+ //dw4
+ header[127:96] = 32'b0;
+ }
+ if (type[4:1] != 5'b0010 && fmt[1]) {
+ for (i=0;i
+
+class pcie_phy_packet {
+ bit [7:0] com;
+ bit [7:0] link;
+ bit [7:0] lane;
+ bit [7:0] n_fts;
+ bit [7:0] rateid;
+ bit [7:0] train_cntrl;
+ bit [7:0] ts_id;
+ bit [7:0] idle;
+ bit [7:0] skp;
+ bit [7:0] fts;
+ integer length;
+ bit [17:0] temp_packet[];
+
+
+ //methods
+ task new(
+ bit [7:0] ic_link = 8'hf7,
+ bit [7:0] ic_lane = 8'hf7,
+ bit [7:0] ic_nfts = 8'hff,
+ bit [7:0] ic_rateid = 8'h2,
+ bit [7:0] ic_train_cntrl = 8'h0,
+ bit [7:0] ic_ts_id = 8'h4a) {
+
+ link = ic_link;
+ lane = ic_lane;
+ n_fts = ic_nfts;
+ rateid = ic_rateid;
+ train_cntrl = ic_train_cntrl;
+ ts_id = ic_ts_id;
+ com = 8'hbc;
+ idle = 8'h7c;
+ skp = 8'h1c;
+ fts = 8'h3c;
+ }
+
+ task build_packet (string pkt_type = "ts") {
+ if (pkt_type == "ts") {
+ length = 8;
+ if (link == 8'hf7) temp_packet[0] = {2'b11,link,com};
+ else temp_packet[0] = {2'b01,link,com};
+ if (lane == 8'hf7) temp_packet[1] = {2'b1,n_fts,lane};
+ else temp_packet[1] = {2'b0,n_fts,lane};
+ temp_packet[2] = {2'b0,train_cntrl,rateid};
+ temp_packet[3] = {2'b0,ts_id,ts_id};
+ temp_packet[4] = {2'b0,ts_id,ts_id};
+ temp_packet[5] = {2'b0,ts_id,ts_id};
+ temp_packet[6] = {2'b0,ts_id,ts_id};
+ temp_packet[7] = {2'b0,ts_id,ts_id};
+ printf ("building training set packet (%0h)\n",
+ {temp_packet[7][15:0],temp_packet[6][15:0],
+ temp_packet[5][15:0],temp_packet[4][15:0],
+ temp_packet[3][15:0],temp_packet[2][15:0],
+ temp_packet[1][15:0],temp_packet[0][15:0]});
+ }
+ else if (pkt_type == "eidle") {
+ length = 2;
+ temp_packet[0] = {2'b11,idle,com};
+ temp_packet[1] = {2'b11,idle,idle};
+ printf ("building eidle packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
+ }
+ else if (pkt_type == "skip"){
+ length = 2;
+ temp_packet[0] = {2'b11,skp,com};
+ temp_packet[1] = {2'b11,skp,skp};
+ printf ("building skip packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
+ }
+ else if (pkt_type == "fast_ts"){
+ length = 2;
+ temp_packet[0] = {2'b11,fts,com};
+ temp_packet[1] = {2'b11,fts,fts};
+ printf ("building fts packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
+ }
+
+ }
+}
Index: pcie_vera_tb/trunk/link_training.vri
===================================================================
--- pcie_vera_tb/trunk/link_training.vri (nonexistent)
+++ pcie_vera_tb/trunk/link_training.vri (revision 8)
@@ -0,0 +1,209 @@
+// ===========================================================================
+// File : link_training.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: link_training.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function :This file performs the link training and link and lane negotiation
+//
+// ===========================================================================
+// ===========================================================================
+#include
+#define COM_s 8'hbc
+#define SKP_s 8'h1c
+#define IDLE_s 8'h7c
+#define FTS_s 8'h3c
+#define STP_s 8'hfb
+#define SDP_s 8'h5c
+#define EDB 8'hfe
+#define END_s 8'hfd
+
+task link_training () {
+
+ fork
+ send_ts();
+ receive_ts();
+ join none
+}
+
+
+task send_ts( ) {
+ integer index;
+ string pkt_type;
+ pkt_type = "ts";
+ //ti_phy_top.t1_count == 9'hff;
+ ti_phy_top.rxvalid16 = 1'b1;
+ wait_var(phy_rdy);
+
+ printf ("send_ts1 = %d \n",send_ts1);
+ while (LINK_UP == 0) {
+ if (send_ts1 == 1) {
+ ts2_cycle_cnt = 1;
+ //printf ("number of ts dut sent %d \n",ti_phy_top.t1_count);
+ printf ("ts #%0d ts 1's ",ts1_cycle_cnt++);
+ pkt_type = "ts";
+ training_set = new(link,lane,*,*,*,*);
+ training_set.build_packet(pkt_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for (index = 0; index < training_set.length; index ++) {
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = training_set.temp_packet[index][17:16];
+ //ti_phy_top.rxdata16 = training_set.temp_packet[index][15:0];
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {training_set.temp_packet[index][17:16],training_set.temp_packet[index][15:0]});
+ }
+ semaphore_put (my_semaphore, 1);
+ }
+ else if (send_ts2 == 1){
+ ts1_cycle_cnt = 1;
+ printf ("ts #%0d ts 2's ",ts2_cycle_cnt++);
+ pkt_type = "ts";
+ training_set = new(lane,link,*,*,*,'h45);
+ training_set.build_packet(pkt_type);
+ for (index = 0; index < training_set.length; index ++) {
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = training_set.temp_packet[index][17:16];
+ //ti_phy_top.rxdata16 = training_set.temp_packet[index][15:0];
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {training_set.temp_packet[index][17:16],training_set.temp_packet[index][15:0]});
+ }
+ }
+ }
+
+ printf ("LINK UP(%0d) !!!!!!!!!!!\n",LINK_UP);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+}
+
+task receive_ts () {
+ integer ret;
+ integer ts1_count=0;
+ integer ts2_count=0;
+ integer ts1_link_count = 0;
+ integer ts1_lane_count = 0;
+ integer ts2_lane_link_count = 0;
+ integer send_ts1_with_link, send_ts1_with_link_lane, send_ts2_with_link_lane;
+ bit [127:0] receive_phy_packet;
+
+ send_ts1 = 1;
+ send_ts2 = 0;
+ send_ts1_with_link = 0;
+ send_ts1_with_link_lane = 0;
+ send_ts2_with_link_lane = 0;
+ while (1) {
+ ret = mailbox_get (WAIT,phy_mailbox,receive_phy_packet,CHECK);
+ //printf ("Recieved PHY PACKET (%0h) added to phy mailbox\n",receive_phy_packet);
+ if (receive_phy_packet == 127'h454545454545454545450002f0f7f7bc) {
+ printf ("Recieved TS 2 PHY PACKET\n");
+ ts2_count++;
+ }
+ if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f0f7f7bc){
+ printf ("Recieved TS 1 PHY PACKET\n");
+ ts1_count++;
+ }
+ if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f0f701bc) {
+ printf ("Recieved TS 1 link accept PHY PACKET\n");
+ ts1_link_count++;
+ }
+ if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f00101bc) {
+ printf ("Recieved TS 1 lane and link accept PHY PACKET\n");
+ ts1_lane_count++;
+ }
+ if (receive_phy_packet == 127'h454545454545454545450002f00101bc) {
+ printf ("Recieved TS 1 lane and link accept PHY PACKET\n");
+ ts2_lane_link_count++;
+ }
+
+ //printf ("send_ts2_with_link_lane(%0d)send_ts1_with_link_lane(%0d)send_ts1_with_link(%0d)send_ts2(%0d)send_ts1(%0d)\n",
+ // send_ts2_with_link_lane,send_ts1_with_link_lane,send_ts1_with_link,send_ts2,send_ts1 );
+ //printf ("ts2_lane_link_count(%0d)ts1_lane_count(%0d)ts1_link_count(%0d)ts1_count(%0d)ts2_count(%0d)\n",
+ // ts2_lane_link_count,ts1_lane_count,ts1_link_count,ts1_count,ts2_count);
+
+ if (send_ts2_with_link_lane && ts2_cycle_cnt > 16 && ts2_lane_link_count > 15) {
+ //clear all signals if we get a ts1 with pad
+ if (ts1_count > 0) {
+ send_ts1 = 1;
+ send_ts2 = 0;
+ send_ts2_with_link_lane = 0;
+ send_ts1_with_link_lane = 0;
+ send_ts1_with_link = 0;
+ LINK_UP = 0;
+ ts2_lane_link_count = 0;
+ ts1_lane_count = 0;
+ ts1_link_count = 0;
+ ts1_count = 0;
+ ts2_count = 0;
+ }
+ else {
+ send_ts1 = 0;
+ send_ts2 = 0;
+ LINK_UP = 1;
+ ts1_lane_count = 0;
+ ts1_link_count = 0;
+ ts1_count = 0;
+ ts2_count = 0;
+
+ }
+
+ }
+ else if (send_ts1_with_link_lane){
+ if (ts1_cycle_cnt > 16 && ts1_lane_count >16 ) {
+ send_ts1 = 0;
+ send_ts2 = 1;
+ link = 8'b1;
+ lane = 8'b1;
+ send_ts2_with_link_lane = 1;
+ ts1_lane_count = 0;
+ ts1_link_count = 0;
+ ts1_count = 0;
+ ts2_count = 0;
+ }
+ }
+ else if (send_ts1_with_link) {
+ if (ts1_cycle_cnt > 16 && ts1_link_count > 16) {
+ send_ts1 = 1;
+ send_ts2 = 0;
+ link = 8'b1;
+ lane = 8'b1;
+ send_ts1_with_link_lane = 1;
+ }
+ }
+ //send at least 16 ts 2
+ else if (send_ts2) {
+ if (ts2_count > 16 && ts2_cycle_cnt > 16) {
+ send_ts1 = 1;
+ send_ts2 = 0;
+ send_ts1_with_link = 1;
+ link = 8'b1;
+ lane = 8'hf7;
+ }
+ }
+ //send at least 100 ts 1's
+ else if (ts2_count > 16 && ts1_cycle_cnt > 100) {
+ send_ts1 = 0;
+ send_ts2 = 1;
+ link = 'hf7;
+ lane = 'hf7;
+ }
+ else {
+ send_ts1 = 1;
+ send_ts2 = 0;
+ link = 'hf7;
+ lane = 'hf7;
+ }
+ }
+}
+
Index: pcie_vera_tb/trunk/docs/PCI_Express_VERA_testbench.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: pcie_vera_tb/trunk/docs/PCI_Express_VERA_testbench.pdf
===================================================================
--- pcie_vera_tb/trunk/docs/PCI_Express_VERA_testbench.pdf (nonexistent)
+++ pcie_vera_tb/trunk/docs/PCI_Express_VERA_testbench.pdf (revision 8)
pcie_vera_tb/trunk/docs/PCI_Express_VERA_testbench.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pcie_vera_tb/trunk/InitFC1.vri
===================================================================
--- pcie_vera_tb/trunk/InitFC1.vri (nonexistent)
+++ pcie_vera_tb/trunk/InitFC1.vri (revision 8)
@@ -0,0 +1,363 @@
+// ===========================================================================
+// File : InitFC1.vri
+// Author : cwinward
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: InitFC1.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file performs the initial flow control sequence.
+//
+// ===========================================================================
+// ===========================================================================
+
+#include
+
+task InitFC1(var bit [7:0] ph_cl, var bit [11:0] pd_cl, var bit [7:0] cplh_cl,var bit [11:0] cpld_cl,var bit [7:0] nph_cl,var bit [11:0] npd_cl,var bit INITFC_DONE){
+ integer index;
+ string dllp_type;
+ bit fc1_p_rcvd = 1'b0;
+ bit fc1_np_rcvd = 1'b0;
+ bit fc1_cpl_rcvd = 1'b0;
+ bit fc2_p_rcvd = 1'b0;
+ bit fc2_np_rcvd = 1'b0;
+ bit fc2_cpl_rcvd = 1'b0;
+
+ bit fc1_completed = 1'b0;
+ bit fc2_completed = 1'b0;
+
+ //****************************************************************************************
+ //new task to read out the dllp's
+ //
+
+ while(fc1_completed == 1'b0){
+ fc1_completed = fc1_p_rcvd & fc1_np_rcvd & fc1_cpl_rcvd;
+ printf("FC1_completed <= %d.\n",fc1_completed);
+ receive_fc1_dllp(fc1_p_rcvd,fc1_np_rcvd,fc1_cpl_rcvd,ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl);
+ dllp_type = "initfc1_p";
+ printf("Sending out an InitFC1_P packet.\n");
+ flowcntrl_1 = new(*,*,*,*);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+
+ dllp_type = "initfc1_np";
+ printf("Sending out an InitFC1_NP packet.\n");
+ flowcntrl_1 = new(8'h00,8'h00,8'h01,8'b01010000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+
+ dllp_type = "initfc1_cpl";
+ printf("Sending out an InitFC1_NP packet.\n");
+ flowcntrl_1 = new(8'h40,8'h00,8'h01,8'b01100000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+ }
+
+ while(fc2_completed == 1'b0){
+ fc2_completed = fc2_p_rcvd | fc2_np_rcvd | fc2_cpl_rcvd;
+ printf("FC2_completed <= %d.\n",fc2_completed);
+ receive_fc2_dllp(fc2_p_rcvd,fc2_np_rcvd,fc2_cpl_rcvd);
+ dllp_type = "initfc1_p";
+ printf("Sending out an InitFC2_P packet.\n");
+ flowcntrl_1 = new(*,*,*,8'b11000000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+
+ dllp_type = "initfc1_np";
+ printf("Sending out an InitFC2_NP packet.\n");
+ flowcntrl_1 = new(8'h00,8'h00,8'h01,8'b11010000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+
+ dllp_type = "initfc1_cpl";
+ printf("Sending out an InitFC2_NP packet.\n");
+ flowcntrl_1 = new(8'h40,8'h00,8'h01,8'b11100000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ INITFC_DONE = fc1_completed & fc2_completed;
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+ }
+
+}
+
+task receive_fc1_dllp (var bit fc1_p_rcvd, var bit fc1_np_rcvd, var bit fc1_cpl_rcvd,var bit [7:0] ph_cl, var bit [11:0] pd_cl, var bit [7:0] cplh_cl,var bit [11:0] cpld_cl,var bit [7:0] nph_cl,var bit [11:0] npd_cl) {
+ integer ret;
+ bit [47:0] receive_dll_packet;
+
+ while (~(fc1_p_rcvd & fc1_np_rcvd & fc1_cpl_rcvd)) {
+ ret = mailbox_get (WAIT,dllp_mailbox,receive_dll_packet,CHECK);
+ if(receive_dll_packet[7:0] == 8'h40){
+ fc1_p_rcvd = 1'b1;
+ ph_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
+ pd_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
+ }
+ else if(receive_dll_packet[7:0] == 8'h50){
+ fc1_np_rcvd = 1'b1;
+ nph_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
+ npd_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
+ }
+ else if(receive_dll_packet[7:0] == 8'h60){
+ fc1_cpl_rcvd = 1'b1;
+ cplh_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
+ cpld_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
+ }
+ printf ("InitFC1 DLL PACKET (%0h) taken out of dll mailbox\n",receive_dll_packet);
+ }
+}
+
+task receive_fc2_dllp (var bit fc2_p_rcvd, var bit fc2_np_rcvd, var bit fc2_cpl_rcvd) {
+ integer ret;
+ bit [47:0] receive_dll_packet;
+
+ while (~(fc2_p_rcvd | fc2_np_rcvd | fc2_cpl_rcvd)) {
+ ret = mailbox_get (WAIT,dllp_mailbox,receive_dll_packet,CHECK);
+ if(receive_dll_packet[7:0] == 8'hC0){
+ fc2_p_rcvd = 1'b1;
+ }
+ else if(receive_dll_packet[7:0] == 8'hD0){
+ fc2_np_rcvd = 1'b1;
+ }
+ else if(receive_dll_packet[7:0] == 8'hE0){
+ fc2_cpl_rcvd = 1'b1;
+ }
+ printf ("InitFC2 DLL PACKET (%0h) taken out of dll mailbox\n",receive_dll_packet);
+ }
+}
+
Index: pcie_vera_tb/trunk/ti_phy_top.vr
===================================================================
--- pcie_vera_tb/trunk/ti_phy_top.vr (nonexistent)
+++ pcie_vera_tb/trunk/ti_phy_top.vr (revision 8)
@@ -0,0 +1,209 @@
+// ===========================================================================
+// File : ti_phy_top.vr
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+// Please contact www.gutzlogic.com for details.
+// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
+// ===========================================================================
+//
+// $Id: ti_phy_top.vr,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This is the top level VERA file. It call all tasks and brings
+// up the PHY.
+// ===========================================================================
+// ===========================================================================
+
+#define OUTPUT_EDGE PHOLD
+#define OUTPUT_SKEW #1
+#define INPUT_SKEW #-1
+#define INPUT_EDGE PSAMPLE
+#include
+
+// define interfaces, and verilog_node here if necessary
+
+#include "ti_phy_top.if.vrh"
+#include "receive_packet.vri"
+#include "send_packet.vri"
+#include "pcie_phy_packet.vri"
+#include "link_training.vri"
+#include "skip_order_set.vri"
+#include "pcie_dllp_packet.vri"
+#include "InitFC1.vri"
+#include "pcie_tlp_packet.vri"
+#include "tlp_gen.vri"
+
+//kcode symbols
+#define COM_s 8'hbc
+#define SKP_s 8'h1c
+#define IDLE_s 8'h7c
+#define FTS_s 8'h3c
+#define STP_s 8'hfb
+#define SDP_s 8'h5c
+#define EDB 8'hfe
+#define END_s 8'hfd
+program ti_phy_top_test {
+
+ pcie_phy_packet training_set;
+ pcie_phy_packet skip_set;
+ //********************************
+ //link training gobal variables
+ integer send_ts1 = 1;
+ integer send_ts2 = 0;
+ bit [11:0] sequence_id;
+ bit [31:0] packet_array [1040];
+ bit [7:0] link = 8'hf7;
+ bit [7:0] lane = 8'hf7;
+ integer ts1_cycle_cnt = 1;
+ integer ts2_cycle_cnt = 1;
+ integer LINK_UP = 0;
+ bit [7:0] ph_cl = 8'b0;
+ bit [11:0] pd_cl = 12'b0;
+ bit [7:0] cplh_cl = 8'b0;
+ bit [11:0] cpld_cl = 12'b0;
+ bit [7:0] nph_cl = 8'b0;
+ bit [11:0] npd_cl = 12'b0;
+ bit INITFC_DONE = 1'b0;
+ //********************************
+ pcie_dllp_packet flowcntrl_1;
+ pcie_dllp_packet ack_seq_num;
+ pcie_tlp_packet tlp_packet;
+ integer phy_rdy = 0;
+ integer my_semaphore;
+ bit [8:0] tx_data_mailbox;
+ bit [15:0] tlp_header_mailbox;
+ bit [31:0] tlp_data_mailbox;
+ bit [47:0] dllp_mailbox;
+ bit [127:0] phy_mailbox;
+ bit [17:0] rx_data_mailbox;
+
+ //create mailboxes for transmit and receive packets
+ tx_data_mailbox = alloc(MAILBOX,0,1);
+ rx_data_mailbox = alloc(MAILBOX,0,1);
+
+ tlp_header_mailbox = alloc(MAILBOX,0,1);
+ tlp_data_mailbox = alloc(MAILBOX,0,1);
+ dllp_mailbox = alloc(MAILBOX,0,1);
+ phy_mailbox = alloc(MAILBOX,0,1);
+
+ //create a packet arbiter for packet going out on the rx line.
+ my_semaphore = alloc(SEMAPHORE, 0, 1, 1);
+ if (!my_semaphore) error ("Semaphore could not be allocated\n");
+
+ fork
+ clk_50mhz_gen();
+ phy_status();
+ skip_order_set();
+ receive_packet();
+ send_packet();
+ wait_var(phy_rdy);
+ link_training();
+ join none
+
+ init_ports ();
+ reset_sequence();
+ wait_var(LINK_UP);
+ fork
+ zero_fill();
+ join none
+ InitFC1(ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl,INITFC_DONE);
+
+ printf("Posted Header credit %h\n",ph_cl);
+ printf("Posted Data credit %h\n",pd_cl);
+
+ printf("NonPosted Header credit %h\n",nph_cl);
+ printf("NonPosted Data credit %h\n",npd_cl);
+
+ printf("Completion Header credit %h\n",cplh_cl);
+ printf("Completion Data credit %h\n",cpld_cl);
+
+ printf("INITFC_DONE=%d\n.",INITFC_DONE);
+ tlp_gen();
+ repeat (10000) @(posedge CLOCK);
+} // end of program ti_phy_top_test
+
+// define tasks/classes/functions here if necessary
+
+task clk_50mhz_gen () {
+ ti_phy_top.clk_50mhz = 0;
+ @(posedge ti_phy_top.rxclk);
+ while(1) {
+ @10 ti_phy_top.clk_50mhz = 1;
+ @10 ti_phy_top.clk_50mhz = 0;
+ }
+}
+
+task init_ports () {
+ printf("Task init_ports\n");
+ @(posedge ti_phy_top.rxclk);
+ ti_phy_top.FPGA_RESET_n = 1'b0;
+ ti_phy_top.rxdata16 = 16'b0;
+ ti_phy_top.rxdatak16 = 2'b0;
+ ti_phy_top.rxvalid16 = 1'b0;
+ ti_phy_top.rxidle16 = 1'b0;
+ ti_phy_top.rxstatus = 1'b1;
+ ti_phy_top.phystatus = 1'b1;
+}
+
+task reset_sequence() {
+ printf("Task phy bring up\n");
+
+ @5 ti_phy_top.FPGA_RESET_n = 1'b0;
+ @1 ti_phy_top.FPGA_RESET_n = 1'b1;
+}
+
+
+task phy_status () {
+ bit [1:0] prev_pwrdwn = 0;
+ integer loop_back_high;
+ integer phy_status_arb;
+ phy_status_arb = alloc(SEMAPHORE,0,1,1);
+ if (!phy_status_arb) error ("Semaphore could not be allocated\n");
+ printf("Look for power changes\n");
+ @50 ti_phy_top.rxidle16 = 1'b0;
+ @100 ti_phy_top.phystatus = 1'b0;
+ while (1){
+ prev_pwrdwn = ti_phy_top.pwrdwn;
+ @(posedge CLOCK);
+ //receiver detect
+ if (ti_phy_top.rxdet_loopb == 1'b1 && ti_phy_top.pwrdwn == 2'b10) {
+ loop_back_high = 1;
+ if (!semaphore_get(WAIT,phy_status_arb,1))
+ error ("Semaphore_get returned 0\n");
+ //printf("GOT PHY ARB1 /n");
+ @10 ti_phy_top.rxstatus = 3'b11;
+ @10 ti_phy_top.phystatus = 1'b1;
+ while(loop_back_high) {
+ @(posedge CLOCK);
+ if (ti_phy_top.rxdet_loopb == 1'b0) {
+ loop_back_high = 1'b0;
+ }
+ }
+ @4 ti_phy_top.phystatus = 1'b0;
+ ti_phy_top.rxstatus = 3'b0;
+ semaphore_put (phy_status_arb, 1);
+ }
+ if (ti_phy_top.pwrdwn != prev_pwrdwn){
+ if (!semaphore_get(WAIT,phy_status_arb,1))
+ error ("Semaphore_get returned 0\n");
+ //printf("GOT PHY ARB2 /n");
+ @1 ti_phy_top.rxstatus = 3'b100;
+ ti_phy_top.phystatus = 1'b1;
+ @1 ti_phy_top.phystatus = 1'b0;
+ if (ti_phy_top.pwrdwn == 2'b00) phy_rdy = 1;
+ semaphore_put (phy_status_arb, 1);
+
+ }
+ }
+}
+
+
+
Index: pcie_vera_tb/trunk/skip_order_set.vri
===================================================================
--- pcie_vera_tb/trunk/skip_order_set.vri (nonexistent)
+++ pcie_vera_tb/trunk/skip_order_set.vri (revision 8)
@@ -0,0 +1,64 @@
+// ===========================================================================
+// File : skip_order_set.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: skip_order_set.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : this file generates skip order sets when the timer expires
+//
+// ===========================================================================
+// ===========================================================================
+#include
+
+//task to send in skip order sets on a regular basis.
+task skip_order_set() {
+ integer time_limit_expire = 0;
+ integer index = 0;
+ wait_var(phy_rdy);
+ while(1) {
+ time_limit_expire++;
+ @ (posedge CLOCK);
+ ti_phy_top.rxdatak16 = 2'b00;
+ ti_phy_top.rxdata16 = 1'b0;
+ //1180 symbols clk is 2 symbols
+ if (time_limit_expire == 1180/2) {
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ skip_set = new(*,*,*,*,*,*);
+ skip_set.build_packet("skip");
+ for (index = 0; index < skip_set.length; index ++) {
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = skip_set.temp_packet[index][17:16];
+ //ti_phy_top.rxdata16 = skip_set.temp_packet[index][15:0];
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {skip_set.temp_packet[index][17:16],skip_set.temp_packet[index][15:0]});
+ time_limit_expire = 0;
+ }
+ semaphore_put (my_semaphore, 1);
+ }
+ }
+}
+
+
+task zero_fill(){
+
+ while(1) {
+ @ (posedge CLOCK);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ mailbox_put (rx_data_mailbox,18'b0);
+ semaphore_put(my_semaphore, 1);
+ }
+}
Index: pcie_vera_tb/trunk
===================================================================
--- pcie_vera_tb/trunk (nonexistent)
+++ pcie_vera_tb/trunk (revision 8)
pcie_vera_tb/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: pcie_vera_tb/web_uploads
===================================================================
--- pcie_vera_tb/web_uploads (nonexistent)
+++ pcie_vera_tb/web_uploads (revision 8)
pcie_vera_tb/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: pcie_vera_tb/branches
===================================================================
--- pcie_vera_tb/branches (nonexistent)
+++ pcie_vera_tb/branches (revision 8)
pcie_vera_tb/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: pcie_vera_tb/tags/gutzlogic_v_0/scramble8.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/scramble8.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/scramble8.vri (revision 8)
@@ -0,0 +1,70 @@
+// ===========================================================================
+// File : scramble8.vri
+// Author : cwinward
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: scramble8.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file scrambles the rx lines and descrambles the tx lines.
+//
+// ===========================================================================
+// ===========================================================================
+#include
+
+
+
+task scramble8(bit [7:0] data_in, bit skp_detect, bit com_detect, bit sram_bypass, bit [15:0] lfsr_old, var bit [7:0] scramble_data, var bit [15:0] lfsr) {
+
+
+ if((sram_bypass == 1'b1) | (com_detect == 1'b1)) {
+ scramble_data = data_in;
+ }
+ else {
+ scramble_data[0] = lfsr_old[15] ^ data_in[0];
+ scramble_data[1] = lfsr_old[14] ^ data_in[1];
+ scramble_data[2] = lfsr_old[13] ^ data_in[2];
+ scramble_data[3] = lfsr_old[12] ^ data_in[3];
+ scramble_data[4] = lfsr_old[11] ^ data_in[4];
+ scramble_data[5] = lfsr_old[10] ^ data_in[5];
+ scramble_data[6] = lfsr_old[9] ^ data_in[6];
+ scramble_data[7] = lfsr_old[8] ^ data_in[7];
+ }
+
+
+ if(com_detect == 1'b1) {
+ lfsr = 16'hFFFF;
+ }
+ else if(skp_detect == 1'b0) {
+ lfsr[0] = lfsr_old[8];
+ lfsr[1] = lfsr_old[9];
+ lfsr[2] = lfsr_old[10];
+ lfsr[3] = lfsr_old[8] ^ lfsr_old[11];
+ lfsr[4] = lfsr_old[8] ^ lfsr_old[9] ^ lfsr_old[12];
+ lfsr[5] = lfsr_old[8] ^ lfsr_old[9] ^ lfsr_old[10] ^ lfsr_old[13];
+ lfsr[6] = lfsr_old[9] ^ lfsr_old[10] ^ lfsr_old[11] ^ lfsr_old[14];
+ lfsr[7] = lfsr_old[10] ^ lfsr_old[11] ^ lfsr_old[12] ^ lfsr_old[15];
+ lfsr[8] = lfsr_old[0] ^ lfsr_old[11] ^ lfsr_old[12] ^ lfsr_old[13];
+ lfsr[9] = lfsr_old[1] ^ lfsr_old[12] ^ lfsr_old[13] ^ lfsr_old[14];
+ lfsr[10] = lfsr_old[2] ^ lfsr_old[13] ^ lfsr_old[14] ^ lfsr_old[15];
+ lfsr[11] = lfsr_old[3] ^ lfsr_old[14] ^ lfsr_old[15];
+ lfsr[12] = lfsr_old[4] ^ lfsr_old[15];
+ lfsr[13] = lfsr_old[5];
+ lfsr[14] = lfsr_old[6];
+ lfsr[15] = lfsr_old[7];
+ }
+ else {
+ lfsr = lfsr_old;
+ }
+
+}
Index: pcie_vera_tb/tags/gutzlogic_v_0/send_packet.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/send_packet.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/send_packet.vri (revision 8)
@@ -0,0 +1,109 @@
+// ===========================================================================
+// File : send_packet.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: send_packet.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file sends all packets on the rx 16 bit data lines
+//
+// ===========================================================================
+// ===========================================================================
+#include
+//#include "scramble8.vri"
+#define COM_s 8'hbc
+#define SKP_s 8'h1c
+#define IDLE_s 8'h7c
+#define FTS_s 8'h3c
+#define STP_s 8'hfb
+#define SDP_s 8'h5c
+#define EDB 8'hfe
+#define END_s 8'hfd
+
+task send_packet () {
+ bit [7:0] rx_data[];
+ bit rx_datak[];
+
+ bit [17:0] rx_pkt;
+ bit [15:0] rx_data_out;
+ bit [1:0] rx_datak_out;
+ integer ret;
+ integer i;
+
+ bit [15:0] lfsr = 16'hFFFF;
+ bit [7:0] scramble_data[];
+ bit skp_detect = 1'b0;
+ bit com_detect = 1'b0;
+ bit scram_bypass = 1'b0;
+ bit [3:0] bypass_count = 4'b0;
+
+
+ ti_phy_top.rxdatak16 = 2'b0;
+ ti_phy_top.rxdata16 = 16'b0;
+ while (1) {
+ @ (posedge CLOCK);
+ ti_phy_top.rxdatak16 = 2'b0;
+ ti_phy_top.rxdata16 = 16'b0;
+
+ ret = mailbox_get (WAIT,rx_data_mailbox,rx_pkt,CHECK);
+ if (ret <= 0)
+ error ("mailbox_get returned %0d\n",ret);
+
+ rx_datak[1] = rx_pkt[17];
+ rx_datak[0] = rx_pkt[16];
+ rx_data[1] = rx_pkt[15:8];
+ rx_data[0] = rx_pkt[7:0];
+
+
+ for (i=0; i<2; i++) {
+
+ if(com_detect == 1'b1){
+ scram_bypass = 1'b1;
+ }
+ else if(((bypass_count == 4'b0011) & rx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
+ scram_bypass = 1'b0;
+ }
+
+ if((com_detect == 1'b1) | scram_bypass){
+ bypass_count = bypass_count + 1'b1;
+ }
+ else if(((bypass_count == 4'b0011) & rx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
+ bypass_count = 4'b0000;
+ }
+
+
+ if({rx_datak[i],rx_data[i]} == {1'b1,SKP_s}){
+ skp_detect = 1'b1;
+ }
+ else{
+ skp_detect = 1'b0;
+ }
+ if({rx_datak[i],rx_data[i]} == {1'b1,COM_s}){
+ com_detect = 1'b1;
+ }
+ else{
+ com_detect = 1'b0;
+ }
+
+ scramble8(rx_data[i],skp_detect,com_detect,(scram_bypass | rx_datak[i]),lfsr,scramble_data[i],lfsr);
+ //printf("K-Code = %h COM = %h SKP = %h bypass = %h unscramble_data = %h scramble_data = %h lfsr = %h bypass_cnt = %d\n",rx_datak[i],com_detect,skp_detect,scram_bypass,rx_data[i],scramble_data[i],lfsr,bypass_count);
+ }
+
+
+ //printf("RX MAILBOX OUT datak(%0h) data(%0h) to be sent\n",rx_pkt[17:16],rx_pkt[15:0]);
+ ti_phy_top.rxdatak16 = {rx_datak[1],rx_datak[0]};
+ ti_phy_top.rxdata16 = {scramble_data[1],scramble_data[0]};
+ }
+
+}
Index: pcie_vera_tb/tags/gutzlogic_v_0/pcie_dllp_packet.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/pcie_dllp_packet.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/pcie_dllp_packet.vri (revision 8)
@@ -0,0 +1,150 @@
+// ===========================================================================
+// File : pcie_dllp_packet.vri
+// Author : cwinward
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: pcie_dllp_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file is a class of pcie packet can be used for all DLLP
+// packet types.
+//
+// ===========================================================================
+// ===========================================================================
+#include
+
+class pcie_dllp_packet {
+ bit [7:0] byte3;
+ bit [7:0] byte2;
+ bit [7:0] byte1;
+ bit [7:0] dllp_type;
+ bit [31:0] temp_packet[];
+
+ task new(
+ bit [7:0] init_byte3 = 8'h40,
+ bit [7:0] init_byte2 = 8'h00,
+ bit [7:0] init_byte1 = 8'h01,
+ bit [7:0] init_dllp_type = 8'b01000000) {
+
+ dllp_type = init_dllp_type;
+ byte1 = init_byte1;
+ byte2 = init_byte2;
+ byte3 = init_byte3;
+ }
+
+ task build_packet (string pkt_type = "initfc1_p") {
+ if(pkt_type == "initfc1_p") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc1_np") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc1_cpl") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc2_p") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc2_np") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if(pkt_type == "initfc1_cpl") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+ else if (pkt_type == "ack") {
+ temp_packet[0] = {byte3,byte2,byte1,dllp_type};
+ temp_packet[1] = {16'b0,crc16d32(temp_packet[0])};
+ }
+
+ }
+
+ function bit[15:0] crc16d32(bit[31:0] d) {
+
+ bit [15:0] crc;
+ bit [15:0] C = 32'hFFFF;
+
+ crc[0] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[8] ^ d[10] ^ d[11] ^ d[16] ^ d[18] ^
+ d[19] ^ d[23] ^ d[27] ^ d[31] ^ C[4] ^ C[5] ^ C[7] ^ C[10] ^ C[12]
+ ^ C[13] ^ C[15];
+ crc[1] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[5] ^ d[7] ^ d[8] ^ d[9] ^ d[11] ^ d[15]
+ ^ d[16] ^ d[17] ^ d[19] ^ d[22] ^ d[23] ^ d[26] ^ d[27] ^ d[30] ^
+ d[31] ^ C[0] ^ C[4] ^ C[6] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ C[12] ^
+ C[14] ^ C[15];
+ crc[2] = d[0] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[14] ^ d[15]
+ ^ d[16] ^ d[18] ^ d[21] ^ d[22] ^ d[25] ^ d[26] ^ d[29] ^ d[30] ^
+ C[0] ^ C[1] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^
+ C[15];
+ crc[3] = d[0] ^ d[1] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[13] ^
+ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[23]
+ ^ d[24] ^ d[25] ^ d[27] ^ d[28] ^ d[29] ^ d[31] ^ C[0] ^ C[1] ^ C[2]
+ ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[14] ^ C[15];
+ crc[4] = d[0] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[12] ^ d[13] ^
+ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[23]
+ ^ d[24] ^ d[26] ^ d[27] ^ d[28] ^ d[30] ^ C[0] ^ C[1] ^ C[2] ^ C[3]
+ ^ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[15];
+ crc[5] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[11] ^ d[12] ^ d[13] ^
+ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[21] ^ d[22] ^ d[23]
+ ^ d[25] ^ d[26] ^ d[27] ^ d[29] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4]
+ ^ C[6] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[11];
+ crc[6] = d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[11] ^ d[12] ^
+ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[22]
+ ^ d[24] ^ d[25] ^ d[26] ^ d[28] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4]
+ ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ C[12];
+ crc[7] = d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[9] ^ d[10] ^ d[11] ^ d[12]
+ ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[19] ^ d[20] ^ d[21] ^
+ d[23] ^ d[24] ^ d[25] ^ d[27] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
+ C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^ C[12] ^ C[13];
+ crc[8] = d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[8] ^ d[9] ^ d[10] ^ d[11]
+ ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^
+ d[22] ^ d[23] ^ d[24] ^ d[26] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
+ C[5] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[12] ^ C[13] ^ C[14];
+ crc[9] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
+ ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[17] ^ d[18] ^ d[19] ^
+ d[21] ^ d[22] ^ d[23] ^ d[25] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
+ C[5] ^ C[6] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^ C[12] ^ C[13] ^ C[14]
+ ^ C[15];
+ crc[10] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
+ ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^
+ d[21] ^ d[22] ^ d[24] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^
+ C[7] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[14] ^ C[15];
+ crc[11] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10]
+ ^ d[11] ^ d[12] ^ d[13] ^ d[15] ^ d[16] ^ d[17] ^ d[19] ^ d[20] ^
+ d[21] ^ d[23] ^ C[0] ^ C[2] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^ C[8]
+ ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[14] ^ C[15];
+ crc[12] = d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[9] ^ d[12] ^ d[14] ^ d[15] ^
+ d[20] ^ d[22] ^ d[23] ^ d[27] ^ d[31] ^ C[0] ^ C[1] ^ C[3] ^ C[6]
+ ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[14];
+ crc[13] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[8] ^ d[11] ^ d[13] ^ d[14] ^
+ d[19] ^ d[21] ^ d[22] ^ d[26] ^ d[30] ^ C[1] ^ C[2] ^ C[4] ^ C[7]
+ ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15];
+ crc[14] = d[1] ^ d[2] ^ d[4] ^ d[5] ^ d[7] ^ d[10] ^ d[12] ^ d[13] ^ d[18] ^
+ d[20] ^ d[21] ^ d[25] ^ d[29] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10]
+ ^ C[11] ^ C[13] ^ C[14];
+ crc[15] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[9] ^ d[11] ^ d[12] ^ d[17] ^
+ d[19] ^ d[20] ^ d[24] ^ d[28] ^ C[3] ^ C[4] ^ C[6] ^ C[9] ^ C[11]
+ ^ C[12] ^ C[14] ^ C[15];
+
+ crc16d32 = {~crc[0],~crc[1],~crc[2],~crc[3],~crc[4],~crc[5],~crc[6],~crc[7],
+ ~crc[8],~crc[9],~crc[10],~crc[11],~crc[12],~crc[13],~crc[14],~crc[15]};
+
+ return;
+ }
+
+
+ }
Index: pcie_vera_tb/tags/gutzlogic_v_0/run_vera
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/run_vera (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/run_vera (revision 8)
@@ -0,0 +1,10 @@
+#!/bin/csh -f
+
+\rm -rf simv csrc simv.daidir comp.log sim.log
+
+ vcs -ntb ti_phy_top.test_top.v ti_phy_top.v ti_phy_top.vr \
+ -P /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/debussy.tab \
+ /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/pli.a \
+ -Mupdate -l vcs_compile.log +vcs+lic+wait +define+SYNOPSYS_NTB -l comp.log $*
+
+ ./simv -l sim.log $*
pcie_vera_tb/tags/gutzlogic_v_0/run_vera
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.test_top.v
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.test_top.v (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.test_top.v (revision 8)
@@ -0,0 +1,231 @@
+// ===========================================================================
+// File : ti_phy_top.test_top.v
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+// Please contact www.gutzlogic.com for details.
+// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
+// ===========================================================================
+//
+// $Id: ti_phy_top.test_top.v,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This is the top level testbench file.
+//
+// ===========================================================================
+// ===========================================================================
+module ti_phy_top_test_top;
+ parameter simulation_cycle = 100;
+
+ reg SystemClock;
+ wire clk_50mhz;
+ wire [1:0] PUSH_BUTTON;
+ wire FPGA_RESET_n;
+ wire rxclk;
+ wire [15:0] rxdata16;
+ wire [1:0] rxdatak16;
+ wire rxvalid16;
+ wire rxidle16;
+ wire rxidle;
+ wire [2:0] rxstatus;
+ wire phystatus;
+ wire [7:0] LED;
+ wire txclk;
+ wire [15:0] txdata16;
+ wire [1:0] txdatak16;
+ wire txidle16;
+ wire rxdet_loopb;
+ wire txcomp;
+ wire rxpol;
+ wire phy_reset_n;
+ wire [1:0] pwrdwn;
+ wire [16:0] sram_addr;
+ wire sram_adscn;
+ wire sram_adspn;
+ wire sram_advn;
+ wire [3:0] sram_ben;
+ wire [2:0] sram_ce;
+ wire sram_clk;
+ wire sram_gwn;
+ wire sram_mode;
+ wire sram_oen;
+ wire sram_wen;
+ wire sram_zz;
+ wire [35:0] sram_data;
+ assign rxclk = SystemClock;
+
+`ifdef SYNOPSYS_NTB
+ ti_phy_top_test vshell(
+ .SystemClock (SystemClock),
+ .\ti_phy_top.clk_50mhz (clk_50mhz),
+ .\ti_phy_top.PUSH_BUTTON (PUSH_BUTTON),
+ .\ti_phy_top.FPGA_RESET_n (FPGA_RESET_n),
+ .\ti_phy_top.rxclk (rxclk),
+ .\ti_phy_top.rxdata16 (rxdata16),
+ .\ti_phy_top.rxdatak16 (rxdatak16),
+ .\ti_phy_top.rxvalid16 (rxvalid16),
+ .\ti_phy_top.rxidle16 (rxidle16),
+ .\ti_phy_top.rxidle (rxidle),
+ .\ti_phy_top.rxstatus (rxstatus),
+ .\ti_phy_top.phystatus (phystatus),
+ .\ti_phy_top.sram_data (sram_data),
+ .\ti_phy_top.LED (LED),
+ .\ti_phy_top.txclk (txclk),
+ .\ti_phy_top.txdata16 (txdata16),
+ .\ti_phy_top.txdatak16 (txdatak16),
+ .\ti_phy_top.txidle16 (txidle16),
+ .\ti_phy_top.rxdet_loopb (rxdet_loopb),
+ .\ti_phy_top.txcomp (txcomp),
+ .\ti_phy_top.rxpol (rxpol),
+ .\ti_phy_top.phy_reset_n (phy_reset_n),
+ .\ti_phy_top.pwrdwn (pwrdwn),
+ .\ti_phy_top.sram_addr (sram_addr),
+ .\ti_phy_top.sram_adscn (sram_adscn),
+ .\ti_phy_top.sram_adspn (sram_adspn),
+ .\ti_phy_top.sram_advn (sram_advn),
+ .\ti_phy_top.sram_ben (sram_ben),
+ .\ti_phy_top.sram_ce (sram_ce),
+ .\ti_phy_top.sram_clk (sram_clk),
+ .\ti_phy_top.sram_gwn (sram_gwn),
+ .\ti_phy_top.sram_mode (sram_mode),
+ .\ti_phy_top.sram_oen (sram_oen),
+ .\ti_phy_top.sram_wen (sram_wen),
+ .\ti_phy_top.sram_zz (sram_zz)
+ );
+`else
+
+ vera_shell vshell(
+ .SystemClock (SystemClock),
+ .ti_phy_top_clk_50mhz (clk_50mhz),
+ .ti_phy_top_PUSH_BUTTON (PUSH_BUTTON),
+ .ti_phy_top_FPGA_RESET_n (FPGA_RESET_n),
+ .ti_phy_top_rxclk (rxclk),
+ .ti_phy_top_rxdata16 (rxdata16),
+ .ti_phy_top_rxdatak16 (rxdatak16),
+ .ti_phy_top_rxvalid16 (rxvalid16),
+ .ti_phy_top_rxidle16 (rxidle16),
+ .ti_phy_top_rxidle (rxidle),
+ .ti_phy_top_rxstatus (rxstatus),
+ .ti_phy_top_phystatus (phystatus),
+ .ti_phy_top_sram_data (sram_data),
+ .ti_phy_top_LED (LED),
+ .ti_phy_top_txclk (txclk),
+ .ti_phy_top_txdata16 (txdata16),
+ .ti_phy_top_txdatak16 (txdatak16),
+ .ti_phy_top_txidle16 (txidle16),
+ .ti_phy_top_rxdet_loopb (rxdet_loopb),
+ .ti_phy_top_txcomp (txcomp),
+ .ti_phy_top_rxpol (rxpol),
+ .ti_phy_top_phy_reset_n (phy_reset_n),
+ .ti_phy_top_pwrdwn (pwrdwn),
+ .ti_phy_top_sram_addr (sram_addr),
+ .ti_phy_top_sram_adscn (sram_adscn),
+ .ti_phy_top_sram_adspn (sram_adspn),
+ .ti_phy_top_sram_advn (sram_advn),
+ .ti_phy_top_sram_ben (sram_ben),
+ .ti_phy_top_sram_ce (sram_ce),
+ .ti_phy_top_sram_clk (sram_clk),
+ .ti_phy_top_sram_gwn (sram_gwn),
+ .ti_phy_top_sram_mode (sram_mode),
+ .ti_phy_top_sram_oen (sram_oen),
+ .ti_phy_top_sram_wen (sram_wen),
+ .ti_phy_top_sram_zz (sram_zz)
+ );
+`endif
+
+
+
+`ifdef emu
+ /* DUT is in emulator, so not instantiated here */
+`else
+ ti_phy_top dut(
+ .clk_50mhz (clk_50mhz),
+ .PUSH_BUTTON (PUSH_BUTTON),
+ .FPGA_RESET_n (FPGA_RESET_n),
+ .rxclk (rxclk),
+ .rxdata16 (rxdata16),
+ .rxdatak16 (rxdatak16),
+ .rxvalid16 (rxvalid16),
+ .rxidle16 (rxidle16),
+ .rxidle (rxidle),
+ .rxstatus (rxstatus),
+ .phystatus (phystatus),
+ .sram_data (sram_data),
+ .LED (LED),
+ .txclk (txclk),
+ .txdata16 (txdata16),
+ .txdatak16 (txdatak16),
+ .txidle16 (txidle16),
+ .rxdet_loopb (rxdet_loopb),
+ .txcomp (txcomp),
+ .rxpol (rxpol),
+ .phy_reset_n (phy_reset_n),
+ .pwrdwn (pwrdwn),
+ .sram_addr (sram_addr),
+ .sram_adscn (sram_adscn),
+ .sram_adspn (sram_adspn),
+ .sram_advn (sram_advn),
+ .sram_ben (sram_ben),
+ .sram_ce (sram_ce),
+ .sram_clk (sram_clk),
+ .sram_gwn (sram_gwn),
+ .sram_mode (sram_mode),
+ .sram_oen (sram_oen),
+ .sram_wen (sram_wen),
+ .sram_zz (sram_zz)
+ );
+`endif
+
+ always @ (posedge SystemClock) begin
+ if (|rxdatak16)
+ $display($time,":datak symbol");
+ end
+
+ reg set_once;
+ //simulation short ts1 sets
+`ifdef REAL_RTL
+ always @ (posedge SystemClock) begin
+ if (dut.phy_layer_top_inst.send_ts1 & ~set_once) begin
+ force dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count = 10'b1111000000;
+ set_once <= #1 1'b1;
+
+ end
+ else begin
+ release dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count;
+ if (dut.phy_layer_top_inst.ltssm_32bit_inst.start_link_training_pm) begin
+ set_once <= #1 1'b0;
+ end
+ end
+ end // always @ (posedge ti_phy_top_inst.clk_125mhz)
+`endif
+
+ initial begin
+ //****************************************************************************************
+ //force scramble bypass until the tb can scramble and de-scramble data.
+ //force dut.phy_layer_top_inst.make_rxdata_path16.scramble16_inst.scram_bypass = 2'b11;
+ //force dut.phy_layer_top_inst.make_tx_data_path16.scramble16_inst.scram_bypass = 2'b11;
+ //****************************************************************************************
+ set_once = 0;
+ SystemClock = 0;
+ forever begin
+ #(simulation_cycle/2)
+ SystemClock = ~SystemClock;
+ end
+
+ end
+
+ initial begin
+ $fsdbDumpfile("vera_test.fsdb");
+ $fsdbDumpvars(dut);
+ end
+
+
+
+endmodule
Index: pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.v
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.v (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.v (revision 8)
@@ -0,0 +1,200 @@
+// ===========================================================================
+// File : ti_phy_top.v
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+// Please contact www.gutzlogic.com for details.
+// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
+//
+// ===========================================================================
+//
+// $Id: ti_phy_top.v,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file is non-synthesizable rtl file to demonstrate TS1's.
+// Insert your own RTL design here. It has dummy signals for a sram if that
+// can be ignored.
+// ===========================================================================
+// ===========================================================================
+
+module ti_phy_top (/*AUTOARG*/
+ // Outputs
+ LED, txclk, txdata16, txdatak16, txidle16, rxdet_loopb, txcomp,
+ rxpol, phy_reset_n, pwrdwn, sram_addr, sram_adscn, sram_adspn,
+ sram_advn, sram_ben, sram_ce, sram_clk, sram_gwn, sram_mode,
+ sram_oen, sram_wen, sram_zz,
+ // Inouts
+ sram_data,
+ // Inputs
+ clk_50mhz, PUSH_BUTTON, FPGA_RESET_n, rxclk, rxdata16, rxdatak16,
+ rxvalid16, rxidle16, rxidle, rxstatus, phystatus
+ );
+ //****************************************************************************************
+ //TI PHY interface
+ //****************************************************************************************
+ //debug ports
+ input clk_50mhz;
+ input [1:0] PUSH_BUTTON;
+ output [7:0] LED;
+ reg [7:0] LED;
+ input FPGA_RESET_n;
+ //****************************************************************************************
+ //Phillips PHY interface
+ output txclk; //source synch 250 Mhz transmit clock from MAC.
+ wire txclk;
+
+ output [15:0] txdata16;
+ reg [15:0] txdata16;
+ output [1:0] txdatak16;
+ reg [1:0] txdatak16;
+ output txidle16; //forces tx output to electrical idle. txidle should be asserted while in power states p0 and p1.
+ reg txidle16;
+ input rxclk; //source synch 250 clk for received data.
+ input [15:0] rxdata16;
+ input [1:0] rxdatak16;
+ input rxvalid16;
+ output rxdet_loopb; //used to tell the phy to begin
+ reg rxdet_loopb;
+ input rxidle16;
+ input rxidle; //indicates receiver detection of an electrical idle; This is a synchronous signal.
+ input [2:0] rxstatus; //encodes receiver status and error codes.
+
+ input phystatus; //used to communicate completion of several phy functions.
+ output txcomp; //used when transmitting the compliance pattern; high-level sets the running disparity to negative.
+ reg txcomp;
+ output rxpol; //signals the phy to perform a polarity inversion on the receive data; low = no polarity inversion; high = polarity inversion.
+ reg rxpol;
+ output phy_reset_n; //phy reset active low
+ reg phy_reset_n;
+ output [1:0] pwrdwn;
+ reg [1:0] pwrdwn;
+
+ //****************************************************************************************
+ //SRAM Interface
+ output [16:0] sram_addr;
+ reg [16:0] sram_addr;
+ output sram_adscn;
+ reg sram_adscn;
+ output sram_adspn;
+ reg sram_adspn;
+ output sram_advn;
+ reg sram_advn;
+ output [3:0] sram_ben;
+ reg [3:0] sram_ben;
+ output [2:0] sram_ce;
+ reg [2:0] sram_ce;
+ output sram_clk;
+ reg sram_clk;
+ output sram_gwn;
+ reg sram_gwn;
+ output sram_mode;
+ reg sram_mode;
+ output sram_oen;
+ reg sram_oen;
+ output sram_wen;
+ reg sram_wen;
+ output sram_zz;
+ reg sram_zz;
+ inout [35:0] sram_data;
+
+
+ assign txclk = rxclk;
+ reg continue;
+
+ initial begin
+ LED <= 'b0;
+ txdata16 <= 15'b0;
+ txdatak16 <= 2'b0;
+ txidle16 <= 1'b0;
+ pwrdwn <= 2'b0;
+ phy_reset_n <= 1'b0;
+ rxpol <= 1'b0;
+ txcomp <= 1'b0;
+ rxdet_loopb <= 1'b0;
+ phy_reset_n <= 1'b0;
+ //ignore these signals
+ sram_addr <= 'b0;
+ sram_adscn <= 'b0;
+ sram_adspn <= 'b0;
+ sram_advn <= 'b0;
+ sram_ben <= 'b0;
+ sram_ce <= 'b0;
+ sram_clk <= 'b0;
+ sram_gwn <= 'b0;
+ sram_mode <= 'b0;
+ sram_oen <= 'b0;
+ sram_wen <= 'b0;
+ sram_zz <= 'b0;
+ //sram_data <= 'b0;
+ continue <= 1'b1;
+ #100;
+ phy_reset_n <= 1'b1;
+ sample_ts1();
+ end
+
+ task sample_ts1;
+ begin
+ pwrdwn <= 2'b10;
+ @ (negedge rxclk);
+ wait (phystatus == 0); //indicate that the pll is locked.
+ repeat (20) @ (negedge rxclk);
+ rxdet_loopb <= 1'b1;
+ wait (phystatus == 1'b1 && rxstatus == 3'b11); //receiver detect
+ repeat (5) @ (negedge rxclk);
+ rxdet_loopb <= 1'b0;
+ repeat (2) @ (negedge rxclk);
+ pwrdwn <= 2'b0;
+ wait (phystatus == 1'b0);
+ wait (phystatus == 1'b1 && rxstatus == 4'b100); //power change accept
+ repeat (100) @ (negedge rxclk);
+
+ while (continue == 1) begin
+ //start sending ts1;
+ @ (negedge rxclk);
+ txdatak16 <= 2'b11;
+ txdata16 <= 16'hf7bc; //PAD LINK,COM
+ @ (negedge rxclk);
+ txdatak16 <= 2'b01;
+ txdata16 <= 16'hf0f7; //NFST,PAD LANE
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h02; //training control Rate ID
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ @ (negedge rxclk);
+ txdatak16 <= 2'b0;
+ txdata16 <= 16'h4a4a; //ts id
+ //add sending ts2;
+ //add link and lane
+ end // while (continue == 1)
+ end
+ endtask // sample_ts1
+
+
+
+
+
+
+endmodule
+
+
+// Local Variables:
+// verilog-library-directories:("." "./dcm" "./ddr_div2" "./single_dcm" "./dll" "./tl")
+// End:
\ No newline at end of file
Index: pcie_vera_tb/tags/gutzlogic_v_0/pcie_tlp_packet.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/pcie_tlp_packet.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/pcie_tlp_packet.vri (revision 8)
@@ -0,0 +1,465 @@
+// ===========================================================================
+// File : pcie_tlp_packet.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: pcie_tlp_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file is a class of pcie packet can be used for all TLP
+// packet types.
+//
+// ===========================================================================
+// ===========================================================================
+#include
+
+class pcie_tlp_packet {
+ bit [15:0] sequence_num;
+ bit [4:0] type;
+ bit [1:0] fmt;
+ bit [9:0] length;
+ bit [2:0] tc;
+ bit [1:0] attr;
+ bit ep;
+ bit td;
+ bit [63:0] address; //used for multiple purposes.
+ bit [15:0] req_id;
+ bit [7:0] tag;
+ bit [3:0] first_be;
+ bit [3:0] last_be;
+ //completion fields
+ bit [15:0] completer_id;
+ bit [11:0] byte_count;
+ bit bcm;
+ bit [2:0] cmp_status;
+ bit [127:0] header;
+ bit [31:0] lcrc;
+ bit [31:0] data [];
+
+ //methods
+ task new(
+ bit [11:0] ic_sequence_num = 12'b0,
+ bit [4:0] ic_type = 5'h0,
+ bit [1:0] ic_fmt = 2'h0,
+ bit [9:0] ic_length = 10'h0,
+ bit [2:0] ic_tc = 3'h0,
+ bit [1:0] ic_attr = 2'h0,
+ bit ic_ep = 1'h0,
+ bit ic_td = 1'h0,
+ bit [63:0] ic_address = 64'h0,
+ bit [15:0] ic_req_id = 16'h0,
+ bit [7:0] ic_tag = 8'h0,
+ bit [3:0] ic_first_be = 4'hf,
+ bit [3:0] ic_last_be = 4'hf,
+ //completion fields
+ bit [15:0] ic_completer_id = 16'h0,
+ bit [11:0] ic_byte_count = 12'h0,
+ bit ic_bcm = 1'h0,
+ bit [2:0] ic_cmp_status = 3'h0,
+ bit [31:0] ic_config_data = 32'b0) {
+
+ sequence_num = {4'b0,ic_sequence_num};
+ type = ic_type;
+ fmt = ic_fmt;
+ length = ic_length;
+ tc = ic_tc;
+ attr = ic_attr;
+ ep = ic_ep;
+ td = ic_td;
+ address = ic_address;
+ req_id = ic_req_id;
+ tag = ic_tag;
+ first_be = ic_first_be;
+ last_be = ic_last_be;
+ completer_id = ic_completer_id;
+ byte_count = ic_byte_count;
+ bcm = ic_bcm;
+ cmp_status = ic_cmp_status;
+ data[0] = ic_config_data;
+ printf ("new seq(%0h),type(%0h),fmt(%0h),length(%0h),tc(%0h),attr(%0h),ep(%0h),td(%0h),addr(%0h),req_id(%0h),tag(%0h),fbe(%0h),lbe(%0h),cmp_id(%0h),bc(%0h),bcm(%0h),cmp_stat(%0h),cfgwr data(%0h)\n",
+ ic_sequence_num,
+ ic_type,
+ ic_fmt,
+ ic_length,
+ ic_tc,
+ ic_attr,
+ ic_ep,
+ ic_td,
+ ic_address,
+ ic_req_id,
+ ic_tag,
+ ic_first_be,
+ ic_last_be,
+ ic_completer_id,
+ ic_byte_count,
+ ic_bcm,
+ ic_cmp_status,
+ ic_config_data
+ );
+ }
+
+ task build_packet (string pkt_type = "posted") {
+ integer reserved = 0;
+ integer i;
+ bit [5:0] register_num;
+ bit [3:0] ext_register_num;
+ bit [2:0] function_number;
+ bit [4:0] device_number;
+ bit [7:0] bus_number;
+ bit [6:0] lower_addr = address[6:0];
+
+ bus_number = address[31:24];
+ function_number = address[23:19];
+ device_number = address[18:16];
+ ext_register_num = address[11:8];
+ register_num = address[7:2];
+
+ if (pkt_type == "posted" || pkt_type == "nonposted") {
+ //dw1
+ header[4:0] = type;
+ header[6:5] = fmt;
+ header[7] = reserved;
+ header[11:8] = reserved;
+ header[14:12] = tc;
+ header[15] = reserved;
+ header[17:16] = length[9:8];
+ header[19:18] = reserved;
+ header[21:20] = attr;
+ header[22] = ep;
+ header[23] = td;
+ header[31:24] = length[7:0];
+ //dw2
+ header[39:32] = req_id[15:8];
+ header[47:40] = req_id[7:0];
+ header[55:48] = tag;
+ header[59:56] = first_be;
+ header[63:60] = last_be;
+ //dw3&4
+ //configurations
+ if (type == 5'b00100 || type == 5'b00101) {
+ header[127:64] = {32'b0,
+ register_num[5:0],2'b0,
+ 4'b0,ext_register_num[3:0],
+ device_number[4:0],function_number[2:0],
+ bus_number[7:0]};
+ }
+ else if (fmt[0] == 1'b1) {
+ header[127:64] = {address[7:2],2'b0,address[15:8],
+ address[23:16],address[31:24],
+ address[39:32],address[47:40],
+ address[55:48],address[63:56]};
+ }
+ else {
+ header[127:64] = {32'b0,address[7:2],2'b0,address[15:8],
+ address[23:16],address[31:24]};
+ }
+ }
+ else if (pkt_type == "completion") {
+ //dw1
+ header[4:0] = type;
+ header[6:5] = fmt;
+ header[7] = reserved;
+ header[11:8] = reserved;
+ header[14:12] = tc;
+ header[15] = reserved;
+ header[17:16] = length[9:8];
+ header[19:18] = reserved;
+ header[21:20] = attr;
+ header[22] = ep;
+ header[23] = td;
+ header[31:24] = length[7:0];
+ //dw 2
+ header[39:32] = completer_id[15:8];
+ header[47:40] = completer_id[7:0];
+ header[51:48] = byte_count[11:8];
+ header[52] = bcm;
+ header[55:53] = cmp_status;
+ header[63:56] = byte_count[7:0];
+ //dw3
+ header[71:64] = req_id[15:8];
+ header[79:72] = req_id[7:0];
+ header[87:80] = tag;
+ header[95:88] = {1'b0,lower_addr};
+ //dw4
+ header[127:96] = 32'b0;
+ }
+ if (type[4:1] != 5'b0010 && fmt[1]) {
+ for (i=0;i
+
+class pcie_phy_packet {
+ bit [7:0] com;
+ bit [7:0] link;
+ bit [7:0] lane;
+ bit [7:0] n_fts;
+ bit [7:0] rateid;
+ bit [7:0] train_cntrl;
+ bit [7:0] ts_id;
+ bit [7:0] idle;
+ bit [7:0] skp;
+ bit [7:0] fts;
+ integer length;
+ bit [17:0] temp_packet[];
+
+
+ //methods
+ task new(
+ bit [7:0] ic_link = 8'hf7,
+ bit [7:0] ic_lane = 8'hf7,
+ bit [7:0] ic_nfts = 8'hff,
+ bit [7:0] ic_rateid = 8'h2,
+ bit [7:0] ic_train_cntrl = 8'h0,
+ bit [7:0] ic_ts_id = 8'h4a) {
+
+ link = ic_link;
+ lane = ic_lane;
+ n_fts = ic_nfts;
+ rateid = ic_rateid;
+ train_cntrl = ic_train_cntrl;
+ ts_id = ic_ts_id;
+ com = 8'hbc;
+ idle = 8'h7c;
+ skp = 8'h1c;
+ fts = 8'h3c;
+ }
+
+ task build_packet (string pkt_type = "ts") {
+ if (pkt_type == "ts") {
+ length = 8;
+ if (link == 8'hf7) temp_packet[0] = {2'b11,link,com};
+ else temp_packet[0] = {2'b01,link,com};
+ if (lane == 8'hf7) temp_packet[1] = {2'b1,n_fts,lane};
+ else temp_packet[1] = {2'b0,n_fts,lane};
+ temp_packet[2] = {2'b0,train_cntrl,rateid};
+ temp_packet[3] = {2'b0,ts_id,ts_id};
+ temp_packet[4] = {2'b0,ts_id,ts_id};
+ temp_packet[5] = {2'b0,ts_id,ts_id};
+ temp_packet[6] = {2'b0,ts_id,ts_id};
+ temp_packet[7] = {2'b0,ts_id,ts_id};
+ printf ("building training set packet (%0h)\n",
+ {temp_packet[7][15:0],temp_packet[6][15:0],
+ temp_packet[5][15:0],temp_packet[4][15:0],
+ temp_packet[3][15:0],temp_packet[2][15:0],
+ temp_packet[1][15:0],temp_packet[0][15:0]});
+ }
+ else if (pkt_type == "eidle") {
+ length = 2;
+ temp_packet[0] = {2'b11,idle,com};
+ temp_packet[1] = {2'b11,idle,idle};
+ printf ("building eidle packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
+ }
+ else if (pkt_type == "skip"){
+ length = 2;
+ temp_packet[0] = {2'b11,skp,com};
+ temp_packet[1] = {2'b11,skp,skp};
+ printf ("building skip packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
+ }
+ else if (pkt_type == "fast_ts"){
+ length = 2;
+ temp_packet[0] = {2'b11,fts,com};
+ temp_packet[1] = {2'b11,fts,fts};
+ printf ("building fts packet (%0h)\n",{temp_packet[1][15:0],temp_packet[0][15:0]});
+ }
+
+ }
+}
Index: pcie_vera_tb/tags/gutzlogic_v_0/link_training.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/link_training.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/link_training.vri (revision 8)
@@ -0,0 +1,209 @@
+// ===========================================================================
+// File : link_training.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: link_training.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function :This file performs the link training and link and lane negotiation
+//
+// ===========================================================================
+// ===========================================================================
+#include
+#define COM_s 8'hbc
+#define SKP_s 8'h1c
+#define IDLE_s 8'h7c
+#define FTS_s 8'h3c
+#define STP_s 8'hfb
+#define SDP_s 8'h5c
+#define EDB 8'hfe
+#define END_s 8'hfd
+
+task link_training () {
+
+ fork
+ send_ts();
+ receive_ts();
+ join none
+}
+
+
+task send_ts( ) {
+ integer index;
+ string pkt_type;
+ pkt_type = "ts";
+ //ti_phy_top.t1_count == 9'hff;
+ ti_phy_top.rxvalid16 = 1'b1;
+ wait_var(phy_rdy);
+
+ printf ("send_ts1 = %d \n",send_ts1);
+ while (LINK_UP == 0) {
+ if (send_ts1 == 1) {
+ ts2_cycle_cnt = 1;
+ //printf ("number of ts dut sent %d \n",ti_phy_top.t1_count);
+ printf ("ts #%0d ts 1's ",ts1_cycle_cnt++);
+ pkt_type = "ts";
+ training_set = new(link,lane,*,*,*,*);
+ training_set.build_packet(pkt_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for (index = 0; index < training_set.length; index ++) {
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = training_set.temp_packet[index][17:16];
+ //ti_phy_top.rxdata16 = training_set.temp_packet[index][15:0];
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {training_set.temp_packet[index][17:16],training_set.temp_packet[index][15:0]});
+ }
+ semaphore_put (my_semaphore, 1);
+ }
+ else if (send_ts2 == 1){
+ ts1_cycle_cnt = 1;
+ printf ("ts #%0d ts 2's ",ts2_cycle_cnt++);
+ pkt_type = "ts";
+ training_set = new(lane,link,*,*,*,'h45);
+ training_set.build_packet(pkt_type);
+ for (index = 0; index < training_set.length; index ++) {
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = training_set.temp_packet[index][17:16];
+ //ti_phy_top.rxdata16 = training_set.temp_packet[index][15:0];
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {training_set.temp_packet[index][17:16],training_set.temp_packet[index][15:0]});
+ }
+ }
+ }
+
+ printf ("LINK UP(%0d) !!!!!!!!!!!\n",LINK_UP);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+}
+
+task receive_ts () {
+ integer ret;
+ integer ts1_count=0;
+ integer ts2_count=0;
+ integer ts1_link_count = 0;
+ integer ts1_lane_count = 0;
+ integer ts2_lane_link_count = 0;
+ integer send_ts1_with_link, send_ts1_with_link_lane, send_ts2_with_link_lane;
+ bit [127:0] receive_phy_packet;
+
+ send_ts1 = 1;
+ send_ts2 = 0;
+ send_ts1_with_link = 0;
+ send_ts1_with_link_lane = 0;
+ send_ts2_with_link_lane = 0;
+ while (1) {
+ ret = mailbox_get (WAIT,phy_mailbox,receive_phy_packet,CHECK);
+ //printf ("Recieved PHY PACKET (%0h) added to phy mailbox\n",receive_phy_packet);
+ if (receive_phy_packet == 127'h454545454545454545450002f0f7f7bc) {
+ printf ("Recieved TS 2 PHY PACKET\n");
+ ts2_count++;
+ }
+ if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f0f7f7bc){
+ printf ("Recieved TS 1 PHY PACKET\n");
+ ts1_count++;
+ }
+ if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f0f701bc) {
+ printf ("Recieved TS 1 link accept PHY PACKET\n");
+ ts1_link_count++;
+ }
+ if (receive_phy_packet == 127'h4a4a4a4a4a4a4a4a4a4a0002f00101bc) {
+ printf ("Recieved TS 1 lane and link accept PHY PACKET\n");
+ ts1_lane_count++;
+ }
+ if (receive_phy_packet == 127'h454545454545454545450002f00101bc) {
+ printf ("Recieved TS 1 lane and link accept PHY PACKET\n");
+ ts2_lane_link_count++;
+ }
+
+ //printf ("send_ts2_with_link_lane(%0d)send_ts1_with_link_lane(%0d)send_ts1_with_link(%0d)send_ts2(%0d)send_ts1(%0d)\n",
+ // send_ts2_with_link_lane,send_ts1_with_link_lane,send_ts1_with_link,send_ts2,send_ts1 );
+ //printf ("ts2_lane_link_count(%0d)ts1_lane_count(%0d)ts1_link_count(%0d)ts1_count(%0d)ts2_count(%0d)\n",
+ // ts2_lane_link_count,ts1_lane_count,ts1_link_count,ts1_count,ts2_count);
+
+ if (send_ts2_with_link_lane && ts2_cycle_cnt > 16 && ts2_lane_link_count > 15) {
+ //clear all signals if we get a ts1 with pad
+ if (ts1_count > 0) {
+ send_ts1 = 1;
+ send_ts2 = 0;
+ send_ts2_with_link_lane = 0;
+ send_ts1_with_link_lane = 0;
+ send_ts1_with_link = 0;
+ LINK_UP = 0;
+ ts2_lane_link_count = 0;
+ ts1_lane_count = 0;
+ ts1_link_count = 0;
+ ts1_count = 0;
+ ts2_count = 0;
+ }
+ else {
+ send_ts1 = 0;
+ send_ts2 = 0;
+ LINK_UP = 1;
+ ts1_lane_count = 0;
+ ts1_link_count = 0;
+ ts1_count = 0;
+ ts2_count = 0;
+
+ }
+
+ }
+ else if (send_ts1_with_link_lane){
+ if (ts1_cycle_cnt > 16 && ts1_lane_count >16 ) {
+ send_ts1 = 0;
+ send_ts2 = 1;
+ link = 8'b1;
+ lane = 8'b1;
+ send_ts2_with_link_lane = 1;
+ ts1_lane_count = 0;
+ ts1_link_count = 0;
+ ts1_count = 0;
+ ts2_count = 0;
+ }
+ }
+ else if (send_ts1_with_link) {
+ if (ts1_cycle_cnt > 16 && ts1_link_count > 16) {
+ send_ts1 = 1;
+ send_ts2 = 0;
+ link = 8'b1;
+ lane = 8'b1;
+ send_ts1_with_link_lane = 1;
+ }
+ }
+ //send at least 16 ts 2
+ else if (send_ts2) {
+ if (ts2_count > 16 && ts2_cycle_cnt > 16) {
+ send_ts1 = 1;
+ send_ts2 = 0;
+ send_ts1_with_link = 1;
+ link = 8'b1;
+ lane = 8'hf7;
+ }
+ }
+ //send at least 100 ts 1's
+ else if (ts2_count > 16 && ts1_cycle_cnt > 100) {
+ send_ts1 = 0;
+ send_ts2 = 1;
+ link = 'hf7;
+ lane = 'hf7;
+ }
+ else {
+ send_ts1 = 1;
+ send_ts2 = 0;
+ link = 'hf7;
+ lane = 'hf7;
+ }
+ }
+}
+
Index: pcie_vera_tb/tags/gutzlogic_v_0/tlp_gen.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/tlp_gen.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/tlp_gen.vri (revision 8)
@@ -0,0 +1,186 @@
+// ===========================================================================
+// File : tlp_gen.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+// Please contact www.gutzlogic.com for details.
+// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
+// ===========================================================================
+//
+// $Id: tlp_gen.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file generates cfgrd/wr memrd/wr.
+//
+// ===========================================================================
+// ===========================================================================
+#include
+#define STP_s 8'hfb
+#define EDB 8'hfe
+task tlp_gen() {
+
+ bit [15:0] req_id;
+ bit [7:0] busnum;
+ bit [7:0] reg_num;
+ bit [3:0] first_be;
+ bit [3:0] last_be;
+ bit [63:0] address;
+ bit [9:0] length;
+ bit [31:0] data;
+ bit [7:0] tag;
+
+ //cfgwr(reg_num,first_be,req_id,tag,data);
+ sequence_id = 0; reg_num=0;first_be=4'hf;req_id=0101;tag=1;busnum=1;
+ printf ("read vendor id\n");
+ cfgrd(reg_num,first_be,req_id,tag,busnum);
+ sequence_id++; reg_num='h5;first_be=4'hf;req_id=0101;tag++;busnum=1;
+ printf ("write base address 1 register\n");
+ cfgwr(reg_num,first_be,req_id,tag,busnum,32'hba120000);
+ sequence_id++;address = 64'hba120000;length=10'h5;first_be=4'hf;last_be=4'hf;req_id=16'h0100;tag++;
+ memwr(address,length,first_be,last_be,req_id,tag);
+ //memrd(address,length,first_be,last_be,req_id,tag);
+}
+
+task cfgrd (bit [7:0] reg_num,
+ bit [3:0] first_be,
+ bit [15:0] req_id,
+ bit [7:0] tag,
+ bit [7:0] busnum) {
+
+ integer index;
+ bit [63:0] address = {32'b0,busnum,5'b1,3'b0,8'b0,reg_num,2'b0};
+
+ tlp_packet = new(sequence_id,5'b00100,2'b0,10'h1,*,*,*,*,
+ address,req_id,tag,first_be,4'b0,*,*,*,*,*);
+ tlp_packet.build_packet("nonposted");
+ printf ("header %0h \n",tlp_packet.header);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ //sequence id
+ printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
+ mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
+ printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
+ mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
+ //loop for sending out packet
+ for (index=1;index<3;index++) {
+ printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
+ printf("%0h put into mailbox index+1 = %0d\n",{2'b00,packet_array[index+1][7:0],packet_array[index][31:24]},index+1);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index+1][7:0],packet_array[index][31:24]});
+ }
+ printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
+ printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]});
+ printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[23:8]});
+ printf("%0h put into mailbox\n",{2'b10,END_s,tlp_packet.lcrc[31:24]});
+ mailbox_put(rx_data_mailbox, {2'b10,END_s,tlp_packet.lcrc[31:24]});
+ semaphore_put (my_semaphore, 1);
+}
+
+task cfgwr (bit [7:0] reg_num,
+ bit [3:0] first_be,
+ bit [15:0] req_id,
+ bit [7:0] tag,
+ bit [7:0] busnum,
+ bit [31:0] data) {
+
+ integer index;
+ //bus num,device num,function num,ext reg reg_num;
+ bit [63:0] address = {32'b0,busnum,5'b1,3'b0,8'b0,reg_num,2'b0};
+ printf ("cfgwr data = %0h\n",data);
+ tlp_packet = new(sequence_id,5'b00100,2'b10,10'h1,*,*,*,*,
+ address,req_id,tag,first_be,4'b0,*,*,*,*,data);
+ tlp_packet.build_packet("nonposted");
+ printf ("header %0h \n",tlp_packet.header);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ //sequence id
+ printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
+ mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
+ printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
+ mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
+ //loop for sending out packet
+ for (index=1;index<4;index++) {
+ printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
+ printf("%0h put into mailbox index+1 = %0d\n",{2'b00,packet_array[index+1][7:0],packet_array[index][31:24]},index+1);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index+1][7:0],packet_array[index][31:24]});
+ }
+ printf("%0h put into mailbox index = %0d\n",{2'b00,packet_array[index][23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,packet_array[index][23:8]});
+ printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[7:0],packet_array[index][31:24]});
+ printf("%0h put into mailbox index = %0d\n",{2'b00,tlp_packet.lcrc[23:8]},index);
+ mailbox_put(rx_data_mailbox, {2'b00,tlp_packet.lcrc[23:8]});
+ printf("%0h put into mailbox\n",{2'b10,END_s,tlp_packet.lcrc[31:24]});
+ mailbox_put(rx_data_mailbox, {2'b10,END_s,tlp_packet.lcrc[31:24]});
+ semaphore_put (my_semaphore, 1);
+}
+
+
+task memwr (bit [63:0] address,
+ bit [9:0] length,
+ bit [3:0] first_be,
+ bit [3:0] last_be,
+ bit [15:0] req_id,
+ bit [7:0] tag){
+ integer index;
+ bit seq_header;
+ integer total_length;
+ bit[1:0] fmt;
+ integer hdr_dw;
+ fmt = |address[63:32] == 1 ? 2'b11 : 2'b10;
+ hdr_dw = |address[63:32] == 1 ? 4 : 3;
+ total_length = hdr_dw + length; //add td when ready
+ //bus num,device num,function num,ext reg reg_num;
+ tlp_packet = new(sequence_id,5'b00000,fmt,length,*,*,*,*,
+ address,req_id,tag,first_be,last_be,*,*,*,*,*);
+ tlp_packet.build_packet("nonposted");
+ printf ("header %0h \n",tlp_packet.header);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ //sequence id
+ printf("%0h put into mailbox\n",{2'b01,packet_array[0][15:8],STP_s});
+ mailbox_put (rx_data_mailbox, {2'b01,packet_array[0][7:0],STP_s});
+ printf("%0h put into mailbox\n",{2'b00,packet_array[1][7:0],packet_array[0][7:0]});
+ mailbox_put (rx_data_mailbox, {2'b00,packet_array[1][7:0],packet_array[0][15:8]});
+ //loop for sending out packet
+ for (index=1;index
pcie_vera_tb/tags/gutzlogic_v_0/docs/PCI_Express_VERA_testbench.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pcie_vera_tb/tags/gutzlogic_v_0/InitFC1.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/InitFC1.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/InitFC1.vri (revision 8)
@@ -0,0 +1,363 @@
+// ===========================================================================
+// File : InitFC1.vri
+// Author : cwinward
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: InitFC1.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file performs the initial flow control sequence.
+//
+// ===========================================================================
+// ===========================================================================
+
+#include
+
+task InitFC1(var bit [7:0] ph_cl, var bit [11:0] pd_cl, var bit [7:0] cplh_cl,var bit [11:0] cpld_cl,var bit [7:0] nph_cl,var bit [11:0] npd_cl,var bit INITFC_DONE){
+ integer index;
+ string dllp_type;
+ bit fc1_p_rcvd = 1'b0;
+ bit fc1_np_rcvd = 1'b0;
+ bit fc1_cpl_rcvd = 1'b0;
+ bit fc2_p_rcvd = 1'b0;
+ bit fc2_np_rcvd = 1'b0;
+ bit fc2_cpl_rcvd = 1'b0;
+
+ bit fc1_completed = 1'b0;
+ bit fc2_completed = 1'b0;
+
+ //****************************************************************************************
+ //new task to read out the dllp's
+ //
+
+ while(fc1_completed == 1'b0){
+ fc1_completed = fc1_p_rcvd & fc1_np_rcvd & fc1_cpl_rcvd;
+ printf("FC1_completed <= %d.\n",fc1_completed);
+ receive_fc1_dllp(fc1_p_rcvd,fc1_np_rcvd,fc1_cpl_rcvd,ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl);
+ dllp_type = "initfc1_p";
+ printf("Sending out an InitFC1_P packet.\n");
+ flowcntrl_1 = new(*,*,*,*);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+
+ dllp_type = "initfc1_np";
+ printf("Sending out an InitFC1_NP packet.\n");
+ flowcntrl_1 = new(8'h00,8'h00,8'h01,8'b01010000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+
+ dllp_type = "initfc1_cpl";
+ printf("Sending out an InitFC1_NP packet.\n");
+ flowcntrl_1 = new(8'h40,8'h00,8'h01,8'b01100000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+ }
+
+ while(fc2_completed == 1'b0){
+ fc2_completed = fc2_p_rcvd | fc2_np_rcvd | fc2_cpl_rcvd;
+ printf("FC2_completed <= %d.\n",fc2_completed);
+ receive_fc2_dllp(fc2_p_rcvd,fc2_np_rcvd,fc2_cpl_rcvd);
+ dllp_type = "initfc1_p";
+ printf("Sending out an InitFC2_P packet.\n");
+ flowcntrl_1 = new(*,*,*,8'b11000000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+
+ dllp_type = "initfc1_np";
+ printf("Sending out an InitFC2_NP packet.\n");
+ flowcntrl_1 = new(8'h00,8'h00,8'h01,8'b11010000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+
+ dllp_type = "initfc1_cpl";
+ printf("Sending out an InitFC2_NP packet.\n");
+ flowcntrl_1 = new(8'h40,8'h00,8'h01,8'b11100000);
+ flowcntrl_1.build_packet(dllp_type);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ for(index=0; index <= 3; index ++)
+ {
+ @ (posedge CLOCK);
+ if(index==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,flowcntrl_1.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",flowcntrl_1.temp_packet[0][7:0],8'h5C);
+ }
+ else if(index==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",flowcntrl_1.temp_packet[0][23:16],flowcntrl_1.temp_packet[0][15:8]);
+ }
+ else if(index==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",flowcntrl_1.temp_packet[1][7:0],flowcntrl_1.temp_packet[0][31:24]);
+ }
+ else if(index==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,flowcntrl_1.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,flowcntrl_1.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,flowcntrl_1.temp_packet[1][15:8]);
+ }
+ }
+
+ @ (posedge CLOCK);
+ INITFC_DONE = fc1_completed & fc2_completed;
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = 1'b0;
+ semaphore_put (my_semaphore, 1);
+ }
+
+}
+
+task receive_fc1_dllp (var bit fc1_p_rcvd, var bit fc1_np_rcvd, var bit fc1_cpl_rcvd,var bit [7:0] ph_cl, var bit [11:0] pd_cl, var bit [7:0] cplh_cl,var bit [11:0] cpld_cl,var bit [7:0] nph_cl,var bit [11:0] npd_cl) {
+ integer ret;
+ bit [47:0] receive_dll_packet;
+
+ while (~(fc1_p_rcvd & fc1_np_rcvd & fc1_cpl_rcvd)) {
+ ret = mailbox_get (WAIT,dllp_mailbox,receive_dll_packet,CHECK);
+ if(receive_dll_packet[7:0] == 8'h40){
+ fc1_p_rcvd = 1'b1;
+ ph_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
+ pd_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
+ }
+ else if(receive_dll_packet[7:0] == 8'h50){
+ fc1_np_rcvd = 1'b1;
+ nph_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
+ npd_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
+ }
+ else if(receive_dll_packet[7:0] == 8'h60){
+ fc1_cpl_rcvd = 1'b1;
+ cplh_cl = {receive_dll_packet[13:8],receive_dll_packet[23:22]};
+ cpld_cl = {receive_dll_packet[19:16],receive_dll_packet[31:24]};
+ }
+ printf ("InitFC1 DLL PACKET (%0h) taken out of dll mailbox\n",receive_dll_packet);
+ }
+}
+
+task receive_fc2_dllp (var bit fc2_p_rcvd, var bit fc2_np_rcvd, var bit fc2_cpl_rcvd) {
+ integer ret;
+ bit [47:0] receive_dll_packet;
+
+ while (~(fc2_p_rcvd | fc2_np_rcvd | fc2_cpl_rcvd)) {
+ ret = mailbox_get (WAIT,dllp_mailbox,receive_dll_packet,CHECK);
+ if(receive_dll_packet[7:0] == 8'hC0){
+ fc2_p_rcvd = 1'b1;
+ }
+ else if(receive_dll_packet[7:0] == 8'hD0){
+ fc2_np_rcvd = 1'b1;
+ }
+ else if(receive_dll_packet[7:0] == 8'hE0){
+ fc2_cpl_rcvd = 1'b1;
+ }
+ printf ("InitFC2 DLL PACKET (%0h) taken out of dll mailbox\n",receive_dll_packet);
+ }
+}
+
Index: pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.vr
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.vr (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.vr (revision 8)
@@ -0,0 +1,209 @@
+// ===========================================================================
+// File : ti_phy_top.vr
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+// Please contact www.gutzlogic.com for details.
+// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
+// ===========================================================================
+//
+// $Id: ti_phy_top.vr,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This is the top level VERA file. It call all tasks and brings
+// up the PHY.
+// ===========================================================================
+// ===========================================================================
+
+#define OUTPUT_EDGE PHOLD
+#define OUTPUT_SKEW #1
+#define INPUT_SKEW #-1
+#define INPUT_EDGE PSAMPLE
+#include
+
+// define interfaces, and verilog_node here if necessary
+
+#include "ti_phy_top.if.vrh"
+#include "receive_packet.vri"
+#include "send_packet.vri"
+#include "pcie_phy_packet.vri"
+#include "link_training.vri"
+#include "skip_order_set.vri"
+#include "pcie_dllp_packet.vri"
+#include "InitFC1.vri"
+#include "pcie_tlp_packet.vri"
+#include "tlp_gen.vri"
+
+//kcode symbols
+#define COM_s 8'hbc
+#define SKP_s 8'h1c
+#define IDLE_s 8'h7c
+#define FTS_s 8'h3c
+#define STP_s 8'hfb
+#define SDP_s 8'h5c
+#define EDB 8'hfe
+#define END_s 8'hfd
+program ti_phy_top_test {
+
+ pcie_phy_packet training_set;
+ pcie_phy_packet skip_set;
+ //********************************
+ //link training gobal variables
+ integer send_ts1 = 1;
+ integer send_ts2 = 0;
+ bit [11:0] sequence_id;
+ bit [31:0] packet_array [1040];
+ bit [7:0] link = 8'hf7;
+ bit [7:0] lane = 8'hf7;
+ integer ts1_cycle_cnt = 1;
+ integer ts2_cycle_cnt = 1;
+ integer LINK_UP = 0;
+ bit [7:0] ph_cl = 8'b0;
+ bit [11:0] pd_cl = 12'b0;
+ bit [7:0] cplh_cl = 8'b0;
+ bit [11:0] cpld_cl = 12'b0;
+ bit [7:0] nph_cl = 8'b0;
+ bit [11:0] npd_cl = 12'b0;
+ bit INITFC_DONE = 1'b0;
+ //********************************
+ pcie_dllp_packet flowcntrl_1;
+ pcie_dllp_packet ack_seq_num;
+ pcie_tlp_packet tlp_packet;
+ integer phy_rdy = 0;
+ integer my_semaphore;
+ bit [8:0] tx_data_mailbox;
+ bit [15:0] tlp_header_mailbox;
+ bit [31:0] tlp_data_mailbox;
+ bit [47:0] dllp_mailbox;
+ bit [127:0] phy_mailbox;
+ bit [17:0] rx_data_mailbox;
+
+ //create mailboxes for transmit and receive packets
+ tx_data_mailbox = alloc(MAILBOX,0,1);
+ rx_data_mailbox = alloc(MAILBOX,0,1);
+
+ tlp_header_mailbox = alloc(MAILBOX,0,1);
+ tlp_data_mailbox = alloc(MAILBOX,0,1);
+ dllp_mailbox = alloc(MAILBOX,0,1);
+ phy_mailbox = alloc(MAILBOX,0,1);
+
+ //create a packet arbiter for packet going out on the rx line.
+ my_semaphore = alloc(SEMAPHORE, 0, 1, 1);
+ if (!my_semaphore) error ("Semaphore could not be allocated\n");
+
+ fork
+ clk_50mhz_gen();
+ phy_status();
+ skip_order_set();
+ receive_packet();
+ send_packet();
+ wait_var(phy_rdy);
+ link_training();
+ join none
+
+ init_ports ();
+ reset_sequence();
+ wait_var(LINK_UP);
+ fork
+ zero_fill();
+ join none
+ InitFC1(ph_cl,pd_cl,cplh_cl,cpld_cl,nph_cl,npd_cl,INITFC_DONE);
+
+ printf("Posted Header credit %h\n",ph_cl);
+ printf("Posted Data credit %h\n",pd_cl);
+
+ printf("NonPosted Header credit %h\n",nph_cl);
+ printf("NonPosted Data credit %h\n",npd_cl);
+
+ printf("Completion Header credit %h\n",cplh_cl);
+ printf("Completion Data credit %h\n",cpld_cl);
+
+ printf("INITFC_DONE=%d\n.",INITFC_DONE);
+ tlp_gen();
+ repeat (10000) @(posedge CLOCK);
+} // end of program ti_phy_top_test
+
+// define tasks/classes/functions here if necessary
+
+task clk_50mhz_gen () {
+ ti_phy_top.clk_50mhz = 0;
+ @(posedge ti_phy_top.rxclk);
+ while(1) {
+ @10 ti_phy_top.clk_50mhz = 1;
+ @10 ti_phy_top.clk_50mhz = 0;
+ }
+}
+
+task init_ports () {
+ printf("Task init_ports\n");
+ @(posedge ti_phy_top.rxclk);
+ ti_phy_top.FPGA_RESET_n = 1'b0;
+ ti_phy_top.rxdata16 = 16'b0;
+ ti_phy_top.rxdatak16 = 2'b0;
+ ti_phy_top.rxvalid16 = 1'b0;
+ ti_phy_top.rxidle16 = 1'b0;
+ ti_phy_top.rxstatus = 1'b1;
+ ti_phy_top.phystatus = 1'b1;
+}
+
+task reset_sequence() {
+ printf("Task phy bring up\n");
+
+ @5 ti_phy_top.FPGA_RESET_n = 1'b0;
+ @1 ti_phy_top.FPGA_RESET_n = 1'b1;
+}
+
+
+task phy_status () {
+ bit [1:0] prev_pwrdwn = 0;
+ integer loop_back_high;
+ integer phy_status_arb;
+ phy_status_arb = alloc(SEMAPHORE,0,1,1);
+ if (!phy_status_arb) error ("Semaphore could not be allocated\n");
+ printf("Look for power changes\n");
+ @50 ti_phy_top.rxidle16 = 1'b0;
+ @100 ti_phy_top.phystatus = 1'b0;
+ while (1){
+ prev_pwrdwn = ti_phy_top.pwrdwn;
+ @(posedge CLOCK);
+ //receiver detect
+ if (ti_phy_top.rxdet_loopb == 1'b1 && ti_phy_top.pwrdwn == 2'b10) {
+ loop_back_high = 1;
+ if (!semaphore_get(WAIT,phy_status_arb,1))
+ error ("Semaphore_get returned 0\n");
+ //printf("GOT PHY ARB1 /n");
+ @10 ti_phy_top.rxstatus = 3'b11;
+ @10 ti_phy_top.phystatus = 1'b1;
+ while(loop_back_high) {
+ @(posedge CLOCK);
+ if (ti_phy_top.rxdet_loopb == 1'b0) {
+ loop_back_high = 1'b0;
+ }
+ }
+ @4 ti_phy_top.phystatus = 1'b0;
+ ti_phy_top.rxstatus = 3'b0;
+ semaphore_put (phy_status_arb, 1);
+ }
+ if (ti_phy_top.pwrdwn != prev_pwrdwn){
+ if (!semaphore_get(WAIT,phy_status_arb,1))
+ error ("Semaphore_get returned 0\n");
+ //printf("GOT PHY ARB2 /n");
+ @1 ti_phy_top.rxstatus = 3'b100;
+ ti_phy_top.phystatus = 1'b1;
+ @1 ti_phy_top.phystatus = 1'b0;
+ if (ti_phy_top.pwrdwn == 2'b00) phy_rdy = 1;
+ semaphore_put (phy_status_arb, 1);
+
+ }
+ }
+}
+
+
+
Index: pcie_vera_tb/tags/gutzlogic_v_0/receive_packet.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/receive_packet.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/receive_packet.vri (revision 8)
@@ -0,0 +1,305 @@
+// ===========================================================================
+// File : receive_packet.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: receive_packet.vri,v 1.1.1.1 2007-12-05 18:37:06 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : This file processes all packets received from the 16 tx interface
+//
+// ===========================================================================
+// ===========================================================================
+#include
+#include "scramble8.vri"
+#define COM_s 8'hbc
+#define SKP_s 8'h1c
+#define IDLE_s 8'h7c
+#define FTS_s 8'h3c
+#define STP_s 8'hfb
+#define SDP_s 8'h5c
+#define EDB 8'hfe
+#define END_s 8'hfd
+
+task receive_packet () {
+ bit [7:0] tx_data[];
+ bit tx_datak[];
+ integer ret,ret1,ret2,ret3,ret4;
+ integer i = 0;
+ integer m = 0;
+ bit[8:0] tx_pkt;
+ event phy_start, phy_done, tlp_start, tlp_done, dllp_start, dllp_done;
+ bit [7:0] phy_pkt[];
+ bit [7:0] dll_pkt[];
+ bit [7:0] tlp_pkt[];
+ integer j,k,l;
+ bit [127:0] build_phy_pkt;
+ bit [47:0] build_dll_pkt;
+ bit [127:0] build_tlp_header;
+ bit [31:0] build_tlp_data;
+ bit [15:0] expected_seq_id = 0;
+ bit [15:0] recv_seq_id = 0;
+ bit [9:0] recv_length = 0;
+ bit [31:0] recv_lcrc = 0;
+ bit td = 0;
+ integer kstart = 0;
+ integer debug = 1;
+ bit [15:0] lfsr = 16'hFFFF;
+ bit [7:0] scramble_data[];
+ bit skp_detect = 1'b0;
+ bit com_detect = 1'b0;
+ bit scram_bypass = 1'b0;
+ bit [3:0] bypass_count = 4'b0;
+
+ printf("Look for transmit packets\n");
+ wait_var(phy_rdy);
+ @ (posedge CLOCK);
+ fork
+ while (1) {
+ @ (posedge CLOCK);
+ tx_data[0] = ti_phy_top.txdata16[7:0];
+ tx_data[1] = ti_phy_top.txdata16[15:8];
+ tx_datak[0] = ti_phy_top.txdatak16[0];
+ tx_datak[1] = ti_phy_top.txdatak16[1];
+ for (i=0; i<2; i++) {
+
+ if(com_detect == 1'b1){
+ scram_bypass = 1'b1;
+ }
+ else if(((bypass_count == 4'b0011) & tx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
+ scram_bypass = 1'b0;
+ }
+
+ if((com_detect == 1'b1) | scram_bypass){
+ bypass_count = bypass_count + 1'b1;
+ }
+ else if(((bypass_count == 4'b0011) & tx_datak[i] == 1'b1) | (bypass_count == 4'b1111)){
+ bypass_count = 4'b0000;
+ }
+
+
+ if({tx_datak[i],tx_data[i]} == {1'b1,SKP_s}){
+ skp_detect = 1'b1;
+ }
+ else{
+ skp_detect = 1'b0;
+ }
+ if({tx_datak[i],tx_data[i]} == {1'b1,COM_s}){
+ com_detect = 1'b1;
+ }
+ else{
+ com_detect = 1'b0;
+ }
+
+
+ //printf("K-Code = %h DATA = %h COM = %h SKP = %h bypass_count = %d scram_bypass = %h\n",tx_datak[i],tx_data[i],com_detect,skp_detect,bypass_count,scram_bypass);
+
+ //if({tx_datak[i],tx_data[i]} == {1'b1,STP_s}){
+ // printf("Start of TLP packet.\n");
+ //}
+
+ scramble8(tx_data[i],skp_detect,com_detect,(scram_bypass | tx_datak[i]),lfsr,scramble_data[i],lfsr);
+ //printf("K-Code = %h COM = %h SKP = %h bypass = %h scramble_data = %h unscramble_data = %h lfsr = %h bypass_cnt = %d\n",tx_datak[i],com_detect,skp_detect,scram_bypass,tx_data[i],scramble_data[i],lfsr,bypass_count);
+
+ mailbox_put (tx_data_mailbox, {tx_datak[i],scramble_data[i]});
+ //printf("Add packet to tx_mailbox %0h\n",tx_data[i]);
+
+ }
+ }
+ while (1) {
+ ret = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ if (ret <= 0)
+ error ("mailbox_get returned %0d\n",ret);
+ //printf ("got tx_pkt %0h\n",tx_pkt);
+ if (tx_pkt == {1'b1,COM_s}) {
+ trigger (ONE_BLAST,phy_start);
+ sync (ALL,phy_done);
+ }
+ if (tx_pkt == {1'b1,STP_s}) {
+ trigger (ONE_BLAST,tlp_start);
+ sync (ALL,tlp_done);
+ }
+ if (tx_pkt == {1'b1,SDP_s}) {
+ trigger (ONE_BLAST,dllp_start);
+ sync (ALL,dllp_done);
+ }
+ }
+ //phy layer packets
+ while (1) {
+ sync(ALL,phy_start);
+ //printf ("got past sync %0h\n",tx_pkt);
+ phy_pkt[0] = COM_s;
+ phy_pkt[4] = 0;
+ phy_pkt[5] = 0;
+ phy_pkt[6] = 0;
+ phy_pkt[7] = 0;
+ phy_pkt[8] = 0;
+ phy_pkt[9] = 0;
+ phy_pkt[10] = 0;
+ phy_pkt[11] = 0;
+ phy_pkt[12] = 0;
+ phy_pkt[13] = 0;
+ phy_pkt[14] = 0;
+ phy_pkt[15] = 0;
+ ret2 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ //printf ("got past mailbox get %0h\n",tx_pkt);
+ phy_pkt[1] = tx_pkt;
+ //training set
+ if ((tx_pkt == 'h1f7) || ~tx_pkt[8]) {
+ for (j = 2; j <16; j++) {
+ ret2 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ phy_pkt[j] = tx_pkt;
+ }
+ }
+ //skip fst idle
+ else {
+ for (j=2;j<4;j++) {
+ ret1 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ phy_pkt[j] = tx_pkt;
+ //printf ("skip loop got past %0h\n",tx_pkt);
+ }
+ }
+ build_phy_pkt = {phy_pkt[15],phy_pkt[14],phy_pkt[13],phy_pkt[12],phy_pkt[11],
+ phy_pkt[10],phy_pkt[9],phy_pkt[8],phy_pkt[7],phy_pkt[6],
+ phy_pkt[5],phy_pkt[4],phy_pkt[3],phy_pkt[2],phy_pkt[1],phy_pkt[0]};
+ mailbox_put (phy_mailbox, build_phy_pkt);
+ printf ("Recieved PHY PACKET (%0h) added to phy mailbox\n",build_phy_pkt);
+ trigger (ONE_BLAST,phy_done);
+ }
+ //dll layer packets
+ while (1) {
+ sync (ALL,dllp_start);
+ //printf ("sync into dllp packet\n");
+ for (k = 0; k < 6; k++) {
+ ret3 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ dll_pkt[k] = tx_pkt;
+ //printf ("dll_pkt(%0h)\n",dll_pkt[k]);
+ }
+ ret3 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ //printf ("dll this should be end(%0h)\n",tx_pkt);
+ if (tx_pkt == {1'b1,END_s}) {
+ build_dll_pkt = {dll_pkt[6],dll_pkt[5],dll_pkt[4],dll_pkt[3],
+ dll_pkt[2],dll_pkt[1],dll_pkt[0]};
+ mailbox_put (dllp_mailbox, build_dll_pkt);
+ printf ("Recieved DLL PACKET (%0h) added to dllp mailbox\n",build_dll_pkt);
+ }
+ else
+ printf ("ERROR ->>>>>>> DLL malformed no END\n");
+
+ trigger (ONE_BLAST,dllp_done);
+ }
+ //tlp layer packets
+ while (1) {
+ sync (ALL,tlp_start);
+ printf ("sync into tlp packet\n");
+ @(posedge CLOCK);
+ //4 dw header + seq.
+ for (k = 0; k < 18; k++) {
+ //printf("debug1 %0d\n",debug++);
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ tlp_pkt[k] = tx_pkt;
+ }
+ recv_seq_id = {tlp_pkt[0],tlp_pkt[1]};
+ if (recv_seq_id != expected_seq_id) printf ("ERROR ->>>>>>> TLP BAD SEQUENCE ID of %0h\n",recv_seq_id);
+ //ack packet
+ else {
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ ack_seq_num = new(recv_seq_id[7:0],{4'b0,recv_seq_id[11:8]},8'b0,8'b0);
+ ack_seq_num.build_packet("ack");
+ for(m=0; m <= 3; m ++) {
+ @ (posedge CLOCK);
+ printf("ACK PACKET Sequence Number (%0h)\n",recv_seq_id);
+ if(m==0){
+ //ti_phy_top.rxdatak16 = 2'b01;
+ //ti_phy_top.rxdata16 = {flowcntrl_1.temp_packet[0][7:0],8'h5C};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b01,ack_seq_num.temp_packet[0][7:0],8'h5C});
+ printf("DLLP bytes SDB & DLL_TYPE %h%h.\n",ack_seq_num.temp_packet[0][7:0],8'h5C);
+ }
+ else if(m==1){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {ack_packet.temp_packet[0][23:16],ack_packet.temp_packet[0][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,ack_seq_num.temp_packet[0][23:16],ack_seq_num.temp_packet[0][15:8]});
+ printf("DLLP bytes 2 & 1 %h%h.\n",ack_seq_num.temp_packet[0][23:16],ack_seq_num.temp_packet[0][15:8]);
+ }
+ else if(m==2){
+ //ti_phy_top.rxdatak16 = 2'b00;
+ //ti_phy_top.rxdata16 = {ack_packet.temp_packet[1][7:0],ack_packet.temp_packet[0][31:24]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b00,ack_seq_num.temp_packet[1][7:0],ack_seq_num.temp_packet[0][31:24]});
+ printf("DLLP CRC and byte 3 %h%h.\n",ack_seq_num.temp_packet[1][7:0],ack_seq_num.temp_packet[0][31:24]);
+ }
+ else if(m==3){
+ //ti_phy_top.rxdatak16 = 2'b10;
+ //ti_phy_top.rxdata16 = {8'hFD,ack_packet.temp_packet[1][15:8]};
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {2'b10,8'hFD,ack_seq_num.temp_packet[1][15:8]});
+ printf("DLLP STP and CRC %h%h.\n",8'hFD,ack_seq_num.temp_packet[1][15:8]);
+ }
+ }
+ semaphore_put (my_semaphore, 1);
+ }
+ expected_seq_id++;
+ build_tlp_header = {tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14],
+ tlp_pkt[13],tlp_pkt[12],tlp_pkt[11],tlp_pkt[10],
+ tlp_pkt[9],tlp_pkt[8],tlp_pkt[7],tlp_pkt[6],
+ tlp_pkt[5],tlp_pkt[4],tlp_pkt[3],tlp_pkt[2]};
+ if (build_tlp_header[5] == 1'b0) {
+ if (build_tlp_header[6] == 0) recv_lcrc = {tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14]};
+ build_tlp_header[127:96] = 32'b0;
+ }
+ mailbox_put (tlp_header_mailbox, build_tlp_header);
+ printf ("Recieved TLP PACKET (%0h) added to tlp header mailbox\n",build_tlp_header);
+ if (build_tlp_header[6] == 1) {
+ td = build_tlp_header[23];
+ recv_length = {build_tlp_header[17:16],build_tlp_header[31:24]};
+ kstart = 0;
+ if (build_tlp_header[5] == 1'b0) {
+ mailbox_put (tlp_data_mailbox, {tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14]});
+ printf ("Recieved TLP DATA (%0h) added to tlp data mailbox\n",{tlp_pkt[17],tlp_pkt[16],tlp_pkt[15],tlp_pkt[14]});
+ kstart = 5;
+ }
+
+ for (k=kstart;k<=((recv_length*4)+(td*4));k++) {
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ //printf("debug2 %0d\n",debug++);
+ tlp_pkt[k] = tx_pkt;
+ if (k%4) {
+ mailbox_put (tlp_data_mailbox, {tlp_pkt[k],tlp_pkt[k-1],tlp_pkt[k-2],tlp_pkt[k-3]});
+ printf ("Recieved TLP DATA (%0h) added to tlp data mailbox\n",{tlp_pkt[k],tlp_pkt[k-1],tlp_pkt[k-2],tlp_pkt[k-3]});
+ }
+
+ }
+ }
+ if (build_tlp_header[5] == 0 & build_tlp_header[6] == 0) printf ("tlp lcrc value = %0h \n",recv_lcrc);
+ else {
+ for (k=0;k<=3;k++) {
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ //printf("debug3 %0d\n",debug++);
+ tlp_pkt[k] = tx_pkt;
+ }
+ printf ("tlp lcrc value = %0h \n",{tlp_pkt[3],tlp_pkt[2],tlp_pkt[1],tlp_pkt[0]});
+ }
+
+ ret4 = mailbox_get (WAIT,tx_data_mailbox,tx_pkt,CHECK);
+ //printf("debug4 %0d\n",debug++);
+ if (tx_pkt != {1'b1,END_s}) printf ("ERROR ->>>>>>> TLP malformed no END(%0h)\n",tx_pkt);
+
+
+ trigger (ONE_BLAST,tlp_done);
+ }
+ join none
+}
+
Index: pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.if.vrh
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.if.vrh (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/ti_phy_top.if.vrh (revision 8)
@@ -0,0 +1,64 @@
+// ===========================================================================
+// File : ti_phy_top.if.vrh
+// Author : cwinward
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: ti_phy_top.if.vrh,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : .This is the interface file linking verilog with VERA
+//
+// ===========================================================================
+// ===========================================================================
+#ifndef INC_TI_PHY_TOP_IF_VRH
+#define INC_TI_PHY_TOP_IF_VRH
+
+ interface ti_phy_top {
+ input rxclk CLOCK;
+ //input [9:0] t1_count PSAMPLE #-1 verilog_node "dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count";
+ output clk_50mhz OUTPUT_EDGE OUTPUT_SKEW;
+ output [1:0] PUSH_BUTTON OUTPUT_EDGE OUTPUT_SKEW;
+ output FPGA_RESET_n OUTPUT_EDGE OUTPUT_SKEW;
+ output [15:0] rxdata16 OUTPUT_EDGE OUTPUT_SKEW;
+ output [1:0] rxdatak16 OUTPUT_EDGE OUTPUT_SKEW;
+ output rxvalid16 OUTPUT_EDGE OUTPUT_SKEW;
+ output rxidle16 OUTPUT_EDGE OUTPUT_SKEW;
+ output rxidle OUTPUT_EDGE OUTPUT_SKEW;
+ output [2:0] rxstatus OUTPUT_EDGE OUTPUT_SKEW;
+ output phystatus OUTPUT_EDGE OUTPUT_SKEW;
+ input [7:0] LED INPUT_EDGE INPUT_SKEW;
+ input txclk INPUT_EDGE INPUT_SKEW;
+ input [15:0] txdata16 INPUT_EDGE INPUT_SKEW;
+ input [1:0] txdatak16 INPUT_EDGE INPUT_SKEW;
+ input txidle16 INPUT_EDGE INPUT_SKEW;
+ input rxdet_loopb INPUT_EDGE INPUT_SKEW;
+ input txcomp INPUT_EDGE INPUT_SKEW;
+ input rxpol INPUT_EDGE INPUT_SKEW;
+ input phy_reset_n INPUT_EDGE INPUT_SKEW;
+ input [1:0] pwrdwn INPUT_EDGE INPUT_SKEW;
+ input [16:0] sram_addr INPUT_EDGE INPUT_SKEW;
+ input sram_adscn INPUT_EDGE INPUT_SKEW;
+ input sram_adspn INPUT_EDGE INPUT_SKEW;
+ input sram_advn INPUT_EDGE INPUT_SKEW;
+ input [3:0] sram_ben INPUT_EDGE INPUT_SKEW;
+ input [2:0] sram_ce INPUT_EDGE INPUT_SKEW;
+ input sram_clk INPUT_EDGE INPUT_SKEW;
+ input sram_gwn INPUT_EDGE INPUT_SKEW;
+ input sram_mode INPUT_EDGE INPUT_SKEW;
+ input sram_oen INPUT_EDGE INPUT_SKEW;
+ input sram_wen INPUT_EDGE INPUT_SKEW;
+ input sram_zz INPUT_EDGE INPUT_SKEW;
+ inout [35:0] sram_data INPUT_EDGE INPUT_SKEW OUTPUT_EDGE OUTPUT_SKEW;
+ } // end of interface ti_phy_top
+
+#endif
Index: pcie_vera_tb/tags/gutzlogic_v_0/skip_order_set.vri
===================================================================
--- pcie_vera_tb/tags/gutzlogic_v_0/skip_order_set.vri (nonexistent)
+++ pcie_vera_tb/tags/gutzlogic_v_0/skip_order_set.vri (revision 8)
@@ -0,0 +1,64 @@
+// ===========================================================================
+// File : skip_order_set.vri
+// Author : cmagleby
+// Date : Mon Dec 3 11:03:46 MST 2007
+// Project : TI PHY design
+//
+// Copyright (c) notice
+// This code adheres to the GNU public license
+//
+// ===========================================================================
+//
+// $Id: skip_order_set.vri,v 1.1.1.1 2007-12-05 18:37:07 cmagleby Exp $
+//
+// ===========================================================================
+//
+// $Log: not supported by cvs2svn $
+//
+// ===========================================================================
+// Function : this file generates skip order sets when the timer expires
+//
+// ===========================================================================
+// ===========================================================================
+#include
+
+//task to send in skip order sets on a regular basis.
+task skip_order_set() {
+ integer time_limit_expire = 0;
+ integer index = 0;
+ wait_var(phy_rdy);
+ while(1) {
+ time_limit_expire++;
+ @ (posedge CLOCK);
+ ti_phy_top.rxdatak16 = 2'b00;
+ ti_phy_top.rxdata16 = 1'b0;
+ //1180 symbols clk is 2 symbols
+ if (time_limit_expire == 1180/2) {
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ skip_set = new(*,*,*,*,*,*);
+ skip_set.build_packet("skip");
+ for (index = 0; index < skip_set.length; index ++) {
+ @ (posedge CLOCK);
+ //ti_phy_top.rxdatak16 = skip_set.temp_packet[index][17:16];
+ //ti_phy_top.rxdata16 = skip_set.temp_packet[index][15:0];
+ //adding mailbox
+ mailbox_put (rx_data_mailbox, {skip_set.temp_packet[index][17:16],skip_set.temp_packet[index][15:0]});
+ time_limit_expire = 0;
+ }
+ semaphore_put (my_semaphore, 1);
+ }
+ }
+}
+
+
+task zero_fill(){
+
+ while(1) {
+ @ (posedge CLOCK);
+ if (!semaphore_get(WAIT,my_semaphore,1))
+ error ("Semaphore_get returned 0\n");
+ mailbox_put (rx_data_mailbox,18'b0);
+ semaphore_put(my_semaphore, 1);
+ }
+}
Index: pcie_vera_tb/tags
===================================================================
--- pcie_vera_tb/tags (nonexistent)
+++ pcie_vera_tb/tags (revision 8)
pcie_vera_tb/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##