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    from Rev 7 to Rev 8
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Rev 7 → Rev 8

/trunk/vhdl/mips_cpu.vhd
32,7 → 32,7
--
-- Writing to memory takes four cycles to meet RAM address hold times.
-- Addresses with a(31)='1' take two cycles (assumed to be clocked).
-- Here are the signals for writing a charater to address 0xffff:
-- Here are the signals for writing a character to address 0xffff:
--
-- mem_write
-- interrupt mem_byte_sel
133,6 → 133,9
intr_enable : out std_logic);
end component;
 
--for all:reg_bank use entity work.reg_bank(ram_block);
for all:reg_bank use entity work.reg_bank(logic);
 
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
228,7 → 231,7
end if;
end process;
 
u1: pc_next PORT MAP (
u1_pc_next: pc_next PORT MAP (
clk => clk,
reset_in => reset_reg,
take_branch => take_branch,
239,7 → 242,7
pc_out => pc,
pc_out_plus4 => pc_plus4);
 
u2: mem_ctrl PORT MAP (
u2_mem_ctrl: mem_ctrl PORT MAP (
clk => clk,
reset_in => reset_reg,
pause_in => pause,
260,7 → 263,7
mem_write => mem_write,
mem_pause => mem_pause);
 
u3: control PORT MAP (
u3_control: control PORT MAP (
opcode => opcode,
intr_signal => intr_signal,
pause_in => pause,
278,7 → 281,7
pc_source_out=> pc_source,
mem_source_out=> mem_source);
 
u4: reg_bank port map (
u4_reg_bank: reg_bank port map (
clk => clk,
rs_index => rs_index,
rt_index => rt_index,
288,7 → 291,7
reg_dest_new => reg_dest,
intr_enable => intr_enable);
 
u5: bus_mux port map (
u5_bus_mux: bus_mux port map (
imm_in => imm,
reg_source => reg_source,
a_mux => a_source,
308,19 → 311,19
branch_func => branch_function,
take_branch => take_branch);
 
u6: alu port map (
u6_alu: alu port map (
a_in => a_bus,
b_in => b_bus,
alu_function => alu_function,
c_alu => c_alu);
 
u7: shifter port map (
u7_shifter: shifter port map (
value => b_bus,
shift_amount => a_bus(4 downto 0),
shift_func => shift_function,
c_shift => c_shift);
 
u8: mult port map (
u8_mult: mult port map (
clk => clk,
a => a_bus,
b => b_bus,
/trunk/vhdl/mem_ctrl.vhd
190,7 → 190,11
setup_state <= setup_state_next;
end if;
 
opcode_out <= opcode_reg;
if reset_in = '0' then
opcode_out <= opcode_reg;
else
opcode_out <= ZERO;
end if;
data_read <= datab;
pause_out <= mem_pause or pause;
mem_byte_sel <= byte_sel_next;
/trunk/vhdl/tbench.vhd
14,7 → 14,6
use work.mips_pack.all;
 
entity tbench is
port(clk_out : out std_logic);
end; --entity tbench
 
architecture logic of tbench is
80,7 → 79,5
mem_data_w => mem_data_w,
mem_data_r => mem_data_r);
 
clk_out <= clk;
 
end; --architecture logic
 
/trunk/vhdl/reg_bank.vhd
12,6 → 12,7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; --needed for conv_integer
use work.mips_pack.all;
 
entity reg_bank is
25,6 → 26,73
intr_enable : out std_logic);
end; --entity reg_bank
 
--------------------------------------------------------------------
-- Change mips_cpu.vhd to use the ram_block architecture.
-- The ram_block architecture attempts to used TWO dual-port memories.
-- If the dual-port memory supports a write and two read ports then
-- change all references of ram_rt to ram_rs so only one dual-port
-- memory will be created.
-- According to the Xilinx answers database record #4075 this architecture
-- may cause Synplify to infer a synchronous dual-port RAM using RAM16x1D.
-- For Altera use either a csdpram or lpm_ram_dq.
--------------------------------------------------------------------
architecture ram_block of reg_bank is
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
signal ram_rs : ram_type;
signal ram_rt : ram_type;
signal reg_status : std_logic;
 
attribute block_ram : boolean;
attribute block_ram of ram_rs : signal is TRUE;
attribute block_ram of ram_rt : signal is TRUE;
begin
 
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
reg_status)
variable rs, rt, rd : natural;
begin
 
rs := conv_integer(rs_index(4 downto 0));
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & reg_status;
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00110000"; --intr vector
when others =>
if rs_index = "101110" then --reg_epc CP0 14
rs := 0;
end if;
reg_source_out <= ram_rs(rs);
end case;
 
rt := conv_integer(rt_index(4 downto 0));
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= ram_rt(rt);
end case;
 
if rising_edge(clk) then
rd := conv_integer(rd_index(4 downto 0));
case rd_index is
when "000000" =>
when "101100" => reg_status <= reg_dest_new(0);
when others =>
if rd_index = "101110" then --reg_epc CP0 14
rd := 0;
reg_status <= '0'; --disable interrupts
end if;
ram_rs(rd) <= reg_dest_new;
ram_rt(rd) <= reg_dest_new;
end case;
end if;
 
intr_enable <= reg_status;
 
end process;
 
end; --architecture ram_block
 
--------------------------------------------------------------------
 
architecture logic of reg_bank is
signal reg31, reg01, reg02, reg03 : std_logic_vector(31 downto 0);
--For Altera simulations, comment out reg04 through reg30
122,7 → 190,7
end case;
 
if rising_edge(clk) then
-- assert reg_dest_new'last_event >= 10 ns
-- assert reg_dest_new'last_event >= 100 ps
-- report "Reg_dest timing error";
case rd_index is
when "000001" => reg01 <= reg_dest_new;
167,3 → 235,4
 
end; --architecture logic
 
 

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