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https://opencores.org/ocsvn/sdram_ctrl/sdram_ctrl/trunk
Subversion Repositories sdram_ctrl
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/tags/V10/syn/sdram_ctrl/cb_generator.pl
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/tags/V10/syn/sdram_ctrl/hdl/sdram_ctrl.vhd
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/tags/V10/syn/sdram_ctrl/class.ptf
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/tags/V10/test_bench/pll.vhd
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/tags/V10/test_bench/old/cpu_simulator_file_based.vhd
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/tags/V10/test_bench/old/Hello_LED_sdram_0.dat
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/tags/V10/test_bench/old/Count_Binary_sdram_0.dat
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/tags/V10/test_bench/old/nios.dat
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/tags/V10/test_bench/sdram_ctrl_tb.vhd
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/tags/V10/test_bench/mt48lc4m32b2.vhd
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/tags/V10/test_bench/cpu_simulator.vhd
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/tags/V10/doc/sdram_ctrl.sxw
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Index: tags/V10/src/sdram_ctrl.vhd
===================================================================
--- tags/V10/src/sdram_ctrl.vhd (revision 7)
+++ tags/V10/src/sdram_ctrl.vhd (nonexistent)
@@ -1,441 +0,0 @@
-------------------------------------------------------------------
---
--- sdram_ctrl.vhd
---
--- Module Description:
--- SDRAM small&fast controller
---
---
--- To Do:
--- multichipselect support
--- configurable times
--- nios simulation support
---
--- Author(s):
--- Aleksey Kuzmenok, ntpqa@opencores.org
---
-------------------------------------------------------------------
---
--- Copyright (C) 2006 Aleksey Kuzmenok and OPENCORES.ORG
---
--- This module is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This module is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this software; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
---
-------------------------------------------------------------------
--- Test results
--- FPGA SDRAM CLK (not less than)
--- EP1C12XXXXC8 MT48LC4M32B2TG-7:G 125 MHz
--- EP1C6XXXXC8 IS42S16100C1-7TL 125 MHz
---
-------------------------------------------------------------------
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity sdram_ctrl is
- generic(
- DATA_WIDTH: integer:=32;
- BANK_WIDTH: integer:=4;
- ROW_WIDTH: integer:=12;
- COLUMN_WIDTH: integer:=8;
-
- clk_MHz: integer:=120
- );
- port(
- signal clk : IN STD_LOGIC;
- signal reset : IN STD_LOGIC;
-
- -- IMPORTANT: for this Avalon(tm) interface
- -- 'Minimum Arbitration Shares'=1
- -- 'Max Pending Read Transactions'=9
- signal avs_nios_chipselect : IN STD_LOGIC;
- signal avs_nios_address : IN STD_LOGIC_VECTOR ((BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH-1) DOWNTO 0);
- signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0);
- signal avs_nios_writedata : IN STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal avs_nios_write : IN STD_LOGIC;
- signal avs_nios_read : IN STD_LOGIC;
- signal avs_nios_waitrequest : OUT STD_LOGIC;
- signal avs_nios_readdata : OUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal avs_nios_readdatavalid : OUT STD_LOGIC;
-
- -- global export signals
- signal sdram_cke : OUT STD_LOGIC; -- This pin has fixed state '1'
- signal sdram_ba : OUT STD_LOGIC_VECTOR ((BANK_WIDTH-1) DOWNTO 0);
- signal sdram_addr : OUT STD_LOGIC_VECTOR ((ROW_WIDTH-1) DOWNTO 0);
- signal sdram_cs_n : OUT STD_LOGIC; -- This pin has fixed state '0'
- signal sdram_ras_n : OUT STD_LOGIC;
- signal sdram_cas_n : OUT STD_LOGIC;
- signal sdram_we_n : OUT STD_LOGIC;
- signal sdram_dq : INOUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal sdram_dqm : OUT STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0)
- );
-end sdram_ctrl;
-
-architecture behaviour of sdram_ctrl is
-
- CONSTANT FIFO_WIDTH: integer:=BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
-
- CONSTANT MODE: std_logic_vector(11 downto 0):="000000110000"; -- 1 word burst, CAS latency=3
- -- Only two times are configurable
- -- tINIT delay between powerup and load mode register = 100 us
- -- tREF refresh period = 15.625 us (64ms/4096rows)
- CONSTANT INIT_PAUSE_CLOCKS: integer:=(clk_MHz*10000)/91; -- 109.9 us just to be on the save side
- CONSTANT REFRESH_PERIOD_CLOCKS: integer:=(clk_MHz*1000)/65; -- 15.384 us the same purpose
- CONSTANT CAS_LATENCY: integer:=3; -- other latencies weren't been tested!
-
- COMPONENT scfifo
- GENERIC (
- add_ram_output_register : STRING;
- intended_device_family : STRING;
- lpm_numwords : NATURAL;
- lpm_showahead : STRING;
- lpm_type : STRING;
- lpm_width : NATURAL;
- lpm_widthu : NATURAL;
- overflow_checking : STRING;
- underflow_checking : STRING;
- use_eab : STRING
- );
- PORT (
- rdreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
- wrreq : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
- full : OUT STD_LOGIC
- );
- END COMPONENT;
-
- -- If you ask me why there are so many states, I'll answer that all times are fixed.
- -- The top speed for MT48LC4M32B2TG-7:G is 7 ns, therefore all times were based on it.
- -- tRP PRECHARGE command period = 3 clocks
- -- tRFC AUTO REFRESH period = 10 clocks
- -- tMRD LOAD MODE REGISTER command to ACTIVE or REFRESH command = 2 clocks
- -- tRCD ACTIVE to READ or WRITE delay = 3 clocks
- -- tRAS ACTIVE to PRECHARGE command = 7 clocks
- -- tRC ACTIVE to ACTIVE command period = 10 clocks
- -- tWR2 Write recovery time = 2 clocks
- type states is (
- INIT0,INIT1,INIT2,INIT3,INIT4,INIT5,INIT6,INIT7,
- INIT8,INIT9,INIT10,INIT11,INIT12,INIT13,INIT14,INIT15,
- INIT16,INIT17,INIT18,INIT19,INIT20,INIT21,INIT22,INIT23,INIT24,
- REFRESH0,REFRESH1,REFRESH2,REFRESH3,REFRESH4,REFRESH5,REFRESH6,REFRESH7,
- REFRESH8,REFRESH9,REFRESH10,REFRESH11,REFRESH12,REFRESH13,REFRESH14,
- ACTIVE0,ACTIVE1,ACTIVE2,ACTIVE3,ACTIVE4,
- IDLE,READ0,WRITE0);
- signal operation: states;
-
- signal fifo_q: std_logic_vector((FIFO_WIDTH-1) downto 0);
-
- signal init_counter: unsigned(15 downto 0):=to_unsigned(INIT_PAUSE_CLOCKS,16);
- signal refresh_counter: unsigned(15 downto 0);
- signal active_counter: unsigned(2 downto 0);
- signal active_address: unsigned((BANK_WIDTH+ROW_WIDTH-1) downto 0);
-
- signal bank: std_logic_vector((sdram_ba'length-1) downto 0);
- signal row: std_logic_vector((sdram_addr'length-1) downto 0);
- signal column: std_logic_vector((COLUMN_WIDTH-1) downto 0);
- signal be: std_logic_vector((sdram_dqm'length-1) downto 0);
- signal data: std_logic_vector((sdram_dq'length-1) downto 0);
-
- signal do_init,do_refresh,do_active,read_is_active,ready,tRCD_not_expired: std_logic:='0';
-
- signal fifo_rdreq,fifo_empty: std_logic;
-
- signal read_latency: std_logic_vector(CAS_LATENCY downto 0);
-
- signal fifo_data: std_logic_vector((FIFO_WIDTH-1) downto 0);
- signal fifo_wrreq,fifo_wrfull: std_logic;
-
- signal i_command : STD_LOGIC_VECTOR(4 downto 0);
- CONSTANT NOP: STD_LOGIC_VECTOR(4 downto 0):="10111";
- CONSTANT ACTIVE: STD_LOGIC_VECTOR(4 downto 0):="10011";
- CONSTANT READ: STD_LOGIC_VECTOR(4 downto 0):="10101";
- CONSTANT WRITE: STD_LOGIC_VECTOR(4 downto 0):="10100";
- CONSTANT PRECHARGE: STD_LOGIC_VECTOR(4 downto 0):="10010";
- CONSTANT AUTO_REFRESH: STD_LOGIC_VECTOR(4 downto 0):="10001";
- CONSTANT LOAD_MODE_REGISTER: STD_LOGIC_VECTOR(4 downto 0):="10000";
-
- signal i_address : STD_LOGIC_VECTOR((sdram_addr'length-1) DOWNTO 0);
- signal i_bank : STD_LOGIC_VECTOR((sdram_ba'length-1) DOWNTO 0);
- signal i_dqm : STD_LOGIC_VECTOR((sdram_dqm'length-1) DOWNTO 0);
- signal i_data : STD_LOGIC_VECTOR((sdram_dq'length-1) DOWNTO 0);
- attribute ALTERA_ATTRIBUTE : string;
- attribute ALTERA_ATTRIBUTE of i_command : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_address : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_bank : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_data : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of avs_nios_readdata : signal is "FAST_INPUT_REGISTER=ON";
-begin
- (sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n) <= i_command;
- sdram_addr <= i_address;
- sdram_ba <= i_bank;
- sdram_dqm <= i_dqm;
- sdram_dq <= i_data;
-
- fifo_data<=avs_nios_address & avs_nios_writedata & avs_nios_byteenable & avs_nios_write & avs_nios_read;
- fifo_wrreq<=(avs_nios_write or avs_nios_read) and avs_nios_chipselect and not fifo_wrfull;
-
- avs_nios_waitrequest<=fifo_wrfull;
-
- fifo_rdreq<=not fifo_empty and not do_refresh and not do_active and not read_is_active and ready;
-
- do_active<='0' when active_address=unsigned((fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)))) else '1';
- read_is_active<='1' when read_latency(CAS_LATENCY-1 downto 0)>"000" and fifo_q(1)='1' else '0';
- ready<='1' when operation=IDLE or operation=READ0 or operation=WRITE0 else '0';
-
- operation_machine:process(reset,clk)
- begin
- if reset='1'
- then
- operation<=INIT0;
- active_address<=(others=>'1');
- elsif rising_edge(clk)
- then
-
- bank<=fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length));
- row<=fifo_q((fifo_q'length-bank'length-1) downto (fifo_q'length-bank'length-row'length));
- column<=fifo_q((column'length+data'length+be'length+2-1) downto (data'length+be'length+2));
- data<=fifo_q((data'length+be'length+2-1) downto (be'length+2));
- be<=fifo_q((be'length+2-1) downto 2);
-
- case operation is
- when INIT0=>
- if do_init='1'
- then operation<=INIT1;row(10)<='1';
- end if;
- when INIT1=>operation<=INIT2;
- when INIT2=>operation<=INIT3;
- when INIT3=>operation<=INIT4;
- when INIT4=>operation<=INIT5;
- when INIT5=>operation<=INIT6;
- when INIT6=>operation<=INIT7;
- when INIT7=>operation<=INIT8;
- when INIT8=>operation<=INIT9;
- when INIT9=>operation<=INIT10;
- when INIT10=>operation<=INIT11;
- when INIT11=>operation<=INIT12;
- when INIT12=>operation<=INIT13;
- when INIT13=>operation<=INIT14;
- when INIT14=>operation<=INIT15;
- when INIT15=>operation<=INIT16;
- when INIT16=>operation<=INIT17;
- when INIT17=>operation<=INIT18;
- when INIT18=>operation<=INIT19;
- when INIT19=>operation<=INIT20;
- when INIT20=>operation<=INIT21;
- when INIT21=>operation<=INIT22;
- when INIT22=>operation<=INIT23;
- when INIT23=>operation<=INIT24;row<=MODE((row'length-1) downto 0);
- when INIT24=>operation<=IDLE;
-
- when REFRESH0=>operation<=REFRESH1;
- when REFRESH1=>operation<=REFRESH2;
- when REFRESH2=>operation<=REFRESH3;
- when REFRESH3=>operation<=REFRESH4;
- when REFRESH4=>operation<=REFRESH5;
- when REFRESH5=>operation<=REFRESH6;
- when REFRESH6=>operation<=REFRESH7;
- when REFRESH7=>operation<=REFRESH8;
- when REFRESH8=>operation<=REFRESH9;
- when REFRESH9=>operation<=REFRESH10;
- when REFRESH10=>operation<=REFRESH11;
- when REFRESH11=>operation<=REFRESH12;
- when REFRESH12=>operation<=REFRESH13;
- active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
- when REFRESH13=>operation<=REFRESH14;
- when REFRESH14=>operation<=IDLE;
-
- when ACTIVE0=>operation<=ACTIVE1;
- when ACTIVE1=>operation<=ACTIVE2;
- when ACTIVE2=>operation<=ACTIVE3;
- active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
- when ACTIVE3=>operation<=ACTIVE4;
- when ACTIVE4=>operation<=IDLE;
-
- when others=>
- if do_refresh='1'
- then
- if tRCD_not_expired='0' and operation=IDLE
- then operation<=REFRESH0;row(10)<='1';
- else operation<=IDLE;
- end if;
- elsif do_active='1'
- then
- if tRCD_not_expired='0' and operation=IDLE
- then operation<=ACTIVE0;row(10)<='1';
- else operation<=IDLE;
- end if;
- elsif fifo_empty='1'
- then
- operation<=IDLE;
- elsif fifo_q(1)='1' --write
- then
- if read_latency(CAS_LATENCY-1 downto 0)>"000"
- then operation<=IDLE;
- else operation<=WRITE0;
- end if;
- elsif fifo_q(0)='1' --read
- then
- operation<=READ0;
- end if;
- end case;
- end if;
- end process;
-
- control_latency:process(reset,clk)
- begin
- if reset='1'
- then
- read_latency<=(others=>'0');
- elsif rising_edge(clk)
- then
- read_latency<=std_logic_vector(unsigned(read_latency) SLL 1);
- if operation=READ0
- then read_latency(0)<='1';
- else read_latency(0)<='0';
- end if;
- end if;
- end process;
- latch_readdata:process(reset,clk)
- begin
- if reset='1'
- then
- avs_nios_readdata<=(others=>'0');
- avs_nios_readdatavalid<='0';
- elsif rising_edge(clk)
- then
- avs_nios_readdata<=sdram_dq;
- avs_nios_readdatavalid<=read_latency(CAS_LATENCY);
- end if;
- end process;
- initialization:process(reset,clk)
- begin
- if rising_edge(clk)
- then
- if init_counter>0
- then
- init_counter<=init_counter-1;
- else do_init<='1';
- end if;
- end if;
- end process;
- refreshing:process(clk,reset)
- begin
- if reset='1'
- then
- refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
- do_refresh<='0';
- elsif rising_edge(clk)
- then
- if refresh_counter=to_unsigned(0,refresh_counter'length)
- then refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
- do_refresh<='1';
- else refresh_counter<=refresh_counter-1;
- end if;
- if operation=REFRESH0 or operation=REFRESH5
- then do_refresh<='0';
- end if;
- end if;
- end process;
- active_period:process(reset,clk)
- begin
- if reset='1'
- then
- active_counter<=(others=>'0');
- tRCD_not_expired<='0';
- elsif rising_edge(clk)
- then
- if operation=ACTIVE3 or operation=REFRESH13
- then active_counter<=to_unsigned(5,active_counter'length);
- elsif active_counter>0
- then active_counter<=active_counter-1;
- end if;
- end if;
- if active_counter>0
- then tRCD_not_expired<='1';
- else tRCD_not_expired<='0';
- end if;
- end process;
- latch_controls:process(clk,reset)
- begin
- if reset='1'
- then
- i_command<=NOP;
- i_address<=(others=>'0');
- i_bank<=(others=>'0');
- i_dqm<=(others=>'0');
- i_data<=(others=>'Z');
- elsif rising_edge(clk)
- then
- i_command<=NOP;
- i_bank<=bank;
- i_address<=(others=>'0');
- i_address((column'length-1) downto 0)<=column;
- i_data<=(others=>'Z');
- i_dqm<=(others=>'0');
-
- case operation is
- when INIT1|REFRESH0|ACTIVE0 =>
- i_command<=PRECHARGE;
- i_address<=row;
- when INIT4|INIT14|REFRESH3 =>
- i_command<=AUTO_REFRESH;
- when INIT24=>
- i_command<=LOAD_MODE_REGISTER;
- i_address<=row;
- when ACTIVE3|REFRESH13 =>
- i_command<=ACTIVE;
- i_address<=row;
- when READ0 =>
- i_command<=READ;
- when WRITE0 =>
- i_command<=WRITE;
- i_dqm<=not be;
- i_data<=data;
- when OTHERS =>
- end case;
- end if;
- end process;
-
- fifo: scfifo
- GENERIC MAP (
- add_ram_output_register => "ON",
- intended_device_family => "Cyclone",
- lpm_numwords => 4,
- lpm_showahead => "ON",
- lpm_type => "scfifo",
- lpm_width => FIFO_WIDTH,
- lpm_widthu => 2,
- overflow_checking => "ON",
- underflow_checking => "ON",
- use_eab => "ON"
- )
- PORT MAP (
- rdreq => fifo_rdreq,
- aclr => reset,
- clock => clk,
- wrreq => fifo_wrreq,
- data => fifo_data,
- empty => fifo_empty,
- q => fifo_q,
- full => fifo_wrfull
- );
-end behaviour;
Index: trunk/test_bench/mt48lc4m32b2.vhd
===================================================================
--- trunk/test_bench/mt48lc4m32b2.vhd (revision 7)
+++ trunk/test_bench/mt48lc4m32b2.vhd (nonexistent)
@@ -1,1134 +0,0 @@
------------------------------------------------------------------------------------------
---
--- File Name: MT48LC4M32B2.VHD
--- Version: 2.0
--- Date: January 24th, 2002
--- Model: Behavioral
--- Simulator: Model Technology
---
--- Dependencies: None
---
--- Email: modelsupport@micron.com
--- Company: Micron Technology, Inc.
--- Part Number: MT48LC4M32A2 (1Mb x 32 x 4 Banks)
---
--- Description: Micron 128Mb SDRAM
---
--- Limitation: - Doesn't check for 4096-cycle refresh
---
--- Note: - Set simulator resolution to "ps" accuracy
---
--- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
--- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
---
--- Copyright (c) 1998 Micron Semiconductor Products, Inc.
--- All rights researved
---
--- Rev Author Date Changes
--- --- -------------------------- -------------------------------------
--- 2.0 SH 01/24/2002 - Second Release
--- Micron Technology Inc.
---
---------------------------------------------------------------------------
-
-LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- USE IEEE.STD_LOGIC_ARITH.ALL;
-
-ENTITY mt48lc4m32b2 IS
- GENERIC (
- -- Timing Parameters for -75 (PC133) and CL = 3
- tAC : TIME := 5.4 ns;
- tHZ : TIME := 5.4 ns;
- tOH : TIME := 2.7 ns;
- tMRD : INTEGER := 2; -- 2 Clk Cycles
- tRAS : TIME := 44.0 ns;
- tRC : TIME := 66.0 ns;
- tRCD : TIME := 20.0 ns;
- tRFC : TIME := 66.0 ns;
- tRP : TIME := 20.0 ns;
- tRRD : TIME := 15.0 ns;
- tWRa : TIME := 7.5 ns; -- Auto precharge
- tWRm : TIME := 15.0 ns; -- Manual Precharge
-
- tAH : TIME := 0.8 ns;
- tAS : TIME := 1.5 ns;
- tCH : TIME := 2.5 ns;
- tCL : TIME := 2.5 ns;
- tCK : TIME := 7.5 ns;
- tDH : TIME := 0.8 ns;
- tDS : TIME := 1.5 ns;
- tCKH : TIME := 0.8 ns;
- tCKS : TIME := 1.5 ns;
- tCMH : TIME := 0.8 ns;
- tCMS : TIME := 1.5 ns;
-
- addr_bits : INTEGER := 12;
- data_bits : INTEGER := 32;
- col_bits : INTEGER := 8
- );
- PORT (
- Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
- Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
- Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- Clk : IN STD_LOGIC := '0';
- Cke : IN STD_LOGIC := '1';
- Cs_n : IN STD_LOGIC := '1';
- Ras_n : IN STD_LOGIC := '1';
- Cas_n : IN STD_LOGIC := '1';
- We_n : IN STD_LOGIC := '1';
- Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"
- );
-END mt48lc4m32b2;
-
-ARCHITECTURE behave OF mt48lc4m32b2 IS
- TYPE State IS (BST, NOP, PRECH, READ, WRITE);
- TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
- TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
- TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
- TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
- TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF STD_LOGIC_VECTOR (Col_bits - 1 DOWNTO 0);
- TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
- SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL Active_enable, Aref_enable, Burst_term : STD_LOGIC := '0';
- SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
- SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : STD_LOGIC := '0';
- SIGNAL Cas_latency_1, Cas_latency_2, Cas_latency_3 : STD_LOGIC := '0';
- SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
- SIGNAL Write_burst_mode : STD_LOGIC := '0';
- SIGNAL Sys_clk, CkeZ : STD_LOGIC := '0';
-
-BEGIN
- -- Strip the strength
- Cs_in <= To_X01 (Cs_n);
- Ras_in <= To_X01 (Ras_n);
- Cas_in <= To_X01 (Cas_n);
- We_in <= To_X01 (We_n);
-
- -- Commands Decode
- Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
- Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
- Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
- Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
- Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
- Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
- Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
-
- -- Burst Length Decode
- Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
- Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
- Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
- Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-
- -- CAS Latency Decode
- Cas_latency_1 <= NOT(Mode_reg(6)) AND NOT(Mode_reg(5)) AND Mode_reg(4);
- Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
- Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-
- -- Write Burst Mode
- Write_burst_mode <= Mode_reg(9);
-
- -- System Clock
- int_clk : PROCESS (Clk)
- BEGIN
- IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN
- CkeZ <= Cke;
- END IF;
- Sys_clk <= CkeZ AND Clk;
- END PROCESS;
-
- state_register : PROCESS
- TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
- TYPE ram_pntr IS ACCESS ram_type;
- TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
- VARIABLE Bank0 : ram_stor;
- VARIABLE Bank1 : ram_stor;
- VARIABLE Bank2 : ram_stor;
- VARIABLE Bank3 : ram_stor;
- VARIABLE Row_index, Col_index : INTEGER := 0;
- VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0');
-
- VARIABLE Col_addr : Array4xCBV;
- VARIABLE Bank_addr : Array4x2BV;
- VARIABLE Dqm_reg0, Dqm_reg1 : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
-
- VARIABLE Bank, Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
- VARIABLE Col_brst : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
- VARIABLE Row : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
- VARIABLE Col : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
- VARIABLE Burst_counter : INTEGER := 0;
-
- VARIABLE Command : Array_state;
- VARIABLE Bank_precharge : Array4x2BV;
- VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
- VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
- VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
- VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
- VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
- VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
- VARIABLE RW_interrupt_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- VARIABLE RW_interrupt_counter : Array4xI := (0 & 0 & 0 & 0);
- VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
-
- VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
- VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
- VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-
- -- Timing Check
- VARIABLE MRD_chk : INTEGER := 0;
- VARIABLE RFC_chk : TIME := 0 ns;
- VARIABLE RRD_chk : TIME := 0 ns;
- VARIABLE WR_chkm : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
- VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
- VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
- VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
- VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-
- -- Initialize empty rows
- PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR (1 DOWNTO 0); Row_index : INTEGER) IS
- VARIABLE i, j : INTEGER := 0;
- BEGIN
- IF Bank = "00" THEN
- IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
- Bank0 (Row_index) := NEW ram_type; -- Open new row for access
- FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank0 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "01" THEN
- IF Bank1 (Row_index) = NULL THEN
- Bank1 (Row_index) := NEW ram_type;
- FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank1 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "10" THEN
- IF Bank2 (Row_index) = NULL THEN
- Bank2 (Row_index) := NEW ram_type;
- FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank2 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "11" THEN
- IF Bank3 (Row_index) = NULL THEN
- Bank3 (Row_index) := NEW ram_type;
- FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank3 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- END IF;
- END;
-
- -- Burst Counter
- PROCEDURE Burst_decode IS
- VARIABLE Col_int : INTEGER := 0;
- VARIABLE Col_vec, Col_temp : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
- BEGIN
- -- Advance Burst Counter
- Burst_counter := Burst_counter + 1;
-
- -- Burst Type
- IF Mode_reg (3) = '0' THEN
- Col_int := conv_integer(Col) + 1;
- Col_temp := CONV_STD_LOGIC_VECTOR(Col_int, col_bits);
- ELSIF Mode_reg (3) = '1' THEN
- Col_vec := CONV_STD_LOGIC_VECTOR(Burst_counter, col_bits);
- Col_temp (2) := Col_vec (2) XOR Col_brst (2);
- Col_temp (1) := Col_vec (1) XOR Col_brst (1);
- Col_temp (0) := Col_vec (0) XOR Col_brst (0);
- END IF;
-
- -- Burst Length
- IF Burst_length_2 = '1' THEN
- Col (0) := Col_temp (0);
- ELSIF Burst_length_4 = '1' THEN
- Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
- ELSIF Burst_length_8 = '1' THEN
- Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
- ELSE
- Col := Col_temp;
- END IF;
-
- -- Burst Read Single Write
- IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
- Data_in_enable := '0';
- END IF;
-
- -- Data counter
- IF Burst_length_1 = '1' THEN
- IF Burst_counter >= 1 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- ELSIF Burst_length_2 = '1' THEN
- IF Burst_counter >= 2 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- ELSIF Burst_length_4 = '1' THEN
- IF Burst_counter >= 4 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- ELSIF Burst_length_8 = '1' THEN
- IF Burst_counter >= 8 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- END IF;
- END;
-
- BEGIN
- WAIT ON Sys_clk;
- IF Sys_clk'event AND Sys_clk = '1' THEN
- -- Internal Pipeline
- Command(0) := Command(1);
- Command(1) := Command(2);
- Command(2) := Command(3);
- Command(3) := NOP;
-
- Col_addr(0) := Col_addr(1);
- Col_addr(1) := Col_addr(2);
- Col_addr(2) := Col_addr(3);
- Col_addr(3) := (OTHERS => '0');
-
- Bank_addr(0) := Bank_addr(1);
- Bank_addr(1) := Bank_addr(2);
- Bank_addr(2) := Bank_addr(3);
- Bank_addr(3) := "00";
-
- Bank_precharge(0) := Bank_precharge(1);
- Bank_precharge(1) := Bank_precharge(2);
- Bank_precharge(2) := Bank_precharge(3);
- Bank_precharge(3) := "00";
-
- A10_precharge(0) := A10_precharge(1);
- A10_precharge(1) := A10_precharge(2);
- A10_precharge(2) := A10_precharge(3);
- A10_precharge(3) := '0';
-
- -- Dqm pipeline for Read
- Dqm_reg0 := Dqm_reg1;
- Dqm_reg1 := Dqm;
-
- -- Read or Write with Auto Precharge Counter
- IF Auto_precharge (0) = '1' THEN
- Count_precharge (0) := Count_precharge (0) + 1;
- END IF;
- IF Auto_precharge (1) = '1' THEN
- Count_precharge (1) := Count_precharge (1) + 1;
- END IF;
- IF Auto_precharge (2) = '1' THEN
- Count_precharge (2) := Count_precharge (2) + 1;
- END IF;
- IF Auto_precharge (3) = '1' THEN
- Count_precharge (3) := Count_precharge (3) + 1;
- END IF;
-
- -- Read or Write Interrupt Counter
- IF RW_interrupt_write (0) = '1' THEN
- RW_interrupt_counter (0) := RW_interrupt_counter (0) + 1;
- END IF;
- IF RW_interrupt_write (1) = '1' THEN
- RW_interrupt_counter (1) := RW_interrupt_counter (1) + 1;
- END IF;
- IF RW_interrupt_write (2) = '1' THEN
- RW_interrupt_counter (2) := RW_interrupt_counter (2) + 1;
- END IF;
- IF RW_interrupt_write (3) = '1' THEN
- RW_interrupt_counter (3) := RW_interrupt_counter (3) + 1;
- END IF;
-
- -- tMRD Counter
- MRD_chk := MRD_chk + 1;
-
- -- Auto Refresh
- IF Aref_enable = '1' THEN
- -- Auto Refresh to Auto Refresh
- ASSERT (NOW - RFC_chk >= tRFC)
- REPORT "tRFC violation during Auto Refresh"
- SEVERITY WARNING;
-
- -- Precharge to Auto Refresh
- ASSERT ((NOW - RP_chk0 >= tRP) OR (NOW - RP_chk1 >= tRP) OR
- (NOW - RP_chk2 >= tRP) OR (NOW - RP_chk3 >= tRP))
- REPORT "tRP violation during Auto Refresh"
- SEVERITY WARNING;
-
- -- Precharge to Auto Refresh
- ASSERT (Pc_b0 ='1' AND Pc_b1 = '1' AND Pc_b2 ='1' AND Pc_b3 = '1')
- REPORT "All banks must be Precharge before Auto Refresh"
- SEVERITY WARNING;
-
- -- Load Mode Register to Auto Refresh
- ASSERT (MRD_chk >= tMRD)
- REPORT "tMRD violation during Auto Refresh"
- SEVERITY WARNING;
-
- -- Record current tRFC time
- RFC_chk := NOW;
- END IF;
-
- -- Load Mode Register
- IF Mode_reg_enable = '1' THEN
- -- Register Mode
- Mode_reg <= Addr;
-
- -- Precharge to Load Mode Register
- ASSERT (Pc_b0 ='1' AND Pc_b1 = '1' AND Pc_b2 ='1' AND Pc_b3 = '1')
- REPORT "All banks must be Precharge before Load Mode Register"
- SEVERITY WARNING;
-
- -- Precharge to Load Mode Register
- ASSERT ((NOW - RP_chk0 >= tRP) OR (NOW - RP_chk1 >= tRP) OR
- (NOW - RP_chk2 >= tRP) OR (NOW - RP_chk3 >= tRP))
- REPORT "tRP violation during Load Mode Register"
- SEVERITY WARNING;
-
- -- Auto Refresh to Load Mode Register
- ASSERT (NOW - RFC_chk >= tRFC)
- REPORT "tRFC violation during Load Mode Register"
- SEVERITY WARNING;
-
- -- Load Mode Register to Load Mode Register
- ASSERT (MRD_chk >= tMRD)
- REPORT "tMRD violation during Load Mode Register"
- SEVERITY WARNING;
-
- -- Record current tMRD time
- MRD_chk := 0;
- END IF;
-
- -- Active Block (Latch Bank and Row Address)
- IF Active_enable = '1' THEN
- -- Activate an OPEN bank can corrupt data
- ASSERT ((Ba = "00" AND Act_b0 = '0') OR (Ba = "01" AND Act_b1 = '0') OR
- (Ba = "10" AND Act_b2 = '0') OR (Ba = "11" AND Act_b3 = '0'))
- REPORT "Bank is already activated - data can be corrupted"
- SEVERITY WARNING;
-
- -- Activate Bank 0
- IF Ba = "00" AND Pc_b0 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk0 >= tRC)
- REPORT "tRC violation during Activate Bank 0"
- SEVERITY WARNING;
-
- -- Precharge to Activate
- ASSERT (NOW - RP_chk0 >= tRP)
- REPORT "tRP violation during Activate Bank 0"
- SEVERITY WARNING;
-
- -- Record variables for checking violation
- Act_b0 := '1';
- Pc_b0 := '0';
- B0_row_addr := Addr;
- RAS_chk0 := NOW;
- RC_chk0 := NOW;
- RCD_chk0 := NOW;
- END IF;
-
- -- Activate Bank 1
- IF Ba = "01" AND Pc_b1 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk1 >= tRC)
- REPORT "tRC violation during Activate Bank 1"
- SEVERITY WARNING;
-
- -- Precharge to Activate
- ASSERT (NOW - RP_chk1 >= tRP)
- REPORT "tRP violation during Activate Bank 1"
- SEVERITY WARNING;
-
- -- Record variables for checking violation
- Act_b1 := '1';
- Pc_b1 := '0';
- B1_row_addr := Addr;
- RAS_chk1 := NOW;
- RC_chk1 := NOW;
- RCD_chk1 := NOW;
- END IF;
-
- -- Activate Bank 2
- IF Ba = "10" AND Pc_b2 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk2 >= tRC)
- REPORT "tRC violation during Activate Bank 2"
- SEVERITY WARNING;
-
- -- Precharge to Activate
- ASSERT (NOW - RP_chk2 >= tRP)
- REPORT "tRP violation during Activate Bank 2"
- SEVERITY WARNING;
-
- -- Record variables for checking violation
- Act_b2 := '1';
- Pc_b2 := '0';
- B2_row_addr := Addr;
- RAS_chk2 := NOW;
- RC_chk2 := NOW;
- RCD_chk2 := NOW;
- END IF;
-
- -- Activate Bank 3
- IF Ba = "11" AND Pc_b3 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk3 >= tRC)
- REPORT "tRC violation during Activate Bank 3"
- SEVERITY WARNING;
-
- -- Precharge to Activate
- ASSERT (NOW - RP_chk3 >= tRP)
- REPORT "tRP violation during Activate Bank 3"
- SEVERITY WARNING;
-
- -- Record variables for checking violation
- Act_b3 := '1';
- Pc_b3 := '0';
- B3_row_addr := Addr;
- RAS_chk3 := NOW;
- RC_chk3 := NOW;
- RCD_chk3 := NOW;
- END IF;
-
- -- Activate to Activate (different bank)
- IF (Prev_bank /= Ba) THEN
- ASSERT (NOW - RRD_chk >= tRRD)
- REPORT "tRRD violation during Activate"
- SEVERITY WARNING;
- END IF;
-
- -- Auto Refresh to Activate
- ASSERT (NOW - RFC_chk >= tRFC)
- REPORT "tRFC violation during Activate"
- SEVERITY WARNING;
-
- -- Load Mode Register to Activate
- ASSERT (MRD_chk >= tMRD)
- REPORT "tMRD violation during Activate"
- SEVERITY WARNING;
-
- -- Record variable for checking violation
- RRD_chk := NOW;
- Prev_Bank := Ba;
- END IF;
-
- -- Precharge Block
- IF Prech_enable = '1' THEN
- -- Load Mode Register to Precharge
- ASSERT (MRD_chk >= tMRD)
- REPORT "tMRD violation during Precharge"
- SEVERITY WARNING;
-
- -- Precharge Bank 0
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
- Act_b0 := '0';
- Pc_b0 := '1';
- RP_chk0 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk0 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chkm(0) >= tWRm)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 1
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
- Act_b1 := '0';
- Pc_b1 := '1';
- RP_chk1 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk1 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chkm(1) >= tWRm)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 2
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
- Act_b2 := '0';
- Pc_b2 := '1';
- RP_chk2 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk2 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chkm(2) >= tWRm)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 3
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
- Act_b3 := '0';
- Pc_b3 := '1';
- RP_chk3 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk3 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chkm(3) >= tWRm)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Terminate a Write Immediately (if same bank or all banks)
- IF (Data_in_enable = '1' AND (Bank = Ba OR Addr(10) = '1')) THEN
- Data_in_enable := '0';
- END IF;
-
- -- Precharge Command Pipeline for READ
- IF CAS_latency_3 = '1' THEN
- Command(2) := PRECH;
- Bank_precharge(2) := Ba;
- A10_precharge(2) := Addr(10);
- ELSIF CAS_latency_2 = '1' THEN
- Command(1) := PRECH;
- Bank_precharge(1) := Ba;
- A10_precharge(1) := Addr(10);
- END IF;
- END IF;
-
- -- Burst Terminate
- IF Burst_term = '1' THEN
- -- Terminate a Write immediately
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- END IF;
-
- -- Terminate a Read depend on CAS Latency
- IF CAS_latency_3 = '1' THEN
- Command(2) := BST;
- ELSIF CAS_latency_2 = '1' THEN
- Command(1) := BST;
- END IF;
- END IF;
-
- -- Read Command
- IF Read_enable = '1' THEN
- -- Activate to Read
- ASSERT ((Ba="00" AND Act_b0='1') OR (Ba="01" AND Act_b1='1') OR
- (Ba="10" AND Act_b2='1') OR (Ba="11" AND Act_b3='1'))
- REPORT "Bank is not Activated for Read"
- SEVERITY WARNING;
-
- -- Activate to Read
- ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
- (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
- (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
- (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
- REPORT "tRCD violation during Read"
- SEVERITY WARNING;
-
- -- CAS Latency Pipeline
- IF Cas_latency_3 = '1' THEN
- Command(2) := READ;
- Col_addr (2) := Addr(col_bits - 1 DOWNTO 0);
- Bank_addr (2) := Ba;
- ELSIF Cas_latency_2 = '1' THEN
- Command(1) := READ;
- Col_addr (1) := Addr(col_bits - 1 DOWNTO 0);
- Bank_addr (1) := Ba;
- ELSIF Cas_latency_1 = '1' THEN
- Command(0) := READ;
- Col_addr (0) := Addr(col_bits - 1 DOWNTO 0);
- Bank_addr (0) := Ba;
- END IF;
-
- -- Read Terminate Write Immediately
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- -- Interrupt a Write with Auto Precharge
- IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN
- RW_interrupt_write(CONV_INTEGER(RW_Interrupt_Bank)) := '1';
- RW_interrupt_counter (CONV_INTEGER(RW_Interrupt_Bank)) := 0;
- ASSERT FALSE REPORT "Read interrupt a Write with Auto Precharge." SEVERITY NOTE;
- END IF;
- END IF;
-
- -- Read Terminate Read after CL - 1
- IF (Data_out_enable = '1' AND ((Cas_latency_2 = '1' AND ((Burst_length_2 = '1' AND Burst_counter < 1) OR
- (Burst_length_4 = '1' AND Burst_counter < 3) OR
- (Burst_length_8 = '1' AND Burst_counter < 7))) OR
- (Cas_latency_3 = '1' AND ((Burst_length_4 = '1' AND Burst_counter < 2) OR
- (Burst_length_8 = '1' AND Burst_counter < 6))))) THEN
- -- Interrupt a Read with Auto Precharge
- IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN
- RW_interrupt_read(CONV_INTEGER(RW_Interrupt_Bank)) := '1';
- ASSERT FALSE REPORT "Read interrupt a Read with Auto Precharge." SEVERITY NOTE;
- END IF;
- END IF;
-
- -- Auto Precharge
- IF Addr(10) = '1' THEN
- Auto_precharge (CONV_INTEGER(Ba)) := '1';
- Count_precharge (CONV_INTEGER(Ba)) := 0;
- RW_Interrupt_Bank := Ba;
- Read_precharge (CONV_INTEGER(Ba)) := '1';
- END IF;
- END IF;
-
- -- Write Command
- IF Write_enable = '1' THEN
- -- Activate to Write
- ASSERT ((Ba="00" AND Act_b0='1') OR (Ba="01" AND Act_b1='1') OR
- (Ba="10" AND Act_b2='1') OR (Ba="11" AND Act_b3='1'))
- REPORT "Bank is not Activated for Write"
- SEVERITY WARNING;
-
- -- Activate to Write
- ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
- (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
- (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
- (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
- REPORT "tRCD violation during Write"
- SEVERITY WARNING;
-
- -- Latch write command, bank, column
- Command(0) := WRITE;
- Col_addr (0) := Addr(col_bits - 1 DOWNTO 0);
- Bank_addr (0) := Ba;
-
- -- Write Terminate Write Immediately
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
-
- -- Interrupt a Write with Auto Precharge
- IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN
- RW_interrupt_write(CONV_INTEGER(RW_Interrupt_Bank)) := '1';
- RW_interrupt_counter (CONV_INTEGER(RW_Interrupt_Bank)) := 0;
- ASSERT FALSE REPORT "Write interrupt a Write with Auto Precharge." SEVERITY NOTE;
- END IF;
- END IF;
-
- -- Write Terminate Read Immediately
- IF Data_out_enable = '1' THEN
- Data_out_enable := '0';
-
- -- Interrupt a Read with Auto Precharge
- IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN
- RW_interrupt_read(CONV_INTEGER(RW_Interrupt_Bank)) := '1';
- ASSERT FALSE REPORT "Write interrupt a Read with Auto Precharge." SEVERITY NOTE;
- END IF;
- END IF;
-
- -- Auto Precharge
- IF Addr(10) = '1' THEN
- Auto_precharge (CONV_INTEGER(Ba)) := '1';
- Count_precharge (CONV_INTEGER(Ba)) := 0;
- RW_Interrupt_Bank := Ba;
- Write_precharge (CONV_INTEGER(Ba)) := '1';
- END IF;
- END IF;
-
- -- Write with AutoPrecharge Calculation
- -- The device start internal precharge when:
- -- 1. Meet tRAS requirement
- -- and 2. tWR cycle(s) after last valid data
- -- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
- --
- -- Note: Model is starting the internal precharge 1 cycle after they meet all the
- -- requirement but tRP will be compensate for the time after the 1 cycle.
- IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
- IF (((NOW - RAS_chk0 >= tRAS) AND
- (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1) OR
- (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
- (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
- (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
- (RW_interrupt_write(0) = '1' AND RW_interrupt_counter(0) >= 1)) THEN
- Auto_precharge(0) := '0';
- Write_precharge(0) := '0';
- RW_interrupt_write(0) := '0';
- Pc_b0 := '1';
- Act_b0 := '0';
- RP_chk0 := NOW + tWRa;
- END IF;
- END IF;
- IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
- IF (((NOW - RAS_chk1 >= tRAS) AND
- (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1) OR
- (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
- (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
- (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
- (RW_interrupt_write(1) = '1' AND RW_interrupt_counter(1) >= 1)) THEN
- Auto_precharge(1) := '0';
- Write_precharge(1) := '0';
- RW_interrupt_write(1) := '0';
- Pc_b1 := '1';
- Act_b1 := '0';
- RP_chk1 := NOW + tWRa;
- END IF;
- END IF;
- IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
- IF (((NOW - RAS_chk2 >= tRAS) AND
- (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1) OR
- (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
- (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
- (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
- (RW_interrupt_write(2) = '1' AND RW_interrupt_counter(2) >= 1)) THEN
- Auto_precharge(2) := '0';
- Write_precharge(2) := '0';
- RW_interrupt_write(2) := '0';
- Pc_b2 := '1';
- Act_b2 := '0';
- RP_chk2 := NOW + tWRa;
- END IF;
- END IF;
- IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
- IF (((NOW - RAS_chk3 >= tRAS) AND
- (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1) OR
- (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
- (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
- (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
- (RW_interrupt_write(0) = '1' AND RW_interrupt_counter(3) >= 1)) THEN
- Auto_precharge(3) := '0';
- Write_precharge(3) := '0';
- RW_interrupt_write(3) := '0';
- Pc_b3 := '1';
- Act_b3 := '0';
- RP_chk3 := NOW + tWRa;
- END IF;
- END IF;
-
- -- Read with AutoPrecharge Calculation
- -- The device start internal precharge when:
- -- 1. Meet minimum tRAS requirement
- -- and 2. CL - 1 cycle(s) before last valid data
- -- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
- IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
- IF (((NOW - RAS_chk0 >= tRAS) AND
- ((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
- (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
- (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
- (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
- (RW_interrupt_read(0) = '1')) THEN
- Pc_b0 := '1';
- Act_b0 := '0';
- RP_chk0 := NOW;
- Auto_precharge(0) := '0';
- Read_precharge(0) := '0';
- RW_interrupt_read(0) := '0';
- END IF;
- END IF;
- IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
- IF (((NOW - RAS_chk1 >= tRAS) AND
- ((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
- (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
- (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
- (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
- (RW_interrupt_read(1) = '1')) THEN
- Pc_b1 := '1';
- Act_b1 := '0';
- RP_chk1 := NOW;
- Auto_precharge(1) := '0';
- Read_precharge(1) := '0';
- RW_interrupt_read(1) := '0';
- END IF;
- END IF;
- IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
- IF (((NOW - RAS_chk2 >= tRAS) AND
- ((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
- (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
- (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
- (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
- (RW_interrupt_read(2) = '1')) THEN
- Pc_b2 := '1';
- Act_b2 := '0';
- RP_chk2 := NOW;
- Auto_precharge(2) := '0';
- Read_precharge(2) := '0';
- RW_interrupt_read(2) := '0';
- END IF;
- END IF;
- IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
- IF (((NOW - RAS_chk3 >= tRAS) AND
- ((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
- (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
- (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
- (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
- (RW_interrupt_read(3) = '1')) THEN
- Pc_b3 := '1';
- Act_b3 := '0';
- RP_chk3 := NOW;
- Auto_precharge(3) := '0';
- Read_precharge(3) := '0';
- RW_interrupt_read(3) := '0';
- END IF;
- END IF;
-
- -- Internal Precharge or Bst
- IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
- IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
- IF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
- IF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
-
- IF Data_out_enable = '0' THEN
- Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
- END IF;
-
- -- Detect Read or Write Command
- IF Command(0) = READ THEN
- Bank := Bank_addr (0);
- Col := Col_addr (0);
- Col_brst := Col_addr (0);
- IF Bank_addr (0) = "00" THEN
- Row := B0_row_addr;
- ELSIF Bank_addr (0) = "01" THEN
- Row := B1_row_addr;
- ELSIF Bank_addr (0) = "10" THEN
- Row := B2_row_addr;
- ELSE
- Row := B3_row_addr;
- END IF;
- Burst_counter := 0;
- Data_in_enable := '0';
- Data_out_enable := '1';
- ELSIF Command(0) = WRITE THEN
- Bank := Bank_addr(0);
- Col := Col_addr(0);
- Col_brst := Col_addr(0);
- IF Bank_addr (0) = "00" THEN
- Row := B0_row_addr;
- ELSIF Bank_addr (0) = "01" THEN
- Row := B1_row_addr;
- ELSIF Bank_addr (0) = "10" THEN
- Row := B2_row_addr;
- ELSE
- Row := B3_row_addr;
- END IF;
- Burst_counter := 0;
- Data_in_enable := '1';
- Data_out_enable := '0';
- END IF;
-
- -- DQ (Driver / Receiver)
- Row_index := CONV_INTEGER (Row);
- Col_index := CONV_INTEGER (Col);
-
- IF Data_in_enable = '1' THEN
- IF Dqm /= "1111" THEN
- -- Initialize Memory
- Init_mem (Bank, Row_index);
-
- -- Array Buffer
- CASE Bank IS
- WHEN "00" => Dq_temp := Bank0 (Row_index) (Col_index);
- WHEN "01" => Dq_temp := Bank1 (Row_index) (Col_index);
- WHEN "10" => Dq_temp := Bank2 (Row_index) (Col_index);
- WHEN OTHERS => Dq_temp := Bank3 (Row_index) (Col_index);
- END CASE;
-
- -- Dqm Operation
- IF Dqm (0) = '0' THEN
- Dq_temp ( 7 DOWNTO 0) := Dq ( 7 DOWNTO 0);
- END IF;
- IF Dqm (1) = '0' THEN
- Dq_temp (15 DOWNTO 8) := Dq (15 DOWNTO 8);
- END IF;
- IF Dqm (2) = '0' THEN
- Dq_temp (23 DOWNTO 16) := Dq (23 DOWNTO 16);
- END IF;
- IF Dqm (3) = '0' THEN
- Dq_temp (31 DOWNTO 24) := Dq (31 DOWNTO 24);
- END IF;
-
- -- Write to Memory
- CASE Bank IS
- WHEN "00" => Bank0 (Row_index) (Col_index) := Dq_temp;
- WHEN "01" => Bank1 (Row_index) (Col_index) := Dq_temp;
- WHEN "10" => Bank2 (Row_index) (Col_index) := Dq_temp;
- WHEN OTHERS => Bank3 (Row_index) (Col_index) := Dq_temp;
- END CASE;
-
- -- Record tWR for manual precharge
- WR_chkm(CONV_INTEGER(Bank)) := NOW;
- END IF;
-
- -- Advance Burst Counter
- Burst_decode;
-
- ELSIF Data_out_enable = '1' THEN
- IF Dqm_reg0 /= "1111" THEN
- -- Initialize Memory
- Init_mem (Bank, Row_index);
-
- -- Array Buffer
- CASE Bank IS
- WHEN "00" => Dq_temp := Bank0 (Row_index) (Col_index);
- WHEN "01" => Dq_temp := Bank1 (Row_index) (Col_index);
- WHEN "10" => Dq_temp := Bank2 (Row_index) (Col_index);
- WHEN OTHERS => Dq_temp := Bank3 (Row_index) (Col_index);
- END CASE;
-
- -- Dqm Operation
- IF Dqm_reg0 (0) = '1' THEN
- Dq_temp ( 7 DOWNTO 0) := (OTHERS => 'Z');
- END IF;
- IF Dqm_reg0 (1) = '1' THEN
- Dq_temp (15 DOWNTO 8) := (OTHERS => 'Z');
- END IF;
- IF Dqm_reg0 (2) = '1' THEN
- Dq_temp (23 DOWNTO 16) := (OTHERS => 'Z');
- END IF;
- IF Dqm_reg0 (3) = '1' THEN
- Dq_temp (31 DOWNTO 24) := (OTHERS => 'Z');
- END IF;
-
- -- Output
- Dq <= TRANSPORT Dq_temp AFTER tAC;
- ELSE
- Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
- END IF;
-
- -- Advance Burst Counter
- Burst_decode;
- END IF;
- END IF;
-
- END PROCESS;
-
- -- Clock timing checks
- Clock_check : PROCESS
- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
- BEGIN
- WAIT ON Clk;
- IF (Clk = '1' AND NOW >= 10 ns) THEN
- ASSERT (NOW - Clk_low >= tCL)
- REPORT "tCL violation"
- SEVERITY WARNING;
- ASSERT (NOW - Clk_high >= tCK)
- REPORT "tCK violation"
- SEVERITY WARNING;
- Clk_high := NOW;
- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
- ASSERT (NOW - Clk_high >= tCH)
- REPORT "tCH violation"
- SEVERITY WARNING;
- Clk_low := NOW;
- END IF;
- END PROCESS;
-
- -- Setup timing checks
- Setup_check : PROCESS
- BEGIN
- WAIT ON Clk;
- IF Clk = '1' THEN
- ASSERT(Cke'LAST_EVENT >= tCKS)
- REPORT "CKE Setup time violation -- tCKS"
- SEVERITY WARNING;
- ASSERT(Cs_n'LAST_EVENT >= tCMS)
- REPORT "CS# Setup time violation -- tCMS"
- SEVERITY WARNING;
- ASSERT(Cas_n'LAST_EVENT >= tCMS)
- REPORT "CAS# Setup time violation -- tCMS"
- SEVERITY WARNING;
- ASSERT(Ras_n'LAST_EVENT >= tCMS)
- REPORT "RAS# Setup time violation -- tCMS"
- SEVERITY WARNING;
- ASSERT(We_n'LAST_EVENT >= tCMS)
- REPORT "WE# Setup time violation -- tCMS"
- SEVERITY WARNING;
- ASSERT(Dqm'LAST_EVENT >= tCMS)
- REPORT "Dqm Setup time violation -- tCMS"
- SEVERITY WARNING;
- ASSERT(Addr'LAST_EVENT >= tAS)
- REPORT "ADDR Setup time violation -- tAS"
- SEVERITY WARNING;
- ASSERT(Ba'LAST_EVENT >= tAS)
- REPORT "BA Setup time violation -- tAS"
- SEVERITY WARNING;
- ASSERT(Dq'LAST_EVENT >= tDS)
- REPORT "Dq Setup time violation -- tDS"
- SEVERITY WARNING;
- END IF;
- END PROCESS;
-
- -- Hold timing checks
- Hold_check : PROCESS
- BEGIN
- WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
- IF Clk'DELAYED (tCKH) = '1' THEN
- ASSERT(Cke'LAST_EVENT > tCKH)
- REPORT "CKE Hold time violation -- tCKH"
- SEVERITY WARNING;
- END IF;
- IF Clk'DELAYED (tCMH) = '1' THEN
- ASSERT(Cs_n'LAST_EVENT > tCMH)
- REPORT "CS# Hold time violation -- tCMH"
- SEVERITY WARNING;
- ASSERT(Cas_n'LAST_EVENT > tCMH)
- REPORT "CAS# Hold time violation -- tCMH"
- SEVERITY WARNING;
- ASSERT(Ras_n'LAST_EVENT > tCMH)
- REPORT "RAS# Hold time violation -- tCMH"
- SEVERITY WARNING;
- ASSERT(We_n'LAST_EVENT > tCMH)
- REPORT "WE# Hold time violation -- tCMH"
- SEVERITY WARNING;
- ASSERT(Dqm'LAST_EVENT > tCMH)
- REPORT "Dqm Hold time violation -- tCMH"
- SEVERITY WARNING;
- END IF;
- IF Clk'DELAYED (tAH) = '1' THEN
- ASSERT(Addr'LAST_EVENT > tAH)
- REPORT "ADDR Hold time violation -- tAH"
- SEVERITY WARNING;
- ASSERT(Ba'LAST_EVENT > tAH)
- REPORT "BA Hold time violation -- tAH"
- SEVERITY WARNING;
- END IF;
- IF Clk'DELAYED (tDH) = '1' THEN
- ASSERT(Dq'LAST_EVENT > tDH)
- REPORT "Dq Hold time violation -- tDH"
- SEVERITY WARNING;
- END IF;
- END PROCESS;
-
-END behave;
Index: trunk/test_bench/cpu_simulator.vhd
===================================================================
--- trunk/test_bench/cpu_simulator.vhd (revision 7)
+++ trunk/test_bench/cpu_simulator.vhd (nonexistent)
@@ -1,72 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY cpu_simulator IS
- PORT(clk, reset: in std_logic;
-
- address : out std_logic_vector(21 downto 0);
- writedata : out std_logic_vector(31 downto 0);
- byteenable : out std_logic_vector(3 downto 0);
- write : out std_logic;
- read : out std_logic;
- readdata : in std_logic_vector(31 downto 0);
- waitrequest : in std_logic;
- readdatavalid : in std_logic
- );
-END cpu_simulator;
-
-ARCHITECTURE behaviour OF cpu_simulator IS
- signal counter: unsigned(3 downto 0);
- type vector is
- record
- address: integer;
- writedata: integer;
- byteenable: std_logic_vector(3 downto 0);
- write: std_logic;
- read: std_logic;
- end record;
- type script is array(0 to (2**counter'length)-1) of vector;
- signal wave_form: script:=(
- (0,0,"1111",'1','0'),
- (1,1,"1111",'1','0'),
- (2,2,"1111",'1','0'),
- (3,3,"1111",'1','0'),
- (1024,1024,"1111",'0','1'),
- (1025,1025,"1111",'0','1'),
- (1026,1026,"1111",'0','1'),
- (1027,1027,"1111",'0','1'),
- (1024,1024,"1111",'1','0'),
- (1025,1025,"1111",'1','0'),
- (1026,1026,"1111",'1','0'),
- (1027,1027,"1111",'1','0'),
- (0,0,"1111",'0','1'),
- (1,1,"1111",'0','1'),
- (2,2,"1111",'0','1'),
- (3,3,"1111",'0','1')
- );
-BEGIN
- process(clk,reset)
- begin
- if reset='1'
- then
- counter<=(others=>'0');
- address<=(others=>'0');
- writedata<=(others=>'0');
- byteenable<=(others=>'0');
- write<='0';
- read<='0';
- elsif rising_edge(clk)
- then
- if waitrequest='0'
- then
- counter<=counter+1;
- address<=std_logic_vector(to_unsigned(wave_form(to_integer(counter)).address,address'length));
- writedata<=std_logic_vector(to_unsigned(wave_form(to_integer(counter)).writedata,writedata'length));
- byteenable<=wave_form(to_integer(counter)).byteenable;
- write<=wave_form(to_integer(counter)).write;
- read<=wave_form(to_integer(counter)).read;
- end if;
- end if;
- end process;
-END behaviour;
\ No newline at end of file
Index: trunk/test_bench/pll.vhd
===================================================================
--- trunk/test_bench/pll.vhd (revision 7)
+++ trunk/test_bench/pll.vhd (nonexistent)
@@ -1,256 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- altpll
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 5.1 Build 213 01/19/2006 SP 1 SJ Full Version
--- ************************************************************
-
-
---Copyright (C) 1991-2006 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY pll IS
- PORT
- (
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- e0 : OUT STD_LOGIC ;
- locked : OUT STD_LOGIC
- );
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
- SIGNAL sub_wire1 : STD_LOGIC ;
- SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
- SIGNAL sub_wire4 : STD_LOGIC ;
- SIGNAL sub_wire5 : STD_LOGIC ;
- SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
- SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
- SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
- COMPONENT altpll
- GENERIC (
- clk0_divide_by : NATURAL;
- clk0_duty_cycle : NATURAL;
- clk0_multiply_by : NATURAL;
- clk0_phase_shift : STRING;
- compensate_clock : STRING;
- extclk0_divide_by : NATURAL;
- extclk0_duty_cycle : NATURAL;
- extclk0_multiply_by : NATURAL;
- extclk0_phase_shift : STRING;
- inclk0_input_frequency : NATURAL;
- intended_device_family : STRING;
- invalid_lock_multiplier : NATURAL;
- lpm_type : STRING;
- operation_mode : STRING;
- pll_type : STRING;
- valid_lock_multiplier : NATURAL
- );
- PORT (
- extclk : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
- inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- locked : OUT STD_LOGIC ;
- clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
- );
- END COMPONENT;
-
-BEGIN
- sub_wire7_bv(0 DOWNTO 0) <= "0";
- sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
- sub_wire1 <= sub_wire0(0);
- c0 <= sub_wire1;
- locked <= sub_wire2;
- sub_wire4 <= sub_wire3(0);
- e0 <= sub_wire4;
- sub_wire5 <= inclk0;
- sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
- altpll_component : altpll
- GENERIC MAP (
- clk0_divide_by => 2,
- clk0_duty_cycle => 50,
- clk0_multiply_by => 11,
- clk0_phase_shift => "0",
- compensate_clock => "CLK0",
- extclk0_divide_by => 2,
- extclk0_duty_cycle => 50,
- extclk0_multiply_by => 11,
- extclk0_phase_shift => "5682",
- inclk0_input_frequency => 41666,
- intended_device_family => "Cyclone",
- invalid_lock_multiplier => 5,
- lpm_type => "altpll",
- operation_mode => "NORMAL",
- pll_type => "AUTO",
- valid_lock_multiplier => 1
- )
- PORT MAP (
- inclk => sub_wire6,
- clk => sub_wire0,
- locked => sub_wire2,
- extclk => sub_wire3
- );
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
--- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "1"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "504.000"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "deg"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "132.000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK6 STRING "0"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK6 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA6 STRING "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: EXTCLK0_DIVIDE_BY NUMERIC "2"
--- Retrieval info: CONSTANT: EXTCLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: EXTCLK0_MULTIPLY_BY NUMERIC "11"
--- Retrieval info: CONSTANT: EXTCLK0_PHASE_SHIFT STRING "5682"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
--- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
--- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
--- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
--- Retrieval info: USED_PORT: e0 0 0 0 0 OUTPUT VCC "e0"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: e0 0 0 0 0 @extclk 0 0 1 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE
Index: trunk/test_bench/old/nios.dat
===================================================================
--- trunk/test_bench/old/nios.dat (revision 7)
+++ trunk/test_bench/old/nios.dat (nonexistent)
@@ -1 +0,0 @@
- ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ
\ No newline at end of file
Index: trunk/test_bench/old/cpu_simulator_file_based.vhd
===================================================================
--- trunk/test_bench/old/cpu_simulator_file_based.vhd (revision 7)
+++ trunk/test_bench/old/cpu_simulator_file_based.vhd (nonexistent)
@@ -1,79 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY cpu_simulator IS
- PORT(clk, reset: in std_logic;
-
- address : out std_logic_vector(21 downto 0);
- writedata : out std_logic_vector(31 downto 0);
- byteenable : out std_logic_vector(3 downto 0);
- write : out std_logic;
- read : out std_logic;
- readdata : in std_logic_vector(31 downto 0);
- waitrequest : in std_logic;
- readdatavalid : in std_logic
- );
-END cpu_simulator;
-
-ARCHITECTURE behaviour OF cpu_simulator IS
- signal address: std_logic_vector(21 downto 0);
- signal writedata: std_logic_vector(31 downto 0);
- signal byteenable: std_logic_vector(3 downto 0);
- signal write: std_logic;
- signal read: std_logic;
-
-BEGIN
- process(clk,reset)
- variable service: std_logic_vector(7 downto 0);
- variable b0,b1,b2,b3,b4,b5,b6,b7: BYTE;
- begin
- if reset='1'
- then
- file_close(NIOS);
- file_open(NIOS, FILES_PATH&"nios.dat", READ_MODE);
- elsif rising_edge(clk)
- then
- if waitrequest='0'
- then
- if Endfile(NIOS)
- then
- file_close(NIOS);
- file_open(NIOS, FILES_PATH&"nios.dat", READ_MODE);
- else
- Read(NIOS,b0);
- Read(NIOS,b1);
- Read(NIOS,b2);
- Read(NIOS,b3);
- Read(NIOS,b4);
- Read(NIOS,b5);
- Read(NIOS,b6);
- Read(NIOS,b7);
- service:=char2std_logic_vector(b0);
- address<=service(5 downto 0)&char2std_logic_vector(b1)&char2std_logic_vector(b2);
- writedata<=char2std_logic_vector(b3)&char2std_logic_vector(b4)&char2std_logic_vector(b5)&char2std_logic_vector(b6);
- service:=char2std_logic_vector(b7);
- byteenable<=not service(7 downto 4);
- write<=service(3);
- read<=service(2);
- end if;
- end if;
- end if;
- end process;
-
- process(clk,reset)
- begin
- if reset='1'
- then
- readed<=(others=>'0');
- new_data<='0';
- elsif rising_edge(clk)
- then
- new_data<=readdatavalid;
- if readdatavalid='1'
- then
- readed<=readdata;
- end if;
- end if;
- end process;
-END behaviour;
\ No newline at end of file
Index: trunk/test_bench/old/Hello_LED_sdram_0.dat
===================================================================
--- trunk/test_bench/old/Hello_LED_sdram_0.dat (revision 7)
+++ trunk/test_bench/old/Hello_LED_sdram_0.dat (nonexistent)
@@ -1,49 +0,0 @@
-@00000000 00400034
-@00000001 08400804
-@00000002 0800683A
-@00000003 00000000
-@00000004 00000000
-@00000005 00000000
-@00000006 00000000
-@00000007 00000000
-@00000008 06C04034
-@00000009 DEC00004
-@0000000A 06800074
-@0000000B D6A03104
-@0000000C 00000340
-@0000000D DEFFFD04
-@0000000E DF000215
-@0000000F D839883A
-@00000010 00800084
-@00000011 E0800005
-@00000012 E0000045
-@00000013 E0800003
-@00000014 1080204C
-@00000015 1005003A
-@00000016 1000031E
-@00000017 E0800043
-@00000018 1080005C
-@00000019 E0800045
-@0000001A E0800043
-@0000001B 1005003A
-@0000001C 1000041E
-@0000001D E0800003
-@0000001E 1004D07A
-@0000001F E0800005
-@00000020 00000306
-@00000021 E0800003
-@00000022 1085883A
-@00000023 E0800005
-@00000024 00C04034
-@00000025 18C21004
-@00000026 E0800003
-@00000027 18800035
-@00000028 E0000115
-@00000029 E0C00117
-@0000002A 008000F4
-@0000002B 10834FC4
-@0000002C 10FFE616
-@0000002D E0800117
-@0000002E 10800044
-@0000002F E0800115
-@00000030 003FF806
Index: trunk/test_bench/old/Count_Binary_sdram_0.dat
===================================================================
--- trunk/test_bench/old/Count_Binary_sdram_0.dat (revision 7)
+++ trunk/test_bench/old/Count_Binary_sdram_0.dat (nonexistent)
@@ -1,5026 +0,0 @@
-;Count Binary
-@00000000 00820014
-@00000001 1001483A
-@00000002 10BFF804
-@00000003 00BFFD16
-@00000004 00400034
-@00000005 08407204
-@00000006 0800683A
-@00000007 00000000
-@00000008 DEFFED04
-@00000009 DFC00015
-@0000000A D8400215
-@0000000B D8800315
-@0000000C D8C00415
-@0000000D D9000515
-@0000000E D9400615
-@0000000F D9800715
-@00000010 D9C00815
-@00000011 000B307A
-@00000012 DA000915
-@00000013 DA400A15
-@00000014 DA800B15
-@00000015 DAC00C15
-@00000016 DB000D15
-@00000017 DB400E15
-@00000018 DB800F15
-@00000019 DBC01015
-@0000001A D9401115
-@0000001B EBFFFF04
-@0000001C DBC01215
-@0000001D 0009313A
-@0000001E 2880004C
-@0000001F 10000326
-@00000020 20000226
-@00000021 00000EC0
-@00000022 00000306
-@00000023 DF401215
-@00000024 E8BFFF17
-@00000025 003DA03A
-@00000026 D9401117
-@00000027 DF401217
-@00000028 DFC00017
-@00000029 2801707A
-@0000002A D8400217
-@0000002B D8800317
-@0000002C D8C00417
-@0000002D D9000517
-@0000002E D9400617
-@0000002F D9800717
-@00000030 D9C00817
-@00000031 DA000917
-@00000032 DA400A17
-@00000033 DA800B17
-@00000034 DAC00C17
-@00000035 DB000D17
-@00000036 DB400E17
-@00000037 DB800F17
-@00000038 DBC01017
-@00000039 DEC01304
-@0000003A E800083A
-@0000003B DEFFF904
-@0000003C DFC00615
-@0000003D DF000515
-@0000003E D839883A
-@0000003F 0005313A
-@00000040 E0800415
-@00000041 E0800417
-@00000042 E0800315
-@00000043 E0800317
-@00000044 E0800015
-@00000045 E0000215
-@00000046 00800044
-@00000047 E0800115
-@00000048 E0C00017
-@00000049 E0800117
-@0000004A 1884703A
-@0000004B 1005003A
-@0000004C 1000101E
-@0000004D 00C00034
-@0000004E 18D3A504
-@0000004F E0800217
-@00000050 100490FA
-@00000051 10C9883A
-@00000052 00C00034
-@00000053 18D3A504
-@00000054 E0800217
-@00000055 100490FA
-@00000056 10C5883A
-@00000057 10800104
-@00000058 20C00017
-@00000059 11000017
-@0000005A E1400217
-@0000005B 183EE83A
-@0000005C 00000706
-@0000005D E0800117
-@0000005E 1085883A
-@0000005F E0800115
-@00000060 E0800217
-@00000061 10800044
-@00000062 E0800215
-@00000063 003FE406
-@00000064 0005313A
-@00000065 E0800315
-@00000066 E0800317
-@00000067 E0800415
-@00000068 E0800417
-@00000069 E0800015
-@0000006A E0800017
-@0000006B 1005003A
-@0000006C 1000011E
-@0000006D 003FD706
-@0000006E DFC00617
-@0000006F DF000517
-@00000070 DEC00704
-@00000071 F800283A
-@00000072 06C04034
-@00000073 DEC00004
-@00000074 06800074
-@00000075 D6B38B04
-@00000076 00800034
-@00000077 1093A104
-@00000078 00C00034
-@00000079 18D42804
-@0000007A 10C00326
-@0000007B 10000015
-@0000007C 10800104
-@0000007D 10FFFD36
-@0000007E 0000DB40
-@0000007F DEFFFE04
-@00000080 DFC00115
-@00000081 DF000015
-@00000082 D839883A
-@00000083 01000034
-@00000084 210D8704
-@00000085 00005100
-@00000086 01000034
-@00000087 210D8F04
-@00000088 00005100
-@00000089 01000034
-@0000008A 210D9604
-@0000008B 00005100
-@0000008C 01000034
-@0000008D 210D9D04
-@0000008E 00005100
-@0000008F DFC00117
-@00000090 DF000017
-@00000091 DEC00204
-@00000092 F800283A
-@00000093 DEFFFF04
-@00000094 DF000015
-@00000095 D839883A
-@00000096 00C04034
-@00000097 18C21004
-@00000098 D0A01603
-@00000099 18800035
-@0000009A DF000017
-@0000009B DEC00104
-@0000009C F800283A
-@0000009D DEFFFF04
-@0000009E DF000015
-@0000009F D839883A
-@000000A0 DF000017
-@000000A1 DEC00104
-@000000A2 F800283A
-@000000A3 DEFFFE04
-@000000A4 DF000115
-@000000A5 D839883A
-@000000A6 E1000015
-@000000A7 DF000117
-@000000A8 DEC00204
-@000000A9 F800283A
-@000000AA DEFFFD04
-@000000AB DFC00215
-@000000AC DF000115
-@000000AD D839883A
-@000000AE E1000015
-@000000AF 000024C0
-@000000B0 00002740
-@000000B1 E1000017
-@000000B2 000028C0
-@000000B3 D1601603
-@000000B4 01000034
-@000000B5 210DA404
-@000000B6 00005100
-@000000B7 DFC00217
-@000000B8 DF000117
-@000000B9 DEC00304
-@000000BA F800283A
-@000000BB DEFFFA04
-@000000BC DFC00515
-@000000BD DF000415
-@000000BE D839883A
-@000000BF E1400115
-@000000C0 E1000005
-@000000C1 E0800003
-@000000C2 108018D8
-@000000C3 1000201E
-@000000C4 D0A01717
-@000000C5 E0800215
-@000000C6 E0C00217
-@000000C7 188000A0
-@000000C8 1000101E
-@000000C9 E0C00217
-@000000CA 188000C8
-@000000CB 1000041E
-@000000CC E0C00217
-@000000CD 18800060
-@000000CE 1000081E
-@000000CF 00001106
-@000000D0 E0C00217
-@000000D1 18800120
-@000000D2 1000081E
-@000000D3 E0C00217
-@000000D4 18800220
-@000000D5 1000081E
-@000000D6 00000A06
-@000000D7 000024C0
-@000000D8 00003106
-@000000D9 00002740
-@000000DA 00002F06
-@000000DB E1000117
-@000000DC 000028C0
-@000000DD 00002C06
-@000000DE E1000117
-@000000DF 00002A80
-@000000E0 00002906
-@000000E1 E1000117
-@000000E2 00002A80
-@000000E3 00002606
-@000000E4 D0A01717
-@000000E5 E0800315
-@000000E6 E0C00317
-@000000E7 188000A0
-@000000E8 1000131E
-@000000E9 E0C00317
-@000000EA 188000C8
-@000000EB 1000041E
-@000000EC E0C00317
-@000000ED 18800060
-@000000EE 1000081E
-@000000EF 00001A06
-@000000F0 E0C00317
-@000000F1 18800120
-@000000F2 10000E1E
-@000000F3 E0C00317
-@000000F4 18800220
-@000000F5 1000101E
-@000000F6 00001306
-@000000F7 01000034
-@000000F8 210DA604
-@000000F9 00005100
-@000000FA D0201715
-@000000FB 00000E06
-@000000FC 01000034
-@000000FD 210DA904
-@000000FE 00005100
-@000000FF D0201715
-@00000100 00000906
-@00000101 01000034
-@00000102 210DAC04
-@00000103 00005100
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Index: trunk/test_bench/sdram_ctrl_tb.vhd
===================================================================
--- trunk/test_bench/sdram_ctrl_tb.vhd (revision 7)
+++ trunk/test_bench/sdram_ctrl_tb.vhd (nonexistent)
@@ -1,169 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-entity sdram_ctrl_tb is
-end sdram_ctrl_tb;
-
-architecture structure of sdram_ctrl_tb is
- component pll
- port (
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- e0 : OUT STD_LOGIC ;
- locked : OUT STD_LOGIC
- ) ;
- end component ;
- component sdram_ctrl is
- port(
- signal clk : IN STD_LOGIC;
- signal reset : IN STD_LOGIC;
-
- signal avs_nios_chipselect : IN STD_LOGIC;
- signal avs_nios_address : IN STD_LOGIC_VECTOR (21 DOWNTO 0);
- signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
- signal avs_nios_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
- signal avs_nios_write : IN STD_LOGIC;
- signal avs_nios_read : IN STD_LOGIC;
- signal avs_nios_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- signal avs_nios_readdatavalid : OUT STD_LOGIC;
- signal avs_nios_waitrequest : OUT STD_LOGIC;
-
- signal sdram_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
- signal sdram_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
- signal sdram_cas_n : OUT STD_LOGIC;
- signal sdram_cke : OUT STD_LOGIC;
- signal sdram_cs_n : OUT STD_LOGIC_VECTOR(0 downto 0);
- signal sdram_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- signal sdram_dqm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
- signal sdram_ras_n : OUT STD_LOGIC;
- signal sdram_we_n : OUT STD_LOGIC
- );
- end component;
-
- component mt48lc4m32b2 IS
- PORT (
- Dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => 'Z');
- Addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
- Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- Clk : IN STD_LOGIC := '0';
- Cke : IN STD_LOGIC := '1';
- Cs_n : IN STD_LOGIC := '1';
- Ras_n : IN STD_LOGIC := '1';
- Cas_n : IN STD_LOGIC := '1';
- We_n : IN STD_LOGIC := '1';
- Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"
- );
- END component;
-
- component cpu_simulator IS
- PORT(clk, reset: IN std_logic;
- address : OUT std_logic_vector(21 downto 0):=(others=>'0');
- writedata : out std_logic_vector(31 downto 0):=(others=>'0');
- byteenable : out std_logic_vector(3 downto 0):=(others=>'0');
- write : out std_logic:='0';
- read : out std_logic:='0';
- readdata : in std_logic_vector(31 downto 0);
- waitrequest : in std_logic;
- readdatavalid : in std_logic
- );
- END component;
-
- signal reset, clk_ok: std_logic;
- signal run_nios_n : std_logic:='1';
- signal clk,i_clk: std_logic:='0';
-
- signal SDRAM_CLK : std_logic;
- signal SDRAM_CKE : std_logic;
- signal SDRAM_NCS : std_logic_vector(0 downto 0);
- signal SDRAM_NRAS : std_logic;
- signal SDRAM_NCAS : std_logic;
- signal SDRAM_NWE : std_logic;
- signal SDRAM_ADDRESS : std_logic_vector(11 downto 0);
- signal SDRAM_BANK : std_logic_vector(1 downto 0);
- signal SDRAM_DQM : std_logic_vector(3 downto 0);
- signal SDRAM_DATA : std_logic_vector(31 downto 0);
-
- signal address : std_logic_vector(21 downto 0);
- signal writedata : std_logic_vector(31 downto 0):=(others=>'0');
- signal byteenable : std_logic_vector(3 downto 0):=(others=>'0');
- signal write : std_logic;
- signal read : std_logic;
- signal chipselect : std_logic:='1';
- signal readdata : std_logic_vector(31 downto 0);
- signal waitrequest : std_logic;
- signal readdatavalid : std_logic;
-
-begin
-
- reset<= not clk_ok;
- run_nios_n<= reset after 140 us;
-
- UUT: sdram_ctrl
- port map(
- clk => i_clk,
- reset => reset,
-
- avs_nios_chipselect => chipselect,
- avs_nios_address => address,
- avs_nios_byteenable => byteenable,
- avs_nios_writedata => writedata,
- avs_nios_write => write,
- avs_nios_read => read,
- avs_nios_readdata => readdata,
- avs_nios_readdatavalid => readdatavalid,
- avs_nios_waitrequest => waitrequest,
-
- sdram_addr => SDRAM_ADDRESS,
- sdram_ba => SDRAM_BANK,
- sdram_cas_n => SDRAM_NCAS,
- sdram_cke => SDRAM_CKE,
- sdram_cs_n => SDRAM_NCS,
- sdram_dq => SDRAM_DATA,
- sdram_dqm => SDRAM_DQM,
- sdram_ras_n => SDRAM_NRAS,
- sdram_we_n => SDRAM_NWE
- );
-
- sdram:mt48lc4m32b2
- PORT MAP(
- Dq => SDRAM_DATA,
- Addr => SDRAM_ADDRESS,
- Ba => SDRAM_BANK,
- Clk => SDRAM_CLK,
- Cke => SDRAM_CKE,
- Cs_n => SDRAM_NCS(0),
- Ras_n => SDRAM_NRAS,
- Cas_n => SDRAM_NCAS,
- We_n => SDRAM_NWE,
- Dqm => SDRAM_DQM
- );
-
- cpu: cpu_simulator
- PORT MAP(
- clk => i_clk,
- reset => run_nios_n,
- address => address,
- writedata => writedata,
- byteenable => byteenable,
- write => write,
- read => read,
- readdata => readdata,
- waitrequest => waitrequest,
- readdatavalid => readdatavalid
- );
-
- U1 : pll
- port map(
- inclk0 => clk,
- c0 => i_clk,
- e0 => SDRAM_CLK,
- locked =>clk_ok
- );
-
- clock_generator:process
- begin
- wait for 21 ns;
- clk<= clk xor '1';
- end process;
-end structure;
Index: trunk/doc/sdram_ctrl.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/sdram_ctrl.sxw
===================================================================
--- trunk/doc/sdram_ctrl.sxw (revision 7)
+++ trunk/doc/sdram_ctrl.sxw (nonexistent)
trunk/doc/sdram_ctrl.sxw
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/readme.txt
===================================================================
--- trunk/doc/readme.txt (revision 7)
+++ trunk/doc/readme.txt (nonexistent)
@@ -1 +0,0 @@
-Please look up inside the source.
\ No newline at end of file
Index: trunk/src/sdram_ctrl.vhd
===================================================================
--- trunk/src/sdram_ctrl.vhd (revision 7)
+++ trunk/src/sdram_ctrl.vhd (nonexistent)
@@ -1,484 +0,0 @@
-------------------------------------------------------------------
---
--- sdram_ctrl.vhd
---
--- Module Description:
--- SDRAM small&fast controller
---
---
--- To Do:
--- multichipselect support done
--- configurable times 50%
--- nios simulation support
---
--- Author(s):
--- Aleksey Kuzmenok, ntpqa@opencores.org
---
-------------------------------------------------------------------
---
--- Copyright (C) 2006 Aleksey Kuzmenok and OPENCORES.ORG
---
--- This module is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This module is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this software; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
---
-------------------------------------------------------------------
--- Hardware test results
--- FPGA SDRAM CLK (not less than)
--- EP1C12XXXXC8 MT48LC4M32B2TG-7:G 125 MHz
--- EP1C6XXXXC8 IS42S16100C1-7TL 125 MHz
---
-------------------------------------------------------------------
--- History
--- 22.10.2006 multichipselect functionaly tested
--- 10.11.2006 first successful hardware test
--- 07.12.2006 proved to be fully reliable
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity sdram_ctrl is
- generic(
- DATA_WIDTH: integer:=32;
- CHIPSELECTS: integer:=1;
- LOG2_OF_CS: integer:=0;
- BANK_WIDTH: integer:=2;
- ROW_WIDTH: integer:=12;
- COLUMN_WIDTH: integer:=8;
-
- MODE_REGISTER: integer:=48; -- 1 word burst, CAS latency=3
-
- -- Only two times are configurable
- -- tINIT delay between powerup and load mode register = 100 us
- -- tREF refresh period = 15.625 us (64ms/4096rows)
- clk_MHz: integer:=120;
- t_INIT_uS: integer:=110; -- 109.9 us just to be on the save side
- t_REF_nS: integer:=15384 -- 15.384 us the same purpose
-
- );
- port(
- signal clk : IN STD_LOGIC;
- signal reset : IN STD_LOGIC;
-
- -- IMPORTANT: for this Avalon(tm) interface
- -- 'Minimum Arbitration Shares'=1
- -- 'Max Pending Read Transactions'=9
- signal avs_nios_chipselect : IN STD_LOGIC;
- signal avs_nios_address : IN STD_LOGIC_VECTOR ((LOG2_OF_CS+BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH-1) DOWNTO 0);
- signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0);
- signal avs_nios_writedata : IN STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal avs_nios_write : IN STD_LOGIC;
- signal avs_nios_read : IN STD_LOGIC;
- signal avs_nios_waitrequest : OUT STD_LOGIC;
- signal avs_nios_readdata : OUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal avs_nios_readdatavalid : OUT STD_LOGIC;
-
- -- global export signals
- signal sdram_cke : OUT STD_LOGIC; -- This pin has the fixed state '1'
- signal sdram_ba : OUT STD_LOGIC_VECTOR ((BANK_WIDTH-1) DOWNTO 0);
- signal sdram_addr : OUT STD_LOGIC_VECTOR ((ROW_WIDTH-1) DOWNTO 0);
- signal sdram_cs_n : OUT STD_LOGIC_VECTOR ((CHIPSELECTS-1) DOWNTO 0);
- signal sdram_ras_n : OUT STD_LOGIC;
- signal sdram_cas_n : OUT STD_LOGIC;
- signal sdram_we_n : OUT STD_LOGIC;
- signal sdram_dq : INOUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal sdram_dqm : OUT STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0)
- );
-end sdram_ctrl;
-
-architecture behaviour of sdram_ctrl is
-
- CONSTANT FIFO_WIDTH: integer:=LOG2_OF_CS+BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
- CONSTANT BE_LOW_BIT: integer:=2;
- CONSTANT DATA_LOW_BIT: integer:=(DATA_WIDTH/8)+2;
- CONSTANT COL_LOW_BIT: integer:=DATA_WIDTH+(DATA_WIDTH/8)+2;
- CONSTANT ROW_LOW_BIT: integer:=COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
- CONSTANT BANK_LOW_BIT: integer:=ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
- CONSTANT CS_LOW_BIT: integer:=BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
-
- --CONSTANT MODE: std_logic_vector((sdram_addr'length-1) downto 0):=std_logic_vector(MODE_REGISTER((sdram_addr'length-1) downto 0));
- CONSTANT INIT_PAUSE_CLOCKS: integer:=clk_MHz*t_INIT_uS;
- CONSTANT REFRESH_PERIOD_CLOCKS: integer:=(clk_MHz*t_REF_nS)/1000;
- CONSTANT CAS_LATENCY: integer:=3; -- other latencies weren't been tested!
-
- COMPONENT scfifo
- GENERIC (
- add_ram_output_register : STRING;
- intended_device_family : STRING;
- lpm_numwords : NATURAL;
- lpm_showahead : STRING;
- lpm_type : STRING;
- lpm_width : NATURAL;
- lpm_widthu : NATURAL;
- overflow_checking : STRING;
- underflow_checking : STRING;
- use_eab : STRING
- );
- PORT (
- rdreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
- wrreq : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
- full : OUT STD_LOGIC
- );
- END COMPONENT;
-
- -- If you ask me why there are so many states, I'll answer that all times are fixed.
- -- The top speed for MT48LC4M32B2TG-7:G is 7 ns, therefore all times were based on it.
- -- tRP PRECHARGE command period = 3 clocks
- -- tRFC AUTO REFRESH period = 10 clocks
- -- tMRD LOAD MODE REGISTER command to ACTIVE or REFRESH command = 2 clocks
- -- tRCD ACTIVE to READ or WRITE delay = 3 clocks
- -- tRAS ACTIVE to PRECHARGE command = 7 clocks
- -- tRC ACTIVE to ACTIVE command period = 10 clocks
- -- tWR2 Write recovery time = 2 clocks
- type states is (
- INIT0,INIT1,INIT2,INIT3,INIT4,INIT5,INIT6,INIT7,
- INIT8,INIT9,INIT10,INIT11,INIT12,INIT13,INIT14,INIT15,
- INIT16,INIT17,INIT18,INIT19,INIT20,INIT21,INIT22,INIT23,INIT24,
- REFRESH0,REFRESH1,REFRESH2,REFRESH3,REFRESH4,REFRESH5,REFRESH6,REFRESH7,
- REFRESH8,REFRESH9,REFRESH10,REFRESH11,REFRESH12,REFRESH13,REFRESH14,
- ACTIVE0,ACTIVE1,ACTIVE2,ACTIVE3,ACTIVE4,
- IDLE,READ0,WRITE0);
- signal operation: states;
-
- signal fifo_q: std_logic_vector((FIFO_WIDTH-1) downto 0);
-
- signal init_counter: unsigned(15 downto 0):=to_unsigned(INIT_PAUSE_CLOCKS,16);
- signal refresh_counter: unsigned(15 downto 0);
- signal active_counter: unsigned(2 downto 0);
- signal active_address: unsigned((LOG2_OF_CS+BANK_WIDTH+ROW_WIDTH-1) downto 0);
-
- signal chipselect: std_logic_vector(LOG2_OF_CS downto 0);
- signal bank: std_logic_vector((sdram_ba'length-1) downto 0);
- signal row: std_logic_vector((sdram_addr'length-1) downto 0);
- signal column: std_logic_vector((COLUMN_WIDTH-1) downto 0);
- signal data: std_logic_vector((sdram_dq'length-1) downto 0);
- signal be: std_logic_vector((sdram_dqm'length-1) downto 0);
-
- signal do_init,do_refresh,do_active,read_is_active,ready,tRCD_not_expired: std_logic:='0';
-
- signal fifo_rdreq,fifo_empty: std_logic;
-
- signal read_latency: std_logic_vector(CAS_LATENCY downto 0);
-
- signal fifo_data: std_logic_vector((FIFO_WIDTH-1) downto 0);
- signal fifo_wrreq,fifo_wrfull: std_logic;
-
- signal i_command : STD_LOGIC_VECTOR(2 downto 0);
- CONSTANT NOP: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="111";
- CONSTANT ACTIVE: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="011";
- CONSTANT READ: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="101";
- CONSTANT WRITE: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="100";
- CONSTANT PRECHARGE: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="010";
- CONSTANT AUTO_REFRESH: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="001";
- CONSTANT LOAD_MODE_REGISTER: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="000";
-
- signal i_address : STD_LOGIC_VECTOR((sdram_addr'length-1) DOWNTO 0);
- signal i_chipselect: STD_LOGIC_VECTOR((sdram_cs_n'length-1) downto 0);
- signal i_bank : STD_LOGIC_VECTOR((sdram_ba'length-1) DOWNTO 0);
- signal i_dqm : STD_LOGIC_VECTOR((sdram_dqm'length-1) DOWNTO 0);
- signal i_data : STD_LOGIC_VECTOR((sdram_dq'length-1) DOWNTO 0);
- attribute ALTERA_ATTRIBUTE : string;
- attribute ALTERA_ATTRIBUTE of i_command : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_address : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_chipselect : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_bank : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_data : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of avs_nios_readdata : signal is "FAST_INPUT_REGISTER=ON";
-
- function DECODE(hex: std_logic_vector; size: integer) return std_logic_vector is
- variable result : std_logic_vector((size-1) downto 0);
- begin
- result:=(others=>'1');
- result(to_integer(unsigned(hex))):='0';
- return result;
- end;
-begin
- sdram_cke<='1';
- (sdram_ras_n,sdram_cas_n,sdram_we_n) <= i_command;
- sdram_cs_n <= i_chipselect;
- sdram_addr <= i_address;
- sdram_ba <= i_bank;
- sdram_dqm <= i_dqm;
- sdram_dq <= i_data;
-
- fifo_data<=avs_nios_address & avs_nios_writedata & avs_nios_byteenable & avs_nios_write & avs_nios_read;
- fifo_wrreq<=(avs_nios_write or avs_nios_read) and avs_nios_chipselect and not fifo_wrfull;
-
- avs_nios_waitrequest<=fifo_wrfull;
-
- fifo_rdreq<=not fifo_empty and not do_refresh and not do_active and not read_is_active and ready;
-
- do_active<='0' when active_address=unsigned(fifo_q((fifo_q'length-1) downto (column'length+data'length+be'length+2))) else '1';
- read_is_active<='1' when read_latency(CAS_LATENCY-1 downto 0)>"000" and fifo_q(1)='1' else '0';
- ready<='1' when operation=IDLE or operation=READ0 or operation=WRITE0 else '0';
-
- operation_machine:process(reset,clk)
- begin
- if reset='1'
- then
- operation<=INIT0;
- active_address<=(others=>'1');
- elsif rising_edge(clk)
- then
- if CHIPSELECTS>1
- then
- chipselect<='0'&fifo_q((FIFO_WIDTH-1) downto CS_LOW_BIT);
- bank<=fifo_q((CS_LOW_BIT-1) downto BANK_LOW_BIT);
- else
- chipselect<=(others=>'0');
- bank<=fifo_q((FIFO_WIDTH-1) downto BANK_LOW_BIT);
- end if;
-
- row<= fifo_q((BANK_LOW_BIT-1) downto ROW_LOW_BIT);
- column<=fifo_q((ROW_LOW_BIT-1) downto COL_LOW_BIT);
- data<= fifo_q((COL_LOW_BIT-1) downto DATA_LOW_BIT);
- be<= fifo_q((DATA_LOW_BIT-1) downto BE_LOW_BIT);
-
- case operation is
- when INIT0=>
- if do_init='1'
- then operation<=INIT1;row(10)<='1';
- end if;
- when INIT1=>operation<=INIT2;
- when INIT2=>operation<=INIT3;
- when INIT3=>operation<=INIT4;
- when INIT4=>operation<=INIT5;
- when INIT5=>operation<=INIT6;
- when INIT6=>operation<=INIT7;
- when INIT7=>operation<=INIT8;
- when INIT8=>operation<=INIT9;
- when INIT9=>operation<=INIT10;
- when INIT10=>operation<=INIT11;
- when INIT11=>operation<=INIT12;
- when INIT12=>operation<=INIT13;
- when INIT13=>operation<=INIT14;
- when INIT14=>operation<=INIT15;
- when INIT15=>operation<=INIT16;
- when INIT16=>operation<=INIT17;
- when INIT17=>operation<=INIT18;
- when INIT18=>operation<=INIT19;
- when INIT19=>operation<=INIT20;
- when INIT20=>operation<=INIT21;
- when INIT21=>operation<=INIT22;
- when INIT22=>operation<=INIT23;
- when INIT23=>operation<=INIT24;row<=std_logic_vector(to_unsigned(MODE_REGISTER,row'length));
- when INIT24=>operation<=IDLE;
-
- when REFRESH0=>operation<=REFRESH1;
- when REFRESH1=>operation<=REFRESH2;
- when REFRESH2=>operation<=REFRESH3;
- when REFRESH3=>operation<=REFRESH4;
- when REFRESH4=>operation<=REFRESH5;
- when REFRESH5=>operation<=REFRESH6;
- when REFRESH6=>operation<=REFRESH7;
- when REFRESH7=>operation<=REFRESH8;
- when REFRESH8=>operation<=REFRESH9;
- when REFRESH9=>operation<=REFRESH10;
- when REFRESH10=>operation<=REFRESH11;
- when REFRESH11=>operation<=REFRESH12;
- when REFRESH12=>operation<=REFRESH13;
- active_address<=unsigned(fifo_q((fifo_q'length-1) downto ROW_LOW_BIT));
- when REFRESH13=>operation<=REFRESH14;
- when REFRESH14=>operation<=IDLE;
-
- when ACTIVE0=>operation<=ACTIVE1;
- when ACTIVE1=>operation<=ACTIVE2;
- when ACTIVE2=>operation<=ACTIVE3;
- active_address<=unsigned(fifo_q((fifo_q'length-1) downto ROW_LOW_BIT));
- when ACTIVE3=>operation<=ACTIVE4;
- when ACTIVE4=>operation<=IDLE;
-
- when others=>
- if do_refresh='1'
- then
- if tRCD_not_expired='0' and operation=IDLE
- then operation<=REFRESH0;row(10)<='1';
- else operation<=IDLE;
- end if;
- elsif do_active='1'
- then
- if tRCD_not_expired='0' and operation=IDLE
- then operation<=ACTIVE0;row(10)<='1';
- else operation<=IDLE;
- end if;
- elsif fifo_empty='1'
- then
- operation<=IDLE;
- elsif fifo_q(1)='1' --write
- then
- if read_latency(CAS_LATENCY-1 downto 0)>"000"
- then operation<=IDLE;
- else operation<=WRITE0;
- end if;
- elsif fifo_q(0)='1' --read
- then
- operation<=READ0;
- end if;
- end case;
- end if;
- end process;
-
- control_latency:process(reset,clk)
- begin
- if reset='1'
- then
- read_latency<=(others=>'0');
- elsif rising_edge(clk)
- then
- read_latency<=std_logic_vector(unsigned(read_latency) SLL 1);
- if operation=READ0
- then read_latency(0)<='1';
- else read_latency(0)<='0';
- end if;
- end if;
- end process;
- latch_readdata:process(reset,clk)
- begin
- if reset='1'
- then
- avs_nios_readdata<=(others=>'0');
- avs_nios_readdatavalid<='0';
- elsif rising_edge(clk)
- then
- avs_nios_readdata<=sdram_dq;
- avs_nios_readdatavalid<=read_latency(CAS_LATENCY);
- end if;
- end process;
- initialization:process(reset,clk)
- begin
- if rising_edge(clk)
- then
- if init_counter>0
- then
- init_counter<=init_counter-1;
- else do_init<='1';
- end if;
- end if;
- end process;
- refreshing:process(clk,reset)
- begin
- if reset='1'
- then
- refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
- do_refresh<='0';
- elsif rising_edge(clk)
- then
- if refresh_counter=to_unsigned(0,refresh_counter'length)
- then refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
- do_refresh<='1';
- else refresh_counter<=refresh_counter-1;
- end if;
- if operation=REFRESH0 or operation=REFRESH5
- then do_refresh<='0';
- end if;
- end if;
- end process;
- active_period:process(reset,clk)
- begin
- if reset='1'
- then
- active_counter<=(others=>'0');
- tRCD_not_expired<='0';
- elsif rising_edge(clk)
- then
- if operation=ACTIVE3 or operation=REFRESH13
- then active_counter<=to_unsigned(5,active_counter'length);
- elsif active_counter>0
- then active_counter<=active_counter-1;
- end if;
- end if;
- if active_counter>0
- then tRCD_not_expired<='1';
- else tRCD_not_expired<='0';
- end if;
- end process;
- latch_controls:process(clk,reset)
- begin
- if reset='1'
- then
- i_command<=NOP;
- i_address<=(others=>'0');
- i_bank<=(others=>'0');
- i_dqm<=(others=>'0');
- i_data<=(others=>'Z');
- i_chipselect<=(others=>'1');
- elsif rising_edge(clk)
- then
- i_command<=NOP;
- i_chipselect<=DECODE(chipselect,i_chipselect'length);
- i_bank<=bank;
- i_address<=(others=>'0');
- i_address((column'length-1) downto 0)<=column;
- i_data<=(others=>'Z');
- i_dqm<=(others=>'0');
-
- case operation is
- when INIT1|REFRESH0|ACTIVE0 =>
- i_command<=PRECHARGE;
- i_address<=row;
- i_chipselect<=(others=>'0');
- when INIT4|INIT14|REFRESH3 =>
- i_command<=AUTO_REFRESH;
- i_chipselect<=(others=>'0');
- when INIT24=>
- i_command<=LOAD_MODE_REGISTER;
- i_address<=row;
- i_chipselect<=(others=>'0');
- when ACTIVE3|REFRESH13 =>
- i_command<=ACTIVE;
- i_address<=row;
- when READ0 =>
- i_command<=READ;
- when WRITE0 =>
- i_command<=WRITE;
- i_dqm<=not be;
- i_data<=data;
- when OTHERS =>
- end case;
- end if;
- end process;
-
- fifo: scfifo
- GENERIC MAP (
- add_ram_output_register => "ON",
- intended_device_family => "Auto",
- lpm_numwords => 4,
- lpm_showahead => "ON",
- lpm_type => "scfifo",
- lpm_width => FIFO_WIDTH,
- lpm_widthu => 2,
- overflow_checking => "ON",
- underflow_checking => "ON",
- use_eab => "ON"
- )
- PORT MAP (
- rdreq => fifo_rdreq,
- aclr => reset,
- clock => clk,
- wrreq => fifo_wrreq,
- data => fifo_data,
- empty => fifo_empty,
- q => fifo_q,
- full => fifo_wrfull
- );
-end behaviour;
Index: trunk/syn/sdram_ctrl/class.ptf
===================================================================
--- trunk/syn/sdram_ctrl/class.ptf (revision 7)
+++ trunk/syn/sdram_ctrl/class.ptf (nonexistent)
@@ -1,972 +0,0 @@
-#
-# This class.ptf file built by Component Editor
-# 2006.09.25.10:24:12
-#
-# DO NOT MODIFY THIS FILE
-# If you hand-modify this file you will likely
-# interfere with Component Editor's ability to
-# read and edit it. And then Component Editor
-# will overwrite your changes anyway. So, for
-# the very best results, just relax and
-# DO NOT MODIFY THIS FILE
-#
-CLASS sdram_ctrl
-{
- CB_GENERATOR
- {
- HDL_FILES
- {
- FILE
- {
- use_in_simulation = "1";
- use_in_synthesis = "1";
- filepath = "hdl/sdram_ctrl.vhd";
- }
- }
- top_module_name = "sdram_ctrl.vhd:sdram_ctrl";
- emit_system_h = "0";
- LIBRARIES
- {
- library = "ieee.std_logic_1164.all";
- library = "ieee.numeric_std.all";
- library = "altera_mf.altera_mf_components.all";
- library = "std.standard.all";
- }
- }
- MODULE_DEFAULTS global_signals
- {
- class = "sdram_ctrl";
- class_version = "1.1";
- SYSTEM_BUILDER_INFO
- {
- Instantiate_In_System_Module = "1";
- Has_Clock = "1";
- Top_Level_Ports_Are_Enumerated = "1";
- }
- COMPONENT_BUILDER
- {
- GLS_SETTINGS
- {
- }
- }
- PORT_WIRING
- {
- PORT clk
- {
- width = "1";
- width_expression = "";
- direction = "input";
- type = "clk";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT reset
- {
- width = "1";
- width_expression = "";
- direction = "input";
- type = "reset";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_cke
- {
- width = "1";
- width_expression = "";
- direction = "output";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_ba
- {
- width = "-1";
- width_expression = "((bank_width - 1)) - (0) + 1";
- direction = "output";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_addr
- {
- width = "-1";
- width_expression = "((row_width - 1)) - (0) + 1";
- direction = "output";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_cs_n
- {
- width = "1";
- width_expression = "";
- direction = "output";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_ras_n
- {
- width = "1";
- width_expression = "";
- direction = "output";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_cas_n
- {
- width = "1";
- width_expression = "";
- direction = "output";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_we_n
- {
- width = "1";
- width_expression = "";
- direction = "output";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_dq
- {
- width = "-1";
- width_expression = "((data_width - 1)) - (0) + 1";
- direction = "inout";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT sdram_dqm
- {
- width = "-1";
- width_expression = "(((data_width / 8) - 1)) - (0) + 1";
- direction = "output";
- type = "export";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- }
- WIZARD_SCRIPT_ARGUMENTS
- {
- hdl_parameters
- {
- data_width = "32";
- bank_width = "4";
- row_width = "12";
- column_width = "8";
- clk_mhz = "120";
- }
- }
- SIMULATION
- {
- DISPLAY
- {
- }
- }
- SLAVE nios
- {
- SYSTEM_BUILDER_INFO
- {
- Bus_Type = "avalon";
- Address_Group = "1";
- Has_Clock = "0";
- Address_Width = "-1";
- Address_Alignment = "dynamic";
- Data_Width = "8";
- Has_Base_Address = "1";
- Has_IRQ = "0";
- Setup_Time = "0";
- Hold_Time = "0";
- Read_Wait_States = "peripheral_controlled";
- Write_Wait_States = "peripheral_controlled";
- Read_Latency = "0";
- Maximum_Pending_Read_Transactions = "9";
- Active_CS_Through_Read_Latency = "0";
- Is_Printable_Device = "1";
- Is_Memory_Device = "1";
- Is_Readable = "1";
- Is_Writable = "1";
- Minimum_Uninterrupted_Run_Length = "1";
- }
- COMPONENT_BUILDER
- {
- AVS_SETTINGS
- {
- Setup_Value = "0";
- Read_Wait_Value = "1";
- Write_Wait_Value = "1";
- Hold_Value = "0";
- Timing_Units = "cycles";
- Read_Latency_Value = "0";
- Minimum_Arbitration_Shares = "1";
- Active_CS_Through_Read_Latency = "0";
- Max_Pending_Read_Transactions_Value = "9";
- Address_Alignment = "dynamic";
- Is_Printable_Device = "1";
- interface_name = "Avalon Slave";
- external_wait = "1";
- Is_Memory_Device = "1";
- }
- }
- PORT_WIRING
- {
- PORT avs_nios_chipselect
- {
- width = "1";
- width_expression = "";
- direction = "input";
- type = "chipselect";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT avs_nios_address
- {
- width = "-1";
- width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1";
- direction = "input";
- type = "address";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT avs_nios_byteenable
- {
- width = "-1";
- width_expression = "(((data_width / 8) - 1)) - (0) + 1";
- direction = "input";
- type = "byteenable";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT avs_nios_writedata
- {
- width = "-1";
- width_expression = "((data_width - 1)) - (0) + 1";
- direction = "input";
- type = "writedata";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT avs_nios_write
- {
- width = "1";
- width_expression = "";
- direction = "input";
- type = "write";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT avs_nios_read
- {
- width = "1";
- width_expression = "";
- direction = "input";
- type = "read";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT avs_nios_waitrequest
- {
- width = "1";
- width_expression = "";
- direction = "output";
- type = "waitrequest";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT avs_nios_readdata
- {
- width = "-1";
- width_expression = "((data_width - 1)) - (0) + 1";
- direction = "output";
- type = "readdata";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- PORT avs_nios_readdatavalid
- {
- width = "1";
- width_expression = "";
- direction = "output";
- type = "readdatavalid";
- is_shared = "0";
- vhdl_record_name = "";
- vhdl_record_type = "";
- }
- }
- }
- }
- USER_INTERFACE
- {
- USER_LABELS
- {
- name = "sdram_ctrl";
- technology = "Opencores";
- }
- WIZARD_UI the_wizard_ui
- {
- title = "sdram_ctrl - {{ $MOD }}";
- CONTEXT
- {
- H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
- M = "";
- SBI_global_signals = "SYSTEM_BUILDER_INFO";
- SBI_nios = "SLAVE nios/SYSTEM_BUILDER_INFO";
- # The following signals have parameterized widths:
- PORT_sdram_ba = "PORT_WIRING/PORT sdram_ba";
- PORT_sdram_addr = "PORT_WIRING/PORT sdram_addr";
- PORT_sdram_dq = "PORT_WIRING/PORT sdram_dq";
- PORT_sdram_dqm = "PORT_WIRING/PORT sdram_dqm";
- PORT_avs_nios_address = "SLAVE nios/PORT_WIRING/PORT avs_nios_address";
- PORT_avs_nios_byteenable = "SLAVE nios/PORT_WIRING/PORT avs_nios_byteenable";
- PORT_avs_nios_writedata = "SLAVE nios/PORT_WIRING/PORT avs_nios_writedata";
- PORT_avs_nios_readdata = "SLAVE nios/PORT_WIRING/PORT avs_nios_readdata";
- }
- PAGES main
- {
- PAGE 1
- {
- align = "left";
- title = "sdram_ctrl 1.1 Settings";
- layout = "vertical";
- TEXT
- {
- title = "Built on: 2006.09.25.10:24:12";
- }
- TEXT
- {
- title = "Class name: sdram_ctrl";
- }
- TEXT
- {
- title = "Class version: 1.1";
- }
- TEXT
- {
- title = "Component name: sdram_ctrl";
- }
- TEXT
- {
- title = "Component Group: Opencores";
- }
- GROUP parameters
- {
- title = "Parameters";
- layout = "form";
- align = "left";
- EDIT e1
- {
- id = "data_width";
- editable = "1";
- title = "data_width:";
- columns = "40";
- tooltip = "default value: 32";
- DATA
- {
- $H/data_width = "$";
- }
- q = "'";
- warning = "{{ if(!(regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/data_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/data_width,'ugly_-?[0-9]+')))'data_width must be numeric constant, not '+$H/data_width; }}";
- }
- EDIT e2
- {
- id = "bank_width";
- editable = "1";
- title = "bank_width:";
- columns = "40";
- tooltip = "default value: 4";
- DATA
- {
- $H/bank_width = "$";
- }
- q = "'";
- warning = "{{ if(!(regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/bank_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/bank_width,'ugly_-?[0-9]+')))'bank_width must be numeric constant, not '+$H/bank_width; }}";
- }
- EDIT e3
- {
- id = "row_width";
- editable = "1";
- title = "row_width:";
- columns = "40";
- tooltip = "default value: 12";
- DATA
- {
- $H/row_width = "$";
- }
- q = "'";
- warning = "{{ if(!(regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/row_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/row_width,'ugly_-?[0-9]+')))'row_width must be numeric constant, not '+$H/row_width; }}";
- }
- EDIT e4
- {
- id = "column_width";
- editable = "1";
- title = "column_width:";
- columns = "40";
- tooltip = "default value: 8";
- DATA
- {
- $H/column_width = "$";
- }
- q = "'";
- warning = "{{ if(!(regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/column_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/column_width,'ugly_-?[0-9]+')))'column_width must be numeric constant, not '+$H/column_width; }}";
- }
- EDIT e5
- {
- id = "clk_mhz";
- editable = "1";
- title = "clk_mhz:";
- columns = "40";
- tooltip = "default value: 120";
- DATA
- {
- $H/clk_mhz = "$";
- }
- q = "'";
- warning = "{{ if(!(regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/clk_mhz,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/clk_mhz,'ugly_-?[0-9]+')))'clk_mhz must be numeric constant, not '+$H/clk_mhz; }}";
- }
- }
- GROUP variable_port_widths
- {
- # This group is for display only, to preview parameterized port widths
- title = "Parameterized Signal Widths";
- layout = "form";
- align = "left";
- EDIT sdram_ba_width
- {
- id = "sdram_ba_width";
- editable = "0";
- title = "sdram_ba[((bank_width - 1)) - (0) + 1]:";
- tooltip = "sdram_ba[((bank_width - 1)) - (0) + 1]
direction: output
signal type: export"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_sdram_ba/width = (int((( ( $H/bank_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_sdram_ba/width = "$"; - } - warning = "{{ if($PORT_sdram_ba/width <= 0)('width of sdram_ba must be greater than zero' ) }}"; - } - EDIT sdram_addr_width - { - id = "sdram_addr_width"; - editable = "0"; - title = "sdram_addr[((row_width - 1)) - (0) + 1]:"; - tooltip = "sdram_addr[((row_width - 1)) - (0) + 1]
direction: output
signal type: export"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_sdram_addr/width = (int((( ( $H/row_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_sdram_addr/width = "$"; - } - warning = "{{ if($PORT_sdram_addr/width <= 0)('width of sdram_addr must be greater than zero' ) }}"; - } - EDIT sdram_dq_width - { - id = "sdram_dq_width"; - editable = "0"; - title = "sdram_dq[((data_width - 1)) - (0) + 1]:"; - tooltip = "sdram_dq[((data_width - 1)) - (0) + 1]
direction: inout
signal type: export"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_sdram_dq/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_sdram_dq/width = "$"; - } - warning = "{{ if($PORT_sdram_dq/width <= 0)('width of sdram_dq must be greater than zero' ) }}"; - } - EDIT sdram_dqm_width - { - id = "sdram_dqm_width"; - editable = "0"; - title = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]:"; - tooltip = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]
direction: output
signal type: export"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_sdram_dqm/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_sdram_dqm/width = "$"; - } - warning = "{{ if($PORT_sdram_dqm/width <= 0)('width of sdram_dqm must be greater than zero' ) }}"; - } - EDIT avs_nios_address_width - { - id = "avs_nios_address_width"; - editable = "0"; - title = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]:"; - tooltip = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]
direction: input
signal type: address"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_avs_nios_address/width = (int((((( ( $H/bank_width ) + ( $H/row_width ) ) + ( $H/column_width ) ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - dummy_dummy = "{{ $SBI_nios/Address_Width = $PORT_avs_nios_address/width; }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_avs_nios_address/width = "$"; - } - warning = "{{ if($PORT_avs_nios_address/width <= 0)('width of avs_nios_address must be greater than zero' ) }}"; - } - EDIT avs_nios_byteenable_width - { - id = "avs_nios_byteenable_width"; - editable = "0"; - title = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]:"; - tooltip = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]
direction: input
signal type: byteenable"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_avs_nios_byteenable/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_avs_nios_byteenable/width = "$"; - } - warning = "{{ if($PORT_avs_nios_byteenable/width <= 0)('width of avs_nios_byteenable must be greater than zero' ) }}"; - } - EDIT avs_nios_writedata_width - { - id = "avs_nios_writedata_width"; - editable = "0"; - title = "avs_nios_writedata[((data_width - 1)) - (0) + 1]:"; - tooltip = "avs_nios_writedata[((data_width - 1)) - (0) + 1]
direction: input
signal type: writedata"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_avs_nios_writedata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_writedata/width - 1) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_avs_nios_writedata/width = "$"; - } - warning = "{{ if($PORT_avs_nios_writedata/width <= 0)('width of avs_nios_writedata must be greater than zero' ) }}"; - } - EDIT avs_nios_readdata_width - { - id = "avs_nios_readdata_width"; - editable = "0"; - title = "avs_nios_readdata[((data_width - 1)) - (0) + 1]:"; - tooltip = "avs_nios_readdata[((data_width - 1)) - (0) + 1]
direction: output
signal type: readdata"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_avs_nios_readdata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_readdata/width - 1) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_avs_nios_readdata/width = "$"; - } - warning = "{{ if($PORT_avs_nios_readdata/width <= 0)('width of avs_nios_readdata must be greater than zero' ) }}"; - } - } - } - } - } - } - SOPC_Builder_Version = "5.10"; - COMPONENT_BUILDER - { - HDL_PARAMETERS - { - # generated by CBDocument.getParameterContainer - # used only by Component Editor - HDL_PARAMETER data_width - { - parameter_name = "data_width"; - type = "integer"; - default_value = "32"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER bank_width - { - parameter_name = "bank_width"; - type = "integer"; - default_value = "4"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER row_width - { - parameter_name = "row_width"; - type = "integer"; - default_value = "12"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER column_width - { - parameter_name = "column_width"; - type = "integer"; - default_value = "8"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER clk_mhz - { - parameter_name = "clk_mhz"; - type = "integer"; - default_value = "120"; - editable = "1"; - tooltip = ""; - } - } - SW_FILES - { - } - built_on = "2006.09.25.10:24:12"; - CACHED_HDL_INFO - { - # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection - # used only by Component Builder - FILE sdram_ctrl.vhd - { - file_mod = "Mon Sep 18 18:08:50 EEST 2006"; - quartus_map_start = "Mon Sep 25 10:22:36 EEST 2006"; - quartus_map_finished = "Mon Sep 25 10:22:58 EEST 2006"; - #found 1 valid modules - WRAPPER sdram_ctrl - { - CLASS sdram_ctrl - { - CB_GENERATOR - { - HDL_FILES - { - FILE - { - use_in_simulation = "1"; - use_in_synthesis = "1"; - filepath = "H:/Work/Home_stuff/opencores/sdram_ctrl/src/sdram_ctrl.vhd"; - } - } - top_module_name = "sdram_ctrl"; - emit_system_h = "0"; - LIBRARIES - { - library = "ieee.std_logic_1164.all"; - library = "ieee.numeric_std.all"; - library = "altera_mf.altera_mf_components.all"; - library = "std.standard.all"; - } - } - MODULE_DEFAULTS global_signals - { - class = "sdram_ctrl"; - class_version = "1.0"; - SYSTEM_BUILDER_INFO - { - Instantiate_In_System_Module = "1"; - } - SLAVE nios - { - SYSTEM_BUILDER_INFO - { - Bus_Type = "avalon"; - } - PORT_WIRING - { - PORT avs_nios_chipselect - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "chipselect"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_address - { - width = "-1"; - width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1"; - direction = "input"; - type = "address"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_byteenable - { - width = "-1"; - width_expression = "(((data_width / 8) - 1)) - (0) + 1"; - direction = "input"; - type = "byteenable"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_writedata - { - width = "-1"; - width_expression = "((data_width - 1)) - (0) + 1"; - direction = "input"; - type = "writedata"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_write - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "write"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_read - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "read"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_waitrequest - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "waitrequest"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_readdata - { - width = "-1"; - width_expression = "((data_width - 1)) - (0) + 1"; - direction = "output"; - type = "readdata"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_readdatavalid - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "readdatavalid"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - } - } - SLAVE avalon_slave_0 - { - SYSTEM_BUILDER_INFO - { - Bus_Type = "avalon"; - } - PORT_WIRING - { - PORT sdram_cke - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_ba - { - width = "-1"; - width_expression = "((bank_width - 1)) - (0) + 1"; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_addr - { - width = "-1"; - width_expression = "((row_width - 1)) - (0) + 1"; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_cs_n - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_ras_n - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_cas_n - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_we_n - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_dq - { - width = "-1"; - width_expression = "((data_width - 1)) - (0) + 1"; - direction = "inout"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_dqm - { - width = "-1"; - width_expression = "(((data_width / 8) - 1)) - (0) + 1"; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - } - } - PORT_WIRING - { - PORT clk - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "clk"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT reset - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "reset"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - } - } - USER_INTERFACE - { - USER_LABELS - { - name = "sdram_ctrl"; - technology = "imported components"; - } - } - SOPC_Builder_Version = "0.0"; - COMPONENT_BUILDER - { - HDL_PARAMETERS - { - # generated by CBDocument.getParameterContainer - # used only by Component Editor - HDL_PARAMETER data_width - { - parameter_name = "data_width"; - type = "integer"; - default_value = "32"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER bank_width - { - parameter_name = "bank_width"; - type = "integer"; - default_value = "4"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER row_width - { - parameter_name = "row_width"; - type = "integer"; - default_value = "12"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER column_width - { - parameter_name = "column_width"; - type = "integer"; - default_value = "8"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER clk_mhz - { - parameter_name = "clk_mhz"; - type = "integer"; - default_value = "120"; - editable = "1"; - tooltip = ""; - } - } - } - } - } - } - } - } - ASSOCIATED_FILES - { - Add_Program = "the_wizard_ui"; - Edit_Program = "the_wizard_ui"; - Generator_Program = "cb_generator.pl"; - } -} Index: trunk/syn/sdram_ctrl/cb_generator.pl =================================================================== --- trunk/syn/sdram_ctrl/cb_generator.pl (revision 7) +++ trunk/syn/sdram_ctrl/cb_generator.pl (nonexistent) @@ -1,1159 +0,0 @@ -# | file: cb_generator.pl -# | -# | This SOPC Builder Generator program is provided by -# | the Component Builder application. It is copied -# | straight across and is data-driven from its command -# | line arguments and the PTF files referenced. -# | -# | Its purpose is to construct an HDL "wrapper" for -# | a particular instance of a particular SOPC Builder -# | peripheral. This wrapper resolves the instance -# | name and any HDL parameterization. -# | -# +------------------------------------------- - - - -# +------------------------------------------- -# | - -use strict; -use format_conversion_utils; -use ptf_parse; -use wiz_utils; -use europa_all; -use run_system_command_utils; - -# | -# +------------------------------------------- - - - -# +------------------------------------------- -# | -# | first pass: include all of generator_libarary.pm RIGHT HERE. -# | dvb04.08.02 -# | then prune down to actual functionality. -# | -# | TODO: Rewrite this whole file into something readable -# | this is much more confusing than I'm comfortable with. dvb04. -# | (though it does seem to work.) -# | - -my $DEBUG_DEFAULT_GEN = 1; - -#This is the global hash of arguments passed in by the generator program - -my $generator_hr = { - wrapper_args => { - make_wrapper => 0, - top_module_name => "", - simulate_hdl => 1, - ports => "", - }, - class_ptf_hr => "", - module_ptf_hr => "", - system_ptf_hr => "", - language => "", - external_args => "", - external_args_hr => "", - project_path_widget => "__PROJECT_DIRECTORY__", - generator_mode => "silent", - }; - - -sub generator_print_verbose -{ - my ($info) = (@_); - - if($generator_hr->{generator_mode} eq "verbose"){ - print("cb_generator.pl: ".$info); - } -} - -sub generator_enable_mode -{ - my ($mode) = (@_); - $generator_hr->{generator_mode} = $mode; -} - -sub generator_get_system_ptf_handle -{ - return $generator_hr->{system_ptf_hr}; -} - -sub generator_get_language -{ - return $generator_hr->{language}; -} - -sub generator_get_class_ptf_handle -{ - return $generator_hr->{class_ptf_hr}; -} - -sub default_ribbit -{ - my ($arg) = (@_); - &ribbit("\n\n--Error: default_gen_lib: $arg\n"); -} - - -sub _copy_files -{ - my ($dest_dir, $source_dir, @files) = (@_); - my $function_name; - - #validate args - &default_ribbit("No target dir for function copy_files!") - unless ($dest_dir ne ""); - - &default_ribbit("No source dir for function copy_files!") - unless ($source_dir ne ""); - - &default_ribbit("No files for function copy_files!") - unless (@files != 0); - - - #check for valid directories - opendir (SDIR, $source_dir) or - &default_ribbit("can't open $source_dir !"); - - opendir (DDIR, $dest_dir) or - &default_ribbit("can't open $dest_dir !"); - - - foreach my $source_file(@files){ - # | - # | Separate out the source subdir and the source filename - # | - my $source_subdir = ""; - my $source_filename = $source_file; - - if($source_filename =~ /^(.*)\/(.*)$/) # break on last slash - { - $source_subdir = "/$1"; # embed its leading slash, for concatty - $source_filename = $2; - } - - my $source_fullpath = "$source_dir$source_subdir/$source_filename"; - my $dest_fullpath = "$dest_dir/$source_filename"; - - &Perlcopy($source_fullpath, $dest_fullpath); - &generator_print_verbose("Copying file: \"$source_fullpath\"" - . " to \"$dest_fullpath\".\n"); - } - - closedir (SDIR); - closedir (DDIR); -} - - -sub get_module_wrapper_arg_hash_from_system_ptf_file -{ - my $module_ptf_hr = $generator_hr->{module_ptf_hr}; - - my @list_of_sections = ("MASTER","SLAVE","PORT_WIRING"); - my @port_list; - foreach my $section(@list_of_sections){ - my $number = get_child_count($module_ptf_hr, $section); - - for(my $initial=0; $initial < $number; $initial++){ - - my $interface_section = get_child($module_ptf_hr, $initial, $section); - my $interface_section_name = get_data($interface_section); - - my $port_wiring_section; - if($section ne "PORT_WIRING"){ - $port_wiring_section = - get_child_by_path($module_ptf_hr, $section." ".$interface_section_name."/PORT_WIRING"); - }else{ - $port_wiring_section = - get_child_by_path($module_ptf_hr, $section); - } - my $num_ports = get_child_count($port_wiring_section, "PORT"); - foreach(my $port_count = 0; $port_count < $num_ports; $port_count++){ - my $port = get_child($port_wiring_section, $port_count, "PORT"); - - my %port_info_struct; - $port_info_struct{name} = get_data($port); - $port_info_struct{direction} = get_data_by_path($port, "direction"); - $port_info_struct{width} = get_data_by_path($port, "width"); - $port_info_struct{vhdl_record_name} = get_data_by_path($port, "vhdl_record_name"); - $port_info_struct{vhdl_record_type} = get_data_by_path($port, "vhdl_record_type"); - - push(@port_list, \%port_info_struct); - - } - } - } - $generator_hr->{wrapper_args}{ports} = \@port_list; -} - - -sub generator_make_module_wrapper -{ - my ($simulate_hdl, $top_module_name, $module_language) = (@_); - - &default_ribbit("generator_make_module_wrapper: no arg0 passed in for simulate_hdl\n") - if($simulate_hdl eq ''); - - &default_ribbit("generator_make_module_wrapper: no arg1 passed in for top_module_name\n") - unless($top_module_name); - - $generator_hr->{wrapper_args}{simulate_hdl} = $simulate_hdl; - $generator_hr->{wrapper_args}{top_module_name} = $top_module_name; - $generator_hr->{wrapper_args}{make_wrapper} = 1; - $generator_hr->{wrapper_args}{module_language} = $module_language; - -} - - - - -# | -# | recognize varous number forms, -# | return 'h0123abcd-ish. -# | -sub turn_anything_into_appropriate_string($$$$) - { - my ($value,$type,$editable,$module_language) = (@_); - - return $value if($value =~ /^\"/); # quoted string: unscathed - return $value if($type eq "string"); # string: anything is ok - - return $value if(!$editable); # and you know, if you can't change it, keep it! - - - # | - # | first, convert to a number - # | - my $base = 10; - my $n = $value; - my $width = 32; - my $number = 0; - - $value = lc($value); # lower case - - if($value =~ /^([0-9]*)\'([hbo])(.*)$/) - { - # | tick notation: AOK for verilog - if($module_language eq "verilog") - { - $number = $value; - } - # | - # | note: at this point, we could notice if the - # | result should be vhdl binary, and convert - # | to that, avoiding the precision-losing - # | integer intermediary - # | - # | (alternatively, we could use a binary string - # | always as the intermediate form, rather than - # | a precision-losing int.) - # | - else - { - $width = $1; - my $baseletter = $2; - my $digits = $3; - - if($baseletter eq "h") - { - $base = 16; - } - elsif($baseletter eq "b") - { - $base = 2; - } - elsif($baseletter eq "o") # must be - { - $base = 8; - } - - $digits =~ s/[ _-]//g; # crush out dividing value - - while(length($digits) > 0) - { - my $digit = substr($digits,0,1); - $digits = substr($digits,1); - my $digitvalue = hex($digit); # how handy - $number = $number * $base + $digitvalue; - } - } - } - elsif($value =~ /^0x(.*)$/) - { - $number = hex($1); - } - else # try for decimal - { - $number = int(1 * $value); - } - - # | - # | ok, we have a number. If our target type - # | is "std_logic_vector(this downto that)" - # | for tricky VHDL, we - # | must quote a binary string out of it. - # | - - if(($module_language eq "vhdl") and ($type =~ /^.*\((\d+) downto (\d+)\).*$/)) - { - my ($high_bit,$low_bit) = ($1,$2); - my $binary = ""; - for(my $bit = $low_bit; $bit <= $high_bit; $bit++) - { - $binary = ($number % 2) . $binary; - $number = int($number >> 1); - } - - $number = '"' . $binary . '"'; - } - - return $number; - } - -# -# return @array of vhdl libraries, if any, from the class.ptf -sub get_libraries() -{ - my $class_ptf = generator_get_class_ptf_handle(); - my @libraries; - my $libraries_ptf = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/LIBRARIES"); - - if($libraries_ptf) - { - my $library_count = get_child_count($libraries_ptf,"library"); - for(my $i = 0; $i < $library_count; $i++) - { - my $library_ptf = get_child($libraries_ptf,$i,"library"); - my $library_name = get_data($library_ptf); - push(@libraries,$library_name); - } - } - - return @libraries; -} - - - -sub _generator_make_module_wrapper -{ - - my $wrapper_args = $generator_hr->{wrapper_args}; - my $no_black_box = $wrapper_args->{simulate_hdl}; - my $top_module_name = $wrapper_args->{top_module_name}; - my $language = $generator_hr->{language}; - my @external_args = @{$generator_hr->{external_args}}; - my $module_ptf_hr = $generator_hr->{module_ptf_hr}; - - ### Build Module - my $project = e_project->new(@external_args); - my $top = $project->top(); - - # add the ports to the system module - my @ports; - - foreach my $port_hash(@{$wrapper_args->{ports}}){ - my $porto = e_port->new({ - name => $port_hash->{name}, - width => $port_hash->{width}, - direction => $port_hash->{direction}, - vhdl_record_name => $port_hash->{vhdl_record_name}, - vhdl_record_type => $port_hash->{vhdl_record_type} - }); - push(@ports, $porto); - } - $top->add_contents(@ports); - - - - - - # +---------------------------------------- - # | Get parameters from class.ptf - # | create @array of parameters, eacho - # | one like name=>, default=>, type=>, - # | - # | These are the definitions of parameters for - # | ANY instance of this module; we need to - # | have them in the "wrapee" module so that - # | when the system bus is knitted together - # | the parameter types can be properly used. - # | - # | (as it turns out, verilog doesnt need - # | them, but vhld does) - # | - # | dvb2004 - - - my @e_hdl_parameters; # list of e_parameters - - my $class_ptf = generator_get_class_ptf_handle(); - my $hdl_parameter_definitions_ptf = get_child_by_path($class_ptf,"CLASS/COMPONENT_BUILDER/HDL_PARAMETERS"); - - my @libraries = get_libraries(); - - my $hdl_parameter_count = get_child_count($hdl_parameter_definitions_ptf,"HDL_PARAMETER"); - - my $module_language = $generator_hr->{wrapper_args}{module_language}; - - for(my $i = 0; $i < $hdl_parameter_count; $i++) - { - my $a_parameter = get_child($hdl_parameter_definitions_ptf,$i,"HDL_PARAMETER"); - my $parameter_editable = get_data_by_path($a_parameter,"editable"); - if($parameter_editable) - { - my $boring_name = get_data($a_parameter); # legal guinevere-ized - my $name = get_data_by_path($a_parameter,"parameter_name"); # original HDL name - my $default = get_data_by_path($a_parameter,"default_value"); - my $type = get_data_by_path($a_parameter,"type"); - - $default = turn_anything_into_appropriate_string($default,$type,1,$module_language); - - my $a_parameter = e_parameter->new - ({ - name => $name, - default => $default, - type => $type - }); - - push (@e_hdl_parameters,$a_parameter); - } - } - - - - # | and @e_hdl_parameters is used below in the wrapee module - # +-------------------------------------------- - - # +-------------------------------------------- - # | Now, we build a "hdl_parameter_map", which is just - # | your basic hash table with keys (parameters) - # | and values (parameter values). - # | - # | these are the particular values for this instance. - # | - - my %hdl_parameter_map; - my $module_ptf = $generator_hr->{module_ptf_hr}; - my $hdl_parameters_ptf = - get_child_by_path($module_ptf,"WIZARD_SCRIPT_ARGUMENTS/hdl_parameters"); - - my $child_count = get_child_count($hdl_parameters_ptf); - - for(my $i = 0; $i < $child_count; $i++) - { - my $a_parameter = get_child($hdl_parameters_ptf,$i); - - my $boring_name = get_name($a_parameter); - my $value = get_data($a_parameter); - - # refer back to the original HDL name... - my $parameter_definition_ptf = get_child_by_path($hdl_parameter_definitions_ptf,"HDL_PARAMETER $boring_name"); - my $parameter_name = get_data_by_path($parameter_definition_ptf,"parameter_name"); - my $parameter_type = get_data_by_path($parameter_definition_ptf,"type"); - my $parameter_editable = get_data_by_path($parameter_definition_ptf,"editable"); - - $value = turn_anything_into_appropriate_string($value,$parameter_type,$parameter_editable,$module_language); - - # | - # | our internal _dummy assignment shows up here - # | without a corresponding hdl entry. we - # | ignore it. - # | - - if(($parameter_name ne "") and $parameter_editable) - { - $hdl_parameter_map{$parameter_name} = $value; - } - } - - my $wrapee_module; - $wrapee_module = e_module->new({ - name => $top_module_name, - contents => [@ports,@e_hdl_parameters], - do_black_box => 0, - do_ptf => 0, - _hdl_generated => 1, - _explicitly_empty_module => 1, - }); - - # VHDL Libraries, from PTF file... - $wrapee_module->add_vhdl_libraries(@libraries); - $top->add_vhdl_libraries(@libraries); - - - $top->add_contents ( - e_instance->new({ - module => $wrapee_module, - parameter_map => \%hdl_parameter_map - }), - ); - - $project->top()->do_ptf(0); - $project->do_write_ptf(0); - - - my $module_file = $project->_target_module_name().".v"; - $module_file = $project->_target_module_name().".vhd" - if($language eq "vhdl"); - - $module_file = $generator_hr->{project_path_widget}."/".$module_file; - &generator_set_files_in_system_ptf("Synthesis_HDL_Files", ($module_file)); - $project->output(); - - - # if you don't want a simulation model, you don't get a simulation model - if($no_black_box eq "0") - { - my $black_project = e_project->new(@external_args); - $black_project->_target_module_name($top_module_name); - my $black_top = $black_project->top(); - - - - $black_top->add_contents(@ports); - my $black_top_instance; - $black_top_instance = e_module->new({ - name => $wrapper_args->{top_module_name}."_bb", - contents => [@ports], - do_black_box => 1, - do_ptf => 0, - _hdl_generated => 0, - _explicitly_empty_module => 1, - }); - - $black_top->add_contents ( - e_instance->new({ - module => $black_top_instance, - }), - ); - - - - - $black_project->top()->do_ptf(0); - $black_project->do_write_ptf(0); - - my $black_module_file = $black_project->_target_module_name().".v"; - $black_module_file = $black_project->_target_module_name().".vhd" - if($language eq "vhdl"); - - - $black_module_file = $generator_hr->{project_path_widget}."/".$black_module_file; - &generator_set_files_in_system_ptf("Simulation_HDL_Files", ($black_module_file)); - -# &set_data_by_path($module_ptf_hr, "HDL_INFO/Simulation_HDL_Files", $black_module_file); - - - $black_project->output(); - } - -} - -#### -# Args: $file_type : "synthesis", "synthesis_only", "simulation" -# @file_list : an array of files. This list of files is assumed to be relative to the -# component's directory - - -my $decoder_ring_hr = { - quartus_only => { - copy => 1, - copy_to => "project", - ptf_set => 0, - }, - simulation_only => { - copy => 1, - copy_to => "simulation", - ptf_set => 1, - ptf_section => "Simulation_HDL_Files", - }, - simulation_and_quartus => { - copy => 1, - copy_to => "project", - ptf_set => 1, - ptf_section => "Synthesis_HDL_Files", - }, - precompiled_simulation_files => { - copy => 0, - ptf_set => 1, - ptf_section => "Precompiled_Simulation_Library_Files", - }, - }; - - - - -sub generator_copy_files_and_set_system_ptf -{ - my ($hdl_section, @file_list) = (@_); - - my $ptf_path_prefix = ""; - my $external_args_hr = $generator_hr->{external_args_hr}; - my @new_file_array; - - #validate first - my $decoder_hash = $decoder_ring_hr->{$hdl_section}; - &default_ribbit("generator_copy_files_and_set_system_ptf: No understood HDL section passed in for first arg\n") - unless($decoder_ring_hr->{$hdl_section} ne ""); - - &generator_print_verbose("generator_copy_files_and_set_system_ptf: copying files for section ".$hdl_section."\n"); - - #copy second - my @new_file_array; - - # If we need to copy over some files, then we need to make sure we are - # keeping track of what files we copy over. - # Otherwise, we just need to keep track of the files that the user has asked to copy over - # and use these instead. - if($decoder_hash->{copy}){ - my $copy_to_location; - my $copy_from_location; - - if($decoder_hash->{copy_to} eq "project"){ - $copy_to_location = $external_args_hr->{system_directory}; - }elsif($decoder_hash->{copy_to} eq "simulation"){ - $copy_to_location = $external_args_hr->{system_sim_dir}; - }else{ - &default_ribbit("generator_copy_files_and_set_system_ptf: No understood copy files to location\n"); - } - - $copy_from_location = $external_args_hr->{class_directory}; - @new_file_array = &generator_copy_files($copy_to_location, $copy_from_location, @file_list); - }else{ - @new_file_array = @file_list; - } - - #scribble on PTF hash last - if($decoder_hash->{ptf_set}){ - - if($decoder_hash->{copy_to} eq "project"){ - foreach my $file(@new_file_array){ - $file =~ s/^.*\/(.*?)$/$1/; - $file = $generator_hr->{project_path_widget}."/".$file; - } - } - &generator_print_verbose("generator_copy_files_and_set_system_ptf: setting system PTF file in section ".$hdl_section."\n"); - if($decoder_hash->{ptf_section} eq "Precompiled_Simulation_Library_Files"){ - @new_file_array = map{$external_args_hr->{class_directory}."/".$_} @new_file_array; - } - &generator_set_files_in_system_ptf($decoder_hash->{ptf_section}, @new_file_array); - } -} - - - -#### -# Name: generator_set_files_in_system_ptf -# Args: $hdl_section -# @list_of_files -# Returns: 1 or 0 -# Purpose: This is an internal function used to set files in the module's section in the system PTF file -# -sub generator_set_files_in_system_ptf -{ - my ($hdl_section, @list_of_files) = (@_); - - my $file_list = join(",", @list_of_files); - my $previous_data; - - &generator_print_verbose("setting HDL_INFO/".$hdl_section." in system PTF file with ".$file_list."\n"); - my $previous_data = &get_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section); - if($previous_data){ - $file_list = $previous_data . ", $file_list"; # spr 132177 - # swapping order, dvb 2003 - } - &set_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section, $file_list); -} - -#### -# Name: generator_copy_files -# Args: $target_directory -# $source_directory -# @list_of_files -# Returns: The list of files which has been copied (suitable for framing!) -# Purpose: This is an internal function used to copy files around in the generator program. -# -sub generator_copy_files -{ - my ($target_directory, $source_directory, @list_of_files) = (@_); - - my @new_file_array; - - foreach my $file_name(@list_of_files){ - $file_name =~ s|\\|\/|g; - if($file_name =~ /\*\.*/){ - $file_name =~ s/\*/$1/; - my @found_list = &_find_all_dir_files_with_ext($source_directory, $file_name); - push(@new_file_array, @found_list); - }else{ - &generator_print_verbose("Copying: ".$file_name."\n"); - push(@new_file_array, $file_name); - } - } - - &_copy_files($target_directory, $source_directory, @new_file_array); - return @new_file_array; -} - - - -sub _find_all_dir_files_with_ext -{ - my ($dir, - $ext) = (@_); - - opendir (DIR, $dir) or - &default_ribbit("can't open $dir !"); - - my @all_files = readdir(DIR); - my @new_file_list; - - - foreach my $file (@all_files){ - if($file =~ /^.*($ext)$/){ - push(@new_file_list, $file); - } - } - - return @new_file_list; -} - -#### -# Name: generator_begin -# Args: Array of generator program launcher args -# Returns: A hash reference to the module's section in the system PTF file -# Purpose: This is the first subroutine a user should call before running the rest of their -# generator program. -# - -sub generator_begin -{ - my @external_args = (@_); - - my ($external_args_hr, - $temp_user_defined, - $temp_db_Module, - $temp_db_PTF_File) = Process_Wizard_Script_Arguments("", @external_args); - - &generator_print_verbose("generator_begin: initializing\n"); - - $generator_hr->{external_args_hr} = $external_args_hr; - $generator_hr->{external_args} = \@external_args; - - # open up class.ptf and - $generator_hr->{class_ptf_hr} = new_ptf_from_file($external_args_hr->{class_directory}."/class.ptf"); - - # get the system.ptf - $generator_hr->{system_ptf_hr} = new_ptf_from_file($external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"); - $generator_hr->{module_ptf_hr} = &get_child_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/MODULE $external_args_hr->{target_module_name}"); - my $class_name = get_data_by_path($generator_hr->{module_ptf_hr}, "class"); - - # find the default generator section - $generator_hr->{language} = get_data_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/WIZARD_SCRIPT_ARGUMENTS/hdl_language"); - - # get some wrapper settings - &get_module_wrapper_arg_hash_from_system_ptf_file(); - - # clear system ptf's HDL section - &delete_child($generator_hr->{module_ptf_hr}, "HDL_INFO"); - - return $generator_hr->{module_ptf_hr}; -} - -#### -# Name: generator_end -# Args: none -# Returns: nothing -# Purpose: This is the last subroutine a user should call from their generator program. -# Not calling this subroutine will make you very sad... =< -# - -sub generator_end -{ - # o.k., time to make the wrapper and output it. - if($generator_hr->{wrapper_args}{make_wrapper}){ - &_generator_make_module_wrapper(); - } - - - my $external_args_hr = $generator_hr->{external_args_hr}; - my $ptf_file_name = $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"; - &generator_print_verbose("generator_end: writing PTF file ".$external_args_hr->{system_name}.".ptf to ".$external_args_hr->{system_directory}."\n"); - - default_ribbit("Cannot write PTF file ".$ptf_file_name."!\n") - unless(&write_ptf_file($generator_hr->{system_ptf_hr}, $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf")); -} - -sub generator_end_read_module_wrapper_string -{ - my $language = &generator_get_language(); - my $ls; - - if($language =~ /vhdl/){ - $ls = ".vhd"; - }elsif($language =~ /verilog/){ - $ls = ".v"; - }else{ - &ribbit("generator_end_read_module_wrapper_string invoked with unkown language"); - } - my $system_dir = $generator_hr->{external_args_hr}->{system_directory}; - my $module_name = $generator_hr->{external_args_hr}->{target_module_name}; - - my $file = $system_dir."/".$module_name.$ls; - &generator_print_verbose("generator library reading file into string: $file\n"); - - open (FILE,"<$file") or ribbit "cannot open file ($file) ($!)\n"; - my $return_string; - while ()
- {
- $return_string .= $_;
- }
- close (FILE);
- return($return_string);
-}
-
-sub generator_end_write_module_wrapper_string
-{
- my $string = shift or ribbit "no string specified\n";
-
- my $language = &generator_get_language();
- my $ls;
-
- print $language;
-
- if($language =~ /vhdl/){
- $ls = ".vhd";
- }elsif($language =~ /verilog/){
- $ls = ".v";
- }else{
- &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
- }
- my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
- my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
-
- my $file = $system_dir."/".$module_name.$ls;
- &generator_print_verbose("generator library writing string into file: $file\n");
-
- open (FILE,">$file") or ribbit "cannot open file ($file) ($!)\n";
- print FILE $string;
- close (FILE);
-}
-# end of generator_library.pm
-
-
-
-
-
-#
-#
-#
-#
-# ---------------------------------------------------------------------
-
-# +----------------------------------------------------
-# | emit_system_h
-# |
-# | if "is_cpu", attempt to emit a system.h
-# | memory map.
-# |
-
-sub emit_system_h($$$)
- {
- my ($sopc_directory,$master,$system_ptf) = (@_);
-
- # |
- # | Build a system.h file for masters.
- # |
-
-
-# as of quartus 5.0, we prefer gtf-generate in sopc_builder directly
-
- my $gtf_generate = "$sopc_directory/bin/gtf-generate";
- my $gtf_filename = "$sopc_directory/bin/gtf/system.h.gtf";
-
- if(! -f $gtf_generate)
- {
- # but if sopc_builder is missing it for whatever reason,
- # try the one in sopc_kit_nios2
-
- my $sopc_kit_nios2 = $ENV{SOPC_KIT_NIOS2};
- if($sopc_kit_nios2 ne "")
- {
- $gtf_generate = "$sopc_kit_nios2/bin/gtf-generate";
- $gtf_filename = "$sopc_kit_nios2/bin/gtf/system.h.gtf";
- }
- }
-
- # |
- # | xml template
- # |
-
- my $stf_template = <
-
-
-
-
-EOP
-
- # |
- # | THINK
- # |
-
- my $output_directory = "./${master}_map";
- my $project_name = "ignored";
- my $stf_filename = "./${master}_project.stf";
-
- # |
- # | build up template variables
- # |
-
- my %template_vars;
- $template_vars{date} = fcu_date_time();
- $template_vars{whoami} = $0;
- $template_vars{project_name} = $project_name;
- $template_vars{system_ptf} = $system_ptf;
- $template_vars{output_directory} = $output_directory;
- $template_vars{master} = $master;
-
- # |
- # | poke in the values to the template
- # |
-
- foreach my $key (sort(keys(%template_vars)))
- {
- $stf_template =~ s/--$key--/$template_vars{$key}/gs;
- }
-
- ## debug print $stf_template;
-
- # |
- # | write out the stf file, so we can soon use it
- # |
-
- fcu_write_file($stf_filename,$stf_template);
-
- # |
- # | and use it
- # |
-
- if(-e $gtf_generate && -e $gtf_filename)
- {
-
- my $generate_cmd = $gtf_generate;
-
- $generate_cmd .= " --output-directory=$output_directory";
- $generate_cmd .= " --gtf=$gtf_filename";
- $generate_cmd .= " --stf=$stf_filename";
-
- r_system($sopc_directory,$generate_cmd);
-
- # |
- # | done with it
- # |
-
- r_system($sopc_directory,"rm $stf_filename");
-
- fcu_print_command("Generated memory map \"$output_directory/system.h\"");
- }
- else
- {
- fcu_print_command("Warning: did NOT emit system.h for $master");
- }
-
-
-
-
- }
-
-
-sub r_system($$)
- {
- my ($sopc_directory,$cmd) = (@_);
- fcu_print_command($cmd);
- return Run_Command_In_Unix_Like_Shell($sopc_directory,$cmd);
- }
-
-
-
-
-
-
-
-# +------------------------------------------
-# | synthesis and simulation files are are
-# | listed in CLASS/CB_GENERATOR/HDL_FILES.
-# |
-
-sub get_synthesis_files($)
- {
- my ($class_ptf) = (@_);
- my $synthesis_files = "";
- my $simulation_files = "";
-
- my $hdl_files = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/HDL_FILES");
- my $child_count = get_child_count($hdl_files);
- for(my $i = 0; $i < $child_count; $i++)
- {
- my $hdl_file = get_child($hdl_files,$i);
- if(get_name($hdl_file) eq "FILE")
- {
- my $filename = get_data_by_path($hdl_file,"filepath");
- my $use_in_synthesis = get_data_by_path($hdl_file,"use_in_synthesis");
- my $use_in_simulation = get_data_by_path($hdl_file,"use_in_simulation");
-
- if($use_in_synthesis)
- {
- $synthesis_files .= ", " if $synthesis_files;
- $synthesis_files .= $filename;
- }
-
- if($use_in_simulation)
- {
- $simulation_files .= ", " if $simulation_files;
- $simulation_files .= $filename;
- }
- }
- }
-
- return $synthesis_files;
- }
-
-
-
-
-
-
-
-
-sub main
- {
-
- push(@ARGV,"--verbose=1") if 0;
- my %args = fcu_parse_args(@ARGV);
-
- if(0)
- {
- foreach my $key (sort(keys(%args)))
- {
- print("--$key = $args{$key} \n");
- }
- }
-
- # |
- # | get the arguments we care about
- # |
-
- my $class_dir = fcu_get_switch(\%args,"module_lib_dir");
-
-
- my $target_module_name = fcu_get_switch(\%args,"target_module_name");
- my $system_name = fcu_get_switch(\%args,"system_name");
- my $sopc_directory = fcu_get_switch(\%args,"sopc_directory");
-
- # |
- # | preflight the arguments a little
- # |
-
- my $error_count = 0;
-
- my $class_ptf_path = "$class_dir/class.ptf";
- if(!-f $class_ptf_path)
- {
- print "error: no class.ptf at \"$class_dir\"\n";
- $error_count++;
- }
-
- die "$error_count errors" if($error_count > 0);
-
- # +-------------------------------------------
- # | ok, let us get to work
- # |
-
-
- my $class_ptf = new_ptf_from_file($class_ptf_path);
-
- # |
- # | emit system.h for this module
- # | TODO iff Is_CPU i guess.
- # |
-
- my $do_emit_system_h = get_data_by_path($class_ptf,
- "CLASS/CB_GENERATOR/emit_system_h");
- if($do_emit_system_h)
- {
- emit_system_h($sopc_directory,
- $target_module_name,
- "./$system_name.ptf");
- }
-
- my $top_module_name = get_data_by_path($class_ptf,
- "CLASS/CB_GENERATOR/top_module_name");
- my $file_name = "";
-
- # | stored as file_name.v:module_name, so we break it open
- if($top_module_name =~ /^(.*):(.*)$/)
- {
- $file_name = $1;
- my $module_name = $2;
- $top_module_name = $module_name;
- }
-
- # | language of this particular module...
-
- my $module_language = "verilog";
- if($file_name =~ /^.*\.vhd$/)
- {
- $module_language = "vhdl";
- }
-
- # |
- # | consult the CB_GENERATOR/HDL_FILES section regarding
- # | where our HDL files for synthesis are.
- # |
-
-
- my $synthesis_files = get_synthesis_files($class_ptf);
-
-
- my $instantiate_in_system_module = get_data_by_path($class_ptf,
- "CLASS/MODULE_DEFAULTS/SYSTEM_BUILDER_INFO/Instantiate_In_System_Module");
-
-
-
- if($instantiate_in_system_module)
- {
- generator_enable_mode ("terse");
-
-
- generator_begin (@ARGV);
-
-
- generator_make_module_wrapper(1,$top_module_name,$module_language);
-
- generator_copy_files_and_set_system_ptf
- (
- "simulation_and_quartus",
- split(/ *, */,$synthesis_files)
-# "$synthesis_files"
- );
-
- generator_end ();
- }
-
- exit (0);
- }
-
-$| = 1; # always polite to flush.
-main()
-
-# end of file
Index: trunk/syn/sdram_ctrl/hdl/sdram_ctrl.vhd
===================================================================
--- trunk/syn/sdram_ctrl/hdl/sdram_ctrl.vhd (revision 7)
+++ trunk/syn/sdram_ctrl/hdl/sdram_ctrl.vhd (nonexistent)
@@ -1,440 +0,0 @@
-------------------------------------------------------------------
---
--- sdram_ctrl.vhd
---
--- Module Description:
--- SDRAM small&fast controller
---
---
--- To Do:
--- configurable times
--- nios simulation support
---
--- Author(s):
--- Aleksey Kuzmenok, ntpqa@opencores.org
---
-------------------------------------------------------------------
---
--- Copyright (C) 2006 Aleksey Kuzmenok and OPENCORES.ORG
---
--- This module is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This module is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this software; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
---
-------------------------------------------------------------------
--- Test results
--- FPGA SDRAM CLK (not less than)
--- EP1C12XXXXC8 MT48LC4M32B2TG-7:G 125 MHz
--- EP1C6XXXXC8 IS42S16100C1-7TL 125 MHz
---
-------------------------------------------------------------------
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity sdram_ctrl is
- generic(
- DATA_WIDTH: integer:=32;
- BANK_WIDTH: integer:=4;
- ROW_WIDTH: integer:=12;
- COLUMN_WIDTH: integer:=8;
-
- clk_MHz: integer:=120
- );
- port(
- signal clk : IN STD_LOGIC;
- signal reset : IN STD_LOGIC;
-
- -- IMPORTANT: for this Avalon(tm) interface
- -- 'Minimum Arbitration Shares'=1
- -- 'Max Pending Read Transactions'=9
- signal avs_nios_chipselect : IN STD_LOGIC;
- signal avs_nios_address : IN STD_LOGIC_VECTOR ((BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH-1) DOWNTO 0);
- signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0);
- signal avs_nios_writedata : IN STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal avs_nios_write : IN STD_LOGIC;
- signal avs_nios_read : IN STD_LOGIC;
- signal avs_nios_waitrequest : OUT STD_LOGIC;
- signal avs_nios_readdata : OUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal avs_nios_readdatavalid : OUT STD_LOGIC;
-
- -- global export signals
- signal sdram_cke : OUT STD_LOGIC; -- This pin has fixed state '1'
- signal sdram_ba : OUT STD_LOGIC_VECTOR ((BANK_WIDTH-1) DOWNTO 0);
- signal sdram_addr : OUT STD_LOGIC_VECTOR ((ROW_WIDTH-1) DOWNTO 0);
- signal sdram_cs_n : OUT STD_LOGIC; -- This pin has fixed state '0'
- signal sdram_ras_n : OUT STD_LOGIC;
- signal sdram_cas_n : OUT STD_LOGIC;
- signal sdram_we_n : OUT STD_LOGIC;
- signal sdram_dq : INOUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
- signal sdram_dqm : OUT STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0)
- );
-end sdram_ctrl;
-
-architecture behaviour of sdram_ctrl is
-
- CONSTANT FIFO_WIDTH: integer:=BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
-
- CONSTANT MODE: std_logic_vector(11 downto 0):="000000110000"; -- 1 word burst, CAS latency=3
- -- Only two times are configurable
- -- tINIT delay between powerup and load mode register = 100 us
- -- tREF refresh period = 15.625 us (64ms/4096rows)
- CONSTANT INIT_PAUSE_CLOCKS: integer:=(clk_MHz*10000)/91; -- 109.9 us just to be on the save side
- CONSTANT REFRESH_PERIOD_CLOCKS: integer:=(clk_MHz*1000)/65; -- 15.384 us the same purpose
- CONSTANT CAS_LATENCY: integer:=3; -- other latencies weren't been tested!
-
- COMPONENT scfifo
- GENERIC (
- add_ram_output_register : STRING;
- intended_device_family : STRING;
- lpm_numwords : NATURAL;
- lpm_showahead : STRING;
- lpm_type : STRING;
- lpm_width : NATURAL;
- lpm_widthu : NATURAL;
- overflow_checking : STRING;
- underflow_checking : STRING;
- use_eab : STRING
- );
- PORT (
- rdreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
- wrreq : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
- full : OUT STD_LOGIC
- );
- END COMPONENT;
-
- -- If you ask me why there are so many states, I'll answer that all times are fixed.
- -- The top speed for MT48LC4M32B2TG-7:G is 7 ns, therefore all times were based on it.
- -- tRP PRECHARGE command period = 3 clocks
- -- tRFC AUTO REFRESH period = 10 clocks
- -- tMRD LOAD MODE REGISTER command to ACTIVE or REFRESH command = 2 clocks
- -- tRCD ACTIVE to READ or WRITE delay = 3 clocks
- -- tRAS ACTIVE to PRECHARGE command = 7 clocks
- -- tRC ACTIVE to ACTIVE command period = 10 clocks
- -- tWR2 Write recovery time = 2 clocks
- type states is (
- INIT0,INIT1,INIT2,INIT3,INIT4,INIT5,INIT6,INIT7,
- INIT8,INIT9,INIT10,INIT11,INIT12,INIT13,INIT14,INIT15,
- INIT16,INIT17,INIT18,INIT19,INIT20,INIT21,INIT22,INIT23,INIT24,
- REFRESH0,REFRESH1,REFRESH2,REFRESH3,REFRESH4,REFRESH5,REFRESH6,REFRESH7,
- REFRESH8,REFRESH9,REFRESH10,REFRESH11,REFRESH12,REFRESH13,REFRESH14,
- ACTIVE0,ACTIVE1,ACTIVE2,ACTIVE3,ACTIVE4,
- IDLE,READ0,WRITE0);
- signal operation: states;
-
- signal fifo_q: std_logic_vector((FIFO_WIDTH-1) downto 0);
-
- signal init_counter: unsigned(15 downto 0):=to_unsigned(INIT_PAUSE_CLOCKS,16);
- signal refresh_counter: unsigned(15 downto 0);
- signal active_counter: unsigned(2 downto 0);
- signal active_address: unsigned((BANK_WIDTH+ROW_WIDTH-1) downto 0);
-
- signal bank: std_logic_vector((sdram_ba'length-1) downto 0);
- signal row: std_logic_vector((sdram_addr'length-1) downto 0);
- signal column: std_logic_vector((COLUMN_WIDTH-1) downto 0);
- signal be: std_logic_vector((sdram_dqm'length-1) downto 0);
- signal data: std_logic_vector((sdram_dq'length-1) downto 0);
-
- signal do_init,do_refresh,do_active,read_is_active,ready,tRCD_not_expired: std_logic:='0';
-
- signal fifo_rdreq,fifo_empty: std_logic;
-
- signal read_latency: std_logic_vector(CAS_LATENCY downto 0);
-
- signal fifo_data: std_logic_vector((FIFO_WIDTH-1) downto 0);
- signal fifo_wrreq,fifo_wrfull: std_logic;
-
- signal i_command : STD_LOGIC_VECTOR(4 downto 0);
- CONSTANT NOP: STD_LOGIC_VECTOR(4 downto 0):="10111";
- CONSTANT ACTIVE: STD_LOGIC_VECTOR(4 downto 0):="10011";
- CONSTANT READ: STD_LOGIC_VECTOR(4 downto 0):="10101";
- CONSTANT WRITE: STD_LOGIC_VECTOR(4 downto 0):="10100";
- CONSTANT PRECHARGE: STD_LOGIC_VECTOR(4 downto 0):="10010";
- CONSTANT AUTO_REFRESH: STD_LOGIC_VECTOR(4 downto 0):="10001";
- CONSTANT LOAD_MODE_REGISTER: STD_LOGIC_VECTOR(4 downto 0):="10000";
-
- signal i_address : STD_LOGIC_VECTOR((sdram_addr'length-1) DOWNTO 0);
- signal i_bank : STD_LOGIC_VECTOR((sdram_ba'length-1) DOWNTO 0);
- signal i_dqm : STD_LOGIC_VECTOR((sdram_dqm'length-1) DOWNTO 0);
- signal i_data : STD_LOGIC_VECTOR((sdram_dq'length-1) DOWNTO 0);
- attribute ALTERA_ATTRIBUTE : string;
- attribute ALTERA_ATTRIBUTE of i_command : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_address : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_bank : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of i_data : signal is "FAST_OUTPUT_REGISTER=ON";
- attribute ALTERA_ATTRIBUTE of avs_nios_readdata : signal is "FAST_INPUT_REGISTER=ON";
-begin
- (sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n) <= i_command;
- sdram_addr <= i_address;
- sdram_ba <= i_bank;
- sdram_dqm <= i_dqm;
- sdram_dq <= i_data;
-
- fifo_data<=avs_nios_address & avs_nios_writedata & avs_nios_byteenable & avs_nios_write & avs_nios_read;
- fifo_wrreq<=(avs_nios_write or avs_nios_read) and avs_nios_chipselect and not fifo_wrfull;
-
- avs_nios_waitrequest<=fifo_wrfull;
-
- fifo_rdreq<=not fifo_empty and not do_refresh and not do_active and not read_is_active and ready;
-
- do_active<='0' when active_address=unsigned((fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)))) else '1';
- read_is_active<='1' when read_latency(CAS_LATENCY-1 downto 0)>"000" and fifo_q(1)='1' else '0';
- ready<='1' when operation=IDLE or operation=READ0 or operation=WRITE0 else '0';
-
- operation_machine:process(reset,clk)
- begin
- if reset='1'
- then
- operation<=INIT0;
- active_address<=(others=>'1');
- elsif rising_edge(clk)
- then
-
- bank<=fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length));
- row<=fifo_q((fifo_q'length-bank'length-1) downto (fifo_q'length-bank'length-row'length));
- column<=fifo_q((column'length+data'length+be'length+2-1) downto (data'length+be'length+2));
- data<=fifo_q((data'length+be'length+2-1) downto (be'length+2));
- be<=fifo_q((be'length+2-1) downto 2);
-
- case operation is
- when INIT0=>
- if do_init='1'
- then operation<=INIT1;row(10)<='1';
- end if;
- when INIT1=>operation<=INIT2;
- when INIT2=>operation<=INIT3;
- when INIT3=>operation<=INIT4;
- when INIT4=>operation<=INIT5;
- when INIT5=>operation<=INIT6;
- when INIT6=>operation<=INIT7;
- when INIT7=>operation<=INIT8;
- when INIT8=>operation<=INIT9;
- when INIT9=>operation<=INIT10;
- when INIT10=>operation<=INIT11;
- when INIT11=>operation<=INIT12;
- when INIT12=>operation<=INIT13;
- when INIT13=>operation<=INIT14;
- when INIT14=>operation<=INIT15;
- when INIT15=>operation<=INIT16;
- when INIT16=>operation<=INIT17;
- when INIT17=>operation<=INIT18;
- when INIT18=>operation<=INIT19;
- when INIT19=>operation<=INIT20;
- when INIT20=>operation<=INIT21;
- when INIT21=>operation<=INIT22;
- when INIT22=>operation<=INIT23;
- when INIT23=>operation<=INIT24;row<=MODE((row'length-1) downto 0);
- when INIT24=>operation<=IDLE;
-
- when REFRESH0=>operation<=REFRESH1;
- when REFRESH1=>operation<=REFRESH2;
- when REFRESH2=>operation<=REFRESH3;
- when REFRESH3=>operation<=REFRESH4;
- when REFRESH4=>operation<=REFRESH5;
- when REFRESH5=>operation<=REFRESH6;
- when REFRESH6=>operation<=REFRESH7;
- when REFRESH7=>operation<=REFRESH8;
- when REFRESH8=>operation<=REFRESH9;
- when REFRESH9=>operation<=REFRESH10;
- when REFRESH10=>operation<=REFRESH11;
- when REFRESH11=>operation<=REFRESH12;
- when REFRESH12=>operation<=REFRESH13;
- active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
- when REFRESH13=>operation<=REFRESH14;
- when REFRESH14=>operation<=IDLE;
-
- when ACTIVE0=>operation<=ACTIVE1;
- when ACTIVE1=>operation<=ACTIVE2;
- when ACTIVE2=>operation<=ACTIVE3;
- active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
- when ACTIVE3=>operation<=ACTIVE4;
- when ACTIVE4=>operation<=IDLE;
-
- when others=>
- if do_refresh='1'
- then
- if tRCD_not_expired='0' and operation=IDLE
- then operation<=REFRESH0;row(10)<='1';
- else operation<=IDLE;
- end if;
- elsif do_active='1'
- then
- if tRCD_not_expired='0' and operation=IDLE
- then operation<=ACTIVE0;row(10)<='1';
- else operation<=IDLE;
- end if;
- elsif fifo_empty='1'
- then
- operation<=IDLE;
- elsif fifo_q(1)='1' --write
- then
- if read_latency(CAS_LATENCY-1 downto 0)>"000"
- then operation<=IDLE;
- else operation<=WRITE0;
- end if;
- elsif fifo_q(0)='1' --read
- then
- operation<=READ0;
- end if;
- end case;
- end if;
- end process;
-
- control_latency:process(reset,clk)
- begin
- if reset='1'
- then
- read_latency<=(others=>'0');
- elsif rising_edge(clk)
- then
- read_latency<=std_logic_vector(unsigned(read_latency) SLL 1);
- if operation=READ0
- then read_latency(0)<='1';
- else read_latency(0)<='0';
- end if;
- end if;
- end process;
- latch_readdata:process(reset,clk)
- begin
- if reset='1'
- then
- avs_nios_readdata<=(others=>'0');
- avs_nios_readdatavalid<='0';
- elsif rising_edge(clk)
- then
- avs_nios_readdata<=sdram_dq;
- avs_nios_readdatavalid<=read_latency(CAS_LATENCY);
- end if;
- end process;
- initialization:process(reset,clk)
- begin
- if rising_edge(clk)
- then
- if init_counter>0
- then
- init_counter<=init_counter-1;
- else do_init<='1';
- end if;
- end if;
- end process;
- refreshing:process(clk,reset)
- begin
- if reset='1'
- then
- refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
- do_refresh<='0';
- elsif rising_edge(clk)
- then
- if refresh_counter=to_unsigned(0,refresh_counter'length)
- then refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
- do_refresh<='1';
- else refresh_counter<=refresh_counter-1;
- end if;
- if operation=REFRESH0 or operation=REFRESH5
- then do_refresh<='0';
- end if;
- end if;
- end process;
- active_period:process(reset,clk)
- begin
- if reset='1'
- then
- active_counter<=(others=>'0');
- tRCD_not_expired<='0';
- elsif rising_edge(clk)
- then
- if operation=ACTIVE3 or operation=REFRESH13
- then active_counter<=to_unsigned(5,active_counter'length);
- elsif active_counter>0
- then active_counter<=active_counter-1;
- end if;
- end if;
- if active_counter>0
- then tRCD_not_expired<='1';
- else tRCD_not_expired<='0';
- end if;
- end process;
- latch_controls:process(clk,reset)
- begin
- if reset='1'
- then
- i_command<=NOP;
- i_address<=(others=>'0');
- i_bank<=(others=>'0');
- i_dqm<=(others=>'0');
- i_data<=(others=>'Z');
- elsif rising_edge(clk)
- then
- i_command<=NOP;
- i_bank<=bank;
- i_address<=(others=>'0');
- i_address((column'length-1) downto 0)<=column;
- i_data<=(others=>'Z');
- i_dqm<=(others=>'0');
-
- case operation is
- when INIT1|REFRESH0|ACTIVE0 =>
- i_command<=PRECHARGE;
- i_address<=row;
- when INIT4|INIT14|REFRESH3 =>
- i_command<=AUTO_REFRESH;
- when INIT24=>
- i_command<=LOAD_MODE_REGISTER;
- i_address<=row;
- when ACTIVE3|REFRESH13 =>
- i_command<=ACTIVE;
- i_address<=row;
- when READ0 =>
- i_command<=READ;
- when WRITE0 =>
- i_command<=WRITE;
- i_dqm<=not be;
- i_data<=data;
- when OTHERS =>
- end case;
- end if;
- end process;
-
- fifo: scfifo
- GENERIC MAP (
- add_ram_output_register => "ON",
- intended_device_family => "Cyclone",
- lpm_numwords => 4,
- lpm_showahead => "ON",
- lpm_type => "scfifo",
- lpm_width => FIFO_WIDTH,
- lpm_widthu => 2,
- overflow_checking => "ON",
- underflow_checking => "ON",
- use_eab => "ON"
- )
- PORT MAP (
- rdreq => fifo_rdreq,
- aclr => reset,
- clock => clk,
- wrreq => fifo_wrreq,
- data => fifo_data,
- empty => fifo_empty,
- q => fifo_q,
- full => fifo_wrfull
- );
-end behaviour;
Index: sdram_ctrl/trunk/src/sdram_ctrl.vhd
===================================================================
--- sdram_ctrl/trunk/src/sdram_ctrl.vhd (nonexistent)
+++ sdram_ctrl/trunk/src/sdram_ctrl.vhd (revision 8)
@@ -0,0 +1,484 @@
+------------------------------------------------------------------
+--
+-- sdram_ctrl.vhd
+--
+-- Module Description:
+-- SDRAM small&fast controller
+--
+--
+-- To Do:
+-- multichipselect support done
+-- configurable times 50%
+-- nios simulation support
+--
+-- Author(s):
+-- Aleksey Kuzmenok, ntpqa@opencores.org
+--
+------------------------------------------------------------------
+--
+-- Copyright (C) 2006 Aleksey Kuzmenok and OPENCORES.ORG
+--
+-- This module is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This module is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this software; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+--
+------------------------------------------------------------------
+-- Hardware test results
+-- FPGA SDRAM CLK (not less than)
+-- EP1C12XXXXC8 MT48LC4M32B2TG-7:G 125 MHz
+-- EP1C6XXXXC8 IS42S16100C1-7TL 125 MHz
+--
+------------------------------------------------------------------
+-- History
+-- 22.10.2006 multichipselect functionaly tested
+-- 10.11.2006 first successful hardware test
+-- 07.12.2006 proved to be fully reliable
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+entity sdram_ctrl is
+ generic(
+ DATA_WIDTH: integer:=32;
+ CHIPSELECTS: integer:=1;
+ LOG2_OF_CS: integer:=0;
+ BANK_WIDTH: integer:=2;
+ ROW_WIDTH: integer:=12;
+ COLUMN_WIDTH: integer:=8;
+
+ MODE_REGISTER: integer:=48; -- 1 word burst, CAS latency=3
+
+ -- Only two times are configurable
+ -- tINIT delay between powerup and load mode register = 100 us
+ -- tREF refresh period = 15.625 us (64ms/4096rows)
+ clk_MHz: integer:=120;
+ t_INIT_uS: integer:=110; -- 109.9 us just to be on the save side
+ t_REF_nS: integer:=15384 -- 15.384 us the same purpose
+
+ );
+ port(
+ signal clk : IN STD_LOGIC;
+ signal reset : IN STD_LOGIC;
+
+ -- IMPORTANT: for this Avalon(tm) interface
+ -- 'Minimum Arbitration Shares'=1
+ -- 'Max Pending Read Transactions'=9
+ signal avs_nios_chipselect : IN STD_LOGIC;
+ signal avs_nios_address : IN STD_LOGIC_VECTOR ((LOG2_OF_CS+BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH-1) DOWNTO 0);
+ signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0);
+ signal avs_nios_writedata : IN STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal avs_nios_write : IN STD_LOGIC;
+ signal avs_nios_read : IN STD_LOGIC;
+ signal avs_nios_waitrequest : OUT STD_LOGIC;
+ signal avs_nios_readdata : OUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal avs_nios_readdatavalid : OUT STD_LOGIC;
+
+ -- global export signals
+ signal sdram_cke : OUT STD_LOGIC; -- This pin has the fixed state '1'
+ signal sdram_ba : OUT STD_LOGIC_VECTOR ((BANK_WIDTH-1) DOWNTO 0);
+ signal sdram_addr : OUT STD_LOGIC_VECTOR ((ROW_WIDTH-1) DOWNTO 0);
+ signal sdram_cs_n : OUT STD_LOGIC_VECTOR ((CHIPSELECTS-1) DOWNTO 0);
+ signal sdram_ras_n : OUT STD_LOGIC;
+ signal sdram_cas_n : OUT STD_LOGIC;
+ signal sdram_we_n : OUT STD_LOGIC;
+ signal sdram_dq : INOUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal sdram_dqm : OUT STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0)
+ );
+end sdram_ctrl;
+
+architecture behaviour of sdram_ctrl is
+
+ CONSTANT FIFO_WIDTH: integer:=LOG2_OF_CS+BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
+ CONSTANT BE_LOW_BIT: integer:=2;
+ CONSTANT DATA_LOW_BIT: integer:=(DATA_WIDTH/8)+2;
+ CONSTANT COL_LOW_BIT: integer:=DATA_WIDTH+(DATA_WIDTH/8)+2;
+ CONSTANT ROW_LOW_BIT: integer:=COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
+ CONSTANT BANK_LOW_BIT: integer:=ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
+ CONSTANT CS_LOW_BIT: integer:=BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
+
+ --CONSTANT MODE: std_logic_vector((sdram_addr'length-1) downto 0):=std_logic_vector(MODE_REGISTER((sdram_addr'length-1) downto 0));
+ CONSTANT INIT_PAUSE_CLOCKS: integer:=clk_MHz*t_INIT_uS;
+ CONSTANT REFRESH_PERIOD_CLOCKS: integer:=(clk_MHz*t_REF_nS)/1000;
+ CONSTANT CAS_LATENCY: integer:=3; -- other latencies weren't been tested!
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ rdreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
+ full : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ -- If you ask me why there are so many states, I'll answer that all times are fixed.
+ -- The top speed for MT48LC4M32B2TG-7:G is 7 ns, therefore all times were based on it.
+ -- tRP PRECHARGE command period = 3 clocks
+ -- tRFC AUTO REFRESH period = 10 clocks
+ -- tMRD LOAD MODE REGISTER command to ACTIVE or REFRESH command = 2 clocks
+ -- tRCD ACTIVE to READ or WRITE delay = 3 clocks
+ -- tRAS ACTIVE to PRECHARGE command = 7 clocks
+ -- tRC ACTIVE to ACTIVE command period = 10 clocks
+ -- tWR2 Write recovery time = 2 clocks
+ type states is (
+ INIT0,INIT1,INIT2,INIT3,INIT4,INIT5,INIT6,INIT7,
+ INIT8,INIT9,INIT10,INIT11,INIT12,INIT13,INIT14,INIT15,
+ INIT16,INIT17,INIT18,INIT19,INIT20,INIT21,INIT22,INIT23,INIT24,
+ REFRESH0,REFRESH1,REFRESH2,REFRESH3,REFRESH4,REFRESH5,REFRESH6,REFRESH7,
+ REFRESH8,REFRESH9,REFRESH10,REFRESH11,REFRESH12,REFRESH13,REFRESH14,
+ ACTIVE0,ACTIVE1,ACTIVE2,ACTIVE3,ACTIVE4,
+ IDLE,READ0,WRITE0);
+ signal operation: states;
+
+ signal fifo_q: std_logic_vector((FIFO_WIDTH-1) downto 0);
+
+ signal init_counter: unsigned(15 downto 0):=to_unsigned(INIT_PAUSE_CLOCKS,16);
+ signal refresh_counter: unsigned(15 downto 0);
+ signal active_counter: unsigned(2 downto 0);
+ signal active_address: unsigned((LOG2_OF_CS+BANK_WIDTH+ROW_WIDTH-1) downto 0);
+
+ signal chipselect: std_logic_vector(LOG2_OF_CS downto 0);
+ signal bank: std_logic_vector((sdram_ba'length-1) downto 0);
+ signal row: std_logic_vector((sdram_addr'length-1) downto 0);
+ signal column: std_logic_vector((COLUMN_WIDTH-1) downto 0);
+ signal data: std_logic_vector((sdram_dq'length-1) downto 0);
+ signal be: std_logic_vector((sdram_dqm'length-1) downto 0);
+
+ signal do_init,do_refresh,do_active,read_is_active,ready,tRCD_not_expired: std_logic:='0';
+
+ signal fifo_rdreq,fifo_empty: std_logic;
+
+ signal read_latency: std_logic_vector(CAS_LATENCY downto 0);
+
+ signal fifo_data: std_logic_vector((FIFO_WIDTH-1) downto 0);
+ signal fifo_wrreq,fifo_wrfull: std_logic;
+
+ signal i_command : STD_LOGIC_VECTOR(2 downto 0);
+ CONSTANT NOP: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="111";
+ CONSTANT ACTIVE: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="011";
+ CONSTANT READ: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="101";
+ CONSTANT WRITE: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="100";
+ CONSTANT PRECHARGE: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="010";
+ CONSTANT AUTO_REFRESH: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="001";
+ CONSTANT LOAD_MODE_REGISTER: STD_LOGIC_VECTOR((i_command'length-1) downto 0):="000";
+
+ signal i_address : STD_LOGIC_VECTOR((sdram_addr'length-1) DOWNTO 0);
+ signal i_chipselect: STD_LOGIC_VECTOR((sdram_cs_n'length-1) downto 0);
+ signal i_bank : STD_LOGIC_VECTOR((sdram_ba'length-1) DOWNTO 0);
+ signal i_dqm : STD_LOGIC_VECTOR((sdram_dqm'length-1) DOWNTO 0);
+ signal i_data : STD_LOGIC_VECTOR((sdram_dq'length-1) DOWNTO 0);
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of i_command : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_address : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_chipselect : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_bank : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_data : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of avs_nios_readdata : signal is "FAST_INPUT_REGISTER=ON";
+
+ function DECODE(hex: std_logic_vector; size: integer) return std_logic_vector is
+ variable result : std_logic_vector((size-1) downto 0);
+ begin
+ result:=(others=>'1');
+ result(to_integer(unsigned(hex))):='0';
+ return result;
+ end;
+begin
+ sdram_cke<='1';
+ (sdram_ras_n,sdram_cas_n,sdram_we_n) <= i_command;
+ sdram_cs_n <= i_chipselect;
+ sdram_addr <= i_address;
+ sdram_ba <= i_bank;
+ sdram_dqm <= i_dqm;
+ sdram_dq <= i_data;
+
+ fifo_data<=avs_nios_address & avs_nios_writedata & avs_nios_byteenable & avs_nios_write & avs_nios_read;
+ fifo_wrreq<=(avs_nios_write or avs_nios_read) and avs_nios_chipselect and not fifo_wrfull;
+
+ avs_nios_waitrequest<=fifo_wrfull;
+
+ fifo_rdreq<=not fifo_empty and not do_refresh and not do_active and not read_is_active and ready;
+
+ do_active<='0' when active_address=unsigned(fifo_q((fifo_q'length-1) downto (column'length+data'length+be'length+2))) else '1';
+ read_is_active<='1' when read_latency(CAS_LATENCY-1 downto 0)>"000" and fifo_q(1)='1' else '0';
+ ready<='1' when operation=IDLE or operation=READ0 or operation=WRITE0 else '0';
+
+ operation_machine:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ operation<=INIT0;
+ active_address<=(others=>'1');
+ elsif rising_edge(clk)
+ then
+ if CHIPSELECTS>1
+ then
+ chipselect<='0'&fifo_q((FIFO_WIDTH-1) downto CS_LOW_BIT);
+ bank<=fifo_q((CS_LOW_BIT-1) downto BANK_LOW_BIT);
+ else
+ chipselect<=(others=>'0');
+ bank<=fifo_q((FIFO_WIDTH-1) downto BANK_LOW_BIT);
+ end if;
+
+ row<= fifo_q((BANK_LOW_BIT-1) downto ROW_LOW_BIT);
+ column<=fifo_q((ROW_LOW_BIT-1) downto COL_LOW_BIT);
+ data<= fifo_q((COL_LOW_BIT-1) downto DATA_LOW_BIT);
+ be<= fifo_q((DATA_LOW_BIT-1) downto BE_LOW_BIT);
+
+ case operation is
+ when INIT0=>
+ if do_init='1'
+ then operation<=INIT1;row(10)<='1';
+ end if;
+ when INIT1=>operation<=INIT2;
+ when INIT2=>operation<=INIT3;
+ when INIT3=>operation<=INIT4;
+ when INIT4=>operation<=INIT5;
+ when INIT5=>operation<=INIT6;
+ when INIT6=>operation<=INIT7;
+ when INIT7=>operation<=INIT8;
+ when INIT8=>operation<=INIT9;
+ when INIT9=>operation<=INIT10;
+ when INIT10=>operation<=INIT11;
+ when INIT11=>operation<=INIT12;
+ when INIT12=>operation<=INIT13;
+ when INIT13=>operation<=INIT14;
+ when INIT14=>operation<=INIT15;
+ when INIT15=>operation<=INIT16;
+ when INIT16=>operation<=INIT17;
+ when INIT17=>operation<=INIT18;
+ when INIT18=>operation<=INIT19;
+ when INIT19=>operation<=INIT20;
+ when INIT20=>operation<=INIT21;
+ when INIT21=>operation<=INIT22;
+ when INIT22=>operation<=INIT23;
+ when INIT23=>operation<=INIT24;row<=std_logic_vector(to_unsigned(MODE_REGISTER,row'length));
+ when INIT24=>operation<=IDLE;
+
+ when REFRESH0=>operation<=REFRESH1;
+ when REFRESH1=>operation<=REFRESH2;
+ when REFRESH2=>operation<=REFRESH3;
+ when REFRESH3=>operation<=REFRESH4;
+ when REFRESH4=>operation<=REFRESH5;
+ when REFRESH5=>operation<=REFRESH6;
+ when REFRESH6=>operation<=REFRESH7;
+ when REFRESH7=>operation<=REFRESH8;
+ when REFRESH8=>operation<=REFRESH9;
+ when REFRESH9=>operation<=REFRESH10;
+ when REFRESH10=>operation<=REFRESH11;
+ when REFRESH11=>operation<=REFRESH12;
+ when REFRESH12=>operation<=REFRESH13;
+ active_address<=unsigned(fifo_q((fifo_q'length-1) downto ROW_LOW_BIT));
+ when REFRESH13=>operation<=REFRESH14;
+ when REFRESH14=>operation<=IDLE;
+
+ when ACTIVE0=>operation<=ACTIVE1;
+ when ACTIVE1=>operation<=ACTIVE2;
+ when ACTIVE2=>operation<=ACTIVE3;
+ active_address<=unsigned(fifo_q((fifo_q'length-1) downto ROW_LOW_BIT));
+ when ACTIVE3=>operation<=ACTIVE4;
+ when ACTIVE4=>operation<=IDLE;
+
+ when others=>
+ if do_refresh='1'
+ then
+ if tRCD_not_expired='0' and operation=IDLE
+ then operation<=REFRESH0;row(10)<='1';
+ else operation<=IDLE;
+ end if;
+ elsif do_active='1'
+ then
+ if tRCD_not_expired='0' and operation=IDLE
+ then operation<=ACTIVE0;row(10)<='1';
+ else operation<=IDLE;
+ end if;
+ elsif fifo_empty='1'
+ then
+ operation<=IDLE;
+ elsif fifo_q(1)='1' --write
+ then
+ if read_latency(CAS_LATENCY-1 downto 0)>"000"
+ then operation<=IDLE;
+ else operation<=WRITE0;
+ end if;
+ elsif fifo_q(0)='1' --read
+ then
+ operation<=READ0;
+ end if;
+ end case;
+ end if;
+ end process;
+
+ control_latency:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ read_latency<=(others=>'0');
+ elsif rising_edge(clk)
+ then
+ read_latency<=std_logic_vector(unsigned(read_latency) SLL 1);
+ if operation=READ0
+ then read_latency(0)<='1';
+ else read_latency(0)<='0';
+ end if;
+ end if;
+ end process;
+ latch_readdata:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ avs_nios_readdata<=(others=>'0');
+ avs_nios_readdatavalid<='0';
+ elsif rising_edge(clk)
+ then
+ avs_nios_readdata<=sdram_dq;
+ avs_nios_readdatavalid<=read_latency(CAS_LATENCY);
+ end if;
+ end process;
+ initialization:process(reset,clk)
+ begin
+ if rising_edge(clk)
+ then
+ if init_counter>0
+ then
+ init_counter<=init_counter-1;
+ else do_init<='1';
+ end if;
+ end if;
+ end process;
+ refreshing:process(clk,reset)
+ begin
+ if reset='1'
+ then
+ refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
+ do_refresh<='0';
+ elsif rising_edge(clk)
+ then
+ if refresh_counter=to_unsigned(0,refresh_counter'length)
+ then refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
+ do_refresh<='1';
+ else refresh_counter<=refresh_counter-1;
+ end if;
+ if operation=REFRESH0 or operation=REFRESH5
+ then do_refresh<='0';
+ end if;
+ end if;
+ end process;
+ active_period:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ active_counter<=(others=>'0');
+ tRCD_not_expired<='0';
+ elsif rising_edge(clk)
+ then
+ if operation=ACTIVE3 or operation=REFRESH13
+ then active_counter<=to_unsigned(5,active_counter'length);
+ elsif active_counter>0
+ then active_counter<=active_counter-1;
+ end if;
+ end if;
+ if active_counter>0
+ then tRCD_not_expired<='1';
+ else tRCD_not_expired<='0';
+ end if;
+ end process;
+ latch_controls:process(clk,reset)
+ begin
+ if reset='1'
+ then
+ i_command<=NOP;
+ i_address<=(others=>'0');
+ i_bank<=(others=>'0');
+ i_dqm<=(others=>'0');
+ i_data<=(others=>'Z');
+ i_chipselect<=(others=>'1');
+ elsif rising_edge(clk)
+ then
+ i_command<=NOP;
+ i_chipselect<=DECODE(chipselect,i_chipselect'length);
+ i_bank<=bank;
+ i_address<=(others=>'0');
+ i_address((column'length-1) downto 0)<=column;
+ i_data<=(others=>'Z');
+ i_dqm<=(others=>'0');
+
+ case operation is
+ when INIT1|REFRESH0|ACTIVE0 =>
+ i_command<=PRECHARGE;
+ i_address<=row;
+ i_chipselect<=(others=>'0');
+ when INIT4|INIT14|REFRESH3 =>
+ i_command<=AUTO_REFRESH;
+ i_chipselect<=(others=>'0');
+ when INIT24=>
+ i_command<=LOAD_MODE_REGISTER;
+ i_address<=row;
+ i_chipselect<=(others=>'0');
+ when ACTIVE3|REFRESH13 =>
+ i_command<=ACTIVE;
+ i_address<=row;
+ when READ0 =>
+ i_command<=READ;
+ when WRITE0 =>
+ i_command<=WRITE;
+ i_dqm<=not be;
+ i_data<=data;
+ when OTHERS =>
+ end case;
+ end if;
+ end process;
+
+ fifo: scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ intended_device_family => "Auto",
+ lpm_numwords => 4,
+ lpm_showahead => "ON",
+ lpm_type => "scfifo",
+ lpm_width => FIFO_WIDTH,
+ lpm_widthu => 2,
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => "ON"
+ )
+ PORT MAP (
+ rdreq => fifo_rdreq,
+ aclr => reset,
+ clock => clk,
+ wrreq => fifo_wrreq,
+ data => fifo_data,
+ empty => fifo_empty,
+ q => fifo_q,
+ full => fifo_wrfull
+ );
+end behaviour;
Index: sdram_ctrl/trunk/test_bench/sdram_ctrl_tb.vhd
===================================================================
--- sdram_ctrl/trunk/test_bench/sdram_ctrl_tb.vhd (nonexistent)
+++ sdram_ctrl/trunk/test_bench/sdram_ctrl_tb.vhd (revision 8)
@@ -0,0 +1,169 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity sdram_ctrl_tb is
+end sdram_ctrl_tb;
+
+architecture structure of sdram_ctrl_tb is
+ component pll
+ port (
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ e0 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ ) ;
+ end component ;
+ component sdram_ctrl is
+ port(
+ signal clk : IN STD_LOGIC;
+ signal reset : IN STD_LOGIC;
+
+ signal avs_nios_chipselect : IN STD_LOGIC;
+ signal avs_nios_address : IN STD_LOGIC_VECTOR (21 DOWNTO 0);
+ signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ signal avs_nios_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ signal avs_nios_write : IN STD_LOGIC;
+ signal avs_nios_read : IN STD_LOGIC;
+ signal avs_nios_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ signal avs_nios_readdatavalid : OUT STD_LOGIC;
+ signal avs_nios_waitrequest : OUT STD_LOGIC;
+
+ signal sdram_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
+ signal sdram_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ signal sdram_cas_n : OUT STD_LOGIC;
+ signal sdram_cke : OUT STD_LOGIC;
+ signal sdram_cs_n : OUT STD_LOGIC_VECTOR(0 downto 0);
+ signal sdram_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ signal sdram_dqm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ signal sdram_ras_n : OUT STD_LOGIC;
+ signal sdram_we_n : OUT STD_LOGIC
+ );
+ end component;
+
+ component mt48lc4m32b2 IS
+ PORT (
+ Dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => 'Z');
+ Addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
+ Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+ Clk : IN STD_LOGIC := '0';
+ Cke : IN STD_LOGIC := '1';
+ Cs_n : IN STD_LOGIC := '1';
+ Ras_n : IN STD_LOGIC := '1';
+ Cas_n : IN STD_LOGIC := '1';
+ We_n : IN STD_LOGIC := '1';
+ Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"
+ );
+ END component;
+
+ component cpu_simulator IS
+ PORT(clk, reset: IN std_logic;
+ address : OUT std_logic_vector(21 downto 0):=(others=>'0');
+ writedata : out std_logic_vector(31 downto 0):=(others=>'0');
+ byteenable : out std_logic_vector(3 downto 0):=(others=>'0');
+ write : out std_logic:='0';
+ read : out std_logic:='0';
+ readdata : in std_logic_vector(31 downto 0);
+ waitrequest : in std_logic;
+ readdatavalid : in std_logic
+ );
+ END component;
+
+ signal reset, clk_ok: std_logic;
+ signal run_nios_n : std_logic:='1';
+ signal clk,i_clk: std_logic:='0';
+
+ signal SDRAM_CLK : std_logic;
+ signal SDRAM_CKE : std_logic;
+ signal SDRAM_NCS : std_logic_vector(0 downto 0);
+ signal SDRAM_NRAS : std_logic;
+ signal SDRAM_NCAS : std_logic;
+ signal SDRAM_NWE : std_logic;
+ signal SDRAM_ADDRESS : std_logic_vector(11 downto 0);
+ signal SDRAM_BANK : std_logic_vector(1 downto 0);
+ signal SDRAM_DQM : std_logic_vector(3 downto 0);
+ signal SDRAM_DATA : std_logic_vector(31 downto 0);
+
+ signal address : std_logic_vector(21 downto 0);
+ signal writedata : std_logic_vector(31 downto 0):=(others=>'0');
+ signal byteenable : std_logic_vector(3 downto 0):=(others=>'0');
+ signal write : std_logic;
+ signal read : std_logic;
+ signal chipselect : std_logic:='1';
+ signal readdata : std_logic_vector(31 downto 0);
+ signal waitrequest : std_logic;
+ signal readdatavalid : std_logic;
+
+begin
+
+ reset<= not clk_ok;
+ run_nios_n<= reset after 140 us;
+
+ UUT: sdram_ctrl
+ port map(
+ clk => i_clk,
+ reset => reset,
+
+ avs_nios_chipselect => chipselect,
+ avs_nios_address => address,
+ avs_nios_byteenable => byteenable,
+ avs_nios_writedata => writedata,
+ avs_nios_write => write,
+ avs_nios_read => read,
+ avs_nios_readdata => readdata,
+ avs_nios_readdatavalid => readdatavalid,
+ avs_nios_waitrequest => waitrequest,
+
+ sdram_addr => SDRAM_ADDRESS,
+ sdram_ba => SDRAM_BANK,
+ sdram_cas_n => SDRAM_NCAS,
+ sdram_cke => SDRAM_CKE,
+ sdram_cs_n => SDRAM_NCS,
+ sdram_dq => SDRAM_DATA,
+ sdram_dqm => SDRAM_DQM,
+ sdram_ras_n => SDRAM_NRAS,
+ sdram_we_n => SDRAM_NWE
+ );
+
+ sdram:mt48lc4m32b2
+ PORT MAP(
+ Dq => SDRAM_DATA,
+ Addr => SDRAM_ADDRESS,
+ Ba => SDRAM_BANK,
+ Clk => SDRAM_CLK,
+ Cke => SDRAM_CKE,
+ Cs_n => SDRAM_NCS(0),
+ Ras_n => SDRAM_NRAS,
+ Cas_n => SDRAM_NCAS,
+ We_n => SDRAM_NWE,
+ Dqm => SDRAM_DQM
+ );
+
+ cpu: cpu_simulator
+ PORT MAP(
+ clk => i_clk,
+ reset => run_nios_n,
+ address => address,
+ writedata => writedata,
+ byteenable => byteenable,
+ write => write,
+ read => read,
+ readdata => readdata,
+ waitrequest => waitrequest,
+ readdatavalid => readdatavalid
+ );
+
+ U1 : pll
+ port map(
+ inclk0 => clk,
+ c0 => i_clk,
+ e0 => SDRAM_CLK,
+ locked =>clk_ok
+ );
+
+ clock_generator:process
+ begin
+ wait for 21 ns;
+ clk<= clk xor '1';
+ end process;
+end structure;
Index: sdram_ctrl/trunk/test_bench/mt48lc4m32b2.vhd
===================================================================
--- sdram_ctrl/trunk/test_bench/mt48lc4m32b2.vhd (nonexistent)
+++ sdram_ctrl/trunk/test_bench/mt48lc4m32b2.vhd (revision 8)
@@ -0,0 +1,1134 @@
+-----------------------------------------------------------------------------------------
+--
+-- File Name: MT48LC4M32B2.VHD
+-- Version: 2.0
+-- Date: January 24th, 2002
+-- Model: Behavioral
+-- Simulator: Model Technology
+--
+-- Dependencies: None
+--
+-- Email: modelsupport@micron.com
+-- Company: Micron Technology, Inc.
+-- Part Number: MT48LC4M32A2 (1Mb x 32 x 4 Banks)
+--
+-- Description: Micron 128Mb SDRAM
+--
+-- Limitation: - Doesn't check for 4096-cycle refresh
+--
+-- Note: - Set simulator resolution to "ps" accuracy
+--
+-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
+-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
+-- All rights researved
+--
+-- Rev Author Date Changes
+-- --- -------------------------- -------------------------------------
+-- 2.0 SH 01/24/2002 - Second Release
+-- Micron Technology Inc.
+--
+--------------------------------------------------------------------------
+
+LIBRARY IEEE;
+ USE IEEE.STD_LOGIC_1164.ALL;
+ USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+ USE IEEE.STD_LOGIC_ARITH.ALL;
+
+ENTITY mt48lc4m32b2 IS
+ GENERIC (
+ -- Timing Parameters for -75 (PC133) and CL = 3
+ tAC : TIME := 5.4 ns;
+ tHZ : TIME := 5.4 ns;
+ tOH : TIME := 2.7 ns;
+ tMRD : INTEGER := 2; -- 2 Clk Cycles
+ tRAS : TIME := 44.0 ns;
+ tRC : TIME := 66.0 ns;
+ tRCD : TIME := 20.0 ns;
+ tRFC : TIME := 66.0 ns;
+ tRP : TIME := 20.0 ns;
+ tRRD : TIME := 15.0 ns;
+ tWRa : TIME := 7.5 ns; -- Auto precharge
+ tWRm : TIME := 15.0 ns; -- Manual Precharge
+
+ tAH : TIME := 0.8 ns;
+ tAS : TIME := 1.5 ns;
+ tCH : TIME := 2.5 ns;
+ tCL : TIME := 2.5 ns;
+ tCK : TIME := 7.5 ns;
+ tDH : TIME := 0.8 ns;
+ tDS : TIME := 1.5 ns;
+ tCKH : TIME := 0.8 ns;
+ tCKS : TIME := 1.5 ns;
+ tCMH : TIME := 0.8 ns;
+ tCMS : TIME := 1.5 ns;
+
+ addr_bits : INTEGER := 12;
+ data_bits : INTEGER := 32;
+ col_bits : INTEGER := 8
+ );
+ PORT (
+ Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+ Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+ Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+ Clk : IN STD_LOGIC := '0';
+ Cke : IN STD_LOGIC := '1';
+ Cs_n : IN STD_LOGIC := '1';
+ Ras_n : IN STD_LOGIC := '1';
+ Cas_n : IN STD_LOGIC := '1';
+ We_n : IN STD_LOGIC := '1';
+ Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"
+ );
+END mt48lc4m32b2;
+
+ARCHITECTURE behave OF mt48lc4m32b2 IS
+ TYPE State IS (BST, NOP, PRECH, READ, WRITE);
+ TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
+ TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
+ TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+ TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+ TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF STD_LOGIC_VECTOR (Col_bits - 1 DOWNTO 0);
+ TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
+ SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL Active_enable, Aref_enable, Burst_term : STD_LOGIC := '0';
+ SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
+ SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : STD_LOGIC := '0';
+ SIGNAL Cas_latency_1, Cas_latency_2, Cas_latency_3 : STD_LOGIC := '0';
+ SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
+ SIGNAL Write_burst_mode : STD_LOGIC := '0';
+ SIGNAL Sys_clk, CkeZ : STD_LOGIC := '0';
+
+BEGIN
+ -- Strip the strength
+ Cs_in <= To_X01 (Cs_n);
+ Ras_in <= To_X01 (Ras_n);
+ Cas_in <= To_X01 (Cas_n);
+ We_in <= To_X01 (We_n);
+
+ -- Commands Decode
+ Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
+ Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
+ Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
+ Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
+ Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
+ Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
+ Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
+
+ -- Burst Length Decode
+ Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
+ Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
+ Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
+ Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
+
+ -- CAS Latency Decode
+ Cas_latency_1 <= NOT(Mode_reg(6)) AND NOT(Mode_reg(5)) AND Mode_reg(4);
+ Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
+ Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
+
+ -- Write Burst Mode
+ Write_burst_mode <= Mode_reg(9);
+
+ -- System Clock
+ int_clk : PROCESS (Clk)
+ BEGIN
+ IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN
+ CkeZ <= Cke;
+ END IF;
+ Sys_clk <= CkeZ AND Clk;
+ END PROCESS;
+
+ state_register : PROCESS
+ TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+ TYPE ram_pntr IS ACCESS ram_type;
+ TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
+ VARIABLE Bank0 : ram_stor;
+ VARIABLE Bank1 : ram_stor;
+ VARIABLE Bank2 : ram_stor;
+ VARIABLE Bank3 : ram_stor;
+ VARIABLE Row_index, Col_index : INTEGER := 0;
+ VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0');
+
+ VARIABLE Col_addr : Array4xCBV;
+ VARIABLE Bank_addr : Array4x2BV;
+ VARIABLE Dqm_reg0, Dqm_reg1 : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
+
+ VARIABLE Bank, Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+ VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+ VARIABLE Col_brst : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+ VARIABLE Row : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+ VARIABLE Col : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+ VARIABLE Burst_counter : INTEGER := 0;
+
+ VARIABLE Command : Array_state;
+ VARIABLE Bank_precharge : Array4x2BV;
+ VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
+ VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
+ VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
+ VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
+ VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
+ VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
+ VARIABLE RW_interrupt_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+ VARIABLE RW_interrupt_counter : Array4xI := (0 & 0 & 0 & 0);
+ VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
+
+ VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
+ VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
+ VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
+
+ -- Timing Check
+ VARIABLE MRD_chk : INTEGER := 0;
+ VARIABLE RFC_chk : TIME := 0 ns;
+ VARIABLE RRD_chk : TIME := 0 ns;
+ VARIABLE WR_chkm : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+ VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
+ VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
+ VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
+ VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
+
+ -- Initialize empty rows
+ PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR (1 DOWNTO 0); Row_index : INTEGER) IS
+ VARIABLE i, j : INTEGER := 0;
+ BEGIN
+ IF Bank = "00" THEN
+ IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
+ Bank0 (Row_index) := NEW ram_type; -- Open new row for access
+ FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
+ FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+ Bank0 (Row_index) (i) (j) := '0';
+ END LOOP;
+ END LOOP;
+ END IF;
+ ELSIF Bank = "01" THEN
+ IF Bank1 (Row_index) = NULL THEN
+ Bank1 (Row_index) := NEW ram_type;
+ FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+ FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+ Bank1 (Row_index) (i) (j) := '0';
+ END LOOP;
+ END LOOP;
+ END IF;
+ ELSIF Bank = "10" THEN
+ IF Bank2 (Row_index) = NULL THEN
+ Bank2 (Row_index) := NEW ram_type;
+ FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+ FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+ Bank2 (Row_index) (i) (j) := '0';
+ END LOOP;
+ END LOOP;
+ END IF;
+ ELSIF Bank = "11" THEN
+ IF Bank3 (Row_index) = NULL THEN
+ Bank3 (Row_index) := NEW ram_type;
+ FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+ FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+ Bank3 (Row_index) (i) (j) := '0';
+ END LOOP;
+ END LOOP;
+ END IF;
+ END IF;
+ END;
+
+ -- Burst Counter
+ PROCEDURE Burst_decode IS
+ VARIABLE Col_int : INTEGER := 0;
+ VARIABLE Col_vec, Col_temp : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+ BEGIN
+ -- Advance Burst Counter
+ Burst_counter := Burst_counter + 1;
+
+ -- Burst Type
+ IF Mode_reg (3) = '0' THEN
+ Col_int := conv_integer(Col) + 1;
+ Col_temp := CONV_STD_LOGIC_VECTOR(Col_int, col_bits);
+ ELSIF Mode_reg (3) = '1' THEN
+ Col_vec := CONV_STD_LOGIC_VECTOR(Burst_counter, col_bits);
+ Col_temp (2) := Col_vec (2) XOR Col_brst (2);
+ Col_temp (1) := Col_vec (1) XOR Col_brst (1);
+ Col_temp (0) := Col_vec (0) XOR Col_brst (0);
+ END IF;
+
+ -- Burst Length
+ IF Burst_length_2 = '1' THEN
+ Col (0) := Col_temp (0);
+ ELSIF Burst_length_4 = '1' THEN
+ Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
+ ELSIF Burst_length_8 = '1' THEN
+ Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
+ ELSE
+ Col := Col_temp;
+ END IF;
+
+ -- Burst Read Single Write
+ IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ END IF;
+
+ -- Data counter
+ IF Burst_length_1 = '1' THEN
+ IF Burst_counter >= 1 THEN
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ ELSIF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+ ELSIF Burst_length_2 = '1' THEN
+ IF Burst_counter >= 2 THEN
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ ELSIF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+ ELSIF Burst_length_4 = '1' THEN
+ IF Burst_counter >= 4 THEN
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ ELSIF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+ ELSIF Burst_length_8 = '1' THEN
+ IF Burst_counter >= 8 THEN
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ ELSIF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+ END IF;
+ END;
+
+ BEGIN
+ WAIT ON Sys_clk;
+ IF Sys_clk'event AND Sys_clk = '1' THEN
+ -- Internal Pipeline
+ Command(0) := Command(1);
+ Command(1) := Command(2);
+ Command(2) := Command(3);
+ Command(3) := NOP;
+
+ Col_addr(0) := Col_addr(1);
+ Col_addr(1) := Col_addr(2);
+ Col_addr(2) := Col_addr(3);
+ Col_addr(3) := (OTHERS => '0');
+
+ Bank_addr(0) := Bank_addr(1);
+ Bank_addr(1) := Bank_addr(2);
+ Bank_addr(2) := Bank_addr(3);
+ Bank_addr(3) := "00";
+
+ Bank_precharge(0) := Bank_precharge(1);
+ Bank_precharge(1) := Bank_precharge(2);
+ Bank_precharge(2) := Bank_precharge(3);
+ Bank_precharge(3) := "00";
+
+ A10_precharge(0) := A10_precharge(1);
+ A10_precharge(1) := A10_precharge(2);
+ A10_precharge(2) := A10_precharge(3);
+ A10_precharge(3) := '0';
+
+ -- Dqm pipeline for Read
+ Dqm_reg0 := Dqm_reg1;
+ Dqm_reg1 := Dqm;
+
+ -- Read or Write with Auto Precharge Counter
+ IF Auto_precharge (0) = '1' THEN
+ Count_precharge (0) := Count_precharge (0) + 1;
+ END IF;
+ IF Auto_precharge (1) = '1' THEN
+ Count_precharge (1) := Count_precharge (1) + 1;
+ END IF;
+ IF Auto_precharge (2) = '1' THEN
+ Count_precharge (2) := Count_precharge (2) + 1;
+ END IF;
+ IF Auto_precharge (3) = '1' THEN
+ Count_precharge (3) := Count_precharge (3) + 1;
+ END IF;
+
+ -- Read or Write Interrupt Counter
+ IF RW_interrupt_write (0) = '1' THEN
+ RW_interrupt_counter (0) := RW_interrupt_counter (0) + 1;
+ END IF;
+ IF RW_interrupt_write (1) = '1' THEN
+ RW_interrupt_counter (1) := RW_interrupt_counter (1) + 1;
+ END IF;
+ IF RW_interrupt_write (2) = '1' THEN
+ RW_interrupt_counter (2) := RW_interrupt_counter (2) + 1;
+ END IF;
+ IF RW_interrupt_write (3) = '1' THEN
+ RW_interrupt_counter (3) := RW_interrupt_counter (3) + 1;
+ END IF;
+
+ -- tMRD Counter
+ MRD_chk := MRD_chk + 1;
+
+ -- Auto Refresh
+ IF Aref_enable = '1' THEN
+ -- Auto Refresh to Auto Refresh
+ ASSERT (NOW - RFC_chk >= tRFC)
+ REPORT "tRFC violation during Auto Refresh"
+ SEVERITY WARNING;
+
+ -- Precharge to Auto Refresh
+ ASSERT ((NOW - RP_chk0 >= tRP) OR (NOW - RP_chk1 >= tRP) OR
+ (NOW - RP_chk2 >= tRP) OR (NOW - RP_chk3 >= tRP))
+ REPORT "tRP violation during Auto Refresh"
+ SEVERITY WARNING;
+
+ -- Precharge to Auto Refresh
+ ASSERT (Pc_b0 ='1' AND Pc_b1 = '1' AND Pc_b2 ='1' AND Pc_b3 = '1')
+ REPORT "All banks must be Precharge before Auto Refresh"
+ SEVERITY WARNING;
+
+ -- Load Mode Register to Auto Refresh
+ ASSERT (MRD_chk >= tMRD)
+ REPORT "tMRD violation during Auto Refresh"
+ SEVERITY WARNING;
+
+ -- Record current tRFC time
+ RFC_chk := NOW;
+ END IF;
+
+ -- Load Mode Register
+ IF Mode_reg_enable = '1' THEN
+ -- Register Mode
+ Mode_reg <= Addr;
+
+ -- Precharge to Load Mode Register
+ ASSERT (Pc_b0 ='1' AND Pc_b1 = '1' AND Pc_b2 ='1' AND Pc_b3 = '1')
+ REPORT "All banks must be Precharge before Load Mode Register"
+ SEVERITY WARNING;
+
+ -- Precharge to Load Mode Register
+ ASSERT ((NOW - RP_chk0 >= tRP) OR (NOW - RP_chk1 >= tRP) OR
+ (NOW - RP_chk2 >= tRP) OR (NOW - RP_chk3 >= tRP))
+ REPORT "tRP violation during Load Mode Register"
+ SEVERITY WARNING;
+
+ -- Auto Refresh to Load Mode Register
+ ASSERT (NOW - RFC_chk >= tRFC)
+ REPORT "tRFC violation during Load Mode Register"
+ SEVERITY WARNING;
+
+ -- Load Mode Register to Load Mode Register
+ ASSERT (MRD_chk >= tMRD)
+ REPORT "tMRD violation during Load Mode Register"
+ SEVERITY WARNING;
+
+ -- Record current tMRD time
+ MRD_chk := 0;
+ END IF;
+
+ -- Active Block (Latch Bank and Row Address)
+ IF Active_enable = '1' THEN
+ -- Activate an OPEN bank can corrupt data
+ ASSERT ((Ba = "00" AND Act_b0 = '0') OR (Ba = "01" AND Act_b1 = '0') OR
+ (Ba = "10" AND Act_b2 = '0') OR (Ba = "11" AND Act_b3 = '0'))
+ REPORT "Bank is already activated - data can be corrupted"
+ SEVERITY WARNING;
+
+ -- Activate Bank 0
+ IF Ba = "00" AND Pc_b0 = '1' THEN
+ -- Activate to Activate (same bank)
+ ASSERT (NOW - RC_chk0 >= tRC)
+ REPORT "tRC violation during Activate Bank 0"
+ SEVERITY WARNING;
+
+ -- Precharge to Activate
+ ASSERT (NOW - RP_chk0 >= tRP)
+ REPORT "tRP violation during Activate Bank 0"
+ SEVERITY WARNING;
+
+ -- Record variables for checking violation
+ Act_b0 := '1';
+ Pc_b0 := '0';
+ B0_row_addr := Addr;
+ RAS_chk0 := NOW;
+ RC_chk0 := NOW;
+ RCD_chk0 := NOW;
+ END IF;
+
+ -- Activate Bank 1
+ IF Ba = "01" AND Pc_b1 = '1' THEN
+ -- Activate to Activate (same bank)
+ ASSERT (NOW - RC_chk1 >= tRC)
+ REPORT "tRC violation during Activate Bank 1"
+ SEVERITY WARNING;
+
+ -- Precharge to Activate
+ ASSERT (NOW - RP_chk1 >= tRP)
+ REPORT "tRP violation during Activate Bank 1"
+ SEVERITY WARNING;
+
+ -- Record variables for checking violation
+ Act_b1 := '1';
+ Pc_b1 := '0';
+ B1_row_addr := Addr;
+ RAS_chk1 := NOW;
+ RC_chk1 := NOW;
+ RCD_chk1 := NOW;
+ END IF;
+
+ -- Activate Bank 2
+ IF Ba = "10" AND Pc_b2 = '1' THEN
+ -- Activate to Activate (same bank)
+ ASSERT (NOW - RC_chk2 >= tRC)
+ REPORT "tRC violation during Activate Bank 2"
+ SEVERITY WARNING;
+
+ -- Precharge to Activate
+ ASSERT (NOW - RP_chk2 >= tRP)
+ REPORT "tRP violation during Activate Bank 2"
+ SEVERITY WARNING;
+
+ -- Record variables for checking violation
+ Act_b2 := '1';
+ Pc_b2 := '0';
+ B2_row_addr := Addr;
+ RAS_chk2 := NOW;
+ RC_chk2 := NOW;
+ RCD_chk2 := NOW;
+ END IF;
+
+ -- Activate Bank 3
+ IF Ba = "11" AND Pc_b3 = '1' THEN
+ -- Activate to Activate (same bank)
+ ASSERT (NOW - RC_chk3 >= tRC)
+ REPORT "tRC violation during Activate Bank 3"
+ SEVERITY WARNING;
+
+ -- Precharge to Activate
+ ASSERT (NOW - RP_chk3 >= tRP)
+ REPORT "tRP violation during Activate Bank 3"
+ SEVERITY WARNING;
+
+ -- Record variables for checking violation
+ Act_b3 := '1';
+ Pc_b3 := '0';
+ B3_row_addr := Addr;
+ RAS_chk3 := NOW;
+ RC_chk3 := NOW;
+ RCD_chk3 := NOW;
+ END IF;
+
+ -- Activate to Activate (different bank)
+ IF (Prev_bank /= Ba) THEN
+ ASSERT (NOW - RRD_chk >= tRRD)
+ REPORT "tRRD violation during Activate"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Auto Refresh to Activate
+ ASSERT (NOW - RFC_chk >= tRFC)
+ REPORT "tRFC violation during Activate"
+ SEVERITY WARNING;
+
+ -- Load Mode Register to Activate
+ ASSERT (MRD_chk >= tMRD)
+ REPORT "tMRD violation during Activate"
+ SEVERITY WARNING;
+
+ -- Record variable for checking violation
+ RRD_chk := NOW;
+ Prev_Bank := Ba;
+ END IF;
+
+ -- Precharge Block
+ IF Prech_enable = '1' THEN
+ -- Load Mode Register to Precharge
+ ASSERT (MRD_chk >= tMRD)
+ REPORT "tMRD violation during Precharge"
+ SEVERITY WARNING;
+
+ -- Precharge Bank 0
+ IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
+ Act_b0 := '0';
+ Pc_b0 := '1';
+ RP_chk0 := NOW;
+
+ -- Activate to Precharge
+ ASSERT (NOW - RAS_chk0 >= tRAS)
+ REPORT "tRAS violation during Precharge"
+ SEVERITY WARNING;
+
+ -- tWR violation check for Write
+ ASSERT (NOW - WR_chkm(0) >= tWRm)
+ REPORT "tWR violation during Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Precharge Bank 1
+ IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
+ Act_b1 := '0';
+ Pc_b1 := '1';
+ RP_chk1 := NOW;
+
+ -- Activate to Precharge
+ ASSERT (NOW - RAS_chk1 >= tRAS)
+ REPORT "tRAS violation during Precharge"
+ SEVERITY WARNING;
+
+ -- tWR violation check for Write
+ ASSERT (NOW - WR_chkm(1) >= tWRm)
+ REPORT "tWR violation during Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Precharge Bank 2
+ IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
+ Act_b2 := '0';
+ Pc_b2 := '1';
+ RP_chk2 := NOW;
+
+ -- Activate to Precharge
+ ASSERT (NOW - RAS_chk2 >= tRAS)
+ REPORT "tRAS violation during Precharge"
+ SEVERITY WARNING;
+
+ -- tWR violation check for Write
+ ASSERT (NOW - WR_chkm(2) >= tWRm)
+ REPORT "tWR violation during Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Precharge Bank 3
+ IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
+ Act_b3 := '0';
+ Pc_b3 := '1';
+ RP_chk3 := NOW;
+
+ -- Activate to Precharge
+ ASSERT (NOW - RAS_chk3 >= tRAS)
+ REPORT "tRAS violation during Precharge"
+ SEVERITY WARNING;
+
+ -- tWR violation check for Write
+ ASSERT (NOW - WR_chkm(3) >= tWRm)
+ REPORT "tWR violation during Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Terminate a Write Immediately (if same bank or all banks)
+ IF (Data_in_enable = '1' AND (Bank = Ba OR Addr(10) = '1')) THEN
+ Data_in_enable := '0';
+ END IF;
+
+ -- Precharge Command Pipeline for READ
+ IF CAS_latency_3 = '1' THEN
+ Command(2) := PRECH;
+ Bank_precharge(2) := Ba;
+ A10_precharge(2) := Addr(10);
+ ELSIF CAS_latency_2 = '1' THEN
+ Command(1) := PRECH;
+ Bank_precharge(1) := Ba;
+ A10_precharge(1) := Addr(10);
+ END IF;
+ END IF;
+
+ -- Burst Terminate
+ IF Burst_term = '1' THEN
+ -- Terminate a Write immediately
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ END IF;
+
+ -- Terminate a Read depend on CAS Latency
+ IF CAS_latency_3 = '1' THEN
+ Command(2) := BST;
+ ELSIF CAS_latency_2 = '1' THEN
+ Command(1) := BST;
+ END IF;
+ END IF;
+
+ -- Read Command
+ IF Read_enable = '1' THEN
+ -- Activate to Read
+ ASSERT ((Ba="00" AND Act_b0='1') OR (Ba="01" AND Act_b1='1') OR
+ (Ba="10" AND Act_b2='1') OR (Ba="11" AND Act_b3='1'))
+ REPORT "Bank is not Activated for Read"
+ SEVERITY WARNING;
+
+ -- Activate to Read
+ ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+ (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+ (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+ (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+ REPORT "tRCD violation during Read"
+ SEVERITY WARNING;
+
+ -- CAS Latency Pipeline
+ IF Cas_latency_3 = '1' THEN
+ Command(2) := READ;
+ Col_addr (2) := Addr(col_bits - 1 DOWNTO 0);
+ Bank_addr (2) := Ba;
+ ELSIF Cas_latency_2 = '1' THEN
+ Command(1) := READ;
+ Col_addr (1) := Addr(col_bits - 1 DOWNTO 0);
+ Bank_addr (1) := Ba;
+ ELSIF Cas_latency_1 = '1' THEN
+ Command(0) := READ;
+ Col_addr (0) := Addr(col_bits - 1 DOWNTO 0);
+ Bank_addr (0) := Ba;
+ END IF;
+
+ -- Read Terminate Write Immediately
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ -- Interrupt a Write with Auto Precharge
+ IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+ RW_interrupt_write(CONV_INTEGER(RW_Interrupt_Bank)) := '1';
+ RW_interrupt_counter (CONV_INTEGER(RW_Interrupt_Bank)) := 0;
+ ASSERT FALSE REPORT "Read interrupt a Write with Auto Precharge." SEVERITY NOTE;
+ END IF;
+ END IF;
+
+ -- Read Terminate Read after CL - 1
+ IF (Data_out_enable = '1' AND ((Cas_latency_2 = '1' AND ((Burst_length_2 = '1' AND Burst_counter < 1) OR
+ (Burst_length_4 = '1' AND Burst_counter < 3) OR
+ (Burst_length_8 = '1' AND Burst_counter < 7))) OR
+ (Cas_latency_3 = '1' AND ((Burst_length_4 = '1' AND Burst_counter < 2) OR
+ (Burst_length_8 = '1' AND Burst_counter < 6))))) THEN
+ -- Interrupt a Read with Auto Precharge
+ IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+ RW_interrupt_read(CONV_INTEGER(RW_Interrupt_Bank)) := '1';
+ ASSERT FALSE REPORT "Read interrupt a Read with Auto Precharge." SEVERITY NOTE;
+ END IF;
+ END IF;
+
+ -- Auto Precharge
+ IF Addr(10) = '1' THEN
+ Auto_precharge (CONV_INTEGER(Ba)) := '1';
+ Count_precharge (CONV_INTEGER(Ba)) := 0;
+ RW_Interrupt_Bank := Ba;
+ Read_precharge (CONV_INTEGER(Ba)) := '1';
+ END IF;
+ END IF;
+
+ -- Write Command
+ IF Write_enable = '1' THEN
+ -- Activate to Write
+ ASSERT ((Ba="00" AND Act_b0='1') OR (Ba="01" AND Act_b1='1') OR
+ (Ba="10" AND Act_b2='1') OR (Ba="11" AND Act_b3='1'))
+ REPORT "Bank is not Activated for Write"
+ SEVERITY WARNING;
+
+ -- Activate to Write
+ ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+ (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+ (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+ (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+ REPORT "tRCD violation during Write"
+ SEVERITY WARNING;
+
+ -- Latch write command, bank, column
+ Command(0) := WRITE;
+ Col_addr (0) := Addr(col_bits - 1 DOWNTO 0);
+ Bank_addr (0) := Ba;
+
+ -- Write Terminate Write Immediately
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+
+ -- Interrupt a Write with Auto Precharge
+ IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+ RW_interrupt_write(CONV_INTEGER(RW_Interrupt_Bank)) := '1';
+ RW_interrupt_counter (CONV_INTEGER(RW_Interrupt_Bank)) := 0;
+ ASSERT FALSE REPORT "Write interrupt a Write with Auto Precharge." SEVERITY NOTE;
+ END IF;
+ END IF;
+
+ -- Write Terminate Read Immediately
+ IF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+
+ -- Interrupt a Read with Auto Precharge
+ IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+ RW_interrupt_read(CONV_INTEGER(RW_Interrupt_Bank)) := '1';
+ ASSERT FALSE REPORT "Write interrupt a Read with Auto Precharge." SEVERITY NOTE;
+ END IF;
+ END IF;
+
+ -- Auto Precharge
+ IF Addr(10) = '1' THEN
+ Auto_precharge (CONV_INTEGER(Ba)) := '1';
+ Count_precharge (CONV_INTEGER(Ba)) := 0;
+ RW_Interrupt_Bank := Ba;
+ Write_precharge (CONV_INTEGER(Ba)) := '1';
+ END IF;
+ END IF;
+
+ -- Write with AutoPrecharge Calculation
+ -- The device start internal precharge when:
+ -- 1. Meet tRAS requirement
+ -- and 2. tWR cycle(s) after last valid data
+ -- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
+ --
+ -- Note: Model is starting the internal precharge 1 cycle after they meet all the
+ -- requirement but tRP will be compensate for the time after the 1 cycle.
+ IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
+ IF (((NOW - RAS_chk0 >= tRAS) AND
+ (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1) OR
+ (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
+ (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
+ (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
+ (RW_interrupt_write(0) = '1' AND RW_interrupt_counter(0) >= 1)) THEN
+ Auto_precharge(0) := '0';
+ Write_precharge(0) := '0';
+ RW_interrupt_write(0) := '0';
+ Pc_b0 := '1';
+ Act_b0 := '0';
+ RP_chk0 := NOW + tWRa;
+ END IF;
+ END IF;
+ IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
+ IF (((NOW - RAS_chk1 >= tRAS) AND
+ (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1) OR
+ (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
+ (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
+ (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
+ (RW_interrupt_write(1) = '1' AND RW_interrupt_counter(1) >= 1)) THEN
+ Auto_precharge(1) := '0';
+ Write_precharge(1) := '0';
+ RW_interrupt_write(1) := '0';
+ Pc_b1 := '1';
+ Act_b1 := '0';
+ RP_chk1 := NOW + tWRa;
+ END IF;
+ END IF;
+ IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
+ IF (((NOW - RAS_chk2 >= tRAS) AND
+ (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1) OR
+ (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
+ (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
+ (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
+ (RW_interrupt_write(2) = '1' AND RW_interrupt_counter(2) >= 1)) THEN
+ Auto_precharge(2) := '0';
+ Write_precharge(2) := '0';
+ RW_interrupt_write(2) := '0';
+ Pc_b2 := '1';
+ Act_b2 := '0';
+ RP_chk2 := NOW + tWRa;
+ END IF;
+ END IF;
+ IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
+ IF (((NOW - RAS_chk3 >= tRAS) AND
+ (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1) OR
+ (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
+ (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
+ (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
+ (RW_interrupt_write(0) = '1' AND RW_interrupt_counter(3) >= 1)) THEN
+ Auto_precharge(3) := '0';
+ Write_precharge(3) := '0';
+ RW_interrupt_write(3) := '0';
+ Pc_b3 := '1';
+ Act_b3 := '0';
+ RP_chk3 := NOW + tWRa;
+ END IF;
+ END IF;
+
+ -- Read with AutoPrecharge Calculation
+ -- The device start internal precharge when:
+ -- 1. Meet minimum tRAS requirement
+ -- and 2. CL - 1 cycle(s) before last valid data
+ -- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
+ IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
+ IF (((NOW - RAS_chk0 >= tRAS) AND
+ ((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
+ (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
+ (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
+ (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
+ (RW_interrupt_read(0) = '1')) THEN
+ Pc_b0 := '1';
+ Act_b0 := '0';
+ RP_chk0 := NOW;
+ Auto_precharge(0) := '0';
+ Read_precharge(0) := '0';
+ RW_interrupt_read(0) := '0';
+ END IF;
+ END IF;
+ IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
+ IF (((NOW - RAS_chk1 >= tRAS) AND
+ ((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
+ (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
+ (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
+ (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
+ (RW_interrupt_read(1) = '1')) THEN
+ Pc_b1 := '1';
+ Act_b1 := '0';
+ RP_chk1 := NOW;
+ Auto_precharge(1) := '0';
+ Read_precharge(1) := '0';
+ RW_interrupt_read(1) := '0';
+ END IF;
+ END IF;
+ IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
+ IF (((NOW - RAS_chk2 >= tRAS) AND
+ ((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
+ (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
+ (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
+ (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
+ (RW_interrupt_read(2) = '1')) THEN
+ Pc_b2 := '1';
+ Act_b2 := '0';
+ RP_chk2 := NOW;
+ Auto_precharge(2) := '0';
+ Read_precharge(2) := '0';
+ RW_interrupt_read(2) := '0';
+ END IF;
+ END IF;
+ IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
+ IF (((NOW - RAS_chk3 >= tRAS) AND
+ ((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
+ (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
+ (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
+ (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
+ (RW_interrupt_read(3) = '1')) THEN
+ Pc_b3 := '1';
+ Act_b3 := '0';
+ RP_chk3 := NOW;
+ Auto_precharge(3) := '0';
+ Read_precharge(3) := '0';
+ RW_interrupt_read(3) := '0';
+ END IF;
+ END IF;
+
+ -- Internal Precharge or Bst
+ IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
+ IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
+ IF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+ ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
+ IF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+
+ IF Data_out_enable = '0' THEN
+ Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
+ END IF;
+
+ -- Detect Read or Write Command
+ IF Command(0) = READ THEN
+ Bank := Bank_addr (0);
+ Col := Col_addr (0);
+ Col_brst := Col_addr (0);
+ IF Bank_addr (0) = "00" THEN
+ Row := B0_row_addr;
+ ELSIF Bank_addr (0) = "01" THEN
+ Row := B1_row_addr;
+ ELSIF Bank_addr (0) = "10" THEN
+ Row := B2_row_addr;
+ ELSE
+ Row := B3_row_addr;
+ END IF;
+ Burst_counter := 0;
+ Data_in_enable := '0';
+ Data_out_enable := '1';
+ ELSIF Command(0) = WRITE THEN
+ Bank := Bank_addr(0);
+ Col := Col_addr(0);
+ Col_brst := Col_addr(0);
+ IF Bank_addr (0) = "00" THEN
+ Row := B0_row_addr;
+ ELSIF Bank_addr (0) = "01" THEN
+ Row := B1_row_addr;
+ ELSIF Bank_addr (0) = "10" THEN
+ Row := B2_row_addr;
+ ELSE
+ Row := B3_row_addr;
+ END IF;
+ Burst_counter := 0;
+ Data_in_enable := '1';
+ Data_out_enable := '0';
+ END IF;
+
+ -- DQ (Driver / Receiver)
+ Row_index := CONV_INTEGER (Row);
+ Col_index := CONV_INTEGER (Col);
+
+ IF Data_in_enable = '1' THEN
+ IF Dqm /= "1111" THEN
+ -- Initialize Memory
+ Init_mem (Bank, Row_index);
+
+ -- Array Buffer
+ CASE Bank IS
+ WHEN "00" => Dq_temp := Bank0 (Row_index) (Col_index);
+ WHEN "01" => Dq_temp := Bank1 (Row_index) (Col_index);
+ WHEN "10" => Dq_temp := Bank2 (Row_index) (Col_index);
+ WHEN OTHERS => Dq_temp := Bank3 (Row_index) (Col_index);
+ END CASE;
+
+ -- Dqm Operation
+ IF Dqm (0) = '0' THEN
+ Dq_temp ( 7 DOWNTO 0) := Dq ( 7 DOWNTO 0);
+ END IF;
+ IF Dqm (1) = '0' THEN
+ Dq_temp (15 DOWNTO 8) := Dq (15 DOWNTO 8);
+ END IF;
+ IF Dqm (2) = '0' THEN
+ Dq_temp (23 DOWNTO 16) := Dq (23 DOWNTO 16);
+ END IF;
+ IF Dqm (3) = '0' THEN
+ Dq_temp (31 DOWNTO 24) := Dq (31 DOWNTO 24);
+ END IF;
+
+ -- Write to Memory
+ CASE Bank IS
+ WHEN "00" => Bank0 (Row_index) (Col_index) := Dq_temp;
+ WHEN "01" => Bank1 (Row_index) (Col_index) := Dq_temp;
+ WHEN "10" => Bank2 (Row_index) (Col_index) := Dq_temp;
+ WHEN OTHERS => Bank3 (Row_index) (Col_index) := Dq_temp;
+ END CASE;
+
+ -- Record tWR for manual precharge
+ WR_chkm(CONV_INTEGER(Bank)) := NOW;
+ END IF;
+
+ -- Advance Burst Counter
+ Burst_decode;
+
+ ELSIF Data_out_enable = '1' THEN
+ IF Dqm_reg0 /= "1111" THEN
+ -- Initialize Memory
+ Init_mem (Bank, Row_index);
+
+ -- Array Buffer
+ CASE Bank IS
+ WHEN "00" => Dq_temp := Bank0 (Row_index) (Col_index);
+ WHEN "01" => Dq_temp := Bank1 (Row_index) (Col_index);
+ WHEN "10" => Dq_temp := Bank2 (Row_index) (Col_index);
+ WHEN OTHERS => Dq_temp := Bank3 (Row_index) (Col_index);
+ END CASE;
+
+ -- Dqm Operation
+ IF Dqm_reg0 (0) = '1' THEN
+ Dq_temp ( 7 DOWNTO 0) := (OTHERS => 'Z');
+ END IF;
+ IF Dqm_reg0 (1) = '1' THEN
+ Dq_temp (15 DOWNTO 8) := (OTHERS => 'Z');
+ END IF;
+ IF Dqm_reg0 (2) = '1' THEN
+ Dq_temp (23 DOWNTO 16) := (OTHERS => 'Z');
+ END IF;
+ IF Dqm_reg0 (3) = '1' THEN
+ Dq_temp (31 DOWNTO 24) := (OTHERS => 'Z');
+ END IF;
+
+ -- Output
+ Dq <= TRANSPORT Dq_temp AFTER tAC;
+ ELSE
+ Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
+ END IF;
+
+ -- Advance Burst Counter
+ Burst_decode;
+ END IF;
+ END IF;
+
+ END PROCESS;
+
+ -- Clock timing checks
+ Clock_check : PROCESS
+ VARIABLE Clk_low, Clk_high : TIME := 0 ns;
+ BEGIN
+ WAIT ON Clk;
+ IF (Clk = '1' AND NOW >= 10 ns) THEN
+ ASSERT (NOW - Clk_low >= tCL)
+ REPORT "tCL violation"
+ SEVERITY WARNING;
+ ASSERT (NOW - Clk_high >= tCK)
+ REPORT "tCK violation"
+ SEVERITY WARNING;
+ Clk_high := NOW;
+ ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
+ ASSERT (NOW - Clk_high >= tCH)
+ REPORT "tCH violation"
+ SEVERITY WARNING;
+ Clk_low := NOW;
+ END IF;
+ END PROCESS;
+
+ -- Setup timing checks
+ Setup_check : PROCESS
+ BEGIN
+ WAIT ON Clk;
+ IF Clk = '1' THEN
+ ASSERT(Cke'LAST_EVENT >= tCKS)
+ REPORT "CKE Setup time violation -- tCKS"
+ SEVERITY WARNING;
+ ASSERT(Cs_n'LAST_EVENT >= tCMS)
+ REPORT "CS# Setup time violation -- tCMS"
+ SEVERITY WARNING;
+ ASSERT(Cas_n'LAST_EVENT >= tCMS)
+ REPORT "CAS# Setup time violation -- tCMS"
+ SEVERITY WARNING;
+ ASSERT(Ras_n'LAST_EVENT >= tCMS)
+ REPORT "RAS# Setup time violation -- tCMS"
+ SEVERITY WARNING;
+ ASSERT(We_n'LAST_EVENT >= tCMS)
+ REPORT "WE# Setup time violation -- tCMS"
+ SEVERITY WARNING;
+ ASSERT(Dqm'LAST_EVENT >= tCMS)
+ REPORT "Dqm Setup time violation -- tCMS"
+ SEVERITY WARNING;
+ ASSERT(Addr'LAST_EVENT >= tAS)
+ REPORT "ADDR Setup time violation -- tAS"
+ SEVERITY WARNING;
+ ASSERT(Ba'LAST_EVENT >= tAS)
+ REPORT "BA Setup time violation -- tAS"
+ SEVERITY WARNING;
+ ASSERT(Dq'LAST_EVENT >= tDS)
+ REPORT "Dq Setup time violation -- tDS"
+ SEVERITY WARNING;
+ END IF;
+ END PROCESS;
+
+ -- Hold timing checks
+ Hold_check : PROCESS
+ BEGIN
+ WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
+ IF Clk'DELAYED (tCKH) = '1' THEN
+ ASSERT(Cke'LAST_EVENT > tCKH)
+ REPORT "CKE Hold time violation -- tCKH"
+ SEVERITY WARNING;
+ END IF;
+ IF Clk'DELAYED (tCMH) = '1' THEN
+ ASSERT(Cs_n'LAST_EVENT > tCMH)
+ REPORT "CS# Hold time violation -- tCMH"
+ SEVERITY WARNING;
+ ASSERT(Cas_n'LAST_EVENT > tCMH)
+ REPORT "CAS# Hold time violation -- tCMH"
+ SEVERITY WARNING;
+ ASSERT(Ras_n'LAST_EVENT > tCMH)
+ REPORT "RAS# Hold time violation -- tCMH"
+ SEVERITY WARNING;
+ ASSERT(We_n'LAST_EVENT > tCMH)
+ REPORT "WE# Hold time violation -- tCMH"
+ SEVERITY WARNING;
+ ASSERT(Dqm'LAST_EVENT > tCMH)
+ REPORT "Dqm Hold time violation -- tCMH"
+ SEVERITY WARNING;
+ END IF;
+ IF Clk'DELAYED (tAH) = '1' THEN
+ ASSERT(Addr'LAST_EVENT > tAH)
+ REPORT "ADDR Hold time violation -- tAH"
+ SEVERITY WARNING;
+ ASSERT(Ba'LAST_EVENT > tAH)
+ REPORT "BA Hold time violation -- tAH"
+ SEVERITY WARNING;
+ END IF;
+ IF Clk'DELAYED (tDH) = '1' THEN
+ ASSERT(Dq'LAST_EVENT > tDH)
+ REPORT "Dq Hold time violation -- tDH"
+ SEVERITY WARNING;
+ END IF;
+ END PROCESS;
+
+END behave;
Index: sdram_ctrl/trunk/test_bench/cpu_simulator.vhd
===================================================================
--- sdram_ctrl/trunk/test_bench/cpu_simulator.vhd (nonexistent)
+++ sdram_ctrl/trunk/test_bench/cpu_simulator.vhd (revision 8)
@@ -0,0 +1,72 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY cpu_simulator IS
+ PORT(clk, reset: in std_logic;
+
+ address : out std_logic_vector(21 downto 0);
+ writedata : out std_logic_vector(31 downto 0);
+ byteenable : out std_logic_vector(3 downto 0);
+ write : out std_logic;
+ read : out std_logic;
+ readdata : in std_logic_vector(31 downto 0);
+ waitrequest : in std_logic;
+ readdatavalid : in std_logic
+ );
+END cpu_simulator;
+
+ARCHITECTURE behaviour OF cpu_simulator IS
+ signal counter: unsigned(3 downto 0);
+ type vector is
+ record
+ address: integer;
+ writedata: integer;
+ byteenable: std_logic_vector(3 downto 0);
+ write: std_logic;
+ read: std_logic;
+ end record;
+ type script is array(0 to (2**counter'length)-1) of vector;
+ signal wave_form: script:=(
+ (0,0,"1111",'1','0'),
+ (1,1,"1111",'1','0'),
+ (2,2,"1111",'1','0'),
+ (3,3,"1111",'1','0'),
+ (1024,1024,"1111",'0','1'),
+ (1025,1025,"1111",'0','1'),
+ (1026,1026,"1111",'0','1'),
+ (1027,1027,"1111",'0','1'),
+ (1024,1024,"1111",'1','0'),
+ (1025,1025,"1111",'1','0'),
+ (1026,1026,"1111",'1','0'),
+ (1027,1027,"1111",'1','0'),
+ (0,0,"1111",'0','1'),
+ (1,1,"1111",'0','1'),
+ (2,2,"1111",'0','1'),
+ (3,3,"1111",'0','1')
+ );
+BEGIN
+ process(clk,reset)
+ begin
+ if reset='1'
+ then
+ counter<=(others=>'0');
+ address<=(others=>'0');
+ writedata<=(others=>'0');
+ byteenable<=(others=>'0');
+ write<='0';
+ read<='0';
+ elsif rising_edge(clk)
+ then
+ if waitrequest='0'
+ then
+ counter<=counter+1;
+ address<=std_logic_vector(to_unsigned(wave_form(to_integer(counter)).address,address'length));
+ writedata<=std_logic_vector(to_unsigned(wave_form(to_integer(counter)).writedata,writedata'length));
+ byteenable<=wave_form(to_integer(counter)).byteenable;
+ write<=wave_form(to_integer(counter)).write;
+ read<=wave_form(to_integer(counter)).read;
+ end if;
+ end if;
+ end process;
+END behaviour;
\ No newline at end of file
Index: sdram_ctrl/trunk/test_bench/pll.vhd
===================================================================
--- sdram_ctrl/trunk/test_bench/pll.vhd (nonexistent)
+++ sdram_ctrl/trunk/test_bench/pll.vhd (revision 8)
@@ -0,0 +1,256 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- altpll
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 5.1 Build 213 01/19/2006 SP 1 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY pll IS
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ e0 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL sub_wire4 : STD_LOGIC ;
+ SIGNAL sub_wire5 : STD_LOGIC ;
+ SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+ COMPONENT altpll
+ GENERIC (
+ clk0_divide_by : NATURAL;
+ clk0_duty_cycle : NATURAL;
+ clk0_multiply_by : NATURAL;
+ clk0_phase_shift : STRING;
+ compensate_clock : STRING;
+ extclk0_divide_by : NATURAL;
+ extclk0_duty_cycle : NATURAL;
+ extclk0_multiply_by : NATURAL;
+ extclk0_phase_shift : STRING;
+ inclk0_input_frequency : NATURAL;
+ intended_device_family : STRING;
+ invalid_lock_multiplier : NATURAL;
+ lpm_type : STRING;
+ operation_mode : STRING;
+ pll_type : STRING;
+ valid_lock_multiplier : NATURAL
+ );
+ PORT (
+ extclk : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ locked : OUT STD_LOGIC ;
+ clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ sub_wire7_bv(0 DOWNTO 0) <= "0";
+ sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
+ sub_wire1 <= sub_wire0(0);
+ c0 <= sub_wire1;
+ locked <= sub_wire2;
+ sub_wire4 <= sub_wire3(0);
+ e0 <= sub_wire4;
+ sub_wire5 <= inclk0;
+ sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+ altpll_component : altpll
+ GENERIC MAP (
+ clk0_divide_by => 2,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 11,
+ clk0_phase_shift => "0",
+ compensate_clock => "CLK0",
+ extclk0_divide_by => 2,
+ extclk0_duty_cycle => 50,
+ extclk0_multiply_by => 11,
+ extclk0_phase_shift => "5682",
+ inclk0_input_frequency => 41666,
+ intended_device_family => "Cyclone",
+ invalid_lock_multiplier => 5,
+ lpm_type => "altpll",
+ operation_mode => "NORMAL",
+ pll_type => "AUTO",
+ valid_lock_multiplier => 1
+ )
+ PORT MAP (
+ inclk => sub_wire6,
+ clk => sub_wire0,
+ locked => sub_wire2,
+ extclk => sub_wire3
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "504.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "deg"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "132.000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK6 STRING "0"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK6 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA6 STRING "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: EXTCLK0_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: EXTCLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: EXTCLK0_MULTIPLY_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: EXTCLK0_PHASE_SHIFT STRING "5682"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+-- Retrieval info: USED_PORT: e0 0 0 0 0 OUTPUT VCC "e0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: e0 0 0 0 0 @extclk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE
Index: sdram_ctrl/trunk/test_bench/old/nios.dat
===================================================================
--- sdram_ctrl/trunk/test_bench/old/nios.dat (nonexistent)
+++ sdram_ctrl/trunk/test_bench/old/nios.dat (revision 8)
@@ -0,0 +1 @@
+ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ
\ No newline at end of file
Index: sdram_ctrl/trunk/test_bench/old/Hello_LED_sdram_0.dat
===================================================================
--- sdram_ctrl/trunk/test_bench/old/Hello_LED_sdram_0.dat (nonexistent)
+++ sdram_ctrl/trunk/test_bench/old/Hello_LED_sdram_0.dat (revision 8)
@@ -0,0 +1,49 @@
+@00000000 00400034
+@00000001 08400804
+@00000002 0800683A
+@00000003 00000000
+@00000004 00000000
+@00000005 00000000
+@00000006 00000000
+@00000007 00000000
+@00000008 06C04034
+@00000009 DEC00004
+@0000000A 06800074
+@0000000B D6A03104
+@0000000C 00000340
+@0000000D DEFFFD04
+@0000000E DF000215
+@0000000F D839883A
+@00000010 00800084
+@00000011 E0800005
+@00000012 E0000045
+@00000013 E0800003
+@00000014 1080204C
+@00000015 1005003A
+@00000016 1000031E
+@00000017 E0800043
+@00000018 1080005C
+@00000019 E0800045
+@0000001A E0800043
+@0000001B 1005003A
+@0000001C 1000041E
+@0000001D E0800003
+@0000001E 1004D07A
+@0000001F E0800005
+@00000020 00000306
+@00000021 E0800003
+@00000022 1085883A
+@00000023 E0800005
+@00000024 00C04034
+@00000025 18C21004
+@00000026 E0800003
+@00000027 18800035
+@00000028 E0000115
+@00000029 E0C00117
+@0000002A 008000F4
+@0000002B 10834FC4
+@0000002C 10FFE616
+@0000002D E0800117
+@0000002E 10800044
+@0000002F E0800115
+@00000030 003FF806
Index: sdram_ctrl/trunk/test_bench/old/cpu_simulator_file_based.vhd
===================================================================
--- sdram_ctrl/trunk/test_bench/old/cpu_simulator_file_based.vhd (nonexistent)
+++ sdram_ctrl/trunk/test_bench/old/cpu_simulator_file_based.vhd (revision 8)
@@ -0,0 +1,79 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY cpu_simulator IS
+ PORT(clk, reset: in std_logic;
+
+ address : out std_logic_vector(21 downto 0);
+ writedata : out std_logic_vector(31 downto 0);
+ byteenable : out std_logic_vector(3 downto 0);
+ write : out std_logic;
+ read : out std_logic;
+ readdata : in std_logic_vector(31 downto 0);
+ waitrequest : in std_logic;
+ readdatavalid : in std_logic
+ );
+END cpu_simulator;
+
+ARCHITECTURE behaviour OF cpu_simulator IS
+ signal address: std_logic_vector(21 downto 0);
+ signal writedata: std_logic_vector(31 downto 0);
+ signal byteenable: std_logic_vector(3 downto 0);
+ signal write: std_logic;
+ signal read: std_logic;
+
+BEGIN
+ process(clk,reset)
+ variable service: std_logic_vector(7 downto 0);
+ variable b0,b1,b2,b3,b4,b5,b6,b7: BYTE;
+ begin
+ if reset='1'
+ then
+ file_close(NIOS);
+ file_open(NIOS, FILES_PATH&"nios.dat", READ_MODE);
+ elsif rising_edge(clk)
+ then
+ if waitrequest='0'
+ then
+ if Endfile(NIOS)
+ then
+ file_close(NIOS);
+ file_open(NIOS, FILES_PATH&"nios.dat", READ_MODE);
+ else
+ Read(NIOS,b0);
+ Read(NIOS,b1);
+ Read(NIOS,b2);
+ Read(NIOS,b3);
+ Read(NIOS,b4);
+ Read(NIOS,b5);
+ Read(NIOS,b6);
+ Read(NIOS,b7);
+ service:=char2std_logic_vector(b0);
+ address<=service(5 downto 0)&char2std_logic_vector(b1)&char2std_logic_vector(b2);
+ writedata<=char2std_logic_vector(b3)&char2std_logic_vector(b4)&char2std_logic_vector(b5)&char2std_logic_vector(b6);
+ service:=char2std_logic_vector(b7);
+ byteenable<=not service(7 downto 4);
+ write<=service(3);
+ read<=service(2);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process(clk,reset)
+ begin
+ if reset='1'
+ then
+ readed<=(others=>'0');
+ new_data<='0';
+ elsif rising_edge(clk)
+ then
+ new_data<=readdatavalid;
+ if readdatavalid='1'
+ then
+ readed<=readdata;
+ end if;
+ end if;
+ end process;
+END behaviour;
\ No newline at end of file
Index: sdram_ctrl/trunk/test_bench/old/Count_Binary_sdram_0.dat
===================================================================
--- sdram_ctrl/trunk/test_bench/old/Count_Binary_sdram_0.dat (nonexistent)
+++ sdram_ctrl/trunk/test_bench/old/Count_Binary_sdram_0.dat (revision 8)
@@ -0,0 +1,5026 @@
+;Count Binary
+@00000000 00820014
+@00000001 1001483A
+@00000002 10BFF804
+@00000003 00BFFD16
+@00000004 00400034
+@00000005 08407204
+@00000006 0800683A
+@00000007 00000000
+@00000008 DEFFED04
+@00000009 DFC00015
+@0000000A D8400215
+@0000000B D8800315
+@0000000C D8C00415
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Index: sdram_ctrl/trunk/doc/readme.txt
===================================================================
--- sdram_ctrl/trunk/doc/readme.txt (nonexistent)
+++ sdram_ctrl/trunk/doc/readme.txt (revision 8)
@@ -0,0 +1 @@
+Please look up inside the source.
\ No newline at end of file
Index: sdram_ctrl/trunk/doc/sdram_ctrl.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: sdram_ctrl/trunk/doc/sdram_ctrl.sxw
===================================================================
--- sdram_ctrl/trunk/doc/sdram_ctrl.sxw (nonexistent)
+++ sdram_ctrl/trunk/doc/sdram_ctrl.sxw (revision 8)
direction: output
signal type: export"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_sdram_ba/width = (int((( ( $H/bank_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_sdram_ba/width = "$"; - } - warning = "{{ if($PORT_sdram_ba/width <= 0)('width of sdram_ba must be greater than zero' ) }}"; - } - EDIT sdram_addr_width - { - id = "sdram_addr_width"; - editable = "0"; - title = "sdram_addr[((row_width - 1)) - (0) + 1]:"; - tooltip = "sdram_addr[((row_width - 1)) - (0) + 1]
direction: output
signal type: export"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_sdram_addr/width = (int((( ( $H/row_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_sdram_addr/width = "$"; - } - warning = "{{ if($PORT_sdram_addr/width <= 0)('width of sdram_addr must be greater than zero' ) }}"; - } - EDIT sdram_dq_width - { - id = "sdram_dq_width"; - editable = "0"; - title = "sdram_dq[((data_width - 1)) - (0) + 1]:"; - tooltip = "sdram_dq[((data_width - 1)) - (0) + 1]
direction: inout
signal type: export"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_sdram_dq/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_sdram_dq/width = "$"; - } - warning = "{{ if($PORT_sdram_dq/width <= 0)('width of sdram_dq must be greater than zero' ) }}"; - } - EDIT sdram_dqm_width - { - id = "sdram_dqm_width"; - editable = "0"; - title = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]:"; - tooltip = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]
direction: output
signal type: export"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_sdram_dqm/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_sdram_dqm/width = "$"; - } - warning = "{{ if($PORT_sdram_dqm/width <= 0)('width of sdram_dqm must be greater than zero' ) }}"; - } - EDIT avs_nios_address_width - { - id = "avs_nios_address_width"; - editable = "0"; - title = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]:"; - tooltip = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]
direction: input
signal type: address"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_avs_nios_address/width = (int((((( ( $H/bank_width ) + ( $H/row_width ) ) + ( $H/column_width ) ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - dummy_dummy = "{{ $SBI_nios/Address_Width = $PORT_avs_nios_address/width; }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_avs_nios_address/width = "$"; - } - warning = "{{ if($PORT_avs_nios_address/width <= 0)('width of avs_nios_address must be greater than zero' ) }}"; - } - EDIT avs_nios_byteenable_width - { - id = "avs_nios_byteenable_width"; - editable = "0"; - title = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]:"; - tooltip = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]
direction: input
signal type: byteenable"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_avs_nios_byteenable/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_avs_nios_byteenable/width = "$"; - } - warning = "{{ if($PORT_avs_nios_byteenable/width <= 0)('width of avs_nios_byteenable must be greater than zero' ) }}"; - } - EDIT avs_nios_writedata_width - { - id = "avs_nios_writedata_width"; - editable = "0"; - title = "avs_nios_writedata[((data_width - 1)) - (0) + 1]:"; - tooltip = "avs_nios_writedata[((data_width - 1)) - (0) + 1]
direction: input
signal type: writedata"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_avs_nios_writedata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_writedata/width - 1) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_avs_nios_writedata/width = "$"; - } - warning = "{{ if($PORT_avs_nios_writedata/width <= 0)('width of avs_nios_writedata must be greater than zero' ) }}"; - } - EDIT avs_nios_readdata_width - { - id = "avs_nios_readdata_width"; - editable = "0"; - title = "avs_nios_readdata[((data_width - 1)) - (0) + 1]:"; - tooltip = "avs_nios_readdata[((data_width - 1)) - (0) + 1]
direction: output
signal type: readdata"; - # This expression should emulate the HDL, and assign the port width - dummy = "{{ $PORT_avs_nios_readdata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; - dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_readdata/width - 1) + 1); }}"; - DATA - { - # The EDIT field is noneditable, so this just reads the current width. - $PORT_avs_nios_readdata/width = "$"; - } - warning = "{{ if($PORT_avs_nios_readdata/width <= 0)('width of avs_nios_readdata must be greater than zero' ) }}"; - } - } - } - } - } - } - SOPC_Builder_Version = "5.10"; - COMPONENT_BUILDER - { - HDL_PARAMETERS - { - # generated by CBDocument.getParameterContainer - # used only by Component Editor - HDL_PARAMETER data_width - { - parameter_name = "data_width"; - type = "integer"; - default_value = "32"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER bank_width - { - parameter_name = "bank_width"; - type = "integer"; - default_value = "4"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER row_width - { - parameter_name = "row_width"; - type = "integer"; - default_value = "12"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER column_width - { - parameter_name = "column_width"; - type = "integer"; - default_value = "8"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER clk_mhz - { - parameter_name = "clk_mhz"; - type = "integer"; - default_value = "120"; - editable = "1"; - tooltip = ""; - } - } - SW_FILES - { - } - built_on = "2006.09.25.10:24:12"; - CACHED_HDL_INFO - { - # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection - # used only by Component Builder - FILE sdram_ctrl.vhd - { - file_mod = "Mon Sep 18 18:08:50 EEST 2006"; - quartus_map_start = "Mon Sep 25 10:22:36 EEST 2006"; - quartus_map_finished = "Mon Sep 25 10:22:58 EEST 2006"; - #found 1 valid modules - WRAPPER sdram_ctrl - { - CLASS sdram_ctrl - { - CB_GENERATOR - { - HDL_FILES - { - FILE - { - use_in_simulation = "1"; - use_in_synthesis = "1"; - filepath = "H:/Work/Home_stuff/opencores/sdram_ctrl/src/sdram_ctrl.vhd"; - } - } - top_module_name = "sdram_ctrl"; - emit_system_h = "0"; - LIBRARIES - { - library = "ieee.std_logic_1164.all"; - library = "ieee.numeric_std.all"; - library = "altera_mf.altera_mf_components.all"; - library = "std.standard.all"; - } - } - MODULE_DEFAULTS global_signals - { - class = "sdram_ctrl"; - class_version = "1.0"; - SYSTEM_BUILDER_INFO - { - Instantiate_In_System_Module = "1"; - } - SLAVE nios - { - SYSTEM_BUILDER_INFO - { - Bus_Type = "avalon"; - } - PORT_WIRING - { - PORT avs_nios_chipselect - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "chipselect"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_address - { - width = "-1"; - width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1"; - direction = "input"; - type = "address"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_byteenable - { - width = "-1"; - width_expression = "(((data_width / 8) - 1)) - (0) + 1"; - direction = "input"; - type = "byteenable"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_writedata - { - width = "-1"; - width_expression = "((data_width - 1)) - (0) + 1"; - direction = "input"; - type = "writedata"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_write - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "write"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_read - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "read"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_waitrequest - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "waitrequest"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_readdata - { - width = "-1"; - width_expression = "((data_width - 1)) - (0) + 1"; - direction = "output"; - type = "readdata"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT avs_nios_readdatavalid - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "readdatavalid"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - } - } - SLAVE avalon_slave_0 - { - SYSTEM_BUILDER_INFO - { - Bus_Type = "avalon"; - } - PORT_WIRING - { - PORT sdram_cke - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_ba - { - width = "-1"; - width_expression = "((bank_width - 1)) - (0) + 1"; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_addr - { - width = "-1"; - width_expression = "((row_width - 1)) - (0) + 1"; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_cs_n - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_ras_n - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_cas_n - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_we_n - { - width = "1"; - width_expression = ""; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_dq - { - width = "-1"; - width_expression = "((data_width - 1)) - (0) + 1"; - direction = "inout"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT sdram_dqm - { - width = "-1"; - width_expression = "(((data_width / 8) - 1)) - (0) + 1"; - direction = "output"; - type = "export"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - } - } - PORT_WIRING - { - PORT clk - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "clk"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - PORT reset - { - width = "1"; - width_expression = ""; - direction = "input"; - type = "reset"; - is_shared = "0"; - vhdl_record_name = ""; - vhdl_record_type = ""; - } - } - } - USER_INTERFACE - { - USER_LABELS - { - name = "sdram_ctrl"; - technology = "imported components"; - } - } - SOPC_Builder_Version = "0.0"; - COMPONENT_BUILDER - { - HDL_PARAMETERS - { - # generated by CBDocument.getParameterContainer - # used only by Component Editor - HDL_PARAMETER data_width - { - parameter_name = "data_width"; - type = "integer"; - default_value = "32"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER bank_width - { - parameter_name = "bank_width"; - type = "integer"; - default_value = "4"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER row_width - { - parameter_name = "row_width"; - type = "integer"; - default_value = "12"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER column_width - { - parameter_name = "column_width"; - type = "integer"; - default_value = "8"; - editable = "1"; - tooltip = ""; - } - HDL_PARAMETER clk_mhz - { - parameter_name = "clk_mhz"; - type = "integer"; - default_value = "120"; - editable = "1"; - tooltip = ""; - } - } - } - } - } - } - } - } - ASSOCIATED_FILES - { - Add_Program = "the_wizard_ui"; - Edit_Program = "the_wizard_ui"; - Generator_Program = "cb_generator.pl"; - } -} Index: trunk/syn/sdram_ctrl/cb_generator.pl =================================================================== --- trunk/syn/sdram_ctrl/cb_generator.pl (revision 7) +++ trunk/syn/sdram_ctrl/cb_generator.pl (nonexistent) @@ -1,1159 +0,0 @@ -# | file: cb_generator.pl -# | -# | This SOPC Builder Generator program is provided by -# | the Component Builder application. It is copied -# | straight across and is data-driven from its command -# | line arguments and the PTF files referenced. -# | -# | Its purpose is to construct an HDL "wrapper" for -# | a particular instance of a particular SOPC Builder -# | peripheral. This wrapper resolves the instance -# | name and any HDL parameterization. -# | -# +------------------------------------------- - - - -# +------------------------------------------- -# | - -use strict; -use format_conversion_utils; -use ptf_parse; -use wiz_utils; -use europa_all; -use run_system_command_utils; - -# | -# +------------------------------------------- - - - -# +------------------------------------------- -# | -# | first pass: include all of generator_libarary.pm RIGHT HERE. -# | dvb04.08.02 -# | then prune down to actual functionality. -# | -# | TODO: Rewrite this whole file into something readable -# | this is much more confusing than I'm comfortable with. dvb04. -# | (though it does seem to work.) -# | - -my $DEBUG_DEFAULT_GEN = 1; - -#This is the global hash of arguments passed in by the generator program - -my $generator_hr = { - wrapper_args => { - make_wrapper => 0, - top_module_name => "", - simulate_hdl => 1, - ports => "", - }, - class_ptf_hr => "", - module_ptf_hr => "", - system_ptf_hr => "", - language => "", - external_args => "", - external_args_hr => "", - project_path_widget => "__PROJECT_DIRECTORY__", - generator_mode => "silent", - }; - - -sub generator_print_verbose -{ - my ($info) = (@_); - - if($generator_hr->{generator_mode} eq "verbose"){ - print("cb_generator.pl: ".$info); - } -} - -sub generator_enable_mode -{ - my ($mode) = (@_); - $generator_hr->{generator_mode} = $mode; -} - -sub generator_get_system_ptf_handle -{ - return $generator_hr->{system_ptf_hr}; -} - -sub generator_get_language -{ - return $generator_hr->{language}; -} - -sub generator_get_class_ptf_handle -{ - return $generator_hr->{class_ptf_hr}; -} - -sub default_ribbit -{ - my ($arg) = (@_); - &ribbit("\n\n--Error: default_gen_lib: $arg\n"); -} - - -sub _copy_files -{ - my ($dest_dir, $source_dir, @files) = (@_); - my $function_name; - - #validate args - &default_ribbit("No target dir for function copy_files!") - unless ($dest_dir ne ""); - - &default_ribbit("No source dir for function copy_files!") - unless ($source_dir ne ""); - - &default_ribbit("No files for function copy_files!") - unless (@files != 0); - - - #check for valid directories - opendir (SDIR, $source_dir) or - &default_ribbit("can't open $source_dir !"); - - opendir (DDIR, $dest_dir) or - &default_ribbit("can't open $dest_dir !"); - - - foreach my $source_file(@files){ - # | - # | Separate out the source subdir and the source filename - # | - my $source_subdir = ""; - my $source_filename = $source_file; - - if($source_filename =~ /^(.*)\/(.*)$/) # break on last slash - { - $source_subdir = "/$1"; # embed its leading slash, for concatty - $source_filename = $2; - } - - my $source_fullpath = "$source_dir$source_subdir/$source_filename"; - my $dest_fullpath = "$dest_dir/$source_filename"; - - &Perlcopy($source_fullpath, $dest_fullpath); - &generator_print_verbose("Copying file: \"$source_fullpath\"" - . " to \"$dest_fullpath\".\n"); - } - - closedir (SDIR); - closedir (DDIR); -} - - -sub get_module_wrapper_arg_hash_from_system_ptf_file -{ - my $module_ptf_hr = $generator_hr->{module_ptf_hr}; - - my @list_of_sections = ("MASTER","SLAVE","PORT_WIRING"); - my @port_list; - foreach my $section(@list_of_sections){ - my $number = get_child_count($module_ptf_hr, $section); - - for(my $initial=0; $initial < $number; $initial++){ - - my $interface_section = get_child($module_ptf_hr, $initial, $section); - my $interface_section_name = get_data($interface_section); - - my $port_wiring_section; - if($section ne "PORT_WIRING"){ - $port_wiring_section = - get_child_by_path($module_ptf_hr, $section." ".$interface_section_name."/PORT_WIRING"); - }else{ - $port_wiring_section = - get_child_by_path($module_ptf_hr, $section); - } - my $num_ports = get_child_count($port_wiring_section, "PORT"); - foreach(my $port_count = 0; $port_count < $num_ports; $port_count++){ - my $port = get_child($port_wiring_section, $port_count, "PORT"); - - my %port_info_struct; - $port_info_struct{name} = get_data($port); - $port_info_struct{direction} = get_data_by_path($port, "direction"); - $port_info_struct{width} = get_data_by_path($port, "width"); - $port_info_struct{vhdl_record_name} = get_data_by_path($port, "vhdl_record_name"); - $port_info_struct{vhdl_record_type} = get_data_by_path($port, "vhdl_record_type"); - - push(@port_list, \%port_info_struct); - - } - } - } - $generator_hr->{wrapper_args}{ports} = \@port_list; -} - - -sub generator_make_module_wrapper -{ - my ($simulate_hdl, $top_module_name, $module_language) = (@_); - - &default_ribbit("generator_make_module_wrapper: no arg0 passed in for simulate_hdl\n") - if($simulate_hdl eq ''); - - &default_ribbit("generator_make_module_wrapper: no arg1 passed in for top_module_name\n") - unless($top_module_name); - - $generator_hr->{wrapper_args}{simulate_hdl} = $simulate_hdl; - $generator_hr->{wrapper_args}{top_module_name} = $top_module_name; - $generator_hr->{wrapper_args}{make_wrapper} = 1; - $generator_hr->{wrapper_args}{module_language} = $module_language; - -} - - - - -# | -# | recognize varous number forms, -# | return 'h0123abcd-ish. -# | -sub turn_anything_into_appropriate_string($$$$) - { - my ($value,$type,$editable,$module_language) = (@_); - - return $value if($value =~ /^\"/); # quoted string: unscathed - return $value if($type eq "string"); # string: anything is ok - - return $value if(!$editable); # and you know, if you can't change it, keep it! - - - # | - # | first, convert to a number - # | - my $base = 10; - my $n = $value; - my $width = 32; - my $number = 0; - - $value = lc($value); # lower case - - if($value =~ /^([0-9]*)\'([hbo])(.*)$/) - { - # | tick notation: AOK for verilog - if($module_language eq "verilog") - { - $number = $value; - } - # | - # | note: at this point, we could notice if the - # | result should be vhdl binary, and convert - # | to that, avoiding the precision-losing - # | integer intermediary - # | - # | (alternatively, we could use a binary string - # | always as the intermediate form, rather than - # | a precision-losing int.) - # | - else - { - $width = $1; - my $baseletter = $2; - my $digits = $3; - - if($baseletter eq "h") - { - $base = 16; - } - elsif($baseletter eq "b") - { - $base = 2; - } - elsif($baseletter eq "o") # must be - { - $base = 8; - } - - $digits =~ s/[ _-]//g; # crush out dividing value - - while(length($digits) > 0) - { - my $digit = substr($digits,0,1); - $digits = substr($digits,1); - my $digitvalue = hex($digit); # how handy - $number = $number * $base + $digitvalue; - } - } - } - elsif($value =~ /^0x(.*)$/) - { - $number = hex($1); - } - else # try for decimal - { - $number = int(1 * $value); - } - - # | - # | ok, we have a number. If our target type - # | is "std_logic_vector(this downto that)" - # | for tricky VHDL, we - # | must quote a binary string out of it. - # | - - if(($module_language eq "vhdl") and ($type =~ /^.*\((\d+) downto (\d+)\).*$/)) - { - my ($high_bit,$low_bit) = ($1,$2); - my $binary = ""; - for(my $bit = $low_bit; $bit <= $high_bit; $bit++) - { - $binary = ($number % 2) . $binary; - $number = int($number >> 1); - } - - $number = '"' . $binary . '"'; - } - - return $number; - } - -# -# return @array of vhdl libraries, if any, from the class.ptf -sub get_libraries() -{ - my $class_ptf = generator_get_class_ptf_handle(); - my @libraries; - my $libraries_ptf = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/LIBRARIES"); - - if($libraries_ptf) - { - my $library_count = get_child_count($libraries_ptf,"library"); - for(my $i = 0; $i < $library_count; $i++) - { - my $library_ptf = get_child($libraries_ptf,$i,"library"); - my $library_name = get_data($library_ptf); - push(@libraries,$library_name); - } - } - - return @libraries; -} - - - -sub _generator_make_module_wrapper -{ - - my $wrapper_args = $generator_hr->{wrapper_args}; - my $no_black_box = $wrapper_args->{simulate_hdl}; - my $top_module_name = $wrapper_args->{top_module_name}; - my $language = $generator_hr->{language}; - my @external_args = @{$generator_hr->{external_args}}; - my $module_ptf_hr = $generator_hr->{module_ptf_hr}; - - ### Build Module - my $project = e_project->new(@external_args); - my $top = $project->top(); - - # add the ports to the system module - my @ports; - - foreach my $port_hash(@{$wrapper_args->{ports}}){ - my $porto = e_port->new({ - name => $port_hash->{name}, - width => $port_hash->{width}, - direction => $port_hash->{direction}, - vhdl_record_name => $port_hash->{vhdl_record_name}, - vhdl_record_type => $port_hash->{vhdl_record_type} - }); - push(@ports, $porto); - } - $top->add_contents(@ports); - - - - - - # +---------------------------------------- - # | Get parameters from class.ptf - # | create @array of parameters, eacho - # | one like name=>, default=>, type=>, - # | - # | These are the definitions of parameters for - # | ANY instance of this module; we need to - # | have them in the "wrapee" module so that - # | when the system bus is knitted together - # | the parameter types can be properly used. - # | - # | (as it turns out, verilog doesnt need - # | them, but vhld does) - # | - # | dvb2004 - - - my @e_hdl_parameters; # list of e_parameters - - my $class_ptf = generator_get_class_ptf_handle(); - my $hdl_parameter_definitions_ptf = get_child_by_path($class_ptf,"CLASS/COMPONENT_BUILDER/HDL_PARAMETERS"); - - my @libraries = get_libraries(); - - my $hdl_parameter_count = get_child_count($hdl_parameter_definitions_ptf,"HDL_PARAMETER"); - - my $module_language = $generator_hr->{wrapper_args}{module_language}; - - for(my $i = 0; $i < $hdl_parameter_count; $i++) - { - my $a_parameter = get_child($hdl_parameter_definitions_ptf,$i,"HDL_PARAMETER"); - my $parameter_editable = get_data_by_path($a_parameter,"editable"); - if($parameter_editable) - { - my $boring_name = get_data($a_parameter); # legal guinevere-ized - my $name = get_data_by_path($a_parameter,"parameter_name"); # original HDL name - my $default = get_data_by_path($a_parameter,"default_value"); - my $type = get_data_by_path($a_parameter,"type"); - - $default = turn_anything_into_appropriate_string($default,$type,1,$module_language); - - my $a_parameter = e_parameter->new - ({ - name => $name, - default => $default, - type => $type - }); - - push (@e_hdl_parameters,$a_parameter); - } - } - - - - # | and @e_hdl_parameters is used below in the wrapee module - # +-------------------------------------------- - - # +-------------------------------------------- - # | Now, we build a "hdl_parameter_map", which is just - # | your basic hash table with keys (parameters) - # | and values (parameter values). - # | - # | these are the particular values for this instance. - # | - - my %hdl_parameter_map; - my $module_ptf = $generator_hr->{module_ptf_hr}; - my $hdl_parameters_ptf = - get_child_by_path($module_ptf,"WIZARD_SCRIPT_ARGUMENTS/hdl_parameters"); - - my $child_count = get_child_count($hdl_parameters_ptf); - - for(my $i = 0; $i < $child_count; $i++) - { - my $a_parameter = get_child($hdl_parameters_ptf,$i); - - my $boring_name = get_name($a_parameter); - my $value = get_data($a_parameter); - - # refer back to the original HDL name... - my $parameter_definition_ptf = get_child_by_path($hdl_parameter_definitions_ptf,"HDL_PARAMETER $boring_name"); - my $parameter_name = get_data_by_path($parameter_definition_ptf,"parameter_name"); - my $parameter_type = get_data_by_path($parameter_definition_ptf,"type"); - my $parameter_editable = get_data_by_path($parameter_definition_ptf,"editable"); - - $value = turn_anything_into_appropriate_string($value,$parameter_type,$parameter_editable,$module_language); - - # | - # | our internal _dummy assignment shows up here - # | without a corresponding hdl entry. we - # | ignore it. - # | - - if(($parameter_name ne "") and $parameter_editable) - { - $hdl_parameter_map{$parameter_name} = $value; - } - } - - my $wrapee_module; - $wrapee_module = e_module->new({ - name => $top_module_name, - contents => [@ports,@e_hdl_parameters], - do_black_box => 0, - do_ptf => 0, - _hdl_generated => 1, - _explicitly_empty_module => 1, - }); - - # VHDL Libraries, from PTF file... - $wrapee_module->add_vhdl_libraries(@libraries); - $top->add_vhdl_libraries(@libraries); - - - $top->add_contents ( - e_instance->new({ - module => $wrapee_module, - parameter_map => \%hdl_parameter_map - }), - ); - - $project->top()->do_ptf(0); - $project->do_write_ptf(0); - - - my $module_file = $project->_target_module_name().".v"; - $module_file = $project->_target_module_name().".vhd" - if($language eq "vhdl"); - - $module_file = $generator_hr->{project_path_widget}."/".$module_file; - &generator_set_files_in_system_ptf("Synthesis_HDL_Files", ($module_file)); - $project->output(); - - - # if you don't want a simulation model, you don't get a simulation model - if($no_black_box eq "0") - { - my $black_project = e_project->new(@external_args); - $black_project->_target_module_name($top_module_name); - my $black_top = $black_project->top(); - - - - $black_top->add_contents(@ports); - my $black_top_instance; - $black_top_instance = e_module->new({ - name => $wrapper_args->{top_module_name}."_bb", - contents => [@ports], - do_black_box => 1, - do_ptf => 0, - _hdl_generated => 0, - _explicitly_empty_module => 1, - }); - - $black_top->add_contents ( - e_instance->new({ - module => $black_top_instance, - }), - ); - - - - - $black_project->top()->do_ptf(0); - $black_project->do_write_ptf(0); - - my $black_module_file = $black_project->_target_module_name().".v"; - $black_module_file = $black_project->_target_module_name().".vhd" - if($language eq "vhdl"); - - - $black_module_file = $generator_hr->{project_path_widget}."/".$black_module_file; - &generator_set_files_in_system_ptf("Simulation_HDL_Files", ($black_module_file)); - -# &set_data_by_path($module_ptf_hr, "HDL_INFO/Simulation_HDL_Files", $black_module_file); - - - $black_project->output(); - } - -} - -#### -# Args: $file_type : "synthesis", "synthesis_only", "simulation" -# @file_list : an array of files. This list of files is assumed to be relative to the -# component's directory - - -my $decoder_ring_hr = { - quartus_only => { - copy => 1, - copy_to => "project", - ptf_set => 0, - }, - simulation_only => { - copy => 1, - copy_to => "simulation", - ptf_set => 1, - ptf_section => "Simulation_HDL_Files", - }, - simulation_and_quartus => { - copy => 1, - copy_to => "project", - ptf_set => 1, - ptf_section => "Synthesis_HDL_Files", - }, - precompiled_simulation_files => { - copy => 0, - ptf_set => 1, - ptf_section => "Precompiled_Simulation_Library_Files", - }, - }; - - - - -sub generator_copy_files_and_set_system_ptf -{ - my ($hdl_section, @file_list) = (@_); - - my $ptf_path_prefix = ""; - my $external_args_hr = $generator_hr->{external_args_hr}; - my @new_file_array; - - #validate first - my $decoder_hash = $decoder_ring_hr->{$hdl_section}; - &default_ribbit("generator_copy_files_and_set_system_ptf: No understood HDL section passed in for first arg\n") - unless($decoder_ring_hr->{$hdl_section} ne ""); - - &generator_print_verbose("generator_copy_files_and_set_system_ptf: copying files for section ".$hdl_section."\n"); - - #copy second - my @new_file_array; - - # If we need to copy over some files, then we need to make sure we are - # keeping track of what files we copy over. - # Otherwise, we just need to keep track of the files that the user has asked to copy over - # and use these instead. - if($decoder_hash->{copy}){ - my $copy_to_location; - my $copy_from_location; - - if($decoder_hash->{copy_to} eq "project"){ - $copy_to_location = $external_args_hr->{system_directory}; - }elsif($decoder_hash->{copy_to} eq "simulation"){ - $copy_to_location = $external_args_hr->{system_sim_dir}; - }else{ - &default_ribbit("generator_copy_files_and_set_system_ptf: No understood copy files to location\n"); - } - - $copy_from_location = $external_args_hr->{class_directory}; - @new_file_array = &generator_copy_files($copy_to_location, $copy_from_location, @file_list); - }else{ - @new_file_array = @file_list; - } - - #scribble on PTF hash last - if($decoder_hash->{ptf_set}){ - - if($decoder_hash->{copy_to} eq "project"){ - foreach my $file(@new_file_array){ - $file =~ s/^.*\/(.*?)$/$1/; - $file = $generator_hr->{project_path_widget}."/".$file; - } - } - &generator_print_verbose("generator_copy_files_and_set_system_ptf: setting system PTF file in section ".$hdl_section."\n"); - if($decoder_hash->{ptf_section} eq "Precompiled_Simulation_Library_Files"){ - @new_file_array = map{$external_args_hr->{class_directory}."/".$_} @new_file_array; - } - &generator_set_files_in_system_ptf($decoder_hash->{ptf_section}, @new_file_array); - } -} - - - -#### -# Name: generator_set_files_in_system_ptf -# Args: $hdl_section -# @list_of_files -# Returns: 1 or 0 -# Purpose: This is an internal function used to set files in the module's section in the system PTF file -# -sub generator_set_files_in_system_ptf -{ - my ($hdl_section, @list_of_files) = (@_); - - my $file_list = join(",", @list_of_files); - my $previous_data; - - &generator_print_verbose("setting HDL_INFO/".$hdl_section." in system PTF file with ".$file_list."\n"); - my $previous_data = &get_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section); - if($previous_data){ - $file_list = $previous_data . ", $file_list"; # spr 132177 - # swapping order, dvb 2003 - } - &set_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section, $file_list); -} - -#### -# Name: generator_copy_files -# Args: $target_directory -# $source_directory -# @list_of_files -# Returns: The list of files which has been copied (suitable for framing!) -# Purpose: This is an internal function used to copy files around in the generator program. -# -sub generator_copy_files -{ - my ($target_directory, $source_directory, @list_of_files) = (@_); - - my @new_file_array; - - foreach my $file_name(@list_of_files){ - $file_name =~ s|\\|\/|g; - if($file_name =~ /\*\.*/){ - $file_name =~ s/\*/$1/; - my @found_list = &_find_all_dir_files_with_ext($source_directory, $file_name); - push(@new_file_array, @found_list); - }else{ - &generator_print_verbose("Copying: ".$file_name."\n"); - push(@new_file_array, $file_name); - } - } - - &_copy_files($target_directory, $source_directory, @new_file_array); - return @new_file_array; -} - - - -sub _find_all_dir_files_with_ext -{ - my ($dir, - $ext) = (@_); - - opendir (DIR, $dir) or - &default_ribbit("can't open $dir !"); - - my @all_files = readdir(DIR); - my @new_file_list; - - - foreach my $file (@all_files){ - if($file =~ /^.*($ext)$/){ - push(@new_file_list, $file); - } - } - - return @new_file_list; -} - -#### -# Name: generator_begin -# Args: Array of generator program launcher args -# Returns: A hash reference to the module's section in the system PTF file -# Purpose: This is the first subroutine a user should call before running the rest of their -# generator program. -# - -sub generator_begin -{ - my @external_args = (@_); - - my ($external_args_hr, - $temp_user_defined, - $temp_db_Module, - $temp_db_PTF_File) = Process_Wizard_Script_Arguments("", @external_args); - - &generator_print_verbose("generator_begin: initializing\n"); - - $generator_hr->{external_args_hr} = $external_args_hr; - $generator_hr->{external_args} = \@external_args; - - # open up class.ptf and - $generator_hr->{class_ptf_hr} = new_ptf_from_file($external_args_hr->{class_directory}."/class.ptf"); - - # get the system.ptf - $generator_hr->{system_ptf_hr} = new_ptf_from_file($external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"); - $generator_hr->{module_ptf_hr} = &get_child_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/MODULE $external_args_hr->{target_module_name}"); - my $class_name = get_data_by_path($generator_hr->{module_ptf_hr}, "class"); - - # find the default generator section - $generator_hr->{language} = get_data_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/WIZARD_SCRIPT_ARGUMENTS/hdl_language"); - - # get some wrapper settings - &get_module_wrapper_arg_hash_from_system_ptf_file(); - - # clear system ptf's HDL section - &delete_child($generator_hr->{module_ptf_hr}, "HDL_INFO"); - - return $generator_hr->{module_ptf_hr}; -} - -#### -# Name: generator_end -# Args: none -# Returns: nothing -# Purpose: This is the last subroutine a user should call from their generator program. -# Not calling this subroutine will make you very sad... =< -# - -sub generator_end -{ - # o.k., time to make the wrapper and output it. - if($generator_hr->{wrapper_args}{make_wrapper}){ - &_generator_make_module_wrapper(); - } - - - my $external_args_hr = $generator_hr->{external_args_hr}; - my $ptf_file_name = $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"; - &generator_print_verbose("generator_end: writing PTF file ".$external_args_hr->{system_name}.".ptf to ".$external_args_hr->{system_directory}."\n"); - - default_ribbit("Cannot write PTF file ".$ptf_file_name."!\n") - unless(&write_ptf_file($generator_hr->{system_ptf_hr}, $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf")); -} - -sub generator_end_read_module_wrapper_string -{ - my $language = &generator_get_language(); - my $ls; - - if($language =~ /vhdl/){ - $ls = ".vhd"; - }elsif($language =~ /verilog/){ - $ls = ".v"; - }else{ - &ribbit("generator_end_read_module_wrapper_string invoked with unkown language"); - } - my $system_dir = $generator_hr->{external_args_hr}->{system_directory}; - my $module_name = $generator_hr->{external_args_hr}->{target_module_name}; - - my $file = $system_dir."/".$module_name.$ls; - &generator_print_verbose("generator library reading file into string: $file\n"); - - open (FILE,"<$file") or ribbit "cannot open file ($file) ($!)\n"; - my $return_string; - while (
sdram_ctrl/trunk/doc/sdram_ctrl.sxw
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sdram_ctrl/trunk/syn/sdram_ctrl/cb_generator.pl
===================================================================
--- sdram_ctrl/trunk/syn/sdram_ctrl/cb_generator.pl (nonexistent)
+++ sdram_ctrl/trunk/syn/sdram_ctrl/cb_generator.pl (revision 8)
@@ -0,0 +1,1159 @@
+# | file: cb_generator.pl
+# |
+# | This SOPC Builder Generator program is provided by
+# | the Component Builder application. It is copied
+# | straight across and is data-driven from its command
+# | line arguments and the PTF files referenced.
+# |
+# | Its purpose is to construct an HDL "wrapper" for
+# | a particular instance of a particular SOPC Builder
+# | peripheral. This wrapper resolves the instance
+# | name and any HDL parameterization.
+# |
+# +-------------------------------------------
+
+
+
+# +-------------------------------------------
+# |
+
+use strict;
+use format_conversion_utils;
+use ptf_parse;
+use wiz_utils;
+use europa_all;
+use run_system_command_utils;
+
+# |
+# +-------------------------------------------
+
+
+
+# +-------------------------------------------
+# |
+# | first pass: include all of generator_libarary.pm RIGHT HERE.
+# | dvb04.08.02
+# | then prune down to actual functionality.
+# |
+# | TODO: Rewrite this whole file into something readable
+# | this is much more confusing than I'm comfortable with. dvb04.
+# | (though it does seem to work.)
+# |
+
+my $DEBUG_DEFAULT_GEN = 1;
+
+#This is the global hash of arguments passed in by the generator program
+
+my $generator_hr = {
+ wrapper_args => {
+ make_wrapper => 0,
+ top_module_name => "",
+ simulate_hdl => 1,
+ ports => "",
+ },
+ class_ptf_hr => "",
+ module_ptf_hr => "",
+ system_ptf_hr => "",
+ language => "",
+ external_args => "",
+ external_args_hr => "",
+ project_path_widget => "__PROJECT_DIRECTORY__",
+ generator_mode => "silent",
+ };
+
+
+sub generator_print_verbose
+{
+ my ($info) = (@_);
+
+ if($generator_hr->{generator_mode} eq "verbose"){
+ print("cb_generator.pl: ".$info);
+ }
+}
+
+sub generator_enable_mode
+{
+ my ($mode) = (@_);
+ $generator_hr->{generator_mode} = $mode;
+}
+
+sub generator_get_system_ptf_handle
+{
+ return $generator_hr->{system_ptf_hr};
+}
+
+sub generator_get_language
+{
+ return $generator_hr->{language};
+}
+
+sub generator_get_class_ptf_handle
+{
+ return $generator_hr->{class_ptf_hr};
+}
+
+sub default_ribbit
+{
+ my ($arg) = (@_);
+ &ribbit("\n\n--Error: default_gen_lib: $arg\n");
+}
+
+
+sub _copy_files
+{
+ my ($dest_dir, $source_dir, @files) = (@_);
+ my $function_name;
+
+ #validate args
+ &default_ribbit("No target dir for function copy_files!")
+ unless ($dest_dir ne "");
+
+ &default_ribbit("No source dir for function copy_files!")
+ unless ($source_dir ne "");
+
+ &default_ribbit("No files for function copy_files!")
+ unless (@files != 0);
+
+
+ #check for valid directories
+ opendir (SDIR, $source_dir) or
+ &default_ribbit("can't open $source_dir !");
+
+ opendir (DDIR, $dest_dir) or
+ &default_ribbit("can't open $dest_dir !");
+
+
+ foreach my $source_file(@files){
+ # |
+ # | Separate out the source subdir and the source filename
+ # |
+ my $source_subdir = "";
+ my $source_filename = $source_file;
+
+ if($source_filename =~ /^(.*)\/(.*)$/) # break on last slash
+ {
+ $source_subdir = "/$1"; # embed its leading slash, for concatty
+ $source_filename = $2;
+ }
+
+ my $source_fullpath = "$source_dir$source_subdir/$source_filename";
+ my $dest_fullpath = "$dest_dir/$source_filename";
+
+ &Perlcopy($source_fullpath, $dest_fullpath);
+ &generator_print_verbose("Copying file: \"$source_fullpath\""
+ . " to \"$dest_fullpath\".\n");
+ }
+
+ closedir (SDIR);
+ closedir (DDIR);
+}
+
+
+sub get_module_wrapper_arg_hash_from_system_ptf_file
+{
+ my $module_ptf_hr = $generator_hr->{module_ptf_hr};
+
+ my @list_of_sections = ("MASTER","SLAVE","PORT_WIRING");
+ my @port_list;
+ foreach my $section(@list_of_sections){
+ my $number = get_child_count($module_ptf_hr, $section);
+
+ for(my $initial=0; $initial < $number; $initial++){
+
+ my $interface_section = get_child($module_ptf_hr, $initial, $section);
+ my $interface_section_name = get_data($interface_section);
+
+ my $port_wiring_section;
+ if($section ne "PORT_WIRING"){
+ $port_wiring_section =
+ get_child_by_path($module_ptf_hr, $section." ".$interface_section_name."/PORT_WIRING");
+ }else{
+ $port_wiring_section =
+ get_child_by_path($module_ptf_hr, $section);
+ }
+ my $num_ports = get_child_count($port_wiring_section, "PORT");
+ foreach(my $port_count = 0; $port_count < $num_ports; $port_count++){
+ my $port = get_child($port_wiring_section, $port_count, "PORT");
+
+ my %port_info_struct;
+ $port_info_struct{name} = get_data($port);
+ $port_info_struct{direction} = get_data_by_path($port, "direction");
+ $port_info_struct{width} = get_data_by_path($port, "width");
+ $port_info_struct{vhdl_record_name} = get_data_by_path($port, "vhdl_record_name");
+ $port_info_struct{vhdl_record_type} = get_data_by_path($port, "vhdl_record_type");
+
+ push(@port_list, \%port_info_struct);
+
+ }
+ }
+ }
+ $generator_hr->{wrapper_args}{ports} = \@port_list;
+}
+
+
+sub generator_make_module_wrapper
+{
+ my ($simulate_hdl, $top_module_name, $module_language) = (@_);
+
+ &default_ribbit("generator_make_module_wrapper: no arg0 passed in for simulate_hdl\n")
+ if($simulate_hdl eq '');
+
+ &default_ribbit("generator_make_module_wrapper: no arg1 passed in for top_module_name\n")
+ unless($top_module_name);
+
+ $generator_hr->{wrapper_args}{simulate_hdl} = $simulate_hdl;
+ $generator_hr->{wrapper_args}{top_module_name} = $top_module_name;
+ $generator_hr->{wrapper_args}{make_wrapper} = 1;
+ $generator_hr->{wrapper_args}{module_language} = $module_language;
+
+}
+
+
+
+
+# |
+# | recognize varous number forms,
+# | return 'h0123abcd-ish.
+# |
+sub turn_anything_into_appropriate_string($$$$)
+ {
+ my ($value,$type,$editable,$module_language) = (@_);
+
+ return $value if($value =~ /^\"/); # quoted string: unscathed
+ return $value if($type eq "string"); # string: anything is ok
+
+ return $value if(!$editable); # and you know, if you can't change it, keep it!
+
+
+ # |
+ # | first, convert to a number
+ # |
+ my $base = 10;
+ my $n = $value;
+ my $width = 32;
+ my $number = 0;
+
+ $value = lc($value); # lower case
+
+ if($value =~ /^([0-9]*)\'([hbo])(.*)$/)
+ {
+ # | tick notation: AOK for verilog
+ if($module_language eq "verilog")
+ {
+ $number = $value;
+ }
+ # |
+ # | note: at this point, we could notice if the
+ # | result should be vhdl binary, and convert
+ # | to that, avoiding the precision-losing
+ # | integer intermediary
+ # |
+ # | (alternatively, we could use a binary string
+ # | always as the intermediate form, rather than
+ # | a precision-losing int.)
+ # |
+ else
+ {
+ $width = $1;
+ my $baseletter = $2;
+ my $digits = $3;
+
+ if($baseletter eq "h")
+ {
+ $base = 16;
+ }
+ elsif($baseletter eq "b")
+ {
+ $base = 2;
+ }
+ elsif($baseletter eq "o") # must be
+ {
+ $base = 8;
+ }
+
+ $digits =~ s/[ _-]//g; # crush out dividing value
+
+ while(length($digits) > 0)
+ {
+ my $digit = substr($digits,0,1);
+ $digits = substr($digits,1);
+ my $digitvalue = hex($digit); # how handy
+ $number = $number * $base + $digitvalue;
+ }
+ }
+ }
+ elsif($value =~ /^0x(.*)$/)
+ {
+ $number = hex($1);
+ }
+ else # try for decimal
+ {
+ $number = int(1 * $value);
+ }
+
+ # |
+ # | ok, we have a number. If our target type
+ # | is "std_logic_vector(this downto that)"
+ # | for tricky VHDL, we
+ # | must quote a binary string out of it.
+ # |
+
+ if(($module_language eq "vhdl") and ($type =~ /^.*\((\d+) downto (\d+)\).*$/))
+ {
+ my ($high_bit,$low_bit) = ($1,$2);
+ my $binary = "";
+ for(my $bit = $low_bit; $bit <= $high_bit; $bit++)
+ {
+ $binary = ($number % 2) . $binary;
+ $number = int($number >> 1);
+ }
+
+ $number = '"' . $binary . '"';
+ }
+
+ return $number;
+ }
+
+#
+# return @array of vhdl libraries, if any, from the class.ptf
+sub get_libraries()
+{
+ my $class_ptf = generator_get_class_ptf_handle();
+ my @libraries;
+ my $libraries_ptf = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/LIBRARIES");
+
+ if($libraries_ptf)
+ {
+ my $library_count = get_child_count($libraries_ptf,"library");
+ for(my $i = 0; $i < $library_count; $i++)
+ {
+ my $library_ptf = get_child($libraries_ptf,$i,"library");
+ my $library_name = get_data($library_ptf);
+ push(@libraries,$library_name);
+ }
+ }
+
+ return @libraries;
+}
+
+
+
+sub _generator_make_module_wrapper
+{
+
+ my $wrapper_args = $generator_hr->{wrapper_args};
+ my $no_black_box = $wrapper_args->{simulate_hdl};
+ my $top_module_name = $wrapper_args->{top_module_name};
+ my $language = $generator_hr->{language};
+ my @external_args = @{$generator_hr->{external_args}};
+ my $module_ptf_hr = $generator_hr->{module_ptf_hr};
+
+ ### Build Module
+ my $project = e_project->new(@external_args);
+ my $top = $project->top();
+
+ # add the ports to the system module
+ my @ports;
+
+ foreach my $port_hash(@{$wrapper_args->{ports}}){
+ my $porto = e_port->new({
+ name => $port_hash->{name},
+ width => $port_hash->{width},
+ direction => $port_hash->{direction},
+ vhdl_record_name => $port_hash->{vhdl_record_name},
+ vhdl_record_type => $port_hash->{vhdl_record_type}
+ });
+ push(@ports, $porto);
+ }
+ $top->add_contents(@ports);
+
+
+
+
+
+ # +----------------------------------------
+ # | Get parameters from class.ptf
+ # | create @array of parameters, eacho
+ # | one like name=>, default=>, type=>,
+ # |
+ # | These are the definitions of parameters for
+ # | ANY instance of this module; we need to
+ # | have them in the "wrapee" module so that
+ # | when the system bus is knitted together
+ # | the parameter types can be properly used.
+ # |
+ # | (as it turns out, verilog doesnt need
+ # | them, but vhld does)
+ # |
+ # | dvb2004
+
+
+ my @e_hdl_parameters; # list of e_parameters
+
+ my $class_ptf = generator_get_class_ptf_handle();
+ my $hdl_parameter_definitions_ptf = get_child_by_path($class_ptf,"CLASS/COMPONENT_BUILDER/HDL_PARAMETERS");
+
+ my @libraries = get_libraries();
+
+ my $hdl_parameter_count = get_child_count($hdl_parameter_definitions_ptf,"HDL_PARAMETER");
+
+ my $module_language = $generator_hr->{wrapper_args}{module_language};
+
+ for(my $i = 0; $i < $hdl_parameter_count; $i++)
+ {
+ my $a_parameter = get_child($hdl_parameter_definitions_ptf,$i,"HDL_PARAMETER");
+ my $parameter_editable = get_data_by_path($a_parameter,"editable");
+ if($parameter_editable)
+ {
+ my $boring_name = get_data($a_parameter); # legal guinevere-ized
+ my $name = get_data_by_path($a_parameter,"parameter_name"); # original HDL name
+ my $default = get_data_by_path($a_parameter,"default_value");
+ my $type = get_data_by_path($a_parameter,"type");
+
+ $default = turn_anything_into_appropriate_string($default,$type,1,$module_language);
+
+ my $a_parameter = e_parameter->new
+ ({
+ name => $name,
+ default => $default,
+ type => $type
+ });
+
+ push (@e_hdl_parameters,$a_parameter);
+ }
+ }
+
+
+
+ # | and @e_hdl_parameters is used below in the wrapee module
+ # +--------------------------------------------
+
+ # +--------------------------------------------
+ # | Now, we build a "hdl_parameter_map", which is just
+ # | your basic hash table with keys (parameters)
+ # | and values (parameter values).
+ # |
+ # | these are the particular values for this instance.
+ # |
+
+ my %hdl_parameter_map;
+ my $module_ptf = $generator_hr->{module_ptf_hr};
+ my $hdl_parameters_ptf =
+ get_child_by_path($module_ptf,"WIZARD_SCRIPT_ARGUMENTS/hdl_parameters");
+
+ my $child_count = get_child_count($hdl_parameters_ptf);
+
+ for(my $i = 0; $i < $child_count; $i++)
+ {
+ my $a_parameter = get_child($hdl_parameters_ptf,$i);
+
+ my $boring_name = get_name($a_parameter);
+ my $value = get_data($a_parameter);
+
+ # refer back to the original HDL name...
+ my $parameter_definition_ptf = get_child_by_path($hdl_parameter_definitions_ptf,"HDL_PARAMETER $boring_name");
+ my $parameter_name = get_data_by_path($parameter_definition_ptf,"parameter_name");
+ my $parameter_type = get_data_by_path($parameter_definition_ptf,"type");
+ my $parameter_editable = get_data_by_path($parameter_definition_ptf,"editable");
+
+ $value = turn_anything_into_appropriate_string($value,$parameter_type,$parameter_editable,$module_language);
+
+ # |
+ # | our internal _dummy assignment shows up here
+ # | without a corresponding hdl entry. we
+ # | ignore it.
+ # |
+
+ if(($parameter_name ne "") and $parameter_editable)
+ {
+ $hdl_parameter_map{$parameter_name} = $value;
+ }
+ }
+
+ my $wrapee_module;
+ $wrapee_module = e_module->new({
+ name => $top_module_name,
+ contents => [@ports,@e_hdl_parameters],
+ do_black_box => 0,
+ do_ptf => 0,
+ _hdl_generated => 1,
+ _explicitly_empty_module => 1,
+ });
+
+ # VHDL Libraries, from PTF file...
+ $wrapee_module->add_vhdl_libraries(@libraries);
+ $top->add_vhdl_libraries(@libraries);
+
+
+ $top->add_contents (
+ e_instance->new({
+ module => $wrapee_module,
+ parameter_map => \%hdl_parameter_map
+ }),
+ );
+
+ $project->top()->do_ptf(0);
+ $project->do_write_ptf(0);
+
+
+ my $module_file = $project->_target_module_name().".v";
+ $module_file = $project->_target_module_name().".vhd"
+ if($language eq "vhdl");
+
+ $module_file = $generator_hr->{project_path_widget}."/".$module_file;
+ &generator_set_files_in_system_ptf("Synthesis_HDL_Files", ($module_file));
+ $project->output();
+
+
+ # if you don't want a simulation model, you don't get a simulation model
+ if($no_black_box eq "0")
+ {
+ my $black_project = e_project->new(@external_args);
+ $black_project->_target_module_name($top_module_name);
+ my $black_top = $black_project->top();
+
+
+
+ $black_top->add_contents(@ports);
+ my $black_top_instance;
+ $black_top_instance = e_module->new({
+ name => $wrapper_args->{top_module_name}."_bb",
+ contents => [@ports],
+ do_black_box => 1,
+ do_ptf => 0,
+ _hdl_generated => 0,
+ _explicitly_empty_module => 1,
+ });
+
+ $black_top->add_contents (
+ e_instance->new({
+ module => $black_top_instance,
+ }),
+ );
+
+
+
+
+ $black_project->top()->do_ptf(0);
+ $black_project->do_write_ptf(0);
+
+ my $black_module_file = $black_project->_target_module_name().".v";
+ $black_module_file = $black_project->_target_module_name().".vhd"
+ if($language eq "vhdl");
+
+
+ $black_module_file = $generator_hr->{project_path_widget}."/".$black_module_file;
+ &generator_set_files_in_system_ptf("Simulation_HDL_Files", ($black_module_file));
+
+# &set_data_by_path($module_ptf_hr, "HDL_INFO/Simulation_HDL_Files", $black_module_file);
+
+
+ $black_project->output();
+ }
+
+}
+
+####
+# Args: $file_type : "synthesis", "synthesis_only", "simulation"
+# @file_list : an array of files. This list of files is assumed to be relative to the
+# component's directory
+
+
+my $decoder_ring_hr = {
+ quartus_only => {
+ copy => 1,
+ copy_to => "project",
+ ptf_set => 0,
+ },
+ simulation_only => {
+ copy => 1,
+ copy_to => "simulation",
+ ptf_set => 1,
+ ptf_section => "Simulation_HDL_Files",
+ },
+ simulation_and_quartus => {
+ copy => 1,
+ copy_to => "project",
+ ptf_set => 1,
+ ptf_section => "Synthesis_HDL_Files",
+ },
+ precompiled_simulation_files => {
+ copy => 0,
+ ptf_set => 1,
+ ptf_section => "Precompiled_Simulation_Library_Files",
+ },
+ };
+
+
+
+
+sub generator_copy_files_and_set_system_ptf
+{
+ my ($hdl_section, @file_list) = (@_);
+
+ my $ptf_path_prefix = "";
+ my $external_args_hr = $generator_hr->{external_args_hr};
+ my @new_file_array;
+
+ #validate first
+ my $decoder_hash = $decoder_ring_hr->{$hdl_section};
+ &default_ribbit("generator_copy_files_and_set_system_ptf: No understood HDL section passed in for first arg\n")
+ unless($decoder_ring_hr->{$hdl_section} ne "");
+
+ &generator_print_verbose("generator_copy_files_and_set_system_ptf: copying files for section ".$hdl_section."\n");
+
+ #copy second
+ my @new_file_array;
+
+ # If we need to copy over some files, then we need to make sure we are
+ # keeping track of what files we copy over.
+ # Otherwise, we just need to keep track of the files that the user has asked to copy over
+ # and use these instead.
+ if($decoder_hash->{copy}){
+ my $copy_to_location;
+ my $copy_from_location;
+
+ if($decoder_hash->{copy_to} eq "project"){
+ $copy_to_location = $external_args_hr->{system_directory};
+ }elsif($decoder_hash->{copy_to} eq "simulation"){
+ $copy_to_location = $external_args_hr->{system_sim_dir};
+ }else{
+ &default_ribbit("generator_copy_files_and_set_system_ptf: No understood copy files to location\n");
+ }
+
+ $copy_from_location = $external_args_hr->{class_directory};
+ @new_file_array = &generator_copy_files($copy_to_location, $copy_from_location, @file_list);
+ }else{
+ @new_file_array = @file_list;
+ }
+
+ #scribble on PTF hash last
+ if($decoder_hash->{ptf_set}){
+
+ if($decoder_hash->{copy_to} eq "project"){
+ foreach my $file(@new_file_array){
+ $file =~ s/^.*\/(.*?)$/$1/;
+ $file = $generator_hr->{project_path_widget}."/".$file;
+ }
+ }
+ &generator_print_verbose("generator_copy_files_and_set_system_ptf: setting system PTF file in section ".$hdl_section."\n");
+ if($decoder_hash->{ptf_section} eq "Precompiled_Simulation_Library_Files"){
+ @new_file_array = map{$external_args_hr->{class_directory}."/".$_} @new_file_array;
+ }
+ &generator_set_files_in_system_ptf($decoder_hash->{ptf_section}, @new_file_array);
+ }
+}
+
+
+
+####
+# Name: generator_set_files_in_system_ptf
+# Args: $hdl_section
+# @list_of_files
+# Returns: 1 or 0
+# Purpose: This is an internal function used to set files in the module's section in the system PTF file
+#
+sub generator_set_files_in_system_ptf
+{
+ my ($hdl_section, @list_of_files) = (@_);
+
+ my $file_list = join(",", @list_of_files);
+ my $previous_data;
+
+ &generator_print_verbose("setting HDL_INFO/".$hdl_section." in system PTF file with ".$file_list."\n");
+ my $previous_data = &get_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section);
+ if($previous_data){
+ $file_list = $previous_data . ", $file_list"; # spr 132177
+ # swapping order, dvb 2003
+ }
+ &set_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section, $file_list);
+}
+
+####
+# Name: generator_copy_files
+# Args: $target_directory
+# $source_directory
+# @list_of_files
+# Returns: The list of files which has been copied (suitable for framing!)
+# Purpose: This is an internal function used to copy files around in the generator program.
+#
+sub generator_copy_files
+{
+ my ($target_directory, $source_directory, @list_of_files) = (@_);
+
+ my @new_file_array;
+
+ foreach my $file_name(@list_of_files){
+ $file_name =~ s|\\|\/|g;
+ if($file_name =~ /\*\.*/){
+ $file_name =~ s/\*/$1/;
+ my @found_list = &_find_all_dir_files_with_ext($source_directory, $file_name);
+ push(@new_file_array, @found_list);
+ }else{
+ &generator_print_verbose("Copying: ".$file_name."\n");
+ push(@new_file_array, $file_name);
+ }
+ }
+
+ &_copy_files($target_directory, $source_directory, @new_file_array);
+ return @new_file_array;
+}
+
+
+
+sub _find_all_dir_files_with_ext
+{
+ my ($dir,
+ $ext) = (@_);
+
+ opendir (DIR, $dir) or
+ &default_ribbit("can't open $dir !");
+
+ my @all_files = readdir(DIR);
+ my @new_file_list;
+
+
+ foreach my $file (@all_files){
+ if($file =~ /^.*($ext)$/){
+ push(@new_file_list, $file);
+ }
+ }
+
+ return @new_file_list;
+}
+
+####
+# Name: generator_begin
+# Args: Array of generator program launcher args
+# Returns: A hash reference to the module's section in the system PTF file
+# Purpose: This is the first subroutine a user should call before running the rest of their
+# generator program.
+#
+
+sub generator_begin
+{
+ my @external_args = (@_);
+
+ my ($external_args_hr,
+ $temp_user_defined,
+ $temp_db_Module,
+ $temp_db_PTF_File) = Process_Wizard_Script_Arguments("", @external_args);
+
+ &generator_print_verbose("generator_begin: initializing\n");
+
+ $generator_hr->{external_args_hr} = $external_args_hr;
+ $generator_hr->{external_args} = \@external_args;
+
+ # open up class.ptf and
+ $generator_hr->{class_ptf_hr} = new_ptf_from_file($external_args_hr->{class_directory}."/class.ptf");
+
+ # get the system.ptf
+ $generator_hr->{system_ptf_hr} = new_ptf_from_file($external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf");
+ $generator_hr->{module_ptf_hr} = &get_child_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/MODULE $external_args_hr->{target_module_name}");
+ my $class_name = get_data_by_path($generator_hr->{module_ptf_hr}, "class");
+
+ # find the default generator section
+ $generator_hr->{language} = get_data_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/WIZARD_SCRIPT_ARGUMENTS/hdl_language");
+
+ # get some wrapper settings
+ &get_module_wrapper_arg_hash_from_system_ptf_file();
+
+ # clear system ptf's HDL section
+ &delete_child($generator_hr->{module_ptf_hr}, "HDL_INFO");
+
+ return $generator_hr->{module_ptf_hr};
+}
+
+####
+# Name: generator_end
+# Args: none
+# Returns: nothing
+# Purpose: This is the last subroutine a user should call from their generator program.
+# Not calling this subroutine will make you very sad... =<
+#
+
+sub generator_end
+{
+ # o.k., time to make the wrapper and output it.
+ if($generator_hr->{wrapper_args}{make_wrapper}){
+ &_generator_make_module_wrapper();
+ }
+
+
+ my $external_args_hr = $generator_hr->{external_args_hr};
+ my $ptf_file_name = $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf";
+ &generator_print_verbose("generator_end: writing PTF file ".$external_args_hr->{system_name}.".ptf to ".$external_args_hr->{system_directory}."\n");
+
+ default_ribbit("Cannot write PTF file ".$ptf_file_name."!\n")
+ unless(&write_ptf_file($generator_hr->{system_ptf_hr}, $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"));
+}
+
+sub generator_end_read_module_wrapper_string
+{
+ my $language = &generator_get_language();
+ my $ls;
+
+ if($language =~ /vhdl/){
+ $ls = ".vhd";
+ }elsif($language =~ /verilog/){
+ $ls = ".v";
+ }else{
+ &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
+ }
+ my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
+ my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
+
+ my $file = $system_dir."/".$module_name.$ls;
+ &generator_print_verbose("generator library reading file into string: $file\n");
+
+ open (FILE,"<$file") or ribbit "cannot open file ($file) ($!)\n";
+ my $return_string;
+ while ()
+ {
+ $return_string .= $_;
+ }
+ close (FILE);
+ return($return_string);
+}
+
+sub generator_end_write_module_wrapper_string
+{
+ my $string = shift or ribbit "no string specified\n";
+
+ my $language = &generator_get_language();
+ my $ls;
+
+ print $language;
+
+ if($language =~ /vhdl/){
+ $ls = ".vhd";
+ }elsif($language =~ /verilog/){
+ $ls = ".v";
+ }else{
+ &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
+ }
+ my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
+ my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
+
+ my $file = $system_dir."/".$module_name.$ls;
+ &generator_print_verbose("generator library writing string into file: $file\n");
+
+ open (FILE,">$file") or ribbit "cannot open file ($file) ($!)\n";
+ print FILE $string;
+ close (FILE);
+}
+# end of generator_library.pm
+
+
+
+
+
+#
+#
+#
+#
+# ---------------------------------------------------------------------
+
+# +----------------------------------------------------
+# | emit_system_h
+# |
+# | if "is_cpu", attempt to emit a system.h
+# | memory map.
+# |
+
+sub emit_system_h($$$)
+ {
+ my ($sopc_directory,$master,$system_ptf) = (@_);
+
+ # |
+ # | Build a system.h file for masters.
+ # |
+
+
+# as of quartus 5.0, we prefer gtf-generate in sopc_builder directly
+
+ my $gtf_generate = "$sopc_directory/bin/gtf-generate";
+ my $gtf_filename = "$sopc_directory/bin/gtf/system.h.gtf";
+
+ if(! -f $gtf_generate)
+ {
+ # but if sopc_builder is missing it for whatever reason,
+ # try the one in sopc_kit_nios2
+
+ my $sopc_kit_nios2 = $ENV{SOPC_KIT_NIOS2};
+ if($sopc_kit_nios2 ne "")
+ {
+ $gtf_generate = "$sopc_kit_nios2/bin/gtf-generate";
+ $gtf_filename = "$sopc_kit_nios2/bin/gtf/system.h.gtf";
+ }
+ }
+
+ # |
+ # | xml template
+ # |
+
+ my $stf_template = <
+
+
+
+
+EOP
+
+ # |
+ # | THINK
+ # |
+
+ my $output_directory = "./${master}_map";
+ my $project_name = "ignored";
+ my $stf_filename = "./${master}_project.stf";
+
+ # |
+ # | build up template variables
+ # |
+
+ my %template_vars;
+ $template_vars{date} = fcu_date_time();
+ $template_vars{whoami} = $0;
+ $template_vars{project_name} = $project_name;
+ $template_vars{system_ptf} = $system_ptf;
+ $template_vars{output_directory} = $output_directory;
+ $template_vars{master} = $master;
+
+ # |
+ # | poke in the values to the template
+ # |
+
+ foreach my $key (sort(keys(%template_vars)))
+ {
+ $stf_template =~ s/--$key--/$template_vars{$key}/gs;
+ }
+
+ ## debug print $stf_template;
+
+ # |
+ # | write out the stf file, so we can soon use it
+ # |
+
+ fcu_write_file($stf_filename,$stf_template);
+
+ # |
+ # | and use it
+ # |
+
+ if(-e $gtf_generate && -e $gtf_filename)
+ {
+
+ my $generate_cmd = $gtf_generate;
+
+ $generate_cmd .= " --output-directory=$output_directory";
+ $generate_cmd .= " --gtf=$gtf_filename";
+ $generate_cmd .= " --stf=$stf_filename";
+
+ r_system($sopc_directory,$generate_cmd);
+
+ # |
+ # | done with it
+ # |
+
+ r_system($sopc_directory,"rm $stf_filename");
+
+ fcu_print_command("Generated memory map \"$output_directory/system.h\"");
+ }
+ else
+ {
+ fcu_print_command("Warning: did NOT emit system.h for $master");
+ }
+
+
+
+
+ }
+
+
+sub r_system($$)
+ {
+ my ($sopc_directory,$cmd) = (@_);
+ fcu_print_command($cmd);
+ return Run_Command_In_Unix_Like_Shell($sopc_directory,$cmd);
+ }
+
+
+
+
+
+
+
+# +------------------------------------------
+# | synthesis and simulation files are are
+# | listed in CLASS/CB_GENERATOR/HDL_FILES.
+# |
+
+sub get_synthesis_files($)
+ {
+ my ($class_ptf) = (@_);
+ my $synthesis_files = "";
+ my $simulation_files = "";
+
+ my $hdl_files = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/HDL_FILES");
+ my $child_count = get_child_count($hdl_files);
+ for(my $i = 0; $i < $child_count; $i++)
+ {
+ my $hdl_file = get_child($hdl_files,$i);
+ if(get_name($hdl_file) eq "FILE")
+ {
+ my $filename = get_data_by_path($hdl_file,"filepath");
+ my $use_in_synthesis = get_data_by_path($hdl_file,"use_in_synthesis");
+ my $use_in_simulation = get_data_by_path($hdl_file,"use_in_simulation");
+
+ if($use_in_synthesis)
+ {
+ $synthesis_files .= ", " if $synthesis_files;
+ $synthesis_files .= $filename;
+ }
+
+ if($use_in_simulation)
+ {
+ $simulation_files .= ", " if $simulation_files;
+ $simulation_files .= $filename;
+ }
+ }
+ }
+
+ return $synthesis_files;
+ }
+
+
+
+
+
+
+
+
+sub main
+ {
+
+ push(@ARGV,"--verbose=1") if 0;
+ my %args = fcu_parse_args(@ARGV);
+
+ if(0)
+ {
+ foreach my $key (sort(keys(%args)))
+ {
+ print("--$key = $args{$key} \n");
+ }
+ }
+
+ # |
+ # | get the arguments we care about
+ # |
+
+ my $class_dir = fcu_get_switch(\%args,"module_lib_dir");
+
+
+ my $target_module_name = fcu_get_switch(\%args,"target_module_name");
+ my $system_name = fcu_get_switch(\%args,"system_name");
+ my $sopc_directory = fcu_get_switch(\%args,"sopc_directory");
+
+ # |
+ # | preflight the arguments a little
+ # |
+
+ my $error_count = 0;
+
+ my $class_ptf_path = "$class_dir/class.ptf";
+ if(!-f $class_ptf_path)
+ {
+ print "error: no class.ptf at \"$class_dir\"\n";
+ $error_count++;
+ }
+
+ die "$error_count errors" if($error_count > 0);
+
+ # +-------------------------------------------
+ # | ok, let us get to work
+ # |
+
+
+ my $class_ptf = new_ptf_from_file($class_ptf_path);
+
+ # |
+ # | emit system.h for this module
+ # | TODO iff Is_CPU i guess.
+ # |
+
+ my $do_emit_system_h = get_data_by_path($class_ptf,
+ "CLASS/CB_GENERATOR/emit_system_h");
+ if($do_emit_system_h)
+ {
+ emit_system_h($sopc_directory,
+ $target_module_name,
+ "./$system_name.ptf");
+ }
+
+ my $top_module_name = get_data_by_path($class_ptf,
+ "CLASS/CB_GENERATOR/top_module_name");
+ my $file_name = "";
+
+ # | stored as file_name.v:module_name, so we break it open
+ if($top_module_name =~ /^(.*):(.*)$/)
+ {
+ $file_name = $1;
+ my $module_name = $2;
+ $top_module_name = $module_name;
+ }
+
+ # | language of this particular module...
+
+ my $module_language = "verilog";
+ if($file_name =~ /^.*\.vhd$/)
+ {
+ $module_language = "vhdl";
+ }
+
+ # |
+ # | consult the CB_GENERATOR/HDL_FILES section regarding
+ # | where our HDL files for synthesis are.
+ # |
+
+
+ my $synthesis_files = get_synthesis_files($class_ptf);
+
+
+ my $instantiate_in_system_module = get_data_by_path($class_ptf,
+ "CLASS/MODULE_DEFAULTS/SYSTEM_BUILDER_INFO/Instantiate_In_System_Module");
+
+
+
+ if($instantiate_in_system_module)
+ {
+ generator_enable_mode ("terse");
+
+
+ generator_begin (@ARGV);
+
+
+ generator_make_module_wrapper(1,$top_module_name,$module_language);
+
+ generator_copy_files_and_set_system_ptf
+ (
+ "simulation_and_quartus",
+ split(/ *, */,$synthesis_files)
+# "$synthesis_files"
+ );
+
+ generator_end ();
+ }
+
+ exit (0);
+ }
+
+$| = 1; # always polite to flush.
+main()
+
+# end of file
Index: sdram_ctrl/trunk/syn/sdram_ctrl/hdl/sdram_ctrl.vhd
===================================================================
--- sdram_ctrl/trunk/syn/sdram_ctrl/hdl/sdram_ctrl.vhd (nonexistent)
+++ sdram_ctrl/trunk/syn/sdram_ctrl/hdl/sdram_ctrl.vhd (revision 8)
@@ -0,0 +1,440 @@
+------------------------------------------------------------------
+--
+-- sdram_ctrl.vhd
+--
+-- Module Description:
+-- SDRAM small&fast controller
+--
+--
+-- To Do:
+-- configurable times
+-- nios simulation support
+--
+-- Author(s):
+-- Aleksey Kuzmenok, ntpqa@opencores.org
+--
+------------------------------------------------------------------
+--
+-- Copyright (C) 2006 Aleksey Kuzmenok and OPENCORES.ORG
+--
+-- This module is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This module is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this software; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+--
+------------------------------------------------------------------
+-- Test results
+-- FPGA SDRAM CLK (not less than)
+-- EP1C12XXXXC8 MT48LC4M32B2TG-7:G 125 MHz
+-- EP1C6XXXXC8 IS42S16100C1-7TL 125 MHz
+--
+------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+entity sdram_ctrl is
+ generic(
+ DATA_WIDTH: integer:=32;
+ BANK_WIDTH: integer:=4;
+ ROW_WIDTH: integer:=12;
+ COLUMN_WIDTH: integer:=8;
+
+ clk_MHz: integer:=120
+ );
+ port(
+ signal clk : IN STD_LOGIC;
+ signal reset : IN STD_LOGIC;
+
+ -- IMPORTANT: for this Avalon(tm) interface
+ -- 'Minimum Arbitration Shares'=1
+ -- 'Max Pending Read Transactions'=9
+ signal avs_nios_chipselect : IN STD_LOGIC;
+ signal avs_nios_address : IN STD_LOGIC_VECTOR ((BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH-1) DOWNTO 0);
+ signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0);
+ signal avs_nios_writedata : IN STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal avs_nios_write : IN STD_LOGIC;
+ signal avs_nios_read : IN STD_LOGIC;
+ signal avs_nios_waitrequest : OUT STD_LOGIC;
+ signal avs_nios_readdata : OUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal avs_nios_readdatavalid : OUT STD_LOGIC;
+
+ -- global export signals
+ signal sdram_cke : OUT STD_LOGIC; -- This pin has fixed state '1'
+ signal sdram_ba : OUT STD_LOGIC_VECTOR ((BANK_WIDTH-1) DOWNTO 0);
+ signal sdram_addr : OUT STD_LOGIC_VECTOR ((ROW_WIDTH-1) DOWNTO 0);
+ signal sdram_cs_n : OUT STD_LOGIC; -- This pin has fixed state '0'
+ signal sdram_ras_n : OUT STD_LOGIC;
+ signal sdram_cas_n : OUT STD_LOGIC;
+ signal sdram_we_n : OUT STD_LOGIC;
+ signal sdram_dq : INOUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal sdram_dqm : OUT STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0)
+ );
+end sdram_ctrl;
+
+architecture behaviour of sdram_ctrl is
+
+ CONSTANT FIFO_WIDTH: integer:=BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
+
+ CONSTANT MODE: std_logic_vector(11 downto 0):="000000110000"; -- 1 word burst, CAS latency=3
+ -- Only two times are configurable
+ -- tINIT delay between powerup and load mode register = 100 us
+ -- tREF refresh period = 15.625 us (64ms/4096rows)
+ CONSTANT INIT_PAUSE_CLOCKS: integer:=(clk_MHz*10000)/91; -- 109.9 us just to be on the save side
+ CONSTANT REFRESH_PERIOD_CLOCKS: integer:=(clk_MHz*1000)/65; -- 15.384 us the same purpose
+ CONSTANT CAS_LATENCY: integer:=3; -- other latencies weren't been tested!
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ rdreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
+ full : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ -- If you ask me why there are so many states, I'll answer that all times are fixed.
+ -- The top speed for MT48LC4M32B2TG-7:G is 7 ns, therefore all times were based on it.
+ -- tRP PRECHARGE command period = 3 clocks
+ -- tRFC AUTO REFRESH period = 10 clocks
+ -- tMRD LOAD MODE REGISTER command to ACTIVE or REFRESH command = 2 clocks
+ -- tRCD ACTIVE to READ or WRITE delay = 3 clocks
+ -- tRAS ACTIVE to PRECHARGE command = 7 clocks
+ -- tRC ACTIVE to ACTIVE command period = 10 clocks
+ -- tWR2 Write recovery time = 2 clocks
+ type states is (
+ INIT0,INIT1,INIT2,INIT3,INIT4,INIT5,INIT6,INIT7,
+ INIT8,INIT9,INIT10,INIT11,INIT12,INIT13,INIT14,INIT15,
+ INIT16,INIT17,INIT18,INIT19,INIT20,INIT21,INIT22,INIT23,INIT24,
+ REFRESH0,REFRESH1,REFRESH2,REFRESH3,REFRESH4,REFRESH5,REFRESH6,REFRESH7,
+ REFRESH8,REFRESH9,REFRESH10,REFRESH11,REFRESH12,REFRESH13,REFRESH14,
+ ACTIVE0,ACTIVE1,ACTIVE2,ACTIVE3,ACTIVE4,
+ IDLE,READ0,WRITE0);
+ signal operation: states;
+
+ signal fifo_q: std_logic_vector((FIFO_WIDTH-1) downto 0);
+
+ signal init_counter: unsigned(15 downto 0):=to_unsigned(INIT_PAUSE_CLOCKS,16);
+ signal refresh_counter: unsigned(15 downto 0);
+ signal active_counter: unsigned(2 downto 0);
+ signal active_address: unsigned((BANK_WIDTH+ROW_WIDTH-1) downto 0);
+
+ signal bank: std_logic_vector((sdram_ba'length-1) downto 0);
+ signal row: std_logic_vector((sdram_addr'length-1) downto 0);
+ signal column: std_logic_vector((COLUMN_WIDTH-1) downto 0);
+ signal be: std_logic_vector((sdram_dqm'length-1) downto 0);
+ signal data: std_logic_vector((sdram_dq'length-1) downto 0);
+
+ signal do_init,do_refresh,do_active,read_is_active,ready,tRCD_not_expired: std_logic:='0';
+
+ signal fifo_rdreq,fifo_empty: std_logic;
+
+ signal read_latency: std_logic_vector(CAS_LATENCY downto 0);
+
+ signal fifo_data: std_logic_vector((FIFO_WIDTH-1) downto 0);
+ signal fifo_wrreq,fifo_wrfull: std_logic;
+
+ signal i_command : STD_LOGIC_VECTOR(4 downto 0);
+ CONSTANT NOP: STD_LOGIC_VECTOR(4 downto 0):="10111";
+ CONSTANT ACTIVE: STD_LOGIC_VECTOR(4 downto 0):="10011";
+ CONSTANT READ: STD_LOGIC_VECTOR(4 downto 0):="10101";
+ CONSTANT WRITE: STD_LOGIC_VECTOR(4 downto 0):="10100";
+ CONSTANT PRECHARGE: STD_LOGIC_VECTOR(4 downto 0):="10010";
+ CONSTANT AUTO_REFRESH: STD_LOGIC_VECTOR(4 downto 0):="10001";
+ CONSTANT LOAD_MODE_REGISTER: STD_LOGIC_VECTOR(4 downto 0):="10000";
+
+ signal i_address : STD_LOGIC_VECTOR((sdram_addr'length-1) DOWNTO 0);
+ signal i_bank : STD_LOGIC_VECTOR((sdram_ba'length-1) DOWNTO 0);
+ signal i_dqm : STD_LOGIC_VECTOR((sdram_dqm'length-1) DOWNTO 0);
+ signal i_data : STD_LOGIC_VECTOR((sdram_dq'length-1) DOWNTO 0);
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of i_command : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_address : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_bank : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_data : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of avs_nios_readdata : signal is "FAST_INPUT_REGISTER=ON";
+begin
+ (sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n) <= i_command;
+ sdram_addr <= i_address;
+ sdram_ba <= i_bank;
+ sdram_dqm <= i_dqm;
+ sdram_dq <= i_data;
+
+ fifo_data<=avs_nios_address & avs_nios_writedata & avs_nios_byteenable & avs_nios_write & avs_nios_read;
+ fifo_wrreq<=(avs_nios_write or avs_nios_read) and avs_nios_chipselect and not fifo_wrfull;
+
+ avs_nios_waitrequest<=fifo_wrfull;
+
+ fifo_rdreq<=not fifo_empty and not do_refresh and not do_active and not read_is_active and ready;
+
+ do_active<='0' when active_address=unsigned((fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)))) else '1';
+ read_is_active<='1' when read_latency(CAS_LATENCY-1 downto 0)>"000" and fifo_q(1)='1' else '0';
+ ready<='1' when operation=IDLE or operation=READ0 or operation=WRITE0 else '0';
+
+ operation_machine:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ operation<=INIT0;
+ active_address<=(others=>'1');
+ elsif rising_edge(clk)
+ then
+
+ bank<=fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length));
+ row<=fifo_q((fifo_q'length-bank'length-1) downto (fifo_q'length-bank'length-row'length));
+ column<=fifo_q((column'length+data'length+be'length+2-1) downto (data'length+be'length+2));
+ data<=fifo_q((data'length+be'length+2-1) downto (be'length+2));
+ be<=fifo_q((be'length+2-1) downto 2);
+
+ case operation is
+ when INIT0=>
+ if do_init='1'
+ then operation<=INIT1;row(10)<='1';
+ end if;
+ when INIT1=>operation<=INIT2;
+ when INIT2=>operation<=INIT3;
+ when INIT3=>operation<=INIT4;
+ when INIT4=>operation<=INIT5;
+ when INIT5=>operation<=INIT6;
+ when INIT6=>operation<=INIT7;
+ when INIT7=>operation<=INIT8;
+ when INIT8=>operation<=INIT9;
+ when INIT9=>operation<=INIT10;
+ when INIT10=>operation<=INIT11;
+ when INIT11=>operation<=INIT12;
+ when INIT12=>operation<=INIT13;
+ when INIT13=>operation<=INIT14;
+ when INIT14=>operation<=INIT15;
+ when INIT15=>operation<=INIT16;
+ when INIT16=>operation<=INIT17;
+ when INIT17=>operation<=INIT18;
+ when INIT18=>operation<=INIT19;
+ when INIT19=>operation<=INIT20;
+ when INIT20=>operation<=INIT21;
+ when INIT21=>operation<=INIT22;
+ when INIT22=>operation<=INIT23;
+ when INIT23=>operation<=INIT24;row<=MODE((row'length-1) downto 0);
+ when INIT24=>operation<=IDLE;
+
+ when REFRESH0=>operation<=REFRESH1;
+ when REFRESH1=>operation<=REFRESH2;
+ when REFRESH2=>operation<=REFRESH3;
+ when REFRESH3=>operation<=REFRESH4;
+ when REFRESH4=>operation<=REFRESH5;
+ when REFRESH5=>operation<=REFRESH6;
+ when REFRESH6=>operation<=REFRESH7;
+ when REFRESH7=>operation<=REFRESH8;
+ when REFRESH8=>operation<=REFRESH9;
+ when REFRESH9=>operation<=REFRESH10;
+ when REFRESH10=>operation<=REFRESH11;
+ when REFRESH11=>operation<=REFRESH12;
+ when REFRESH12=>operation<=REFRESH13;
+ active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
+ when REFRESH13=>operation<=REFRESH14;
+ when REFRESH14=>operation<=IDLE;
+
+ when ACTIVE0=>operation<=ACTIVE1;
+ when ACTIVE1=>operation<=ACTIVE2;
+ when ACTIVE2=>operation<=ACTIVE3;
+ active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
+ when ACTIVE3=>operation<=ACTIVE4;
+ when ACTIVE4=>operation<=IDLE;
+
+ when others=>
+ if do_refresh='1'
+ then
+ if tRCD_not_expired='0' and operation=IDLE
+ then operation<=REFRESH0;row(10)<='1';
+ else operation<=IDLE;
+ end if;
+ elsif do_active='1'
+ then
+ if tRCD_not_expired='0' and operation=IDLE
+ then operation<=ACTIVE0;row(10)<='1';
+ else operation<=IDLE;
+ end if;
+ elsif fifo_empty='1'
+ then
+ operation<=IDLE;
+ elsif fifo_q(1)='1' --write
+ then
+ if read_latency(CAS_LATENCY-1 downto 0)>"000"
+ then operation<=IDLE;
+ else operation<=WRITE0;
+ end if;
+ elsif fifo_q(0)='1' --read
+ then
+ operation<=READ0;
+ end if;
+ end case;
+ end if;
+ end process;
+
+ control_latency:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ read_latency<=(others=>'0');
+ elsif rising_edge(clk)
+ then
+ read_latency<=std_logic_vector(unsigned(read_latency) SLL 1);
+ if operation=READ0
+ then read_latency(0)<='1';
+ else read_latency(0)<='0';
+ end if;
+ end if;
+ end process;
+ latch_readdata:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ avs_nios_readdata<=(others=>'0');
+ avs_nios_readdatavalid<='0';
+ elsif rising_edge(clk)
+ then
+ avs_nios_readdata<=sdram_dq;
+ avs_nios_readdatavalid<=read_latency(CAS_LATENCY);
+ end if;
+ end process;
+ initialization:process(reset,clk)
+ begin
+ if rising_edge(clk)
+ then
+ if init_counter>0
+ then
+ init_counter<=init_counter-1;
+ else do_init<='1';
+ end if;
+ end if;
+ end process;
+ refreshing:process(clk,reset)
+ begin
+ if reset='1'
+ then
+ refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
+ do_refresh<='0';
+ elsif rising_edge(clk)
+ then
+ if refresh_counter=to_unsigned(0,refresh_counter'length)
+ then refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
+ do_refresh<='1';
+ else refresh_counter<=refresh_counter-1;
+ end if;
+ if operation=REFRESH0 or operation=REFRESH5
+ then do_refresh<='0';
+ end if;
+ end if;
+ end process;
+ active_period:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ active_counter<=(others=>'0');
+ tRCD_not_expired<='0';
+ elsif rising_edge(clk)
+ then
+ if operation=ACTIVE3 or operation=REFRESH13
+ then active_counter<=to_unsigned(5,active_counter'length);
+ elsif active_counter>0
+ then active_counter<=active_counter-1;
+ end if;
+ end if;
+ if active_counter>0
+ then tRCD_not_expired<='1';
+ else tRCD_not_expired<='0';
+ end if;
+ end process;
+ latch_controls:process(clk,reset)
+ begin
+ if reset='1'
+ then
+ i_command<=NOP;
+ i_address<=(others=>'0');
+ i_bank<=(others=>'0');
+ i_dqm<=(others=>'0');
+ i_data<=(others=>'Z');
+ elsif rising_edge(clk)
+ then
+ i_command<=NOP;
+ i_bank<=bank;
+ i_address<=(others=>'0');
+ i_address((column'length-1) downto 0)<=column;
+ i_data<=(others=>'Z');
+ i_dqm<=(others=>'0');
+
+ case operation is
+ when INIT1|REFRESH0|ACTIVE0 =>
+ i_command<=PRECHARGE;
+ i_address<=row;
+ when INIT4|INIT14|REFRESH3 =>
+ i_command<=AUTO_REFRESH;
+ when INIT24=>
+ i_command<=LOAD_MODE_REGISTER;
+ i_address<=row;
+ when ACTIVE3|REFRESH13 =>
+ i_command<=ACTIVE;
+ i_address<=row;
+ when READ0 =>
+ i_command<=READ;
+ when WRITE0 =>
+ i_command<=WRITE;
+ i_dqm<=not be;
+ i_data<=data;
+ when OTHERS =>
+ end case;
+ end if;
+ end process;
+
+ fifo: scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ intended_device_family => "Cyclone",
+ lpm_numwords => 4,
+ lpm_showahead => "ON",
+ lpm_type => "scfifo",
+ lpm_width => FIFO_WIDTH,
+ lpm_widthu => 2,
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => "ON"
+ )
+ PORT MAP (
+ rdreq => fifo_rdreq,
+ aclr => reset,
+ clock => clk,
+ wrreq => fifo_wrreq,
+ data => fifo_data,
+ empty => fifo_empty,
+ q => fifo_q,
+ full => fifo_wrfull
+ );
+end behaviour;
Index: sdram_ctrl/trunk/syn/sdram_ctrl/class.ptf
===================================================================
--- sdram_ctrl/trunk/syn/sdram_ctrl/class.ptf (nonexistent)
+++ sdram_ctrl/trunk/syn/sdram_ctrl/class.ptf (revision 8)
@@ -0,0 +1,972 @@
+#
+# This class.ptf file built by Component Editor
+# 2006.09.25.10:24:12
+#
+# DO NOT MODIFY THIS FILE
+# If you hand-modify this file you will likely
+# interfere with Component Editor's ability to
+# read and edit it. And then Component Editor
+# will overwrite your changes anyway. So, for
+# the very best results, just relax and
+# DO NOT MODIFY THIS FILE
+#
+CLASS sdram_ctrl
+{
+ CB_GENERATOR
+ {
+ HDL_FILES
+ {
+ FILE
+ {
+ use_in_simulation = "1";
+ use_in_synthesis = "1";
+ filepath = "hdl/sdram_ctrl.vhd";
+ }
+ }
+ top_module_name = "sdram_ctrl.vhd:sdram_ctrl";
+ emit_system_h = "0";
+ LIBRARIES
+ {
+ library = "ieee.std_logic_1164.all";
+ library = "ieee.numeric_std.all";
+ library = "altera_mf.altera_mf_components.all";
+ library = "std.standard.all";
+ }
+ }
+ MODULE_DEFAULTS global_signals
+ {
+ class = "sdram_ctrl";
+ class_version = "1.1";
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Has_Clock = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ }
+ COMPONENT_BUILDER
+ {
+ GLS_SETTINGS
+ {
+ }
+ }
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "clk";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT reset
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "reset";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_cke
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_ba
+ {
+ width = "-1";
+ width_expression = "((bank_width - 1)) - (0) + 1";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_addr
+ {
+ width = "-1";
+ width_expression = "((row_width - 1)) - (0) + 1";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_cs_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_ras_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_cas_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_we_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_dq
+ {
+ width = "-1";
+ width_expression = "((data_width - 1)) - (0) + 1";
+ direction = "inout";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_dqm
+ {
+ width = "-1";
+ width_expression = "(((data_width / 8) - 1)) - (0) + 1";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ hdl_parameters
+ {
+ data_width = "32";
+ bank_width = "4";
+ row_width = "12";
+ column_width = "8";
+ clk_mhz = "120";
+ }
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ }
+ }
+ SLAVE nios
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Address_Group = "1";
+ Has_Clock = "0";
+ Address_Width = "-1";
+ Address_Alignment = "dynamic";
+ Data_Width = "8";
+ Has_Base_Address = "1";
+ Has_IRQ = "0";
+ Setup_Time = "0";
+ Hold_Time = "0";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ Read_Latency = "0";
+ Maximum_Pending_Read_Transactions = "9";
+ Active_CS_Through_Read_Latency = "0";
+ Is_Printable_Device = "1";
+ Is_Memory_Device = "1";
+ Is_Readable = "1";
+ Is_Writable = "1";
+ Minimum_Uninterrupted_Run_Length = "1";
+ }
+ COMPONENT_BUILDER
+ {
+ AVS_SETTINGS
+ {
+ Setup_Value = "0";
+ Read_Wait_Value = "1";
+ Write_Wait_Value = "1";
+ Hold_Value = "0";
+ Timing_Units = "cycles";
+ Read_Latency_Value = "0";
+ Minimum_Arbitration_Shares = "1";
+ Active_CS_Through_Read_Latency = "0";
+ Max_Pending_Read_Transactions_Value = "9";
+ Address_Alignment = "dynamic";
+ Is_Printable_Device = "1";
+ interface_name = "Avalon Slave";
+ external_wait = "1";
+ Is_Memory_Device = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT avs_nios_chipselect
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "chipselect";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_address
+ {
+ width = "-1";
+ width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1";
+ direction = "input";
+ type = "address";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_byteenable
+ {
+ width = "-1";
+ width_expression = "(((data_width / 8) - 1)) - (0) + 1";
+ direction = "input";
+ type = "byteenable";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_writedata
+ {
+ width = "-1";
+ width_expression = "((data_width - 1)) - (0) + 1";
+ direction = "input";
+ type = "writedata";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_write
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "write";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_read
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "read";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_waitrequest
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "waitrequest";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_readdata
+ {
+ width = "-1";
+ width_expression = "((data_width - 1)) - (0) + 1";
+ direction = "output";
+ type = "readdata";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_readdatavalid
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "readdatavalid";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ }
+ }
+ }
+ USER_INTERFACE
+ {
+ USER_LABELS
+ {
+ name = "sdram_ctrl";
+ technology = "Opencores";
+ }
+ WIZARD_UI the_wizard_ui
+ {
+ title = "sdram_ctrl - {{ $MOD }}";
+ CONTEXT
+ {
+ H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
+ M = "";
+ SBI_global_signals = "SYSTEM_BUILDER_INFO";
+ SBI_nios = "SLAVE nios/SYSTEM_BUILDER_INFO";
+ # The following signals have parameterized widths:
+ PORT_sdram_ba = "PORT_WIRING/PORT sdram_ba";
+ PORT_sdram_addr = "PORT_WIRING/PORT sdram_addr";
+ PORT_sdram_dq = "PORT_WIRING/PORT sdram_dq";
+ PORT_sdram_dqm = "PORT_WIRING/PORT sdram_dqm";
+ PORT_avs_nios_address = "SLAVE nios/PORT_WIRING/PORT avs_nios_address";
+ PORT_avs_nios_byteenable = "SLAVE nios/PORT_WIRING/PORT avs_nios_byteenable";
+ PORT_avs_nios_writedata = "SLAVE nios/PORT_WIRING/PORT avs_nios_writedata";
+ PORT_avs_nios_readdata = "SLAVE nios/PORT_WIRING/PORT avs_nios_readdata";
+ }
+ PAGES main
+ {
+ PAGE 1
+ {
+ align = "left";
+ title = "sdram_ctrl 1.1 Settings";
+ layout = "vertical";
+ TEXT
+ {
+ title = "Built on: 2006.09.25.10:24:12";
+ }
+ TEXT
+ {
+ title = "Class name: sdram_ctrl";
+ }
+ TEXT
+ {
+ title = "Class version: 1.1";
+ }
+ TEXT
+ {
+ title = "Component name: sdram_ctrl";
+ }
+ TEXT
+ {
+ title = "Component Group: Opencores";
+ }
+ GROUP parameters
+ {
+ title = "Parameters";
+ layout = "form";
+ align = "left";
+ EDIT e1
+ {
+ id = "data_width";
+ editable = "1";
+ title = "data_width:";
+ columns = "40";
+ tooltip = "default value: 32";
+ DATA
+ {
+ $H/data_width = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/data_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/data_width,'ugly_-?[0-9]+')))'data_width must be numeric constant, not '+$H/data_width; }}";
+ }
+ EDIT e2
+ {
+ id = "bank_width";
+ editable = "1";
+ title = "bank_width:";
+ columns = "40";
+ tooltip = "default value: 4";
+ DATA
+ {
+ $H/bank_width = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/bank_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/bank_width,'ugly_-?[0-9]+')))'bank_width must be numeric constant, not '+$H/bank_width; }}";
+ }
+ EDIT e3
+ {
+ id = "row_width";
+ editable = "1";
+ title = "row_width:";
+ columns = "40";
+ tooltip = "default value: 12";
+ DATA
+ {
+ $H/row_width = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/row_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/row_width,'ugly_-?[0-9]+')))'row_width must be numeric constant, not '+$H/row_width; }}";
+ }
+ EDIT e4
+ {
+ id = "column_width";
+ editable = "1";
+ title = "column_width:";
+ columns = "40";
+ tooltip = "default value: 8";
+ DATA
+ {
+ $H/column_width = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/column_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/column_width,'ugly_-?[0-9]+')))'column_width must be numeric constant, not '+$H/column_width; }}";
+ }
+ EDIT e5
+ {
+ id = "clk_mhz";
+ editable = "1";
+ title = "clk_mhz:";
+ columns = "40";
+ tooltip = "default value: 120";
+ DATA
+ {
+ $H/clk_mhz = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/clk_mhz,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/clk_mhz,'ugly_-?[0-9]+')))'clk_mhz must be numeric constant, not '+$H/clk_mhz; }}";
+ }
+ }
+ GROUP variable_port_widths
+ {
+ # This group is for display only, to preview parameterized port widths
+ title = "Parameterized Signal Widths";
+ layout = "form";
+ align = "left";
+ EDIT sdram_ba_width
+ {
+ id = "sdram_ba_width";
+ editable = "0";
+ title = "sdram_ba[((bank_width - 1)) - (0) + 1]:";
+ tooltip = "sdram_ba[((bank_width - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_ba/width = (int((( ( $H/bank_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_ba/width = "$"; + } + warning = "{{ if($PORT_sdram_ba/width <= 0)('width of sdram_ba must be greater than zero' ) }}"; + } + EDIT sdram_addr_width + { + id = "sdram_addr_width"; + editable = "0"; + title = "sdram_addr[((row_width - 1)) - (0) + 1]:"; + tooltip = "sdram_addr[((row_width - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_addr/width = (int((( ( $H/row_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_addr/width = "$"; + } + warning = "{{ if($PORT_sdram_addr/width <= 0)('width of sdram_addr must be greater than zero' ) }}"; + } + EDIT sdram_dq_width + { + id = "sdram_dq_width"; + editable = "0"; + title = "sdram_dq[((data_width - 1)) - (0) + 1]:"; + tooltip = "sdram_dq[((data_width - 1)) - (0) + 1]
direction: inout
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_dq/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_dq/width = "$"; + } + warning = "{{ if($PORT_sdram_dq/width <= 0)('width of sdram_dq must be greater than zero' ) }}"; + } + EDIT sdram_dqm_width + { + id = "sdram_dqm_width"; + editable = "0"; + title = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]:"; + tooltip = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_dqm/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_dqm/width = "$"; + } + warning = "{{ if($PORT_sdram_dqm/width <= 0)('width of sdram_dqm must be greater than zero' ) }}"; + } + EDIT avs_nios_address_width + { + id = "avs_nios_address_width"; + editable = "0"; + title = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]:"; + tooltip = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]
direction: input
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_address/width = (int((((( ( $H/bank_width ) + ( $H/row_width ) ) + ( $H/column_width ) ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Address_Width = $PORT_avs_nios_address/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_address/width = "$"; + } + warning = "{{ if($PORT_avs_nios_address/width <= 0)('width of avs_nios_address must be greater than zero' ) }}"; + } + EDIT avs_nios_byteenable_width + { + id = "avs_nios_byteenable_width"; + editable = "0"; + title = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]:"; + tooltip = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]
direction: input
signal type: byteenable"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_byteenable/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_byteenable/width = "$"; + } + warning = "{{ if($PORT_avs_nios_byteenable/width <= 0)('width of avs_nios_byteenable must be greater than zero' ) }}"; + } + EDIT avs_nios_writedata_width + { + id = "avs_nios_writedata_width"; + editable = "0"; + title = "avs_nios_writedata[((data_width - 1)) - (0) + 1]:"; + tooltip = "avs_nios_writedata[((data_width - 1)) - (0) + 1]
direction: input
signal type: writedata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_writedata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_writedata/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_writedata/width = "$"; + } + warning = "{{ if($PORT_avs_nios_writedata/width <= 0)('width of avs_nios_writedata must be greater than zero' ) }}"; + } + EDIT avs_nios_readdata_width + { + id = "avs_nios_readdata_width"; + editable = "0"; + title = "avs_nios_readdata[((data_width - 1)) - (0) + 1]:"; + tooltip = "avs_nios_readdata[((data_width - 1)) - (0) + 1]
direction: output
signal type: readdata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_readdata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_readdata/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_readdata/width = "$"; + } + warning = "{{ if($PORT_avs_nios_readdata/width <= 0)('width of avs_nios_readdata must be greater than zero' ) }}"; + } + } + } + } + } + } + SOPC_Builder_Version = "5.10"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by CBDocument.getParameterContainer + # used only by Component Editor + HDL_PARAMETER data_width + { + parameter_name = "data_width"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER bank_width + { + parameter_name = "bank_width"; + type = "integer"; + default_value = "4"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER row_width + { + parameter_name = "row_width"; + type = "integer"; + default_value = "12"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER column_width + { + parameter_name = "column_width"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER clk_mhz + { + parameter_name = "clk_mhz"; + type = "integer"; + default_value = "120"; + editable = "1"; + tooltip = ""; + } + } + SW_FILES + { + } + built_on = "2006.09.25.10:24:12"; + CACHED_HDL_INFO + { + # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection + # used only by Component Builder + FILE sdram_ctrl.vhd + { + file_mod = "Mon Sep 18 18:08:50 EEST 2006"; + quartus_map_start = "Mon Sep 25 10:22:36 EEST 2006"; + quartus_map_finished = "Mon Sep 25 10:22:58 EEST 2006"; + #found 1 valid modules + WRAPPER sdram_ctrl + { + CLASS sdram_ctrl + { + CB_GENERATOR + { + HDL_FILES + { + FILE + { + use_in_simulation = "1"; + use_in_synthesis = "1"; + filepath = "H:/Work/Home_stuff/opencores/sdram_ctrl/src/sdram_ctrl.vhd"; + } + } + top_module_name = "sdram_ctrl"; + emit_system_h = "0"; + LIBRARIES + { + library = "ieee.std_logic_1164.all"; + library = "ieee.numeric_std.all"; + library = "altera_mf.altera_mf_components.all"; + library = "std.standard.all"; + } + } + MODULE_DEFAULTS global_signals + { + class = "sdram_ctrl"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE nios + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT avs_nios_chipselect + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "chipselect"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_address + { + width = "-1"; + width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1"; + direction = "input"; + type = "address"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_byteenable + { + width = "-1"; + width_expression = "(((data_width / 8) - 1)) - (0) + 1"; + direction = "input"; + type = "byteenable"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_writedata + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "input"; + type = "writedata"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_write + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "write"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_read + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "read"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_waitrequest + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "waitrequest"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_readdata + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "output"; + type = "readdata"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_readdatavalid + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "readdatavalid"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT sdram_cke + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_ba + { + width = "-1"; + width_expression = "((bank_width - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_addr + { + width = "-1"; + width_expression = "((row_width - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_cs_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_ras_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_cas_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_we_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_dq + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "inout"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_dqm + { + width = "-1"; + width_expression = "(((data_width / 8) - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT reset + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "reset"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "sdram_ctrl"; + technology = "imported components"; + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by CBDocument.getParameterContainer + # used only by Component Editor + HDL_PARAMETER data_width + { + parameter_name = "data_width"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER bank_width + { + parameter_name = "bank_width"; + type = "integer"; + default_value = "4"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER row_width + { + parameter_name = "row_width"; + type = "integer"; + default_value = "12"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER column_width + { + parameter_name = "column_width"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER clk_mhz + { + parameter_name = "clk_mhz"; + type = "integer"; + default_value = "120"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + } + } + ASSOCIATED_FILES + { + Add_Program = "the_wizard_ui"; + Edit_Program = "the_wizard_ui"; + Generator_Program = "cb_generator.pl"; + } +} Index: sdram_ctrl/trunk =================================================================== --- sdram_ctrl/trunk (nonexistent) +++ sdram_ctrl/trunk (revision 8)
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_ba/width = (int((( ( $H/bank_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_ba/width = "$"; + } + warning = "{{ if($PORT_sdram_ba/width <= 0)('width of sdram_ba must be greater than zero' ) }}"; + } + EDIT sdram_addr_width + { + id = "sdram_addr_width"; + editable = "0"; + title = "sdram_addr[((row_width - 1)) - (0) + 1]:"; + tooltip = "sdram_addr[((row_width - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_addr/width = (int((( ( $H/row_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_addr/width = "$"; + } + warning = "{{ if($PORT_sdram_addr/width <= 0)('width of sdram_addr must be greater than zero' ) }}"; + } + EDIT sdram_dq_width + { + id = "sdram_dq_width"; + editable = "0"; + title = "sdram_dq[((data_width - 1)) - (0) + 1]:"; + tooltip = "sdram_dq[((data_width - 1)) - (0) + 1]
direction: inout
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_dq/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_dq/width = "$"; + } + warning = "{{ if($PORT_sdram_dq/width <= 0)('width of sdram_dq must be greater than zero' ) }}"; + } + EDIT sdram_dqm_width + { + id = "sdram_dqm_width"; + editable = "0"; + title = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]:"; + tooltip = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_dqm/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_dqm/width = "$"; + } + warning = "{{ if($PORT_sdram_dqm/width <= 0)('width of sdram_dqm must be greater than zero' ) }}"; + } + EDIT avs_nios_address_width + { + id = "avs_nios_address_width"; + editable = "0"; + title = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]:"; + tooltip = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]
direction: input
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_address/width = (int((((( ( $H/bank_width ) + ( $H/row_width ) ) + ( $H/column_width ) ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Address_Width = $PORT_avs_nios_address/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_address/width = "$"; + } + warning = "{{ if($PORT_avs_nios_address/width <= 0)('width of avs_nios_address must be greater than zero' ) }}"; + } + EDIT avs_nios_byteenable_width + { + id = "avs_nios_byteenable_width"; + editable = "0"; + title = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]:"; + tooltip = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]
direction: input
signal type: byteenable"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_byteenable/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_byteenable/width = "$"; + } + warning = "{{ if($PORT_avs_nios_byteenable/width <= 0)('width of avs_nios_byteenable must be greater than zero' ) }}"; + } + EDIT avs_nios_writedata_width + { + id = "avs_nios_writedata_width"; + editable = "0"; + title = "avs_nios_writedata[((data_width - 1)) - (0) + 1]:"; + tooltip = "avs_nios_writedata[((data_width - 1)) - (0) + 1]
direction: input
signal type: writedata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_writedata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_writedata/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_writedata/width = "$"; + } + warning = "{{ if($PORT_avs_nios_writedata/width <= 0)('width of avs_nios_writedata must be greater than zero' ) }}"; + } + EDIT avs_nios_readdata_width + { + id = "avs_nios_readdata_width"; + editable = "0"; + title = "avs_nios_readdata[((data_width - 1)) - (0) + 1]:"; + tooltip = "avs_nios_readdata[((data_width - 1)) - (0) + 1]
direction: output
signal type: readdata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_readdata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_readdata/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_readdata/width = "$"; + } + warning = "{{ if($PORT_avs_nios_readdata/width <= 0)('width of avs_nios_readdata must be greater than zero' ) }}"; + } + } + } + } + } + } + SOPC_Builder_Version = "5.10"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by CBDocument.getParameterContainer + # used only by Component Editor + HDL_PARAMETER data_width + { + parameter_name = "data_width"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER bank_width + { + parameter_name = "bank_width"; + type = "integer"; + default_value = "4"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER row_width + { + parameter_name = "row_width"; + type = "integer"; + default_value = "12"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER column_width + { + parameter_name = "column_width"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER clk_mhz + { + parameter_name = "clk_mhz"; + type = "integer"; + default_value = "120"; + editable = "1"; + tooltip = ""; + } + } + SW_FILES + { + } + built_on = "2006.09.25.10:24:12"; + CACHED_HDL_INFO + { + # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection + # used only by Component Builder + FILE sdram_ctrl.vhd + { + file_mod = "Mon Sep 18 18:08:50 EEST 2006"; + quartus_map_start = "Mon Sep 25 10:22:36 EEST 2006"; + quartus_map_finished = "Mon Sep 25 10:22:58 EEST 2006"; + #found 1 valid modules + WRAPPER sdram_ctrl + { + CLASS sdram_ctrl + { + CB_GENERATOR + { + HDL_FILES + { + FILE + { + use_in_simulation = "1"; + use_in_synthesis = "1"; + filepath = "H:/Work/Home_stuff/opencores/sdram_ctrl/src/sdram_ctrl.vhd"; + } + } + top_module_name = "sdram_ctrl"; + emit_system_h = "0"; + LIBRARIES + { + library = "ieee.std_logic_1164.all"; + library = "ieee.numeric_std.all"; + library = "altera_mf.altera_mf_components.all"; + library = "std.standard.all"; + } + } + MODULE_DEFAULTS global_signals + { + class = "sdram_ctrl"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE nios + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT avs_nios_chipselect + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "chipselect"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_address + { + width = "-1"; + width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1"; + direction = "input"; + type = "address"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_byteenable + { + width = "-1"; + width_expression = "(((data_width / 8) - 1)) - (0) + 1"; + direction = "input"; + type = "byteenable"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_writedata + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "input"; + type = "writedata"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_write + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "write"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_read + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "read"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_waitrequest + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "waitrequest"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_readdata + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "output"; + type = "readdata"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_readdatavalid + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "readdatavalid"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT sdram_cke + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_ba + { + width = "-1"; + width_expression = "((bank_width - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_addr + { + width = "-1"; + width_expression = "((row_width - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_cs_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_ras_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_cas_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_we_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_dq + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "inout"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_dqm + { + width = "-1"; + width_expression = "(((data_width / 8) - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT reset + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "reset"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "sdram_ctrl"; + technology = "imported components"; + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by CBDocument.getParameterContainer + # used only by Component Editor + HDL_PARAMETER data_width + { + parameter_name = "data_width"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER bank_width + { + parameter_name = "bank_width"; + type = "integer"; + default_value = "4"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER row_width + { + parameter_name = "row_width"; + type = "integer"; + default_value = "12"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER column_width + { + parameter_name = "column_width"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER clk_mhz + { + parameter_name = "clk_mhz"; + type = "integer"; + default_value = "120"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + } + } + ASSOCIATED_FILES + { + Add_Program = "the_wizard_ui"; + Edit_Program = "the_wizard_ui"; + Generator_Program = "cb_generator.pl"; + } +} Index: sdram_ctrl/trunk =================================================================== --- sdram_ctrl/trunk (nonexistent) +++ sdram_ctrl/trunk (revision 8)
sdram_ctrl/trunk
Property changes :
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Index: sdram_ctrl/web_uploads
===================================================================
--- sdram_ctrl/web_uploads (nonexistent)
+++ sdram_ctrl/web_uploads (revision 8)
sdram_ctrl/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: sdram_ctrl/branches
===================================================================
--- sdram_ctrl/branches (nonexistent)
+++ sdram_ctrl/branches (revision 8)
sdram_ctrl/branches
Property changes :
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## -0,0 +0,0 ##
Index: sdram_ctrl/tags/V10/doc/sdram_ctrl.sxw
===================================================================
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svn:mime-type = application/octet-stream
Index: sdram_ctrl/tags/V10/doc/sdram_ctrl.sxw
===================================================================
--- sdram_ctrl/tags/V10/doc/sdram_ctrl.sxw (nonexistent)
+++ sdram_ctrl/tags/V10/doc/sdram_ctrl.sxw (revision 8)
sdram_ctrl/tags/V10/doc/sdram_ctrl.sxw
Property changes :
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+application/octet-stream
\ No newline at end of property
Index: sdram_ctrl/tags/V10/src/sdram_ctrl.vhd
===================================================================
--- sdram_ctrl/tags/V10/src/sdram_ctrl.vhd (nonexistent)
+++ sdram_ctrl/tags/V10/src/sdram_ctrl.vhd (revision 8)
@@ -0,0 +1,441 @@
+------------------------------------------------------------------
+--
+-- sdram_ctrl.vhd
+--
+-- Module Description:
+-- SDRAM small&fast controller
+--
+--
+-- To Do:
+-- multichipselect support
+-- configurable times
+-- nios simulation support
+--
+-- Author(s):
+-- Aleksey Kuzmenok, ntpqa@opencores.org
+--
+------------------------------------------------------------------
+--
+-- Copyright (C) 2006 Aleksey Kuzmenok and OPENCORES.ORG
+--
+-- This module is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This module is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this software; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+--
+------------------------------------------------------------------
+-- Test results
+-- FPGA SDRAM CLK (not less than)
+-- EP1C12XXXXC8 MT48LC4M32B2TG-7:G 125 MHz
+-- EP1C6XXXXC8 IS42S16100C1-7TL 125 MHz
+--
+------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+entity sdram_ctrl is
+ generic(
+ DATA_WIDTH: integer:=32;
+ BANK_WIDTH: integer:=4;
+ ROW_WIDTH: integer:=12;
+ COLUMN_WIDTH: integer:=8;
+
+ clk_MHz: integer:=120
+ );
+ port(
+ signal clk : IN STD_LOGIC;
+ signal reset : IN STD_LOGIC;
+
+ -- IMPORTANT: for this Avalon(tm) interface
+ -- 'Minimum Arbitration Shares'=1
+ -- 'Max Pending Read Transactions'=9
+ signal avs_nios_chipselect : IN STD_LOGIC;
+ signal avs_nios_address : IN STD_LOGIC_VECTOR ((BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH-1) DOWNTO 0);
+ signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0);
+ signal avs_nios_writedata : IN STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal avs_nios_write : IN STD_LOGIC;
+ signal avs_nios_read : IN STD_LOGIC;
+ signal avs_nios_waitrequest : OUT STD_LOGIC;
+ signal avs_nios_readdata : OUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal avs_nios_readdatavalid : OUT STD_LOGIC;
+
+ -- global export signals
+ signal sdram_cke : OUT STD_LOGIC; -- This pin has fixed state '1'
+ signal sdram_ba : OUT STD_LOGIC_VECTOR ((BANK_WIDTH-1) DOWNTO 0);
+ signal sdram_addr : OUT STD_LOGIC_VECTOR ((ROW_WIDTH-1) DOWNTO 0);
+ signal sdram_cs_n : OUT STD_LOGIC; -- This pin has fixed state '0'
+ signal sdram_ras_n : OUT STD_LOGIC;
+ signal sdram_cas_n : OUT STD_LOGIC;
+ signal sdram_we_n : OUT STD_LOGIC;
+ signal sdram_dq : INOUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal sdram_dqm : OUT STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0)
+ );
+end sdram_ctrl;
+
+architecture behaviour of sdram_ctrl is
+
+ CONSTANT FIFO_WIDTH: integer:=BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
+
+ CONSTANT MODE: std_logic_vector(11 downto 0):="000000110000"; -- 1 word burst, CAS latency=3
+ -- Only two times are configurable
+ -- tINIT delay between powerup and load mode register = 100 us
+ -- tREF refresh period = 15.625 us (64ms/4096rows)
+ CONSTANT INIT_PAUSE_CLOCKS: integer:=(clk_MHz*10000)/91; -- 109.9 us just to be on the save side
+ CONSTANT REFRESH_PERIOD_CLOCKS: integer:=(clk_MHz*1000)/65; -- 15.384 us the same purpose
+ CONSTANT CAS_LATENCY: integer:=3; -- other latencies weren't been tested!
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ rdreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
+ full : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ -- If you ask me why there are so many states, I'll answer that all times are fixed.
+ -- The top speed for MT48LC4M32B2TG-7:G is 7 ns, therefore all times were based on it.
+ -- tRP PRECHARGE command period = 3 clocks
+ -- tRFC AUTO REFRESH period = 10 clocks
+ -- tMRD LOAD MODE REGISTER command to ACTIVE or REFRESH command = 2 clocks
+ -- tRCD ACTIVE to READ or WRITE delay = 3 clocks
+ -- tRAS ACTIVE to PRECHARGE command = 7 clocks
+ -- tRC ACTIVE to ACTIVE command period = 10 clocks
+ -- tWR2 Write recovery time = 2 clocks
+ type states is (
+ INIT0,INIT1,INIT2,INIT3,INIT4,INIT5,INIT6,INIT7,
+ INIT8,INIT9,INIT10,INIT11,INIT12,INIT13,INIT14,INIT15,
+ INIT16,INIT17,INIT18,INIT19,INIT20,INIT21,INIT22,INIT23,INIT24,
+ REFRESH0,REFRESH1,REFRESH2,REFRESH3,REFRESH4,REFRESH5,REFRESH6,REFRESH7,
+ REFRESH8,REFRESH9,REFRESH10,REFRESH11,REFRESH12,REFRESH13,REFRESH14,
+ ACTIVE0,ACTIVE1,ACTIVE2,ACTIVE3,ACTIVE4,
+ IDLE,READ0,WRITE0);
+ signal operation: states;
+
+ signal fifo_q: std_logic_vector((FIFO_WIDTH-1) downto 0);
+
+ signal init_counter: unsigned(15 downto 0):=to_unsigned(INIT_PAUSE_CLOCKS,16);
+ signal refresh_counter: unsigned(15 downto 0);
+ signal active_counter: unsigned(2 downto 0);
+ signal active_address: unsigned((BANK_WIDTH+ROW_WIDTH-1) downto 0);
+
+ signal bank: std_logic_vector((sdram_ba'length-1) downto 0);
+ signal row: std_logic_vector((sdram_addr'length-1) downto 0);
+ signal column: std_logic_vector((COLUMN_WIDTH-1) downto 0);
+ signal be: std_logic_vector((sdram_dqm'length-1) downto 0);
+ signal data: std_logic_vector((sdram_dq'length-1) downto 0);
+
+ signal do_init,do_refresh,do_active,read_is_active,ready,tRCD_not_expired: std_logic:='0';
+
+ signal fifo_rdreq,fifo_empty: std_logic;
+
+ signal read_latency: std_logic_vector(CAS_LATENCY downto 0);
+
+ signal fifo_data: std_logic_vector((FIFO_WIDTH-1) downto 0);
+ signal fifo_wrreq,fifo_wrfull: std_logic;
+
+ signal i_command : STD_LOGIC_VECTOR(4 downto 0);
+ CONSTANT NOP: STD_LOGIC_VECTOR(4 downto 0):="10111";
+ CONSTANT ACTIVE: STD_LOGIC_VECTOR(4 downto 0):="10011";
+ CONSTANT READ: STD_LOGIC_VECTOR(4 downto 0):="10101";
+ CONSTANT WRITE: STD_LOGIC_VECTOR(4 downto 0):="10100";
+ CONSTANT PRECHARGE: STD_LOGIC_VECTOR(4 downto 0):="10010";
+ CONSTANT AUTO_REFRESH: STD_LOGIC_VECTOR(4 downto 0):="10001";
+ CONSTANT LOAD_MODE_REGISTER: STD_LOGIC_VECTOR(4 downto 0):="10000";
+
+ signal i_address : STD_LOGIC_VECTOR((sdram_addr'length-1) DOWNTO 0);
+ signal i_bank : STD_LOGIC_VECTOR((sdram_ba'length-1) DOWNTO 0);
+ signal i_dqm : STD_LOGIC_VECTOR((sdram_dqm'length-1) DOWNTO 0);
+ signal i_data : STD_LOGIC_VECTOR((sdram_dq'length-1) DOWNTO 0);
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of i_command : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_address : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_bank : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_data : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of avs_nios_readdata : signal is "FAST_INPUT_REGISTER=ON";
+begin
+ (sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n) <= i_command;
+ sdram_addr <= i_address;
+ sdram_ba <= i_bank;
+ sdram_dqm <= i_dqm;
+ sdram_dq <= i_data;
+
+ fifo_data<=avs_nios_address & avs_nios_writedata & avs_nios_byteenable & avs_nios_write & avs_nios_read;
+ fifo_wrreq<=(avs_nios_write or avs_nios_read) and avs_nios_chipselect and not fifo_wrfull;
+
+ avs_nios_waitrequest<=fifo_wrfull;
+
+ fifo_rdreq<=not fifo_empty and not do_refresh and not do_active and not read_is_active and ready;
+
+ do_active<='0' when active_address=unsigned((fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)))) else '1';
+ read_is_active<='1' when read_latency(CAS_LATENCY-1 downto 0)>"000" and fifo_q(1)='1' else '0';
+ ready<='1' when operation=IDLE or operation=READ0 or operation=WRITE0 else '0';
+
+ operation_machine:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ operation<=INIT0;
+ active_address<=(others=>'1');
+ elsif rising_edge(clk)
+ then
+
+ bank<=fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length));
+ row<=fifo_q((fifo_q'length-bank'length-1) downto (fifo_q'length-bank'length-row'length));
+ column<=fifo_q((column'length+data'length+be'length+2-1) downto (data'length+be'length+2));
+ data<=fifo_q((data'length+be'length+2-1) downto (be'length+2));
+ be<=fifo_q((be'length+2-1) downto 2);
+
+ case operation is
+ when INIT0=>
+ if do_init='1'
+ then operation<=INIT1;row(10)<='1';
+ end if;
+ when INIT1=>operation<=INIT2;
+ when INIT2=>operation<=INIT3;
+ when INIT3=>operation<=INIT4;
+ when INIT4=>operation<=INIT5;
+ when INIT5=>operation<=INIT6;
+ when INIT6=>operation<=INIT7;
+ when INIT7=>operation<=INIT8;
+ when INIT8=>operation<=INIT9;
+ when INIT9=>operation<=INIT10;
+ when INIT10=>operation<=INIT11;
+ when INIT11=>operation<=INIT12;
+ when INIT12=>operation<=INIT13;
+ when INIT13=>operation<=INIT14;
+ when INIT14=>operation<=INIT15;
+ when INIT15=>operation<=INIT16;
+ when INIT16=>operation<=INIT17;
+ when INIT17=>operation<=INIT18;
+ when INIT18=>operation<=INIT19;
+ when INIT19=>operation<=INIT20;
+ when INIT20=>operation<=INIT21;
+ when INIT21=>operation<=INIT22;
+ when INIT22=>operation<=INIT23;
+ when INIT23=>operation<=INIT24;row<=MODE((row'length-1) downto 0);
+ when INIT24=>operation<=IDLE;
+
+ when REFRESH0=>operation<=REFRESH1;
+ when REFRESH1=>operation<=REFRESH2;
+ when REFRESH2=>operation<=REFRESH3;
+ when REFRESH3=>operation<=REFRESH4;
+ when REFRESH4=>operation<=REFRESH5;
+ when REFRESH5=>operation<=REFRESH6;
+ when REFRESH6=>operation<=REFRESH7;
+ when REFRESH7=>operation<=REFRESH8;
+ when REFRESH8=>operation<=REFRESH9;
+ when REFRESH9=>operation<=REFRESH10;
+ when REFRESH10=>operation<=REFRESH11;
+ when REFRESH11=>operation<=REFRESH12;
+ when REFRESH12=>operation<=REFRESH13;
+ active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
+ when REFRESH13=>operation<=REFRESH14;
+ when REFRESH14=>operation<=IDLE;
+
+ when ACTIVE0=>operation<=ACTIVE1;
+ when ACTIVE1=>operation<=ACTIVE2;
+ when ACTIVE2=>operation<=ACTIVE3;
+ active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
+ when ACTIVE3=>operation<=ACTIVE4;
+ when ACTIVE4=>operation<=IDLE;
+
+ when others=>
+ if do_refresh='1'
+ then
+ if tRCD_not_expired='0' and operation=IDLE
+ then operation<=REFRESH0;row(10)<='1';
+ else operation<=IDLE;
+ end if;
+ elsif do_active='1'
+ then
+ if tRCD_not_expired='0' and operation=IDLE
+ then operation<=ACTIVE0;row(10)<='1';
+ else operation<=IDLE;
+ end if;
+ elsif fifo_empty='1'
+ then
+ operation<=IDLE;
+ elsif fifo_q(1)='1' --write
+ then
+ if read_latency(CAS_LATENCY-1 downto 0)>"000"
+ then operation<=IDLE;
+ else operation<=WRITE0;
+ end if;
+ elsif fifo_q(0)='1' --read
+ then
+ operation<=READ0;
+ end if;
+ end case;
+ end if;
+ end process;
+
+ control_latency:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ read_latency<=(others=>'0');
+ elsif rising_edge(clk)
+ then
+ read_latency<=std_logic_vector(unsigned(read_latency) SLL 1);
+ if operation=READ0
+ then read_latency(0)<='1';
+ else read_latency(0)<='0';
+ end if;
+ end if;
+ end process;
+ latch_readdata:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ avs_nios_readdata<=(others=>'0');
+ avs_nios_readdatavalid<='0';
+ elsif rising_edge(clk)
+ then
+ avs_nios_readdata<=sdram_dq;
+ avs_nios_readdatavalid<=read_latency(CAS_LATENCY);
+ end if;
+ end process;
+ initialization:process(reset,clk)
+ begin
+ if rising_edge(clk)
+ then
+ if init_counter>0
+ then
+ init_counter<=init_counter-1;
+ else do_init<='1';
+ end if;
+ end if;
+ end process;
+ refreshing:process(clk,reset)
+ begin
+ if reset='1'
+ then
+ refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
+ do_refresh<='0';
+ elsif rising_edge(clk)
+ then
+ if refresh_counter=to_unsigned(0,refresh_counter'length)
+ then refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
+ do_refresh<='1';
+ else refresh_counter<=refresh_counter-1;
+ end if;
+ if operation=REFRESH0 or operation=REFRESH5
+ then do_refresh<='0';
+ end if;
+ end if;
+ end process;
+ active_period:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ active_counter<=(others=>'0');
+ tRCD_not_expired<='0';
+ elsif rising_edge(clk)
+ then
+ if operation=ACTIVE3 or operation=REFRESH13
+ then active_counter<=to_unsigned(5,active_counter'length);
+ elsif active_counter>0
+ then active_counter<=active_counter-1;
+ end if;
+ end if;
+ if active_counter>0
+ then tRCD_not_expired<='1';
+ else tRCD_not_expired<='0';
+ end if;
+ end process;
+ latch_controls:process(clk,reset)
+ begin
+ if reset='1'
+ then
+ i_command<=NOP;
+ i_address<=(others=>'0');
+ i_bank<=(others=>'0');
+ i_dqm<=(others=>'0');
+ i_data<=(others=>'Z');
+ elsif rising_edge(clk)
+ then
+ i_command<=NOP;
+ i_bank<=bank;
+ i_address<=(others=>'0');
+ i_address((column'length-1) downto 0)<=column;
+ i_data<=(others=>'Z');
+ i_dqm<=(others=>'0');
+
+ case operation is
+ when INIT1|REFRESH0|ACTIVE0 =>
+ i_command<=PRECHARGE;
+ i_address<=row;
+ when INIT4|INIT14|REFRESH3 =>
+ i_command<=AUTO_REFRESH;
+ when INIT24=>
+ i_command<=LOAD_MODE_REGISTER;
+ i_address<=row;
+ when ACTIVE3|REFRESH13 =>
+ i_command<=ACTIVE;
+ i_address<=row;
+ when READ0 =>
+ i_command<=READ;
+ when WRITE0 =>
+ i_command<=WRITE;
+ i_dqm<=not be;
+ i_data<=data;
+ when OTHERS =>
+ end case;
+ end if;
+ end process;
+
+ fifo: scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ intended_device_family => "Cyclone",
+ lpm_numwords => 4,
+ lpm_showahead => "ON",
+ lpm_type => "scfifo",
+ lpm_width => FIFO_WIDTH,
+ lpm_widthu => 2,
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => "ON"
+ )
+ PORT MAP (
+ rdreq => fifo_rdreq,
+ aclr => reset,
+ clock => clk,
+ wrreq => fifo_wrreq,
+ data => fifo_data,
+ empty => fifo_empty,
+ q => fifo_q,
+ full => fifo_wrfull
+ );
+end behaviour;
Index: sdram_ctrl/tags/V10/syn/sdram_ctrl/cb_generator.pl
===================================================================
--- sdram_ctrl/tags/V10/syn/sdram_ctrl/cb_generator.pl (nonexistent)
+++ sdram_ctrl/tags/V10/syn/sdram_ctrl/cb_generator.pl (revision 8)
@@ -0,0 +1,1159 @@
+# | file: cb_generator.pl
+# |
+# | This SOPC Builder Generator program is provided by
+# | the Component Builder application. It is copied
+# | straight across and is data-driven from its command
+# | line arguments and the PTF files referenced.
+# |
+# | Its purpose is to construct an HDL "wrapper" for
+# | a particular instance of a particular SOPC Builder
+# | peripheral. This wrapper resolves the instance
+# | name and any HDL parameterization.
+# |
+# +-------------------------------------------
+
+
+
+# +-------------------------------------------
+# |
+
+use strict;
+use format_conversion_utils;
+use ptf_parse;
+use wiz_utils;
+use europa_all;
+use run_system_command_utils;
+
+# |
+# +-------------------------------------------
+
+
+
+# +-------------------------------------------
+# |
+# | first pass: include all of generator_libarary.pm RIGHT HERE.
+# | dvb04.08.02
+# | then prune down to actual functionality.
+# |
+# | TODO: Rewrite this whole file into something readable
+# | this is much more confusing than I'm comfortable with. dvb04.
+# | (though it does seem to work.)
+# |
+
+my $DEBUG_DEFAULT_GEN = 1;
+
+#This is the global hash of arguments passed in by the generator program
+
+my $generator_hr = {
+ wrapper_args => {
+ make_wrapper => 0,
+ top_module_name => "",
+ simulate_hdl => 1,
+ ports => "",
+ },
+ class_ptf_hr => "",
+ module_ptf_hr => "",
+ system_ptf_hr => "",
+ language => "",
+ external_args => "",
+ external_args_hr => "",
+ project_path_widget => "__PROJECT_DIRECTORY__",
+ generator_mode => "silent",
+ };
+
+
+sub generator_print_verbose
+{
+ my ($info) = (@_);
+
+ if($generator_hr->{generator_mode} eq "verbose"){
+ print("cb_generator.pl: ".$info);
+ }
+}
+
+sub generator_enable_mode
+{
+ my ($mode) = (@_);
+ $generator_hr->{generator_mode} = $mode;
+}
+
+sub generator_get_system_ptf_handle
+{
+ return $generator_hr->{system_ptf_hr};
+}
+
+sub generator_get_language
+{
+ return $generator_hr->{language};
+}
+
+sub generator_get_class_ptf_handle
+{
+ return $generator_hr->{class_ptf_hr};
+}
+
+sub default_ribbit
+{
+ my ($arg) = (@_);
+ &ribbit("\n\n--Error: default_gen_lib: $arg\n");
+}
+
+
+sub _copy_files
+{
+ my ($dest_dir, $source_dir, @files) = (@_);
+ my $function_name;
+
+ #validate args
+ &default_ribbit("No target dir for function copy_files!")
+ unless ($dest_dir ne "");
+
+ &default_ribbit("No source dir for function copy_files!")
+ unless ($source_dir ne "");
+
+ &default_ribbit("No files for function copy_files!")
+ unless (@files != 0);
+
+
+ #check for valid directories
+ opendir (SDIR, $source_dir) or
+ &default_ribbit("can't open $source_dir !");
+
+ opendir (DDIR, $dest_dir) or
+ &default_ribbit("can't open $dest_dir !");
+
+
+ foreach my $source_file(@files){
+ # |
+ # | Separate out the source subdir and the source filename
+ # |
+ my $source_subdir = "";
+ my $source_filename = $source_file;
+
+ if($source_filename =~ /^(.*)\/(.*)$/) # break on last slash
+ {
+ $source_subdir = "/$1"; # embed its leading slash, for concatty
+ $source_filename = $2;
+ }
+
+ my $source_fullpath = "$source_dir$source_subdir/$source_filename";
+ my $dest_fullpath = "$dest_dir/$source_filename";
+
+ &Perlcopy($source_fullpath, $dest_fullpath);
+ &generator_print_verbose("Copying file: \"$source_fullpath\""
+ . " to \"$dest_fullpath\".\n");
+ }
+
+ closedir (SDIR);
+ closedir (DDIR);
+}
+
+
+sub get_module_wrapper_arg_hash_from_system_ptf_file
+{
+ my $module_ptf_hr = $generator_hr->{module_ptf_hr};
+
+ my @list_of_sections = ("MASTER","SLAVE","PORT_WIRING");
+ my @port_list;
+ foreach my $section(@list_of_sections){
+ my $number = get_child_count($module_ptf_hr, $section);
+
+ for(my $initial=0; $initial < $number; $initial++){
+
+ my $interface_section = get_child($module_ptf_hr, $initial, $section);
+ my $interface_section_name = get_data($interface_section);
+
+ my $port_wiring_section;
+ if($section ne "PORT_WIRING"){
+ $port_wiring_section =
+ get_child_by_path($module_ptf_hr, $section." ".$interface_section_name."/PORT_WIRING");
+ }else{
+ $port_wiring_section =
+ get_child_by_path($module_ptf_hr, $section);
+ }
+ my $num_ports = get_child_count($port_wiring_section, "PORT");
+ foreach(my $port_count = 0; $port_count < $num_ports; $port_count++){
+ my $port = get_child($port_wiring_section, $port_count, "PORT");
+
+ my %port_info_struct;
+ $port_info_struct{name} = get_data($port);
+ $port_info_struct{direction} = get_data_by_path($port, "direction");
+ $port_info_struct{width} = get_data_by_path($port, "width");
+ $port_info_struct{vhdl_record_name} = get_data_by_path($port, "vhdl_record_name");
+ $port_info_struct{vhdl_record_type} = get_data_by_path($port, "vhdl_record_type");
+
+ push(@port_list, \%port_info_struct);
+
+ }
+ }
+ }
+ $generator_hr->{wrapper_args}{ports} = \@port_list;
+}
+
+
+sub generator_make_module_wrapper
+{
+ my ($simulate_hdl, $top_module_name, $module_language) = (@_);
+
+ &default_ribbit("generator_make_module_wrapper: no arg0 passed in for simulate_hdl\n")
+ if($simulate_hdl eq '');
+
+ &default_ribbit("generator_make_module_wrapper: no arg1 passed in for top_module_name\n")
+ unless($top_module_name);
+
+ $generator_hr->{wrapper_args}{simulate_hdl} = $simulate_hdl;
+ $generator_hr->{wrapper_args}{top_module_name} = $top_module_name;
+ $generator_hr->{wrapper_args}{make_wrapper} = 1;
+ $generator_hr->{wrapper_args}{module_language} = $module_language;
+
+}
+
+
+
+
+# |
+# | recognize varous number forms,
+# | return 'h0123abcd-ish.
+# |
+sub turn_anything_into_appropriate_string($$$$)
+ {
+ my ($value,$type,$editable,$module_language) = (@_);
+
+ return $value if($value =~ /^\"/); # quoted string: unscathed
+ return $value if($type eq "string"); # string: anything is ok
+
+ return $value if(!$editable); # and you know, if you can't change it, keep it!
+
+
+ # |
+ # | first, convert to a number
+ # |
+ my $base = 10;
+ my $n = $value;
+ my $width = 32;
+ my $number = 0;
+
+ $value = lc($value); # lower case
+
+ if($value =~ /^([0-9]*)\'([hbo])(.*)$/)
+ {
+ # | tick notation: AOK for verilog
+ if($module_language eq "verilog")
+ {
+ $number = $value;
+ }
+ # |
+ # | note: at this point, we could notice if the
+ # | result should be vhdl binary, and convert
+ # | to that, avoiding the precision-losing
+ # | integer intermediary
+ # |
+ # | (alternatively, we could use a binary string
+ # | always as the intermediate form, rather than
+ # | a precision-losing int.)
+ # |
+ else
+ {
+ $width = $1;
+ my $baseletter = $2;
+ my $digits = $3;
+
+ if($baseletter eq "h")
+ {
+ $base = 16;
+ }
+ elsif($baseletter eq "b")
+ {
+ $base = 2;
+ }
+ elsif($baseletter eq "o") # must be
+ {
+ $base = 8;
+ }
+
+ $digits =~ s/[ _-]//g; # crush out dividing value
+
+ while(length($digits) > 0)
+ {
+ my $digit = substr($digits,0,1);
+ $digits = substr($digits,1);
+ my $digitvalue = hex($digit); # how handy
+ $number = $number * $base + $digitvalue;
+ }
+ }
+ }
+ elsif($value =~ /^0x(.*)$/)
+ {
+ $number = hex($1);
+ }
+ else # try for decimal
+ {
+ $number = int(1 * $value);
+ }
+
+ # |
+ # | ok, we have a number. If our target type
+ # | is "std_logic_vector(this downto that)"
+ # | for tricky VHDL, we
+ # | must quote a binary string out of it.
+ # |
+
+ if(($module_language eq "vhdl") and ($type =~ /^.*\((\d+) downto (\d+)\).*$/))
+ {
+ my ($high_bit,$low_bit) = ($1,$2);
+ my $binary = "";
+ for(my $bit = $low_bit; $bit <= $high_bit; $bit++)
+ {
+ $binary = ($number % 2) . $binary;
+ $number = int($number >> 1);
+ }
+
+ $number = '"' . $binary . '"';
+ }
+
+ return $number;
+ }
+
+#
+# return @array of vhdl libraries, if any, from the class.ptf
+sub get_libraries()
+{
+ my $class_ptf = generator_get_class_ptf_handle();
+ my @libraries;
+ my $libraries_ptf = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/LIBRARIES");
+
+ if($libraries_ptf)
+ {
+ my $library_count = get_child_count($libraries_ptf,"library");
+ for(my $i = 0; $i < $library_count; $i++)
+ {
+ my $library_ptf = get_child($libraries_ptf,$i,"library");
+ my $library_name = get_data($library_ptf);
+ push(@libraries,$library_name);
+ }
+ }
+
+ return @libraries;
+}
+
+
+
+sub _generator_make_module_wrapper
+{
+
+ my $wrapper_args = $generator_hr->{wrapper_args};
+ my $no_black_box = $wrapper_args->{simulate_hdl};
+ my $top_module_name = $wrapper_args->{top_module_name};
+ my $language = $generator_hr->{language};
+ my @external_args = @{$generator_hr->{external_args}};
+ my $module_ptf_hr = $generator_hr->{module_ptf_hr};
+
+ ### Build Module
+ my $project = e_project->new(@external_args);
+ my $top = $project->top();
+
+ # add the ports to the system module
+ my @ports;
+
+ foreach my $port_hash(@{$wrapper_args->{ports}}){
+ my $porto = e_port->new({
+ name => $port_hash->{name},
+ width => $port_hash->{width},
+ direction => $port_hash->{direction},
+ vhdl_record_name => $port_hash->{vhdl_record_name},
+ vhdl_record_type => $port_hash->{vhdl_record_type}
+ });
+ push(@ports, $porto);
+ }
+ $top->add_contents(@ports);
+
+
+
+
+
+ # +----------------------------------------
+ # | Get parameters from class.ptf
+ # | create @array of parameters, eacho
+ # | one like name=>, default=>, type=>,
+ # |
+ # | These are the definitions of parameters for
+ # | ANY instance of this module; we need to
+ # | have them in the "wrapee" module so that
+ # | when the system bus is knitted together
+ # | the parameter types can be properly used.
+ # |
+ # | (as it turns out, verilog doesnt need
+ # | them, but vhld does)
+ # |
+ # | dvb2004
+
+
+ my @e_hdl_parameters; # list of e_parameters
+
+ my $class_ptf = generator_get_class_ptf_handle();
+ my $hdl_parameter_definitions_ptf = get_child_by_path($class_ptf,"CLASS/COMPONENT_BUILDER/HDL_PARAMETERS");
+
+ my @libraries = get_libraries();
+
+ my $hdl_parameter_count = get_child_count($hdl_parameter_definitions_ptf,"HDL_PARAMETER");
+
+ my $module_language = $generator_hr->{wrapper_args}{module_language};
+
+ for(my $i = 0; $i < $hdl_parameter_count; $i++)
+ {
+ my $a_parameter = get_child($hdl_parameter_definitions_ptf,$i,"HDL_PARAMETER");
+ my $parameter_editable = get_data_by_path($a_parameter,"editable");
+ if($parameter_editable)
+ {
+ my $boring_name = get_data($a_parameter); # legal guinevere-ized
+ my $name = get_data_by_path($a_parameter,"parameter_name"); # original HDL name
+ my $default = get_data_by_path($a_parameter,"default_value");
+ my $type = get_data_by_path($a_parameter,"type");
+
+ $default = turn_anything_into_appropriate_string($default,$type,1,$module_language);
+
+ my $a_parameter = e_parameter->new
+ ({
+ name => $name,
+ default => $default,
+ type => $type
+ });
+
+ push (@e_hdl_parameters,$a_parameter);
+ }
+ }
+
+
+
+ # | and @e_hdl_parameters is used below in the wrapee module
+ # +--------------------------------------------
+
+ # +--------------------------------------------
+ # | Now, we build a "hdl_parameter_map", which is just
+ # | your basic hash table with keys (parameters)
+ # | and values (parameter values).
+ # |
+ # | these are the particular values for this instance.
+ # |
+
+ my %hdl_parameter_map;
+ my $module_ptf = $generator_hr->{module_ptf_hr};
+ my $hdl_parameters_ptf =
+ get_child_by_path($module_ptf,"WIZARD_SCRIPT_ARGUMENTS/hdl_parameters");
+
+ my $child_count = get_child_count($hdl_parameters_ptf);
+
+ for(my $i = 0; $i < $child_count; $i++)
+ {
+ my $a_parameter = get_child($hdl_parameters_ptf,$i);
+
+ my $boring_name = get_name($a_parameter);
+ my $value = get_data($a_parameter);
+
+ # refer back to the original HDL name...
+ my $parameter_definition_ptf = get_child_by_path($hdl_parameter_definitions_ptf,"HDL_PARAMETER $boring_name");
+ my $parameter_name = get_data_by_path($parameter_definition_ptf,"parameter_name");
+ my $parameter_type = get_data_by_path($parameter_definition_ptf,"type");
+ my $parameter_editable = get_data_by_path($parameter_definition_ptf,"editable");
+
+ $value = turn_anything_into_appropriate_string($value,$parameter_type,$parameter_editable,$module_language);
+
+ # |
+ # | our internal _dummy assignment shows up here
+ # | without a corresponding hdl entry. we
+ # | ignore it.
+ # |
+
+ if(($parameter_name ne "") and $parameter_editable)
+ {
+ $hdl_parameter_map{$parameter_name} = $value;
+ }
+ }
+
+ my $wrapee_module;
+ $wrapee_module = e_module->new({
+ name => $top_module_name,
+ contents => [@ports,@e_hdl_parameters],
+ do_black_box => 0,
+ do_ptf => 0,
+ _hdl_generated => 1,
+ _explicitly_empty_module => 1,
+ });
+
+ # VHDL Libraries, from PTF file...
+ $wrapee_module->add_vhdl_libraries(@libraries);
+ $top->add_vhdl_libraries(@libraries);
+
+
+ $top->add_contents (
+ e_instance->new({
+ module => $wrapee_module,
+ parameter_map => \%hdl_parameter_map
+ }),
+ );
+
+ $project->top()->do_ptf(0);
+ $project->do_write_ptf(0);
+
+
+ my $module_file = $project->_target_module_name().".v";
+ $module_file = $project->_target_module_name().".vhd"
+ if($language eq "vhdl");
+
+ $module_file = $generator_hr->{project_path_widget}."/".$module_file;
+ &generator_set_files_in_system_ptf("Synthesis_HDL_Files", ($module_file));
+ $project->output();
+
+
+ # if you don't want a simulation model, you don't get a simulation model
+ if($no_black_box eq "0")
+ {
+ my $black_project = e_project->new(@external_args);
+ $black_project->_target_module_name($top_module_name);
+ my $black_top = $black_project->top();
+
+
+
+ $black_top->add_contents(@ports);
+ my $black_top_instance;
+ $black_top_instance = e_module->new({
+ name => $wrapper_args->{top_module_name}."_bb",
+ contents => [@ports],
+ do_black_box => 1,
+ do_ptf => 0,
+ _hdl_generated => 0,
+ _explicitly_empty_module => 1,
+ });
+
+ $black_top->add_contents (
+ e_instance->new({
+ module => $black_top_instance,
+ }),
+ );
+
+
+
+
+ $black_project->top()->do_ptf(0);
+ $black_project->do_write_ptf(0);
+
+ my $black_module_file = $black_project->_target_module_name().".v";
+ $black_module_file = $black_project->_target_module_name().".vhd"
+ if($language eq "vhdl");
+
+
+ $black_module_file = $generator_hr->{project_path_widget}."/".$black_module_file;
+ &generator_set_files_in_system_ptf("Simulation_HDL_Files", ($black_module_file));
+
+# &set_data_by_path($module_ptf_hr, "HDL_INFO/Simulation_HDL_Files", $black_module_file);
+
+
+ $black_project->output();
+ }
+
+}
+
+####
+# Args: $file_type : "synthesis", "synthesis_only", "simulation"
+# @file_list : an array of files. This list of files is assumed to be relative to the
+# component's directory
+
+
+my $decoder_ring_hr = {
+ quartus_only => {
+ copy => 1,
+ copy_to => "project",
+ ptf_set => 0,
+ },
+ simulation_only => {
+ copy => 1,
+ copy_to => "simulation",
+ ptf_set => 1,
+ ptf_section => "Simulation_HDL_Files",
+ },
+ simulation_and_quartus => {
+ copy => 1,
+ copy_to => "project",
+ ptf_set => 1,
+ ptf_section => "Synthesis_HDL_Files",
+ },
+ precompiled_simulation_files => {
+ copy => 0,
+ ptf_set => 1,
+ ptf_section => "Precompiled_Simulation_Library_Files",
+ },
+ };
+
+
+
+
+sub generator_copy_files_and_set_system_ptf
+{
+ my ($hdl_section, @file_list) = (@_);
+
+ my $ptf_path_prefix = "";
+ my $external_args_hr = $generator_hr->{external_args_hr};
+ my @new_file_array;
+
+ #validate first
+ my $decoder_hash = $decoder_ring_hr->{$hdl_section};
+ &default_ribbit("generator_copy_files_and_set_system_ptf: No understood HDL section passed in for first arg\n")
+ unless($decoder_ring_hr->{$hdl_section} ne "");
+
+ &generator_print_verbose("generator_copy_files_and_set_system_ptf: copying files for section ".$hdl_section."\n");
+
+ #copy second
+ my @new_file_array;
+
+ # If we need to copy over some files, then we need to make sure we are
+ # keeping track of what files we copy over.
+ # Otherwise, we just need to keep track of the files that the user has asked to copy over
+ # and use these instead.
+ if($decoder_hash->{copy}){
+ my $copy_to_location;
+ my $copy_from_location;
+
+ if($decoder_hash->{copy_to} eq "project"){
+ $copy_to_location = $external_args_hr->{system_directory};
+ }elsif($decoder_hash->{copy_to} eq "simulation"){
+ $copy_to_location = $external_args_hr->{system_sim_dir};
+ }else{
+ &default_ribbit("generator_copy_files_and_set_system_ptf: No understood copy files to location\n");
+ }
+
+ $copy_from_location = $external_args_hr->{class_directory};
+ @new_file_array = &generator_copy_files($copy_to_location, $copy_from_location, @file_list);
+ }else{
+ @new_file_array = @file_list;
+ }
+
+ #scribble on PTF hash last
+ if($decoder_hash->{ptf_set}){
+
+ if($decoder_hash->{copy_to} eq "project"){
+ foreach my $file(@new_file_array){
+ $file =~ s/^.*\/(.*?)$/$1/;
+ $file = $generator_hr->{project_path_widget}."/".$file;
+ }
+ }
+ &generator_print_verbose("generator_copy_files_and_set_system_ptf: setting system PTF file in section ".$hdl_section."\n");
+ if($decoder_hash->{ptf_section} eq "Precompiled_Simulation_Library_Files"){
+ @new_file_array = map{$external_args_hr->{class_directory}."/".$_} @new_file_array;
+ }
+ &generator_set_files_in_system_ptf($decoder_hash->{ptf_section}, @new_file_array);
+ }
+}
+
+
+
+####
+# Name: generator_set_files_in_system_ptf
+# Args: $hdl_section
+# @list_of_files
+# Returns: 1 or 0
+# Purpose: This is an internal function used to set files in the module's section in the system PTF file
+#
+sub generator_set_files_in_system_ptf
+{
+ my ($hdl_section, @list_of_files) = (@_);
+
+ my $file_list = join(",", @list_of_files);
+ my $previous_data;
+
+ &generator_print_verbose("setting HDL_INFO/".$hdl_section." in system PTF file with ".$file_list."\n");
+ my $previous_data = &get_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section);
+ if($previous_data){
+ $file_list = $previous_data . ", $file_list"; # spr 132177
+ # swapping order, dvb 2003
+ }
+ &set_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section, $file_list);
+}
+
+####
+# Name: generator_copy_files
+# Args: $target_directory
+# $source_directory
+# @list_of_files
+# Returns: The list of files which has been copied (suitable for framing!)
+# Purpose: This is an internal function used to copy files around in the generator program.
+#
+sub generator_copy_files
+{
+ my ($target_directory, $source_directory, @list_of_files) = (@_);
+
+ my @new_file_array;
+
+ foreach my $file_name(@list_of_files){
+ $file_name =~ s|\\|\/|g;
+ if($file_name =~ /\*\.*/){
+ $file_name =~ s/\*/$1/;
+ my @found_list = &_find_all_dir_files_with_ext($source_directory, $file_name);
+ push(@new_file_array, @found_list);
+ }else{
+ &generator_print_verbose("Copying: ".$file_name."\n");
+ push(@new_file_array, $file_name);
+ }
+ }
+
+ &_copy_files($target_directory, $source_directory, @new_file_array);
+ return @new_file_array;
+}
+
+
+
+sub _find_all_dir_files_with_ext
+{
+ my ($dir,
+ $ext) = (@_);
+
+ opendir (DIR, $dir) or
+ &default_ribbit("can't open $dir !");
+
+ my @all_files = readdir(DIR);
+ my @new_file_list;
+
+
+ foreach my $file (@all_files){
+ if($file =~ /^.*($ext)$/){
+ push(@new_file_list, $file);
+ }
+ }
+
+ return @new_file_list;
+}
+
+####
+# Name: generator_begin
+# Args: Array of generator program launcher args
+# Returns: A hash reference to the module's section in the system PTF file
+# Purpose: This is the first subroutine a user should call before running the rest of their
+# generator program.
+#
+
+sub generator_begin
+{
+ my @external_args = (@_);
+
+ my ($external_args_hr,
+ $temp_user_defined,
+ $temp_db_Module,
+ $temp_db_PTF_File) = Process_Wizard_Script_Arguments("", @external_args);
+
+ &generator_print_verbose("generator_begin: initializing\n");
+
+ $generator_hr->{external_args_hr} = $external_args_hr;
+ $generator_hr->{external_args} = \@external_args;
+
+ # open up class.ptf and
+ $generator_hr->{class_ptf_hr} = new_ptf_from_file($external_args_hr->{class_directory}."/class.ptf");
+
+ # get the system.ptf
+ $generator_hr->{system_ptf_hr} = new_ptf_from_file($external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf");
+ $generator_hr->{module_ptf_hr} = &get_child_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/MODULE $external_args_hr->{target_module_name}");
+ my $class_name = get_data_by_path($generator_hr->{module_ptf_hr}, "class");
+
+ # find the default generator section
+ $generator_hr->{language} = get_data_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/WIZARD_SCRIPT_ARGUMENTS/hdl_language");
+
+ # get some wrapper settings
+ &get_module_wrapper_arg_hash_from_system_ptf_file();
+
+ # clear system ptf's HDL section
+ &delete_child($generator_hr->{module_ptf_hr}, "HDL_INFO");
+
+ return $generator_hr->{module_ptf_hr};
+}
+
+####
+# Name: generator_end
+# Args: none
+# Returns: nothing
+# Purpose: This is the last subroutine a user should call from their generator program.
+# Not calling this subroutine will make you very sad... =<
+#
+
+sub generator_end
+{
+ # o.k., time to make the wrapper and output it.
+ if($generator_hr->{wrapper_args}{make_wrapper}){
+ &_generator_make_module_wrapper();
+ }
+
+
+ my $external_args_hr = $generator_hr->{external_args_hr};
+ my $ptf_file_name = $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf";
+ &generator_print_verbose("generator_end: writing PTF file ".$external_args_hr->{system_name}.".ptf to ".$external_args_hr->{system_directory}."\n");
+
+ default_ribbit("Cannot write PTF file ".$ptf_file_name."!\n")
+ unless(&write_ptf_file($generator_hr->{system_ptf_hr}, $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"));
+}
+
+sub generator_end_read_module_wrapper_string
+{
+ my $language = &generator_get_language();
+ my $ls;
+
+ if($language =~ /vhdl/){
+ $ls = ".vhd";
+ }elsif($language =~ /verilog/){
+ $ls = ".v";
+ }else{
+ &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
+ }
+ my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
+ my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
+
+ my $file = $system_dir."/".$module_name.$ls;
+ &generator_print_verbose("generator library reading file into string: $file\n");
+
+ open (FILE,"<$file") or ribbit "cannot open file ($file) ($!)\n";
+ my $return_string;
+ while ()
+ {
+ $return_string .= $_;
+ }
+ close (FILE);
+ return($return_string);
+}
+
+sub generator_end_write_module_wrapper_string
+{
+ my $string = shift or ribbit "no string specified\n";
+
+ my $language = &generator_get_language();
+ my $ls;
+
+ print $language;
+
+ if($language =~ /vhdl/){
+ $ls = ".vhd";
+ }elsif($language =~ /verilog/){
+ $ls = ".v";
+ }else{
+ &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
+ }
+ my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
+ my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
+
+ my $file = $system_dir."/".$module_name.$ls;
+ &generator_print_verbose("generator library writing string into file: $file\n");
+
+ open (FILE,">$file") or ribbit "cannot open file ($file) ($!)\n";
+ print FILE $string;
+ close (FILE);
+}
+# end of generator_library.pm
+
+
+
+
+
+#
+#
+#
+#
+# ---------------------------------------------------------------------
+
+# +----------------------------------------------------
+# | emit_system_h
+# |
+# | if "is_cpu", attempt to emit a system.h
+# | memory map.
+# |
+
+sub emit_system_h($$$)
+ {
+ my ($sopc_directory,$master,$system_ptf) = (@_);
+
+ # |
+ # | Build a system.h file for masters.
+ # |
+
+
+# as of quartus 5.0, we prefer gtf-generate in sopc_builder directly
+
+ my $gtf_generate = "$sopc_directory/bin/gtf-generate";
+ my $gtf_filename = "$sopc_directory/bin/gtf/system.h.gtf";
+
+ if(! -f $gtf_generate)
+ {
+ # but if sopc_builder is missing it for whatever reason,
+ # try the one in sopc_kit_nios2
+
+ my $sopc_kit_nios2 = $ENV{SOPC_KIT_NIOS2};
+ if($sopc_kit_nios2 ne "")
+ {
+ $gtf_generate = "$sopc_kit_nios2/bin/gtf-generate";
+ $gtf_filename = "$sopc_kit_nios2/bin/gtf/system.h.gtf";
+ }
+ }
+
+ # |
+ # | xml template
+ # |
+
+ my $stf_template = <
+
+
+
+
+EOP
+
+ # |
+ # | THINK
+ # |
+
+ my $output_directory = "./${master}_map";
+ my $project_name = "ignored";
+ my $stf_filename = "./${master}_project.stf";
+
+ # |
+ # | build up template variables
+ # |
+
+ my %template_vars;
+ $template_vars{date} = fcu_date_time();
+ $template_vars{whoami} = $0;
+ $template_vars{project_name} = $project_name;
+ $template_vars{system_ptf} = $system_ptf;
+ $template_vars{output_directory} = $output_directory;
+ $template_vars{master} = $master;
+
+ # |
+ # | poke in the values to the template
+ # |
+
+ foreach my $key (sort(keys(%template_vars)))
+ {
+ $stf_template =~ s/--$key--/$template_vars{$key}/gs;
+ }
+
+ ## debug print $stf_template;
+
+ # |
+ # | write out the stf file, so we can soon use it
+ # |
+
+ fcu_write_file($stf_filename,$stf_template);
+
+ # |
+ # | and use it
+ # |
+
+ if(-e $gtf_generate && -e $gtf_filename)
+ {
+
+ my $generate_cmd = $gtf_generate;
+
+ $generate_cmd .= " --output-directory=$output_directory";
+ $generate_cmd .= " --gtf=$gtf_filename";
+ $generate_cmd .= " --stf=$stf_filename";
+
+ r_system($sopc_directory,$generate_cmd);
+
+ # |
+ # | done with it
+ # |
+
+ r_system($sopc_directory,"rm $stf_filename");
+
+ fcu_print_command("Generated memory map \"$output_directory/system.h\"");
+ }
+ else
+ {
+ fcu_print_command("Warning: did NOT emit system.h for $master");
+ }
+
+
+
+
+ }
+
+
+sub r_system($$)
+ {
+ my ($sopc_directory,$cmd) = (@_);
+ fcu_print_command($cmd);
+ return Run_Command_In_Unix_Like_Shell($sopc_directory,$cmd);
+ }
+
+
+
+
+
+
+
+# +------------------------------------------
+# | synthesis and simulation files are are
+# | listed in CLASS/CB_GENERATOR/HDL_FILES.
+# |
+
+sub get_synthesis_files($)
+ {
+ my ($class_ptf) = (@_);
+ my $synthesis_files = "";
+ my $simulation_files = "";
+
+ my $hdl_files = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/HDL_FILES");
+ my $child_count = get_child_count($hdl_files);
+ for(my $i = 0; $i < $child_count; $i++)
+ {
+ my $hdl_file = get_child($hdl_files,$i);
+ if(get_name($hdl_file) eq "FILE")
+ {
+ my $filename = get_data_by_path($hdl_file,"filepath");
+ my $use_in_synthesis = get_data_by_path($hdl_file,"use_in_synthesis");
+ my $use_in_simulation = get_data_by_path($hdl_file,"use_in_simulation");
+
+ if($use_in_synthesis)
+ {
+ $synthesis_files .= ", " if $synthesis_files;
+ $synthesis_files .= $filename;
+ }
+
+ if($use_in_simulation)
+ {
+ $simulation_files .= ", " if $simulation_files;
+ $simulation_files .= $filename;
+ }
+ }
+ }
+
+ return $synthesis_files;
+ }
+
+
+
+
+
+
+
+
+sub main
+ {
+
+ push(@ARGV,"--verbose=1") if 0;
+ my %args = fcu_parse_args(@ARGV);
+
+ if(0)
+ {
+ foreach my $key (sort(keys(%args)))
+ {
+ print("--$key = $args{$key} \n");
+ }
+ }
+
+ # |
+ # | get the arguments we care about
+ # |
+
+ my $class_dir = fcu_get_switch(\%args,"module_lib_dir");
+
+
+ my $target_module_name = fcu_get_switch(\%args,"target_module_name");
+ my $system_name = fcu_get_switch(\%args,"system_name");
+ my $sopc_directory = fcu_get_switch(\%args,"sopc_directory");
+
+ # |
+ # | preflight the arguments a little
+ # |
+
+ my $error_count = 0;
+
+ my $class_ptf_path = "$class_dir/class.ptf";
+ if(!-f $class_ptf_path)
+ {
+ print "error: no class.ptf at \"$class_dir\"\n";
+ $error_count++;
+ }
+
+ die "$error_count errors" if($error_count > 0);
+
+ # +-------------------------------------------
+ # | ok, let us get to work
+ # |
+
+
+ my $class_ptf = new_ptf_from_file($class_ptf_path);
+
+ # |
+ # | emit system.h for this module
+ # | TODO iff Is_CPU i guess.
+ # |
+
+ my $do_emit_system_h = get_data_by_path($class_ptf,
+ "CLASS/CB_GENERATOR/emit_system_h");
+ if($do_emit_system_h)
+ {
+ emit_system_h($sopc_directory,
+ $target_module_name,
+ "./$system_name.ptf");
+ }
+
+ my $top_module_name = get_data_by_path($class_ptf,
+ "CLASS/CB_GENERATOR/top_module_name");
+ my $file_name = "";
+
+ # | stored as file_name.v:module_name, so we break it open
+ if($top_module_name =~ /^(.*):(.*)$/)
+ {
+ $file_name = $1;
+ my $module_name = $2;
+ $top_module_name = $module_name;
+ }
+
+ # | language of this particular module...
+
+ my $module_language = "verilog";
+ if($file_name =~ /^.*\.vhd$/)
+ {
+ $module_language = "vhdl";
+ }
+
+ # |
+ # | consult the CB_GENERATOR/HDL_FILES section regarding
+ # | where our HDL files for synthesis are.
+ # |
+
+
+ my $synthesis_files = get_synthesis_files($class_ptf);
+
+
+ my $instantiate_in_system_module = get_data_by_path($class_ptf,
+ "CLASS/MODULE_DEFAULTS/SYSTEM_BUILDER_INFO/Instantiate_In_System_Module");
+
+
+
+ if($instantiate_in_system_module)
+ {
+ generator_enable_mode ("terse");
+
+
+ generator_begin (@ARGV);
+
+
+ generator_make_module_wrapper(1,$top_module_name,$module_language);
+
+ generator_copy_files_and_set_system_ptf
+ (
+ "simulation_and_quartus",
+ split(/ *, */,$synthesis_files)
+# "$synthesis_files"
+ );
+
+ generator_end ();
+ }
+
+ exit (0);
+ }
+
+$| = 1; # always polite to flush.
+main()
+
+# end of file
Index: sdram_ctrl/tags/V10/syn/sdram_ctrl/hdl/sdram_ctrl.vhd
===================================================================
--- sdram_ctrl/tags/V10/syn/sdram_ctrl/hdl/sdram_ctrl.vhd (nonexistent)
+++ sdram_ctrl/tags/V10/syn/sdram_ctrl/hdl/sdram_ctrl.vhd (revision 8)
@@ -0,0 +1,440 @@
+------------------------------------------------------------------
+--
+-- sdram_ctrl.vhd
+--
+-- Module Description:
+-- SDRAM small&fast controller
+--
+--
+-- To Do:
+-- configurable times
+-- nios simulation support
+--
+-- Author(s):
+-- Aleksey Kuzmenok, ntpqa@opencores.org
+--
+------------------------------------------------------------------
+--
+-- Copyright (C) 2006 Aleksey Kuzmenok and OPENCORES.ORG
+--
+-- This module is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This module is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this software; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+--
+------------------------------------------------------------------
+-- Test results
+-- FPGA SDRAM CLK (not less than)
+-- EP1C12XXXXC8 MT48LC4M32B2TG-7:G 125 MHz
+-- EP1C6XXXXC8 IS42S16100C1-7TL 125 MHz
+--
+------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+entity sdram_ctrl is
+ generic(
+ DATA_WIDTH: integer:=32;
+ BANK_WIDTH: integer:=4;
+ ROW_WIDTH: integer:=12;
+ COLUMN_WIDTH: integer:=8;
+
+ clk_MHz: integer:=120
+ );
+ port(
+ signal clk : IN STD_LOGIC;
+ signal reset : IN STD_LOGIC;
+
+ -- IMPORTANT: for this Avalon(tm) interface
+ -- 'Minimum Arbitration Shares'=1
+ -- 'Max Pending Read Transactions'=9
+ signal avs_nios_chipselect : IN STD_LOGIC;
+ signal avs_nios_address : IN STD_LOGIC_VECTOR ((BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH-1) DOWNTO 0);
+ signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0);
+ signal avs_nios_writedata : IN STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal avs_nios_write : IN STD_LOGIC;
+ signal avs_nios_read : IN STD_LOGIC;
+ signal avs_nios_waitrequest : OUT STD_LOGIC;
+ signal avs_nios_readdata : OUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal avs_nios_readdatavalid : OUT STD_LOGIC;
+
+ -- global export signals
+ signal sdram_cke : OUT STD_LOGIC; -- This pin has fixed state '1'
+ signal sdram_ba : OUT STD_LOGIC_VECTOR ((BANK_WIDTH-1) DOWNTO 0);
+ signal sdram_addr : OUT STD_LOGIC_VECTOR ((ROW_WIDTH-1) DOWNTO 0);
+ signal sdram_cs_n : OUT STD_LOGIC; -- This pin has fixed state '0'
+ signal sdram_ras_n : OUT STD_LOGIC;
+ signal sdram_cas_n : OUT STD_LOGIC;
+ signal sdram_we_n : OUT STD_LOGIC;
+ signal sdram_dq : INOUT STD_LOGIC_VECTOR ((DATA_WIDTH-1) DOWNTO 0);
+ signal sdram_dqm : OUT STD_LOGIC_VECTOR (((DATA_WIDTH/8)-1) DOWNTO 0)
+ );
+end sdram_ctrl;
+
+architecture behaviour of sdram_ctrl is
+
+ CONSTANT FIFO_WIDTH: integer:=BANK_WIDTH+ROW_WIDTH+COLUMN_WIDTH+DATA_WIDTH+(DATA_WIDTH/8)+2;
+
+ CONSTANT MODE: std_logic_vector(11 downto 0):="000000110000"; -- 1 word burst, CAS latency=3
+ -- Only two times are configurable
+ -- tINIT delay between powerup and load mode register = 100 us
+ -- tREF refresh period = 15.625 us (64ms/4096rows)
+ CONSTANT INIT_PAUSE_CLOCKS: integer:=(clk_MHz*10000)/91; -- 109.9 us just to be on the save side
+ CONSTANT REFRESH_PERIOD_CLOCKS: integer:=(clk_MHz*1000)/65; -- 15.384 us the same purpose
+ CONSTANT CAS_LATENCY: integer:=3; -- other latencies weren't been tested!
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ rdreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR ((FIFO_WIDTH-1) DOWNTO 0);
+ full : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ -- If you ask me why there are so many states, I'll answer that all times are fixed.
+ -- The top speed for MT48LC4M32B2TG-7:G is 7 ns, therefore all times were based on it.
+ -- tRP PRECHARGE command period = 3 clocks
+ -- tRFC AUTO REFRESH period = 10 clocks
+ -- tMRD LOAD MODE REGISTER command to ACTIVE or REFRESH command = 2 clocks
+ -- tRCD ACTIVE to READ or WRITE delay = 3 clocks
+ -- tRAS ACTIVE to PRECHARGE command = 7 clocks
+ -- tRC ACTIVE to ACTIVE command period = 10 clocks
+ -- tWR2 Write recovery time = 2 clocks
+ type states is (
+ INIT0,INIT1,INIT2,INIT3,INIT4,INIT5,INIT6,INIT7,
+ INIT8,INIT9,INIT10,INIT11,INIT12,INIT13,INIT14,INIT15,
+ INIT16,INIT17,INIT18,INIT19,INIT20,INIT21,INIT22,INIT23,INIT24,
+ REFRESH0,REFRESH1,REFRESH2,REFRESH3,REFRESH4,REFRESH5,REFRESH6,REFRESH7,
+ REFRESH8,REFRESH9,REFRESH10,REFRESH11,REFRESH12,REFRESH13,REFRESH14,
+ ACTIVE0,ACTIVE1,ACTIVE2,ACTIVE3,ACTIVE4,
+ IDLE,READ0,WRITE0);
+ signal operation: states;
+
+ signal fifo_q: std_logic_vector((FIFO_WIDTH-1) downto 0);
+
+ signal init_counter: unsigned(15 downto 0):=to_unsigned(INIT_PAUSE_CLOCKS,16);
+ signal refresh_counter: unsigned(15 downto 0);
+ signal active_counter: unsigned(2 downto 0);
+ signal active_address: unsigned((BANK_WIDTH+ROW_WIDTH-1) downto 0);
+
+ signal bank: std_logic_vector((sdram_ba'length-1) downto 0);
+ signal row: std_logic_vector((sdram_addr'length-1) downto 0);
+ signal column: std_logic_vector((COLUMN_WIDTH-1) downto 0);
+ signal be: std_logic_vector((sdram_dqm'length-1) downto 0);
+ signal data: std_logic_vector((sdram_dq'length-1) downto 0);
+
+ signal do_init,do_refresh,do_active,read_is_active,ready,tRCD_not_expired: std_logic:='0';
+
+ signal fifo_rdreq,fifo_empty: std_logic;
+
+ signal read_latency: std_logic_vector(CAS_LATENCY downto 0);
+
+ signal fifo_data: std_logic_vector((FIFO_WIDTH-1) downto 0);
+ signal fifo_wrreq,fifo_wrfull: std_logic;
+
+ signal i_command : STD_LOGIC_VECTOR(4 downto 0);
+ CONSTANT NOP: STD_LOGIC_VECTOR(4 downto 0):="10111";
+ CONSTANT ACTIVE: STD_LOGIC_VECTOR(4 downto 0):="10011";
+ CONSTANT READ: STD_LOGIC_VECTOR(4 downto 0):="10101";
+ CONSTANT WRITE: STD_LOGIC_VECTOR(4 downto 0):="10100";
+ CONSTANT PRECHARGE: STD_LOGIC_VECTOR(4 downto 0):="10010";
+ CONSTANT AUTO_REFRESH: STD_LOGIC_VECTOR(4 downto 0):="10001";
+ CONSTANT LOAD_MODE_REGISTER: STD_LOGIC_VECTOR(4 downto 0):="10000";
+
+ signal i_address : STD_LOGIC_VECTOR((sdram_addr'length-1) DOWNTO 0);
+ signal i_bank : STD_LOGIC_VECTOR((sdram_ba'length-1) DOWNTO 0);
+ signal i_dqm : STD_LOGIC_VECTOR((sdram_dqm'length-1) DOWNTO 0);
+ signal i_data : STD_LOGIC_VECTOR((sdram_dq'length-1) DOWNTO 0);
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of i_command : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_address : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_bank : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of i_data : signal is "FAST_OUTPUT_REGISTER=ON";
+ attribute ALTERA_ATTRIBUTE of avs_nios_readdata : signal is "FAST_INPUT_REGISTER=ON";
+begin
+ (sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n) <= i_command;
+ sdram_addr <= i_address;
+ sdram_ba <= i_bank;
+ sdram_dqm <= i_dqm;
+ sdram_dq <= i_data;
+
+ fifo_data<=avs_nios_address & avs_nios_writedata & avs_nios_byteenable & avs_nios_write & avs_nios_read;
+ fifo_wrreq<=(avs_nios_write or avs_nios_read) and avs_nios_chipselect and not fifo_wrfull;
+
+ avs_nios_waitrequest<=fifo_wrfull;
+
+ fifo_rdreq<=not fifo_empty and not do_refresh and not do_active and not read_is_active and ready;
+
+ do_active<='0' when active_address=unsigned((fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)))) else '1';
+ read_is_active<='1' when read_latency(CAS_LATENCY-1 downto 0)>"000" and fifo_q(1)='1' else '0';
+ ready<='1' when operation=IDLE or operation=READ0 or operation=WRITE0 else '0';
+
+ operation_machine:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ operation<=INIT0;
+ active_address<=(others=>'1');
+ elsif rising_edge(clk)
+ then
+
+ bank<=fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length));
+ row<=fifo_q((fifo_q'length-bank'length-1) downto (fifo_q'length-bank'length-row'length));
+ column<=fifo_q((column'length+data'length+be'length+2-1) downto (data'length+be'length+2));
+ data<=fifo_q((data'length+be'length+2-1) downto (be'length+2));
+ be<=fifo_q((be'length+2-1) downto 2);
+
+ case operation is
+ when INIT0=>
+ if do_init='1'
+ then operation<=INIT1;row(10)<='1';
+ end if;
+ when INIT1=>operation<=INIT2;
+ when INIT2=>operation<=INIT3;
+ when INIT3=>operation<=INIT4;
+ when INIT4=>operation<=INIT5;
+ when INIT5=>operation<=INIT6;
+ when INIT6=>operation<=INIT7;
+ when INIT7=>operation<=INIT8;
+ when INIT8=>operation<=INIT9;
+ when INIT9=>operation<=INIT10;
+ when INIT10=>operation<=INIT11;
+ when INIT11=>operation<=INIT12;
+ when INIT12=>operation<=INIT13;
+ when INIT13=>operation<=INIT14;
+ when INIT14=>operation<=INIT15;
+ when INIT15=>operation<=INIT16;
+ when INIT16=>operation<=INIT17;
+ when INIT17=>operation<=INIT18;
+ when INIT18=>operation<=INIT19;
+ when INIT19=>operation<=INIT20;
+ when INIT20=>operation<=INIT21;
+ when INIT21=>operation<=INIT22;
+ when INIT22=>operation<=INIT23;
+ when INIT23=>operation<=INIT24;row<=MODE((row'length-1) downto 0);
+ when INIT24=>operation<=IDLE;
+
+ when REFRESH0=>operation<=REFRESH1;
+ when REFRESH1=>operation<=REFRESH2;
+ when REFRESH2=>operation<=REFRESH3;
+ when REFRESH3=>operation<=REFRESH4;
+ when REFRESH4=>operation<=REFRESH5;
+ when REFRESH5=>operation<=REFRESH6;
+ when REFRESH6=>operation<=REFRESH7;
+ when REFRESH7=>operation<=REFRESH8;
+ when REFRESH8=>operation<=REFRESH9;
+ when REFRESH9=>operation<=REFRESH10;
+ when REFRESH10=>operation<=REFRESH11;
+ when REFRESH11=>operation<=REFRESH12;
+ when REFRESH12=>operation<=REFRESH13;
+ active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
+ when REFRESH13=>operation<=REFRESH14;
+ when REFRESH14=>operation<=IDLE;
+
+ when ACTIVE0=>operation<=ACTIVE1;
+ when ACTIVE1=>operation<=ACTIVE2;
+ when ACTIVE2=>operation<=ACTIVE3;
+ active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
+ when ACTIVE3=>operation<=ACTIVE4;
+ when ACTIVE4=>operation<=IDLE;
+
+ when others=>
+ if do_refresh='1'
+ then
+ if tRCD_not_expired='0' and operation=IDLE
+ then operation<=REFRESH0;row(10)<='1';
+ else operation<=IDLE;
+ end if;
+ elsif do_active='1'
+ then
+ if tRCD_not_expired='0' and operation=IDLE
+ then operation<=ACTIVE0;row(10)<='1';
+ else operation<=IDLE;
+ end if;
+ elsif fifo_empty='1'
+ then
+ operation<=IDLE;
+ elsif fifo_q(1)='1' --write
+ then
+ if read_latency(CAS_LATENCY-1 downto 0)>"000"
+ then operation<=IDLE;
+ else operation<=WRITE0;
+ end if;
+ elsif fifo_q(0)='1' --read
+ then
+ operation<=READ0;
+ end if;
+ end case;
+ end if;
+ end process;
+
+ control_latency:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ read_latency<=(others=>'0');
+ elsif rising_edge(clk)
+ then
+ read_latency<=std_logic_vector(unsigned(read_latency) SLL 1);
+ if operation=READ0
+ then read_latency(0)<='1';
+ else read_latency(0)<='0';
+ end if;
+ end if;
+ end process;
+ latch_readdata:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ avs_nios_readdata<=(others=>'0');
+ avs_nios_readdatavalid<='0';
+ elsif rising_edge(clk)
+ then
+ avs_nios_readdata<=sdram_dq;
+ avs_nios_readdatavalid<=read_latency(CAS_LATENCY);
+ end if;
+ end process;
+ initialization:process(reset,clk)
+ begin
+ if rising_edge(clk)
+ then
+ if init_counter>0
+ then
+ init_counter<=init_counter-1;
+ else do_init<='1';
+ end if;
+ end if;
+ end process;
+ refreshing:process(clk,reset)
+ begin
+ if reset='1'
+ then
+ refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
+ do_refresh<='0';
+ elsif rising_edge(clk)
+ then
+ if refresh_counter=to_unsigned(0,refresh_counter'length)
+ then refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);
+ do_refresh<='1';
+ else refresh_counter<=refresh_counter-1;
+ end if;
+ if operation=REFRESH0 or operation=REFRESH5
+ then do_refresh<='0';
+ end if;
+ end if;
+ end process;
+ active_period:process(reset,clk)
+ begin
+ if reset='1'
+ then
+ active_counter<=(others=>'0');
+ tRCD_not_expired<='0';
+ elsif rising_edge(clk)
+ then
+ if operation=ACTIVE3 or operation=REFRESH13
+ then active_counter<=to_unsigned(5,active_counter'length);
+ elsif active_counter>0
+ then active_counter<=active_counter-1;
+ end if;
+ end if;
+ if active_counter>0
+ then tRCD_not_expired<='1';
+ else tRCD_not_expired<='0';
+ end if;
+ end process;
+ latch_controls:process(clk,reset)
+ begin
+ if reset='1'
+ then
+ i_command<=NOP;
+ i_address<=(others=>'0');
+ i_bank<=(others=>'0');
+ i_dqm<=(others=>'0');
+ i_data<=(others=>'Z');
+ elsif rising_edge(clk)
+ then
+ i_command<=NOP;
+ i_bank<=bank;
+ i_address<=(others=>'0');
+ i_address((column'length-1) downto 0)<=column;
+ i_data<=(others=>'Z');
+ i_dqm<=(others=>'0');
+
+ case operation is
+ when INIT1|REFRESH0|ACTIVE0 =>
+ i_command<=PRECHARGE;
+ i_address<=row;
+ when INIT4|INIT14|REFRESH3 =>
+ i_command<=AUTO_REFRESH;
+ when INIT24=>
+ i_command<=LOAD_MODE_REGISTER;
+ i_address<=row;
+ when ACTIVE3|REFRESH13 =>
+ i_command<=ACTIVE;
+ i_address<=row;
+ when READ0 =>
+ i_command<=READ;
+ when WRITE0 =>
+ i_command<=WRITE;
+ i_dqm<=not be;
+ i_data<=data;
+ when OTHERS =>
+ end case;
+ end if;
+ end process;
+
+ fifo: scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ intended_device_family => "Cyclone",
+ lpm_numwords => 4,
+ lpm_showahead => "ON",
+ lpm_type => "scfifo",
+ lpm_width => FIFO_WIDTH,
+ lpm_widthu => 2,
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => "ON"
+ )
+ PORT MAP (
+ rdreq => fifo_rdreq,
+ aclr => reset,
+ clock => clk,
+ wrreq => fifo_wrreq,
+ data => fifo_data,
+ empty => fifo_empty,
+ q => fifo_q,
+ full => fifo_wrfull
+ );
+end behaviour;
Index: sdram_ctrl/tags/V10/syn/sdram_ctrl/class.ptf
===================================================================
--- sdram_ctrl/tags/V10/syn/sdram_ctrl/class.ptf (nonexistent)
+++ sdram_ctrl/tags/V10/syn/sdram_ctrl/class.ptf (revision 8)
@@ -0,0 +1,972 @@
+#
+# This class.ptf file built by Component Editor
+# 2006.09.25.10:24:12
+#
+# DO NOT MODIFY THIS FILE
+# If you hand-modify this file you will likely
+# interfere with Component Editor's ability to
+# read and edit it. And then Component Editor
+# will overwrite your changes anyway. So, for
+# the very best results, just relax and
+# DO NOT MODIFY THIS FILE
+#
+CLASS sdram_ctrl
+{
+ CB_GENERATOR
+ {
+ HDL_FILES
+ {
+ FILE
+ {
+ use_in_simulation = "1";
+ use_in_synthesis = "1";
+ filepath = "hdl/sdram_ctrl.vhd";
+ }
+ }
+ top_module_name = "sdram_ctrl.vhd:sdram_ctrl";
+ emit_system_h = "0";
+ LIBRARIES
+ {
+ library = "ieee.std_logic_1164.all";
+ library = "ieee.numeric_std.all";
+ library = "altera_mf.altera_mf_components.all";
+ library = "std.standard.all";
+ }
+ }
+ MODULE_DEFAULTS global_signals
+ {
+ class = "sdram_ctrl";
+ class_version = "1.1";
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Has_Clock = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ }
+ COMPONENT_BUILDER
+ {
+ GLS_SETTINGS
+ {
+ }
+ }
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "clk";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT reset
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "reset";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_cke
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_ba
+ {
+ width = "-1";
+ width_expression = "((bank_width - 1)) - (0) + 1";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_addr
+ {
+ width = "-1";
+ width_expression = "((row_width - 1)) - (0) + 1";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_cs_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_ras_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_cas_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_we_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_dq
+ {
+ width = "-1";
+ width_expression = "((data_width - 1)) - (0) + 1";
+ direction = "inout";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT sdram_dqm
+ {
+ width = "-1";
+ width_expression = "(((data_width / 8) - 1)) - (0) + 1";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ hdl_parameters
+ {
+ data_width = "32";
+ bank_width = "4";
+ row_width = "12";
+ column_width = "8";
+ clk_mhz = "120";
+ }
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ }
+ }
+ SLAVE nios
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Address_Group = "1";
+ Has_Clock = "0";
+ Address_Width = "-1";
+ Address_Alignment = "dynamic";
+ Data_Width = "8";
+ Has_Base_Address = "1";
+ Has_IRQ = "0";
+ Setup_Time = "0";
+ Hold_Time = "0";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ Read_Latency = "0";
+ Maximum_Pending_Read_Transactions = "9";
+ Active_CS_Through_Read_Latency = "0";
+ Is_Printable_Device = "1";
+ Is_Memory_Device = "1";
+ Is_Readable = "1";
+ Is_Writable = "1";
+ Minimum_Uninterrupted_Run_Length = "1";
+ }
+ COMPONENT_BUILDER
+ {
+ AVS_SETTINGS
+ {
+ Setup_Value = "0";
+ Read_Wait_Value = "1";
+ Write_Wait_Value = "1";
+ Hold_Value = "0";
+ Timing_Units = "cycles";
+ Read_Latency_Value = "0";
+ Minimum_Arbitration_Shares = "1";
+ Active_CS_Through_Read_Latency = "0";
+ Max_Pending_Read_Transactions_Value = "9";
+ Address_Alignment = "dynamic";
+ Is_Printable_Device = "1";
+ interface_name = "Avalon Slave";
+ external_wait = "1";
+ Is_Memory_Device = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT avs_nios_chipselect
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "chipselect";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_address
+ {
+ width = "-1";
+ width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1";
+ direction = "input";
+ type = "address";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_byteenable
+ {
+ width = "-1";
+ width_expression = "(((data_width / 8) - 1)) - (0) + 1";
+ direction = "input";
+ type = "byteenable";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_writedata
+ {
+ width = "-1";
+ width_expression = "((data_width - 1)) - (0) + 1";
+ direction = "input";
+ type = "writedata";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_write
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "write";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_read
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "read";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_waitrequest
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "waitrequest";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_readdata
+ {
+ width = "-1";
+ width_expression = "((data_width - 1)) - (0) + 1";
+ direction = "output";
+ type = "readdata";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ PORT avs_nios_readdatavalid
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "readdatavalid";
+ is_shared = "0";
+ vhdl_record_name = "";
+ vhdl_record_type = "";
+ }
+ }
+ }
+ }
+ USER_INTERFACE
+ {
+ USER_LABELS
+ {
+ name = "sdram_ctrl";
+ technology = "Opencores";
+ }
+ WIZARD_UI the_wizard_ui
+ {
+ title = "sdram_ctrl - {{ $MOD }}";
+ CONTEXT
+ {
+ H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
+ M = "";
+ SBI_global_signals = "SYSTEM_BUILDER_INFO";
+ SBI_nios = "SLAVE nios/SYSTEM_BUILDER_INFO";
+ # The following signals have parameterized widths:
+ PORT_sdram_ba = "PORT_WIRING/PORT sdram_ba";
+ PORT_sdram_addr = "PORT_WIRING/PORT sdram_addr";
+ PORT_sdram_dq = "PORT_WIRING/PORT sdram_dq";
+ PORT_sdram_dqm = "PORT_WIRING/PORT sdram_dqm";
+ PORT_avs_nios_address = "SLAVE nios/PORT_WIRING/PORT avs_nios_address";
+ PORT_avs_nios_byteenable = "SLAVE nios/PORT_WIRING/PORT avs_nios_byteenable";
+ PORT_avs_nios_writedata = "SLAVE nios/PORT_WIRING/PORT avs_nios_writedata";
+ PORT_avs_nios_readdata = "SLAVE nios/PORT_WIRING/PORT avs_nios_readdata";
+ }
+ PAGES main
+ {
+ PAGE 1
+ {
+ align = "left";
+ title = "sdram_ctrl 1.1 Settings";
+ layout = "vertical";
+ TEXT
+ {
+ title = "Built on: 2006.09.25.10:24:12";
+ }
+ TEXT
+ {
+ title = "Class name: sdram_ctrl";
+ }
+ TEXT
+ {
+ title = "Class version: 1.1";
+ }
+ TEXT
+ {
+ title = "Component name: sdram_ctrl";
+ }
+ TEXT
+ {
+ title = "Component Group: Opencores";
+ }
+ GROUP parameters
+ {
+ title = "Parameters";
+ layout = "form";
+ align = "left";
+ EDIT e1
+ {
+ id = "data_width";
+ editable = "1";
+ title = "data_width:";
+ columns = "40";
+ tooltip = "default value: 32";
+ DATA
+ {
+ $H/data_width = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/data_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/data_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/data_width,'ugly_-?[0-9]+')))'data_width must be numeric constant, not '+$H/data_width; }}";
+ }
+ EDIT e2
+ {
+ id = "bank_width";
+ editable = "1";
+ title = "bank_width:";
+ columns = "40";
+ tooltip = "default value: 4";
+ DATA
+ {
+ $H/bank_width = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/bank_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/bank_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/bank_width,'ugly_-?[0-9]+')))'bank_width must be numeric constant, not '+$H/bank_width; }}";
+ }
+ EDIT e3
+ {
+ id = "row_width";
+ editable = "1";
+ title = "row_width:";
+ columns = "40";
+ tooltip = "default value: 12";
+ DATA
+ {
+ $H/row_width = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/row_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/row_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/row_width,'ugly_-?[0-9]+')))'row_width must be numeric constant, not '+$H/row_width; }}";
+ }
+ EDIT e4
+ {
+ id = "column_width";
+ editable = "1";
+ title = "column_width:";
+ columns = "40";
+ tooltip = "default value: 8";
+ DATA
+ {
+ $H/column_width = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/column_width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/column_width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/column_width,'ugly_-?[0-9]+')))'column_width must be numeric constant, not '+$H/column_width; }}";
+ }
+ EDIT e5
+ {
+ id = "clk_mhz";
+ editable = "1";
+ title = "clk_mhz:";
+ columns = "40";
+ tooltip = "default value: 120";
+ DATA
+ {
+ $H/clk_mhz = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/clk_mhz,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/clk_mhz,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/clk_mhz,'ugly_-?[0-9]+')))'clk_mhz must be numeric constant, not '+$H/clk_mhz; }}";
+ }
+ }
+ GROUP variable_port_widths
+ {
+ # This group is for display only, to preview parameterized port widths
+ title = "Parameterized Signal Widths";
+ layout = "form";
+ align = "left";
+ EDIT sdram_ba_width
+ {
+ id = "sdram_ba_width";
+ editable = "0";
+ title = "sdram_ba[((bank_width - 1)) - (0) + 1]:";
+ tooltip = "sdram_ba[((bank_width - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_ba/width = (int((( ( $H/bank_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_ba/width = "$"; + } + warning = "{{ if($PORT_sdram_ba/width <= 0)('width of sdram_ba must be greater than zero' ) }}"; + } + EDIT sdram_addr_width + { + id = "sdram_addr_width"; + editable = "0"; + title = "sdram_addr[((row_width - 1)) - (0) + 1]:"; + tooltip = "sdram_addr[((row_width - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_addr/width = (int((( ( $H/row_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_addr/width = "$"; + } + warning = "{{ if($PORT_sdram_addr/width <= 0)('width of sdram_addr must be greater than zero' ) }}"; + } + EDIT sdram_dq_width + { + id = "sdram_dq_width"; + editable = "0"; + title = "sdram_dq[((data_width - 1)) - (0) + 1]:"; + tooltip = "sdram_dq[((data_width - 1)) - (0) + 1]
direction: inout
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_dq/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_dq/width = "$"; + } + warning = "{{ if($PORT_sdram_dq/width <= 0)('width of sdram_dq must be greater than zero' ) }}"; + } + EDIT sdram_dqm_width + { + id = "sdram_dqm_width"; + editable = "0"; + title = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]:"; + tooltip = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_dqm/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_dqm/width = "$"; + } + warning = "{{ if($PORT_sdram_dqm/width <= 0)('width of sdram_dqm must be greater than zero' ) }}"; + } + EDIT avs_nios_address_width + { + id = "avs_nios_address_width"; + editable = "0"; + title = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]:"; + tooltip = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]
direction: input
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_address/width = (int((((( ( $H/bank_width ) + ( $H/row_width ) ) + ( $H/column_width ) ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Address_Width = $PORT_avs_nios_address/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_address/width = "$"; + } + warning = "{{ if($PORT_avs_nios_address/width <= 0)('width of avs_nios_address must be greater than zero' ) }}"; + } + EDIT avs_nios_byteenable_width + { + id = "avs_nios_byteenable_width"; + editable = "0"; + title = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]:"; + tooltip = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]
direction: input
signal type: byteenable"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_byteenable/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_byteenable/width = "$"; + } + warning = "{{ if($PORT_avs_nios_byteenable/width <= 0)('width of avs_nios_byteenable must be greater than zero' ) }}"; + } + EDIT avs_nios_writedata_width + { + id = "avs_nios_writedata_width"; + editable = "0"; + title = "avs_nios_writedata[((data_width - 1)) - (0) + 1]:"; + tooltip = "avs_nios_writedata[((data_width - 1)) - (0) + 1]
direction: input
signal type: writedata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_writedata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_writedata/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_writedata/width = "$"; + } + warning = "{{ if($PORT_avs_nios_writedata/width <= 0)('width of avs_nios_writedata must be greater than zero' ) }}"; + } + EDIT avs_nios_readdata_width + { + id = "avs_nios_readdata_width"; + editable = "0"; + title = "avs_nios_readdata[((data_width - 1)) - (0) + 1]:"; + tooltip = "avs_nios_readdata[((data_width - 1)) - (0) + 1]
direction: output
signal type: readdata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_readdata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_readdata/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_readdata/width = "$"; + } + warning = "{{ if($PORT_avs_nios_readdata/width <= 0)('width of avs_nios_readdata must be greater than zero' ) }}"; + } + } + } + } + } + } + SOPC_Builder_Version = "5.10"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by CBDocument.getParameterContainer + # used only by Component Editor + HDL_PARAMETER data_width + { + parameter_name = "data_width"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER bank_width + { + parameter_name = "bank_width"; + type = "integer"; + default_value = "4"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER row_width + { + parameter_name = "row_width"; + type = "integer"; + default_value = "12"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER column_width + { + parameter_name = "column_width"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER clk_mhz + { + parameter_name = "clk_mhz"; + type = "integer"; + default_value = "120"; + editable = "1"; + tooltip = ""; + } + } + SW_FILES + { + } + built_on = "2006.09.25.10:24:12"; + CACHED_HDL_INFO + { + # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection + # used only by Component Builder + FILE sdram_ctrl.vhd + { + file_mod = "Mon Sep 18 18:08:50 EEST 2006"; + quartus_map_start = "Mon Sep 25 10:22:36 EEST 2006"; + quartus_map_finished = "Mon Sep 25 10:22:58 EEST 2006"; + #found 1 valid modules + WRAPPER sdram_ctrl + { + CLASS sdram_ctrl + { + CB_GENERATOR + { + HDL_FILES + { + FILE + { + use_in_simulation = "1"; + use_in_synthesis = "1"; + filepath = "H:/Work/Home_stuff/opencores/sdram_ctrl/src/sdram_ctrl.vhd"; + } + } + top_module_name = "sdram_ctrl"; + emit_system_h = "0"; + LIBRARIES + { + library = "ieee.std_logic_1164.all"; + library = "ieee.numeric_std.all"; + library = "altera_mf.altera_mf_components.all"; + library = "std.standard.all"; + } + } + MODULE_DEFAULTS global_signals + { + class = "sdram_ctrl"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE nios + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT avs_nios_chipselect + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "chipselect"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_address + { + width = "-1"; + width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1"; + direction = "input"; + type = "address"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_byteenable + { + width = "-1"; + width_expression = "(((data_width / 8) - 1)) - (0) + 1"; + direction = "input"; + type = "byteenable"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_writedata + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "input"; + type = "writedata"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_write + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "write"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_read + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "read"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_waitrequest + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "waitrequest"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_readdata + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "output"; + type = "readdata"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_readdatavalid + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "readdatavalid"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT sdram_cke + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_ba + { + width = "-1"; + width_expression = "((bank_width - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_addr + { + width = "-1"; + width_expression = "((row_width - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_cs_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_ras_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_cas_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_we_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_dq + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "inout"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_dqm + { + width = "-1"; + width_expression = "(((data_width / 8) - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT reset + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "reset"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "sdram_ctrl"; + technology = "imported components"; + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by CBDocument.getParameterContainer + # used only by Component Editor + HDL_PARAMETER data_width + { + parameter_name = "data_width"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER bank_width + { + parameter_name = "bank_width"; + type = "integer"; + default_value = "4"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER row_width + { + parameter_name = "row_width"; + type = "integer"; + default_value = "12"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER column_width + { + parameter_name = "column_width"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER clk_mhz + { + parameter_name = "clk_mhz"; + type = "integer"; + default_value = "120"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + } + } + ASSOCIATED_FILES + { + Add_Program = "the_wizard_ui"; + Edit_Program = "the_wizard_ui"; + Generator_Program = "cb_generator.pl"; + } +} Index: sdram_ctrl/tags/V10/test_bench/sdram_ctrl_tb.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/sdram_ctrl_tb.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/sdram_ctrl_tb.vhd (revision 8) @@ -0,0 +1,169 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +entity sdram_ctrl_tb is +end sdram_ctrl_tb; + +architecture structure of sdram_ctrl_tb is + component pll + port ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + e0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ) ; + end component ; + component sdram_ctrl is + port( + signal clk : IN STD_LOGIC; + signal reset : IN STD_LOGIC; + + signal avs_nios_chipselect : IN STD_LOGIC; + signal avs_nios_address : IN STD_LOGIC_VECTOR (21 DOWNTO 0); + signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + signal avs_nios_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + signal avs_nios_write : IN STD_LOGIC; + signal avs_nios_read : IN STD_LOGIC; + signal avs_nios_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + signal avs_nios_readdatavalid : OUT STD_LOGIC; + signal avs_nios_waitrequest : OUT STD_LOGIC; + + signal sdram_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + signal sdram_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + signal sdram_cas_n : OUT STD_LOGIC; + signal sdram_cke : OUT STD_LOGIC; + signal sdram_cs_n : OUT STD_LOGIC; + signal sdram_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); + signal sdram_dqm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + signal sdram_ras_n : OUT STD_LOGIC; + signal sdram_we_n : OUT STD_LOGIC + ); + end component; + + component mt48lc4m32b2 IS + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => 'Z'); + Addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + Clk : IN STD_LOGIC := '0'; + Cke : IN STD_LOGIC := '1'; + Cs_n : IN STD_LOGIC := '1'; + Ras_n : IN STD_LOGIC := '1'; + Cas_n : IN STD_LOGIC := '1'; + We_n : IN STD_LOGIC := '1'; + Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000" + ); + END component; + + component cpu_simulator IS + PORT(clk, reset: IN std_logic; + address : OUT std_logic_vector(21 downto 0):=(others=>'0'); + writedata : out std_logic_vector(31 downto 0):=(others=>'0'); + byteenable : out std_logic_vector(3 downto 0):=(others=>'0'); + write : out std_logic:='0'; + read : out std_logic:='0'; + readdata : in std_logic_vector(31 downto 0); + waitrequest : in std_logic; + readdatavalid : in std_logic + ); + END component; + + signal reset, clk_ok: std_logic; + signal run_nios_n : std_logic:='1'; + signal clk,i_clk: std_logic:='0'; + + signal SDRAM_CLK : std_logic; + signal SDRAM_CKE : std_logic; + signal SDRAM_NCS : std_logic; + signal SDRAM_NRAS : std_logic; + signal SDRAM_NCAS : std_logic; + signal SDRAM_NWE : std_logic; + signal SDRAM_ADDRESS : std_logic_vector(11 downto 0); + signal SDRAM_BANK : std_logic_vector(1 downto 0); + signal SDRAM_DQM : std_logic_vector(3 downto 0); + signal SDRAM_DATA : std_logic_vector(31 downto 0); + + signal address : std_logic_vector(21 downto 0); + signal writedata : std_logic_vector(31 downto 0):=(others=>'0'); + signal byteenable : std_logic_vector(3 downto 0):=(others=>'0'); + signal write : std_logic; + signal read : std_logic; + signal chipselect : std_logic:='1'; + signal readdata : std_logic_vector(31 downto 0); + signal waitrequest : std_logic; + signal readdatavalid : std_logic; + +begin + + reset<= not clk_ok; + run_nios_n<= reset after 140 us; + + UUT: sdram_ctrl + port map( + clk => i_clk, + reset => reset, + + avs_nios_chipselect => chipselect, + avs_nios_address => address, + avs_nios_byteenable => byteenable, + avs_nios_writedata => writedata, + avs_nios_write => write, + avs_nios_read => read, + avs_nios_readdata => readdata, + avs_nios_readdatavalid => readdatavalid, + avs_nios_waitrequest => waitrequest, + + sdram_addr => SDRAM_ADDRESS, + sdram_ba => SDRAM_BANK, + sdram_cas_n => SDRAM_NCAS, + sdram_cke => SDRAM_CKE, + sdram_cs_n => SDRAM_NCS, + sdram_dq => SDRAM_DATA, + sdram_dqm => SDRAM_DQM, + sdram_ras_n => SDRAM_NRAS, + sdram_we_n => SDRAM_NWE + ); + + sdram:mt48lc4m32b2 + PORT MAP( + Dq => SDRAM_DATA, + Addr => SDRAM_ADDRESS, + Ba => SDRAM_BANK, + Clk => SDRAM_CLK, + Cke => SDRAM_CKE, + Cs_n => SDRAM_NCS, + Ras_n => SDRAM_NRAS, + Cas_n => SDRAM_NCAS, + We_n => SDRAM_NWE, + Dqm => SDRAM_DQM + ); + + cpu: cpu_simulator + PORT MAP( + clk => i_clk, + reset => run_nios_n, + address => address, + writedata => writedata, + byteenable => byteenable, + write => write, + read => read, + readdata => readdata, + waitrequest => waitrequest, + readdatavalid => readdatavalid + ); + + U1 : pll + port map( + inclk0 => clk, + c0 => i_clk, + e0 => SDRAM_CLK, + locked =>clk_ok + ); + + clock_generator:process + begin + wait for 21 ns; + clk<= clk xor '1'; + end process; +end structure; Index: sdram_ctrl/tags/V10/test_bench/mt48lc4m32b2.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/mt48lc4m32b2.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/mt48lc4m32b2.vhd (revision 8) @@ -0,0 +1,1134 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: MT48LC4M32B2.VHD +-- Version: 2.0 +-- Date: January 24th, 2002 +-- Model: Behavioral +-- Simulator: Model Technology +-- +-- Dependencies: None +-- +-- Email: modelsupport@micron.com +-- Company: Micron Technology, Inc. +-- Part Number: MT48LC4M32A2 (1Mb x 32 x 4 Banks) +-- +-- Description: Micron 128Mb SDRAM +-- +-- Limitation: - Doesn't check for 4096-cycle refresh +-- +-- Note: - Set simulator resolution to "ps" accuracy +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 1998 Micron Semiconductor Products, Inc. +-- All rights researved +-- +-- Rev Author Date Changes +-- --- -------------------------- ------------------------------------- +-- 2.0 SH 01/24/2002 - Second Release +-- Micron Technology Inc. +-- +-------------------------------------------------------------------------- + +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.STD_LOGIC_UNSIGNED.ALL; + USE IEEE.STD_LOGIC_ARITH.ALL; + +ENTITY mt48lc4m32b2 IS + GENERIC ( + -- Timing Parameters for -75 (PC133) and CL = 3 + tAC : TIME := 5.4 ns; + tHZ : TIME := 5.4 ns; + tOH : TIME := 2.7 ns; + tMRD : INTEGER := 2; -- 2 Clk Cycles + tRAS : TIME := 44.0 ns; + tRC : TIME := 66.0 ns; + tRCD : TIME := 20.0 ns; + tRFC : TIME := 66.0 ns; + tRP : TIME := 20.0 ns; + tRRD : TIME := 15.0 ns; + tWRa : TIME := 7.5 ns; -- Auto precharge + tWRm : TIME := 15.0 ns; -- Manual Precharge + + tAH : TIME := 0.8 ns; + tAS : TIME := 1.5 ns; + tCH : TIME := 2.5 ns; + tCL : TIME := 2.5 ns; + tCK : TIME := 7.5 ns; + tDH : TIME := 0.8 ns; + tDS : TIME := 1.5 ns; + tCKH : TIME := 0.8 ns; + tCKS : TIME := 1.5 ns; + tCMH : TIME := 0.8 ns; + tCMS : TIME := 1.5 ns; + + addr_bits : INTEGER := 12; + data_bits : INTEGER := 32; + col_bits : INTEGER := 8 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + Clk : IN STD_LOGIC := '0'; + Cke : IN STD_LOGIC := '1'; + Cs_n : IN STD_LOGIC := '1'; + Ras_n : IN STD_LOGIC := '1'; + Cas_n : IN STD_LOGIC := '1'; + We_n : IN STD_LOGIC := '1'; + Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000" + ); +END mt48lc4m32b2; + +ARCHITECTURE behave OF mt48lc4m32b2 IS + TYPE State IS (BST, NOP, PRECH, READ, WRITE); + TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER; + TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME; + TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; + TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF STD_LOGIC_VECTOR (Col_bits - 1 DOWNTO 0); + TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State; + SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Active_enable, Aref_enable, Burst_term : STD_LOGIC := '0'; + SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; + SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : STD_LOGIC := '0'; + SIGNAL Cas_latency_1, Cas_latency_2, Cas_latency_3 : STD_LOGIC := '0'; + SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; + SIGNAL Write_burst_mode : STD_LOGIC := '0'; + SIGNAL Sys_clk, CkeZ : STD_LOGIC := '0'; + +BEGIN + -- Strip the strength + Cs_in <= To_X01 (Cs_n); + Ras_in <= To_X01 (Ras_n); + Cas_in <= To_X01 (Cas_n); + We_in <= To_X01 (We_n); + + -- Commands Decode + Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; + Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; + Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); + Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in); + Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); + Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; + Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); + + -- Burst Length Decode + Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0)); + Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); + Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); + Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + + -- CAS Latency Decode + Cas_latency_1 <= NOT(Mode_reg(6)) AND NOT(Mode_reg(5)) AND Mode_reg(4); + Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); + + -- Write Burst Mode + Write_burst_mode <= Mode_reg(9); + + -- System Clock + int_clk : PROCESS (Clk) + BEGIN + IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN + CkeZ <= Cke; + END IF; + Sys_clk <= CkeZ AND Clk; + END PROCESS; + + state_register : PROCESS + TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + TYPE ram_pntr IS ACCESS ram_type; + TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr; + VARIABLE Bank0 : ram_stor; + VARIABLE Bank1 : ram_stor; + VARIABLE Bank2 : ram_stor; + VARIABLE Bank3 : ram_stor; + VARIABLE Row_index, Col_index : INTEGER := 0; + VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0'); + + VARIABLE Col_addr : Array4xCBV; + VARIABLE Bank_addr : Array4x2BV; + VARIABLE Dqm_reg0, Dqm_reg1 : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"; + + VARIABLE Bank, Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col_brst : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Row : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Burst_counter : INTEGER := 0; + + VARIABLE Command : Array_state; + VARIABLE Bank_precharge : Array4x2BV; + VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE RW_interrupt_counter : Array4xI := (0 & 0 & 0 & 0); + VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0); + + VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; + VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; + VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; + + -- Timing Check + VARIABLE MRD_chk : INTEGER := 0; + VARIABLE RFC_chk : TIME := 0 ns; + VARIABLE RRD_chk : TIME := 0 ns; + VARIABLE WR_chkm : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns); + VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; + VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; + VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; + VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; + + -- Initialize empty rows + PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR (1 DOWNTO 0); Row_index : INTEGER) IS + VARIABLE i, j : INTEGER := 0; + BEGIN + IF Bank = "00" THEN + IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty + Bank0 (Row_index) := NEW ram_type; -- Open new row for access + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank0 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "01" THEN + IF Bank1 (Row_index) = NULL THEN + Bank1 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank1 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "10" THEN + IF Bank2 (Row_index) = NULL THEN + Bank2 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank2 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "11" THEN + IF Bank3 (Row_index) = NULL THEN + Bank3 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank3 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + END IF; + END; + + -- Burst Counter + PROCEDURE Burst_decode IS + VARIABLE Col_int : INTEGER := 0; + VARIABLE Col_vec, Col_temp : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + -- Advance Burst Counter + Burst_counter := Burst_counter + 1; + + -- Burst Type + IF Mode_reg (3) = '0' THEN + Col_int := conv_integer(Col) + 1; + Col_temp := CONV_STD_LOGIC_VECTOR(Col_int, col_bits); + ELSIF Mode_reg (3) = '1' THEN + Col_vec := CONV_STD_LOGIC_VECTOR(Burst_counter, col_bits); + Col_temp (2) := Col_vec (2) XOR Col_brst (2); + Col_temp (1) := Col_vec (1) XOR Col_brst (1); + Col_temp (0) := Col_vec (0) XOR Col_brst (0); + END IF; + + -- Burst Length + IF Burst_length_2 = '1' THEN + Col (0) := Col_temp (0); + ELSIF Burst_length_4 = '1' THEN + Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0); + ELSIF Burst_length_8 = '1' THEN + Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0); + ELSE + Col := Col_temp; + END IF; + + -- Burst Read Single Write + IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Data counter + IF Burst_length_1 = '1' THEN + IF Burst_counter >= 1 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_2 = '1' THEN + IF Burst_counter >= 2 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_4 = '1' THEN + IF Burst_counter >= 4 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_8 = '1' THEN + IF Burst_counter >= 8 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + END IF; + END; + + BEGIN + WAIT ON Sys_clk; + IF Sys_clk'event AND Sys_clk = '1' THEN + -- Internal Pipeline + Command(0) := Command(1); + Command(1) := Command(2); + Command(2) := Command(3); + Command(3) := NOP; + + Col_addr(0) := Col_addr(1); + Col_addr(1) := Col_addr(2); + Col_addr(2) := Col_addr(3); + Col_addr(3) := (OTHERS => '0'); + + Bank_addr(0) := Bank_addr(1); + Bank_addr(1) := Bank_addr(2); + Bank_addr(2) := Bank_addr(3); + Bank_addr(3) := "00"; + + Bank_precharge(0) := Bank_precharge(1); + Bank_precharge(1) := Bank_precharge(2); + Bank_precharge(2) := Bank_precharge(3); + Bank_precharge(3) := "00"; + + A10_precharge(0) := A10_precharge(1); + A10_precharge(1) := A10_precharge(2); + A10_precharge(2) := A10_precharge(3); + A10_precharge(3) := '0'; + + -- Dqm pipeline for Read + Dqm_reg0 := Dqm_reg1; + Dqm_reg1 := Dqm; + + -- Read or Write with Auto Precharge Counter + IF Auto_precharge (0) = '1' THEN + Count_precharge (0) := Count_precharge (0) + 1; + END IF; + IF Auto_precharge (1) = '1' THEN + Count_precharge (1) := Count_precharge (1) + 1; + END IF; + IF Auto_precharge (2) = '1' THEN + Count_precharge (2) := Count_precharge (2) + 1; + END IF; + IF Auto_precharge (3) = '1' THEN + Count_precharge (3) := Count_precharge (3) + 1; + END IF; + + -- Read or Write Interrupt Counter + IF RW_interrupt_write (0) = '1' THEN + RW_interrupt_counter (0) := RW_interrupt_counter (0) + 1; + END IF; + IF RW_interrupt_write (1) = '1' THEN + RW_interrupt_counter (1) := RW_interrupt_counter (1) + 1; + END IF; + IF RW_interrupt_write (2) = '1' THEN + RW_interrupt_counter (2) := RW_interrupt_counter (2) + 1; + END IF; + IF RW_interrupt_write (3) = '1' THEN + RW_interrupt_counter (3) := RW_interrupt_counter (3) + 1; + END IF; + + -- tMRD Counter + MRD_chk := MRD_chk + 1; + + -- Auto Refresh + IF Aref_enable = '1' THEN + -- Auto Refresh to Auto Refresh + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT ((NOW - RP_chk0 >= tRP) OR (NOW - RP_chk1 >= tRP) OR + (NOW - RP_chk2 >= tRP) OR (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT (Pc_b0 ='1' AND Pc_b1 = '1' AND Pc_b2 ='1' AND Pc_b3 = '1') + REPORT "All banks must be Precharge before Auto Refresh" + SEVERITY WARNING; + + -- Load Mode Register to Auto Refresh + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Auto Refresh" + SEVERITY WARNING; + + -- Record current tRFC time + RFC_chk := NOW; + END IF; + + -- Load Mode Register + IF Mode_reg_enable = '1' THEN + -- Register Mode + Mode_reg <= Addr; + + -- Precharge to Load Mode Register + ASSERT (Pc_b0 ='1' AND Pc_b1 = '1' AND Pc_b2 ='1' AND Pc_b3 = '1') + REPORT "All banks must be Precharge before Load Mode Register" + SEVERITY WARNING; + + -- Precharge to Load Mode Register + ASSERT ((NOW - RP_chk0 >= tRP) OR (NOW - RP_chk1 >= tRP) OR + (NOW - RP_chk2 >= tRP) OR (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Load Mode Register" + SEVERITY WARNING; + + -- Auto Refresh to Load Mode Register + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Load Mode Register" + SEVERITY WARNING; + + -- Load Mode Register to Load Mode Register + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Load Mode Register" + SEVERITY WARNING; + + -- Record current tMRD time + MRD_chk := 0; + END IF; + + -- Active Block (Latch Bank and Row Address) + IF Active_enable = '1' THEN + -- Activate an OPEN bank can corrupt data + ASSERT ((Ba = "00" AND Act_b0 = '0') OR (Ba = "01" AND Act_b1 = '0') OR + (Ba = "10" AND Act_b2 = '0') OR (Ba = "11" AND Act_b3 = '0')) + REPORT "Bank is already activated - data can be corrupted" + SEVERITY WARNING; + + -- Activate Bank 0 + IF Ba = "00" AND Pc_b0 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk0 >= tRC) + REPORT "tRC violation during Activate Bank 0" + SEVERITY WARNING; + + -- Precharge to Activate + ASSERT (NOW - RP_chk0 >= tRP) + REPORT "tRP violation during Activate Bank 0" + SEVERITY WARNING; + + -- Record variables for checking violation + Act_b0 := '1'; + Pc_b0 := '0'; + B0_row_addr := Addr; + RAS_chk0 := NOW; + RC_chk0 := NOW; + RCD_chk0 := NOW; + END IF; + + -- Activate Bank 1 + IF Ba = "01" AND Pc_b1 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk1 >= tRC) + REPORT "tRC violation during Activate Bank 1" + SEVERITY WARNING; + + -- Precharge to Activate + ASSERT (NOW - RP_chk1 >= tRP) + REPORT "tRP violation during Activate Bank 1" + SEVERITY WARNING; + + -- Record variables for checking violation + Act_b1 := '1'; + Pc_b1 := '0'; + B1_row_addr := Addr; + RAS_chk1 := NOW; + RC_chk1 := NOW; + RCD_chk1 := NOW; + END IF; + + -- Activate Bank 2 + IF Ba = "10" AND Pc_b2 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk2 >= tRC) + REPORT "tRC violation during Activate Bank 2" + SEVERITY WARNING; + + -- Precharge to Activate + ASSERT (NOW - RP_chk2 >= tRP) + REPORT "tRP violation during Activate Bank 2" + SEVERITY WARNING; + + -- Record variables for checking violation + Act_b2 := '1'; + Pc_b2 := '0'; + B2_row_addr := Addr; + RAS_chk2 := NOW; + RC_chk2 := NOW; + RCD_chk2 := NOW; + END IF; + + -- Activate Bank 3 + IF Ba = "11" AND Pc_b3 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk3 >= tRC) + REPORT "tRC violation during Activate Bank 3" + SEVERITY WARNING; + + -- Precharge to Activate + ASSERT (NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Activate Bank 3" + SEVERITY WARNING; + + -- Record variables for checking violation + Act_b3 := '1'; + Pc_b3 := '0'; + B3_row_addr := Addr; + RAS_chk3 := NOW; + RC_chk3 := NOW; + RCD_chk3 := NOW; + END IF; + + -- Activate to Activate (different bank) + IF (Prev_bank /= Ba) THEN + ASSERT (NOW - RRD_chk >= tRRD) + REPORT "tRRD violation during Activate" + SEVERITY WARNING; + END IF; + + -- Auto Refresh to Activate + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Activate" + SEVERITY WARNING; + + -- Load Mode Register to Activate + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Activate" + SEVERITY WARNING; + + -- Record variable for checking violation + RRD_chk := NOW; + Prev_Bank := Ba; + END IF; + + -- Precharge Block + IF Prech_enable = '1' THEN + -- Load Mode Register to Precharge + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Precharge" + SEVERITY WARNING; + + -- Precharge Bank 0 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN + Act_b0 := '0'; + Pc_b0 := '1'; + RP_chk0 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk0 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chkm(0) >= tWRm) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 1 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN + Act_b1 := '0'; + Pc_b1 := '1'; + RP_chk1 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk1 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chkm(1) >= tWRm) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 2 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN + Act_b2 := '0'; + Pc_b2 := '1'; + RP_chk2 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk2 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chkm(2) >= tWRm) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 3 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN + Act_b3 := '0'; + Pc_b3 := '1'; + RP_chk3 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk3 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chkm(3) >= tWRm) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Terminate a Write Immediately (if same bank or all banks) + IF (Data_in_enable = '1' AND (Bank = Ba OR Addr(10) = '1')) THEN + Data_in_enable := '0'; + END IF; + + -- Precharge Command Pipeline for READ + IF CAS_latency_3 = '1' THEN + Command(2) := PRECH; + Bank_precharge(2) := Ba; + A10_precharge(2) := Addr(10); + ELSIF CAS_latency_2 = '1' THEN + Command(1) := PRECH; + Bank_precharge(1) := Ba; + A10_precharge(1) := Addr(10); + END IF; + END IF; + + -- Burst Terminate + IF Burst_term = '1' THEN + -- Terminate a Write immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Terminate a Read depend on CAS Latency + IF CAS_latency_3 = '1' THEN + Command(2) := BST; + ELSIF CAS_latency_2 = '1' THEN + Command(1) := BST; + END IF; + END IF; + + -- Read Command + IF Read_enable = '1' THEN + -- Activate to Read + ASSERT ((Ba="00" AND Act_b0='1') OR (Ba="01" AND Act_b1='1') OR + (Ba="10" AND Act_b2='1') OR (Ba="11" AND Act_b3='1')) + REPORT "Bank is not Activated for Read" + SEVERITY WARNING; + + -- Activate to Read + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Read" + SEVERITY WARNING; + + -- CAS Latency Pipeline + IF Cas_latency_3 = '1' THEN + Command(2) := READ; + Col_addr (2) := Addr(col_bits - 1 DOWNTO 0); + Bank_addr (2) := Ba; + ELSIF Cas_latency_2 = '1' THEN + Command(1) := READ; + Col_addr (1) := Addr(col_bits - 1 DOWNTO 0); + Bank_addr (1) := Ba; + ELSIF Cas_latency_1 = '1' THEN + Command(0) := READ; + Col_addr (0) := Addr(col_bits - 1 DOWNTO 0); + Bank_addr (0) := Ba; + END IF; + + -- Read Terminate Write Immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + -- Interrupt a Write with Auto Precharge + IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_write(CONV_INTEGER(RW_Interrupt_Bank)) := '1'; + RW_interrupt_counter (CONV_INTEGER(RW_Interrupt_Bank)) := 0; + ASSERT FALSE REPORT "Read interrupt a Write with Auto Precharge." SEVERITY NOTE; + END IF; + END IF; + + -- Read Terminate Read after CL - 1 + IF (Data_out_enable = '1' AND ((Cas_latency_2 = '1' AND ((Burst_length_2 = '1' AND Burst_counter < 1) OR + (Burst_length_4 = '1' AND Burst_counter < 3) OR + (Burst_length_8 = '1' AND Burst_counter < 7))) OR + (Cas_latency_3 = '1' AND ((Burst_length_4 = '1' AND Burst_counter < 2) OR + (Burst_length_8 = '1' AND Burst_counter < 6))))) THEN + -- Interrupt a Read with Auto Precharge + IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_read(CONV_INTEGER(RW_Interrupt_Bank)) := '1'; + ASSERT FALSE REPORT "Read interrupt a Read with Auto Precharge." SEVERITY NOTE; + END IF; + END IF; + + -- Auto Precharge + IF Addr(10) = '1' THEN + Auto_precharge (CONV_INTEGER(Ba)) := '1'; + Count_precharge (CONV_INTEGER(Ba)) := 0; + RW_Interrupt_Bank := Ba; + Read_precharge (CONV_INTEGER(Ba)) := '1'; + END IF; + END IF; + + -- Write Command + IF Write_enable = '1' THEN + -- Activate to Write + ASSERT ((Ba="00" AND Act_b0='1') OR (Ba="01" AND Act_b1='1') OR + (Ba="10" AND Act_b2='1') OR (Ba="11" AND Act_b3='1')) + REPORT "Bank is not Activated for Write" + SEVERITY WARNING; + + -- Activate to Write + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Write" + SEVERITY WARNING; + + -- Latch write command, bank, column + Command(0) := WRITE; + Col_addr (0) := Addr(col_bits - 1 DOWNTO 0); + Bank_addr (0) := Ba; + + -- Write Terminate Write Immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + + -- Interrupt a Write with Auto Precharge + IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_write(CONV_INTEGER(RW_Interrupt_Bank)) := '1'; + RW_interrupt_counter (CONV_INTEGER(RW_Interrupt_Bank)) := 0; + ASSERT FALSE REPORT "Write interrupt a Write with Auto Precharge." SEVERITY NOTE; + END IF; + END IF; + + -- Write Terminate Read Immediately + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + + -- Interrupt a Read with Auto Precharge + IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_read(CONV_INTEGER(RW_Interrupt_Bank)) := '1'; + ASSERT FALSE REPORT "Write interrupt a Read with Auto Precharge." SEVERITY NOTE; + END IF; + END IF; + + -- Auto Precharge + IF Addr(10) = '1' THEN + Auto_precharge (CONV_INTEGER(Ba)) := '1'; + Count_precharge (CONV_INTEGER(Ba)) := 0; + RW_Interrupt_Bank := Ba; + Write_precharge (CONV_INTEGER(Ba)) := '1'; + END IF; + END IF; + + -- Write with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet tRAS requirement + -- and 2. tWR cycle(s) after last valid data + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + -- + -- Note: Model is starting the internal precharge 1 cycle after they meet all the + -- requirement but tRP will be compensate for the time after the 1 cycle. + IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR + (RW_interrupt_write(0) = '1' AND RW_interrupt_counter(0) >= 1)) THEN + Auto_precharge(0) := '0'; + Write_precharge(0) := '0'; + RW_interrupt_write(0) := '0'; + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW + tWRa; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR + (RW_interrupt_write(1) = '1' AND RW_interrupt_counter(1) >= 1)) THEN + Auto_precharge(1) := '0'; + Write_precharge(1) := '0'; + RW_interrupt_write(1) := '0'; + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW + tWRa; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR + (RW_interrupt_write(2) = '1' AND RW_interrupt_counter(2) >= 1)) THEN + Auto_precharge(2) := '0'; + Write_precharge(2) := '0'; + RW_interrupt_write(2) := '0'; + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW + tWRa; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR + (RW_interrupt_write(0) = '1' AND RW_interrupt_counter(3) >= 1)) THEN + Auto_precharge(3) := '0'; + Write_precharge(3) := '0'; + RW_interrupt_write(3) := '0'; + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW + tWRa; + END IF; + END IF; + + -- Read with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet minimum tRAS requirement + -- and 2. CL - 1 cycle(s) before last valid data + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR + (RW_interrupt_read(0) = '1')) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Auto_precharge(0) := '0'; + Read_precharge(0) := '0'; + RW_interrupt_read(0) := '0'; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR + (RW_interrupt_read(1) = '1')) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Auto_precharge(1) := '0'; + Read_precharge(1) := '0'; + RW_interrupt_read(1) := '0'; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR + (RW_interrupt_read(2) = '1')) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Auto_precharge(2) := '0'; + Read_precharge(2) := '0'; + RW_interrupt_read(2) := '0'; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR + (RW_interrupt_read(3) = '1')) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Auto_precharge(3) := '0'; + Read_precharge(3) := '0'; + RW_interrupt_read(3) := '0'; + END IF; + END IF; + + -- Internal Precharge or Bst + IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks + IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + + IF Data_out_enable = '0' THEN + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH; + END IF; + + -- Detect Read or Write Command + IF Command(0) = READ THEN + Bank := Bank_addr (0); + Col := Col_addr (0); + Col_brst := Col_addr (0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '0'; + Data_out_enable := '1'; + ELSIF Command(0) = WRITE THEN + Bank := Bank_addr(0); + Col := Col_addr(0); + Col_brst := Col_addr(0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '1'; + Data_out_enable := '0'; + END IF; + + -- DQ (Driver / Receiver) + Row_index := CONV_INTEGER (Row); + Col_index := CONV_INTEGER (Col); + + IF Data_in_enable = '1' THEN + IF Dqm /= "1111" THEN + -- Initialize Memory + Init_mem (Bank, Row_index); + + -- Array Buffer + CASE Bank IS + WHEN "00" => Dq_temp := Bank0 (Row_index) (Col_index); + WHEN "01" => Dq_temp := Bank1 (Row_index) (Col_index); + WHEN "10" => Dq_temp := Bank2 (Row_index) (Col_index); + WHEN OTHERS => Dq_temp := Bank3 (Row_index) (Col_index); + END CASE; + + -- Dqm Operation + IF Dqm (0) = '0' THEN + Dq_temp ( 7 DOWNTO 0) := Dq ( 7 DOWNTO 0); + END IF; + IF Dqm (1) = '0' THEN + Dq_temp (15 DOWNTO 8) := Dq (15 DOWNTO 8); + END IF; + IF Dqm (2) = '0' THEN + Dq_temp (23 DOWNTO 16) := Dq (23 DOWNTO 16); + END IF; + IF Dqm (3) = '0' THEN + Dq_temp (31 DOWNTO 24) := Dq (31 DOWNTO 24); + END IF; + + -- Write to Memory + CASE Bank IS + WHEN "00" => Bank0 (Row_index) (Col_index) := Dq_temp; + WHEN "01" => Bank1 (Row_index) (Col_index) := Dq_temp; + WHEN "10" => Bank2 (Row_index) (Col_index) := Dq_temp; + WHEN OTHERS => Bank3 (Row_index) (Col_index) := Dq_temp; + END CASE; + + -- Record tWR for manual precharge + WR_chkm(CONV_INTEGER(Bank)) := NOW; + END IF; + + -- Advance Burst Counter + Burst_decode; + + ELSIF Data_out_enable = '1' THEN + IF Dqm_reg0 /= "1111" THEN + -- Initialize Memory + Init_mem (Bank, Row_index); + + -- Array Buffer + CASE Bank IS + WHEN "00" => Dq_temp := Bank0 (Row_index) (Col_index); + WHEN "01" => Dq_temp := Bank1 (Row_index) (Col_index); + WHEN "10" => Dq_temp := Bank2 (Row_index) (Col_index); + WHEN OTHERS => Dq_temp := Bank3 (Row_index) (Col_index); + END CASE; + + -- Dqm Operation + IF Dqm_reg0 (0) = '1' THEN + Dq_temp ( 7 DOWNTO 0) := (OTHERS => 'Z'); + END IF; + IF Dqm_reg0 (1) = '1' THEN + Dq_temp (15 DOWNTO 8) := (OTHERS => 'Z'); + END IF; + IF Dqm_reg0 (2) = '1' THEN + Dq_temp (23 DOWNTO 16) := (OTHERS => 'Z'); + END IF; + IF Dqm_reg0 (3) = '1' THEN + Dq_temp (31 DOWNTO 24) := (OTHERS => 'Z'); + END IF; + + -- Output + Dq <= TRANSPORT Dq_temp AFTER tAC; + ELSE + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ; + END IF; + + -- Advance Burst Counter + Burst_decode; + END IF; + END IF; + + END PROCESS; + + -- Clock timing checks + Clock_check : PROCESS + VARIABLE Clk_low, Clk_high : TIME := 0 ns; + BEGIN + WAIT ON Clk; + IF (Clk = '1' AND NOW >= 10 ns) THEN + ASSERT (NOW - Clk_low >= tCL) + REPORT "tCL violation" + SEVERITY WARNING; + ASSERT (NOW - Clk_high >= tCK) + REPORT "tCK violation" + SEVERITY WARNING; + Clk_high := NOW; + ELSIF (Clk = '0' AND NOW /= 0 ns) THEN + ASSERT (NOW - Clk_high >= tCH) + REPORT "tCH violation" + SEVERITY WARNING; + Clk_low := NOW; + END IF; + END PROCESS; + + -- Setup timing checks + Setup_check : PROCESS + BEGIN + WAIT ON Clk; + IF Clk = '1' THEN + ASSERT(Cke'LAST_EVENT >= tCKS) + REPORT "CKE Setup time violation -- tCKS" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tCMS) + REPORT "CS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tCMS) + REPORT "CAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tCMS) + REPORT "RAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tCMS) + REPORT "WE# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT >= tCMS) + REPORT "Dqm Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tAS) + REPORT "ADDR Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tAS) + REPORT "BA Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Dq'LAST_EVENT >= tDS) + REPORT "Dq Setup time violation -- tDS" + SEVERITY WARNING; + END IF; + END PROCESS; + + -- Hold timing checks + Hold_check : PROCESS + BEGIN + WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH); + IF Clk'DELAYED (tCKH) = '1' THEN + ASSERT(Cke'LAST_EVENT > tCKH) + REPORT "CKE Hold time violation -- tCKH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tCMH) = '1' THEN + ASSERT(Cs_n'LAST_EVENT > tCMH) + REPORT "CS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT > tCMH) + REPORT "CAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT > tCMH) + REPORT "RAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT > tCMH) + REPORT "WE# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT > tCMH) + REPORT "Dqm Hold time violation -- tCMH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tAH) = '1' THEN + ASSERT(Addr'LAST_EVENT > tAH) + REPORT "ADDR Hold time violation -- tAH" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT > tAH) + REPORT "BA Hold time violation -- tAH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tDH) = '1' THEN + ASSERT(Dq'LAST_EVENT > tDH) + REPORT "Dq Hold time violation -- tDH" + SEVERITY WARNING; + END IF; + END PROCESS; + +END behave; Index: sdram_ctrl/tags/V10/test_bench/cpu_simulator.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/cpu_simulator.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/cpu_simulator.vhd (revision 8) @@ -0,0 +1,72 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY cpu_simulator IS + PORT(clk, reset: in std_logic; + + address : out std_logic_vector(21 downto 0); + writedata : out std_logic_vector(31 downto 0); + byteenable : out std_logic_vector(3 downto 0); + write : out std_logic; + read : out std_logic; + readdata : in std_logic_vector(31 downto 0); + waitrequest : in std_logic; + readdatavalid : in std_logic + ); +END cpu_simulator; + +ARCHITECTURE behaviour OF cpu_simulator IS + signal counter: unsigned(3 downto 0); + type vector is + record + address: integer; + writedata: integer; + byteenable: std_logic_vector(3 downto 0); + write: std_logic; + read: std_logic; + end record; + type script is array(0 to (2**counter'length)-1) of vector; + signal wave_form: script:=( + (0,0,"1111",'1','0'), + (1,1,"1111",'1','0'), + (2,2,"1111",'1','0'), + (3,3,"1111",'1','0'), + (1024,1024,"1111",'0','1'), + (1025,1025,"1111",'0','1'), + (1026,1026,"1111",'0','1'), + (1027,1027,"1111",'0','1'), + (1024,1024,"1111",'1','0'), + (1025,1025,"1111",'1','0'), + (1026,1026,"1111",'1','0'), + (1027,1027,"1111",'1','0'), + (0,0,"1111",'0','1'), + (1,1,"1111",'0','1'), + (2,2,"1111",'0','1'), + (3,3,"1111",'0','1') + ); +BEGIN + process(clk,reset) + begin + if reset='1' + then + counter<=(others=>'0'); + address<=(others=>'0'); + writedata<=(others=>'0'); + byteenable<=(others=>'0'); + write<='0'; + read<='0'; + elsif rising_edge(clk) + then + if waitrequest='0' + then + counter<=counter+1; + address<=std_logic_vector(to_unsigned(wave_form(to_integer(counter)).address,address'length)); + writedata<=std_logic_vector(to_unsigned(wave_form(to_integer(counter)).writedata,writedata'length)); + byteenable<=wave_form(to_integer(counter)).byteenable; + write<=wave_form(to_integer(counter)).write; + read<=wave_form(to_integer(counter)).read; + end if; + end if; + end process; +END behaviour; \ No newline at end of file Index: sdram_ctrl/tags/V10/test_bench/pll.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/pll.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/pll.vhd (revision 8) @@ -0,0 +1,256 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 5.1 Build 213 01/19/2006 SP 1 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + e0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + extclk0_divide_by : NATURAL; + extclk0_duty_cycle : NATURAL; + extclk0_multiply_by : NATURAL; + extclk0_phase_shift : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + extclk : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire4 <= sub_wire3(0); + e0 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => 2, + clk0_duty_cycle => 50, + clk0_multiply_by => 11, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + extclk0_divide_by => 2, + extclk0_duty_cycle => 50, + extclk0_multiply_by => 11, + extclk0_phase_shift => "5682", + inclk0_input_frequency => 41666, + intended_device_family => "Cyclone", + invalid_lock_multiplier => 5, + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + valid_lock_multiplier => 1 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2, + extclk => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "504.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "deg" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "132.000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK6 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK6 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA6 STRING "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: EXTCLK0_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: EXTCLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: EXTCLK0_MULTIPLY_BY NUMERIC "11" +-- Retrieval info: CONSTANT: EXTCLK0_PHASE_SHIFT STRING "5682" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +-- Retrieval info: USED_PORT: e0 0 0 0 0 OUTPUT VCC "e0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: e0 0 0 0 0 @extclk 0 0 1 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE Index: sdram_ctrl/tags/V10/test_bench/old/nios.dat =================================================================== --- sdram_ctrl/tags/V10/test_bench/old/nios.dat (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/old/nios.dat (revision 8) @@ -0,0 +1 @@ + ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ \ No newline at end of file Index: sdram_ctrl/tags/V10/test_bench/old/Hello_LED_sdram_0.dat =================================================================== --- sdram_ctrl/tags/V10/test_bench/old/Hello_LED_sdram_0.dat (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/old/Hello_LED_sdram_0.dat (revision 8) @@ -0,0 +1,49 @@ +@00000000 00400034 +@00000001 08400804 +@00000002 0800683A +@00000003 00000000 +@00000004 00000000 +@00000005 00000000 +@00000006 00000000 +@00000007 00000000 +@00000008 06C04034 +@00000009 DEC00004 +@0000000A 06800074 +@0000000B D6A03104 +@0000000C 00000340 +@0000000D DEFFFD04 +@0000000E DF000215 +@0000000F D839883A +@00000010 00800084 +@00000011 E0800005 +@00000012 E0000045 +@00000013 E0800003 +@00000014 1080204C +@00000015 1005003A +@00000016 1000031E +@00000017 E0800043 +@00000018 1080005C +@00000019 E0800045 +@0000001A E0800043 +@0000001B 1005003A +@0000001C 1000041E +@0000001D E0800003 +@0000001E 1004D07A +@0000001F E0800005 +@00000020 00000306 +@00000021 E0800003 +@00000022 1085883A +@00000023 E0800005 +@00000024 00C04034 +@00000025 18C21004 +@00000026 E0800003 +@00000027 18800035 +@00000028 E0000115 +@00000029 E0C00117 +@0000002A 008000F4 +@0000002B 10834FC4 +@0000002C 10FFE616 +@0000002D E0800117 +@0000002E 10800044 +@0000002F E0800115 +@00000030 003FF806 Index: sdram_ctrl/tags/V10/test_bench/old/cpu_simulator_file_based.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/old/cpu_simulator_file_based.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/old/cpu_simulator_file_based.vhd (revision 8) @@ -0,0 +1,79 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY cpu_simulator IS + PORT(clk, reset: in std_logic; + + address : out std_logic_vector(21 downto 0); + writedata : out std_logic_vector(31 downto 0); + byteenable : out std_logic_vector(3 downto 0); + write : out std_logic; + read : out std_logic; + readdata : in std_logic_vector(31 downto 0); + waitrequest : in std_logic; + readdatavalid : in std_logic + ); +END cpu_simulator; + +ARCHITECTURE behaviour OF cpu_simulator IS + signal address: std_logic_vector(21 downto 0); + signal writedata: std_logic_vector(31 downto 0); + signal byteenable: std_logic_vector(3 downto 0); + signal write: std_logic; + signal read: std_logic; + +BEGIN + process(clk,reset) + variable service: std_logic_vector(7 downto 0); + variable b0,b1,b2,b3,b4,b5,b6,b7: BYTE; + begin + if reset='1' + then + file_close(NIOS); + file_open(NIOS, FILES_PATH&"nios.dat", READ_MODE); + elsif rising_edge(clk) + then + if waitrequest='0' + then + if Endfile(NIOS) + then + file_close(NIOS); + file_open(NIOS, FILES_PATH&"nios.dat", READ_MODE); + else + Read(NIOS,b0); + Read(NIOS,b1); + Read(NIOS,b2); + Read(NIOS,b3); + Read(NIOS,b4); + Read(NIOS,b5); + Read(NIOS,b6); + Read(NIOS,b7); + service:=char2std_logic_vector(b0); + address<=service(5 downto 0)&char2std_logic_vector(b1)&char2std_logic_vector(b2); + writedata<=char2std_logic_vector(b3)&char2std_logic_vector(b4)&char2std_logic_vector(b5)&char2std_logic_vector(b6); + service:=char2std_logic_vector(b7); + byteenable<=not service(7 downto 4); + write<=service(3); + read<=service(2); + end if; + end if; + end if; + end process; + + process(clk,reset) + begin + if reset='1' + then + readed<=(others=>'0'); + new_data<='0'; + elsif rising_edge(clk) + then + new_data<=readdatavalid; + if readdatavalid='1' + then + readed<=readdata; + end if; + end if; + end process; +END behaviour; \ No newline at end of file Index: sdram_ctrl/tags/V10/test_bench/old/Count_Binary_sdram_0.dat =================================================================== --- sdram_ctrl/tags/V10/test_bench/old/Count_Binary_sdram_0.dat (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/old/Count_Binary_sdram_0.dat (revision 8) @@ -0,0 +1,5026 @@ +;Count Binary +@00000000 00820014 +@00000001 1001483A +@00000002 10BFF804 +@00000003 00BFFD16 +@00000004 00400034 +@00000005 08407204 +@00000006 0800683A +@00000007 00000000 +@00000008 DEFFED04 +@00000009 DFC00015 +@0000000A D8400215 +@0000000B D8800315 +@0000000C D8C00415 +@0000000D D9000515 +@0000000E D9400615 +@0000000F D9800715 +@00000010 D9C00815 +@00000011 000B307A +@00000012 DA000915 +@00000013 DA400A15 +@00000014 DA800B15 +@00000015 DAC00C15 +@00000016 DB000D15 +@00000017 DB400E15 +@00000018 DB800F15 +@00000019 DBC01015 +@0000001A D9401115 +@0000001B EBFFFF04 +@0000001C DBC01215 +@0000001D 0009313A +@0000001E 2880004C +@0000001F 10000326 +@00000020 20000226 +@00000021 00000EC0 +@00000022 00000306 +@00000023 DF401215 +@00000024 E8BFFF17 +@00000025 003DA03A +@00000026 D9401117 +@00000027 DF401217 +@00000028 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direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_ba/width = (int((( ( $H/bank_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_ba/width = "$"; + } + warning = "{{ if($PORT_sdram_ba/width <= 0)('width of sdram_ba must be greater than zero' ) }}"; + } + EDIT sdram_addr_width + { + id = "sdram_addr_width"; + editable = "0"; + title = "sdram_addr[((row_width - 1)) - (0) + 1]:"; + tooltip = "sdram_addr[((row_width - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_addr/width = (int((( ( $H/row_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_addr/width = "$"; + } + warning = "{{ if($PORT_sdram_addr/width <= 0)('width of sdram_addr must be greater than zero' ) }}"; + } + EDIT sdram_dq_width + { + id = "sdram_dq_width"; + editable = "0"; + title = "sdram_dq[((data_width - 1)) - (0) + 1]:"; + tooltip = "sdram_dq[((data_width - 1)) - (0) + 1]
direction: inout
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_dq/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_dq/width = "$"; + } + warning = "{{ if($PORT_sdram_dq/width <= 0)('width of sdram_dq must be greater than zero' ) }}"; + } + EDIT sdram_dqm_width + { + id = "sdram_dqm_width"; + editable = "0"; + title = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]:"; + tooltip = "sdram_dqm[(((data_width / 8) - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_sdram_dqm/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_sdram_dqm/width = "$"; + } + warning = "{{ if($PORT_sdram_dqm/width <= 0)('width of sdram_dqm must be greater than zero' ) }}"; + } + EDIT avs_nios_address_width + { + id = "avs_nios_address_width"; + editable = "0"; + title = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]:"; + tooltip = "avs_nios_address[((((bank_width + row_width) + column_width) - 1)) - (0) + 1]
direction: input
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_address/width = (int((((( ( $H/bank_width ) + ( $H/row_width ) ) + ( $H/column_width ) ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Address_Width = $PORT_avs_nios_address/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_address/width = "$"; + } + warning = "{{ if($PORT_avs_nios_address/width <= 0)('width of avs_nios_address must be greater than zero' ) }}"; + } + EDIT avs_nios_byteenable_width + { + id = "avs_nios_byteenable_width"; + editable = "0"; + title = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]:"; + tooltip = "avs_nios_byteenable[(((data_width / 8) - 1)) - (0) + 1]
direction: input
signal type: byteenable"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_byteenable/width = (int(((( ( $H/data_width ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_byteenable/width = "$"; + } + warning = "{{ if($PORT_avs_nios_byteenable/width <= 0)('width of avs_nios_byteenable must be greater than zero' ) }}"; + } + EDIT avs_nios_writedata_width + { + id = "avs_nios_writedata_width"; + editable = "0"; + title = "avs_nios_writedata[((data_width - 1)) - (0) + 1]:"; + tooltip = "avs_nios_writedata[((data_width - 1)) - (0) + 1]
direction: input
signal type: writedata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_writedata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_writedata/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_writedata/width = "$"; + } + warning = "{{ if($PORT_avs_nios_writedata/width <= 0)('width of avs_nios_writedata must be greater than zero' ) }}"; + } + EDIT avs_nios_readdata_width + { + id = "avs_nios_readdata_width"; + editable = "0"; + title = "avs_nios_readdata[((data_width - 1)) - (0) + 1]:"; + tooltip = "avs_nios_readdata[((data_width - 1)) - (0) + 1]
direction: output
signal type: readdata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avs_nios_readdata/width = (int((( ( $H/data_width ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_nios/Data_Width = 2 ^ int(log2($PORT_avs_nios_readdata/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avs_nios_readdata/width = "$"; + } + warning = "{{ if($PORT_avs_nios_readdata/width <= 0)('width of avs_nios_readdata must be greater than zero' ) }}"; + } + } + } + } + } + } + SOPC_Builder_Version = "5.10"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by CBDocument.getParameterContainer + # used only by Component Editor + HDL_PARAMETER data_width + { + parameter_name = "data_width"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER bank_width + { + parameter_name = "bank_width"; + type = "integer"; + default_value = "4"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER row_width + { + parameter_name = "row_width"; + type = "integer"; + default_value = "12"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER column_width + { + parameter_name = "column_width"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER clk_mhz + { + parameter_name = "clk_mhz"; + type = "integer"; + default_value = "120"; + editable = "1"; + tooltip = ""; + } + } + SW_FILES + { + } + built_on = "2006.09.25.10:24:12"; + CACHED_HDL_INFO + { + # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection + # used only by Component Builder + FILE sdram_ctrl.vhd + { + file_mod = "Mon Sep 18 18:08:50 EEST 2006"; + quartus_map_start = "Mon Sep 25 10:22:36 EEST 2006"; + quartus_map_finished = "Mon Sep 25 10:22:58 EEST 2006"; + #found 1 valid modules + WRAPPER sdram_ctrl + { + CLASS sdram_ctrl + { + CB_GENERATOR + { + HDL_FILES + { + FILE + { + use_in_simulation = "1"; + use_in_synthesis = "1"; + filepath = "H:/Work/Home_stuff/opencores/sdram_ctrl/src/sdram_ctrl.vhd"; + } + } + top_module_name = "sdram_ctrl"; + emit_system_h = "0"; + LIBRARIES + { + library = "ieee.std_logic_1164.all"; + library = "ieee.numeric_std.all"; + library = "altera_mf.altera_mf_components.all"; + library = "std.standard.all"; + } + } + MODULE_DEFAULTS global_signals + { + class = "sdram_ctrl"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE nios + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT avs_nios_chipselect + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "chipselect"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_address + { + width = "-1"; + width_expression = "((((bank_width + row_width) + column_width) - 1)) - (0) + 1"; + direction = "input"; + type = "address"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_byteenable + { + width = "-1"; + width_expression = "(((data_width / 8) - 1)) - (0) + 1"; + direction = "input"; + type = "byteenable"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_writedata + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "input"; + type = "writedata"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_write + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "write"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_read + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "read"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_waitrequest + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "waitrequest"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_readdata + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "output"; + type = "readdata"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT avs_nios_readdatavalid + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "readdatavalid"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT sdram_cke + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_ba + { + width = "-1"; + width_expression = "((bank_width - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_addr + { + width = "-1"; + width_expression = "((row_width - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_cs_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_ras_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_cas_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_we_n + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_dq + { + width = "-1"; + width_expression = "((data_width - 1)) - (0) + 1"; + direction = "inout"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT sdram_dqm + { + width = "-1"; + width_expression = "(((data_width / 8) - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + PORT reset + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "reset"; + is_shared = "0"; + vhdl_record_name = ""; + vhdl_record_type = ""; + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "sdram_ctrl"; + technology = "imported components"; + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by CBDocument.getParameterContainer + # used only by Component Editor + HDL_PARAMETER data_width + { + parameter_name = "data_width"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER bank_width + { + parameter_name = "bank_width"; + type = "integer"; + default_value = "4"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER row_width + { + parameter_name = "row_width"; + type = "integer"; + default_value = "12"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER column_width + { + parameter_name = "column_width"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER clk_mhz + { + parameter_name = "clk_mhz"; + type = "integer"; + default_value = "120"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + } + } + ASSOCIATED_FILES + { + Add_Program = "the_wizard_ui"; + Edit_Program = "the_wizard_ui"; + Generator_Program = "cb_generator.pl"; + } +} Index: sdram_ctrl/tags/V10/test_bench/sdram_ctrl_tb.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/sdram_ctrl_tb.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/sdram_ctrl_tb.vhd (revision 8) @@ -0,0 +1,169 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +entity sdram_ctrl_tb is +end sdram_ctrl_tb; + +architecture structure of sdram_ctrl_tb is + component pll + port ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + e0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ) ; + end component ; + component sdram_ctrl is + port( + signal clk : IN STD_LOGIC; + signal reset : IN STD_LOGIC; + + signal avs_nios_chipselect : IN STD_LOGIC; + signal avs_nios_address : IN STD_LOGIC_VECTOR (21 DOWNTO 0); + signal avs_nios_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + signal avs_nios_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + signal avs_nios_write : IN STD_LOGIC; + signal avs_nios_read : IN STD_LOGIC; + signal avs_nios_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + signal avs_nios_readdatavalid : OUT STD_LOGIC; + signal avs_nios_waitrequest : OUT STD_LOGIC; + + signal sdram_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + signal sdram_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + signal sdram_cas_n : OUT STD_LOGIC; + signal sdram_cke : OUT STD_LOGIC; + signal sdram_cs_n : OUT STD_LOGIC; + signal sdram_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); + signal sdram_dqm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + signal sdram_ras_n : OUT STD_LOGIC; + signal sdram_we_n : OUT STD_LOGIC + ); + end component; + + component mt48lc4m32b2 IS + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => 'Z'); + Addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + Clk : IN STD_LOGIC := '0'; + Cke : IN STD_LOGIC := '1'; + Cs_n : IN STD_LOGIC := '1'; + Ras_n : IN STD_LOGIC := '1'; + Cas_n : IN STD_LOGIC := '1'; + We_n : IN STD_LOGIC := '1'; + Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000" + ); + END component; + + component cpu_simulator IS + PORT(clk, reset: IN std_logic; + address : OUT std_logic_vector(21 downto 0):=(others=>'0'); + writedata : out std_logic_vector(31 downto 0):=(others=>'0'); + byteenable : out std_logic_vector(3 downto 0):=(others=>'0'); + write : out std_logic:='0'; + read : out std_logic:='0'; + readdata : in std_logic_vector(31 downto 0); + waitrequest : in std_logic; + readdatavalid : in std_logic + ); + END component; + + signal reset, clk_ok: std_logic; + signal run_nios_n : std_logic:='1'; + signal clk,i_clk: std_logic:='0'; + + signal SDRAM_CLK : std_logic; + signal SDRAM_CKE : std_logic; + signal SDRAM_NCS : std_logic; + signal SDRAM_NRAS : std_logic; + signal SDRAM_NCAS : std_logic; + signal SDRAM_NWE : std_logic; + signal SDRAM_ADDRESS : std_logic_vector(11 downto 0); + signal SDRAM_BANK : std_logic_vector(1 downto 0); + signal SDRAM_DQM : std_logic_vector(3 downto 0); + signal SDRAM_DATA : std_logic_vector(31 downto 0); + + signal address : std_logic_vector(21 downto 0); + signal writedata : std_logic_vector(31 downto 0):=(others=>'0'); + signal byteenable : std_logic_vector(3 downto 0):=(others=>'0'); + signal write : std_logic; + signal read : std_logic; + signal chipselect : std_logic:='1'; + signal readdata : std_logic_vector(31 downto 0); + signal waitrequest : std_logic; + signal readdatavalid : std_logic; + +begin + + reset<= not clk_ok; + run_nios_n<= reset after 140 us; + + UUT: sdram_ctrl + port map( + clk => i_clk, + reset => reset, + + avs_nios_chipselect => chipselect, + avs_nios_address => address, + avs_nios_byteenable => byteenable, + avs_nios_writedata => writedata, + avs_nios_write => write, + avs_nios_read => read, + avs_nios_readdata => readdata, + avs_nios_readdatavalid => readdatavalid, + avs_nios_waitrequest => waitrequest, + + sdram_addr => SDRAM_ADDRESS, + sdram_ba => SDRAM_BANK, + sdram_cas_n => SDRAM_NCAS, + sdram_cke => SDRAM_CKE, + sdram_cs_n => SDRAM_NCS, + sdram_dq => SDRAM_DATA, + sdram_dqm => SDRAM_DQM, + sdram_ras_n => SDRAM_NRAS, + sdram_we_n => SDRAM_NWE + ); + + sdram:mt48lc4m32b2 + PORT MAP( + Dq => SDRAM_DATA, + Addr => SDRAM_ADDRESS, + Ba => SDRAM_BANK, + Clk => SDRAM_CLK, + Cke => SDRAM_CKE, + Cs_n => SDRAM_NCS, + Ras_n => SDRAM_NRAS, + Cas_n => SDRAM_NCAS, + We_n => SDRAM_NWE, + Dqm => SDRAM_DQM + ); + + cpu: cpu_simulator + PORT MAP( + clk => i_clk, + reset => run_nios_n, + address => address, + writedata => writedata, + byteenable => byteenable, + write => write, + read => read, + readdata => readdata, + waitrequest => waitrequest, + readdatavalid => readdatavalid + ); + + U1 : pll + port map( + inclk0 => clk, + c0 => i_clk, + e0 => SDRAM_CLK, + locked =>clk_ok + ); + + clock_generator:process + begin + wait for 21 ns; + clk<= clk xor '1'; + end process; +end structure; Index: sdram_ctrl/tags/V10/test_bench/mt48lc4m32b2.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/mt48lc4m32b2.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/mt48lc4m32b2.vhd (revision 8) @@ -0,0 +1,1134 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: MT48LC4M32B2.VHD +-- Version: 2.0 +-- Date: January 24th, 2002 +-- Model: Behavioral +-- Simulator: Model Technology +-- +-- Dependencies: None +-- +-- Email: modelsupport@micron.com +-- Company: Micron Technology, Inc. +-- Part Number: MT48LC4M32A2 (1Mb x 32 x 4 Banks) +-- +-- Description: Micron 128Mb SDRAM +-- +-- Limitation: - Doesn't check for 4096-cycle refresh +-- +-- Note: - Set simulator resolution to "ps" accuracy +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 1998 Micron Semiconductor Products, Inc. +-- All rights researved +-- +-- Rev Author Date Changes +-- --- -------------------------- ------------------------------------- +-- 2.0 SH 01/24/2002 - Second Release +-- Micron Technology Inc. +-- +-------------------------------------------------------------------------- + +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.STD_LOGIC_UNSIGNED.ALL; + USE IEEE.STD_LOGIC_ARITH.ALL; + +ENTITY mt48lc4m32b2 IS + GENERIC ( + -- Timing Parameters for -75 (PC133) and CL = 3 + tAC : TIME := 5.4 ns; + tHZ : TIME := 5.4 ns; + tOH : TIME := 2.7 ns; + tMRD : INTEGER := 2; -- 2 Clk Cycles + tRAS : TIME := 44.0 ns; + tRC : TIME := 66.0 ns; + tRCD : TIME := 20.0 ns; + tRFC : TIME := 66.0 ns; + tRP : TIME := 20.0 ns; + tRRD : TIME := 15.0 ns; + tWRa : TIME := 7.5 ns; -- Auto precharge + tWRm : TIME := 15.0 ns; -- Manual Precharge + + tAH : TIME := 0.8 ns; + tAS : TIME := 1.5 ns; + tCH : TIME := 2.5 ns; + tCL : TIME := 2.5 ns; + tCK : TIME := 7.5 ns; + tDH : TIME := 0.8 ns; + tDS : TIME := 1.5 ns; + tCKH : TIME := 0.8 ns; + tCKS : TIME := 1.5 ns; + tCMH : TIME := 0.8 ns; + tCMS : TIME := 1.5 ns; + + addr_bits : INTEGER := 12; + data_bits : INTEGER := 32; + col_bits : INTEGER := 8 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + Clk : IN STD_LOGIC := '0'; + Cke : IN STD_LOGIC := '1'; + Cs_n : IN STD_LOGIC := '1'; + Ras_n : IN STD_LOGIC := '1'; + Cas_n : IN STD_LOGIC := '1'; + We_n : IN STD_LOGIC := '1'; + Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000" + ); +END mt48lc4m32b2; + +ARCHITECTURE behave OF mt48lc4m32b2 IS + TYPE State IS (BST, NOP, PRECH, READ, WRITE); + TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER; + TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME; + TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; + TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF STD_LOGIC_VECTOR (Col_bits - 1 DOWNTO 0); + TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State; + SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Active_enable, Aref_enable, Burst_term : STD_LOGIC := '0'; + SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; + SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : STD_LOGIC := '0'; + SIGNAL Cas_latency_1, Cas_latency_2, Cas_latency_3 : STD_LOGIC := '0'; + SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; + SIGNAL Write_burst_mode : STD_LOGIC := '0'; + SIGNAL Sys_clk, CkeZ : STD_LOGIC := '0'; + +BEGIN + -- Strip the strength + Cs_in <= To_X01 (Cs_n); + Ras_in <= To_X01 (Ras_n); + Cas_in <= To_X01 (Cas_n); + We_in <= To_X01 (We_n); + + -- Commands Decode + Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; + Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; + Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); + Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in); + Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); + Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; + Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); + + -- Burst Length Decode + Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0)); + Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); + Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); + Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + + -- CAS Latency Decode + Cas_latency_1 <= NOT(Mode_reg(6)) AND NOT(Mode_reg(5)) AND Mode_reg(4); + Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); + + -- Write Burst Mode + Write_burst_mode <= Mode_reg(9); + + -- System Clock + int_clk : PROCESS (Clk) + BEGIN + IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN + CkeZ <= Cke; + END IF; + Sys_clk <= CkeZ AND Clk; + END PROCESS; + + state_register : PROCESS + TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + TYPE ram_pntr IS ACCESS ram_type; + TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr; + VARIABLE Bank0 : ram_stor; + VARIABLE Bank1 : ram_stor; + VARIABLE Bank2 : ram_stor; + VARIABLE Bank3 : ram_stor; + VARIABLE Row_index, Col_index : INTEGER := 0; + VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0'); + + VARIABLE Col_addr : Array4xCBV; + VARIABLE Bank_addr : Array4x2BV; + VARIABLE Dqm_reg0, Dqm_reg1 : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"; + + VARIABLE Bank, Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col_brst : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Row : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Burst_counter : INTEGER := 0; + + VARIABLE Command : Array_state; + VARIABLE Bank_precharge : Array4x2BV; + VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE RW_interrupt_counter : Array4xI := (0 & 0 & 0 & 0); + VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0); + + VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; + VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; + VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; + + -- Timing Check + VARIABLE MRD_chk : INTEGER := 0; + VARIABLE RFC_chk : TIME := 0 ns; + VARIABLE RRD_chk : TIME := 0 ns; + VARIABLE WR_chkm : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns); + VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; + VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; + VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; + VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; + + -- Initialize empty rows + PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR (1 DOWNTO 0); Row_index : INTEGER) IS + VARIABLE i, j : INTEGER := 0; + BEGIN + IF Bank = "00" THEN + IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty + Bank0 (Row_index) := NEW ram_type; -- Open new row for access + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank0 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "01" THEN + IF Bank1 (Row_index) = NULL THEN + Bank1 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank1 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "10" THEN + IF Bank2 (Row_index) = NULL THEN + Bank2 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank2 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "11" THEN + IF Bank3 (Row_index) = NULL THEN + Bank3 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank3 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + END IF; + END; + + -- Burst Counter + PROCEDURE Burst_decode IS + VARIABLE Col_int : INTEGER := 0; + VARIABLE Col_vec, Col_temp : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + -- Advance Burst Counter + Burst_counter := Burst_counter + 1; + + -- Burst Type + IF Mode_reg (3) = '0' THEN + Col_int := conv_integer(Col) + 1; + Col_temp := CONV_STD_LOGIC_VECTOR(Col_int, col_bits); + ELSIF Mode_reg (3) = '1' THEN + Col_vec := CONV_STD_LOGIC_VECTOR(Burst_counter, col_bits); + Col_temp (2) := Col_vec (2) XOR Col_brst (2); + Col_temp (1) := Col_vec (1) XOR Col_brst (1); + Col_temp (0) := Col_vec (0) XOR Col_brst (0); + END IF; + + -- Burst Length + IF Burst_length_2 = '1' THEN + Col (0) := Col_temp (0); + ELSIF Burst_length_4 = '1' THEN + Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0); + ELSIF Burst_length_8 = '1' THEN + Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0); + ELSE + Col := Col_temp; + END IF; + + -- Burst Read Single Write + IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Data counter + IF Burst_length_1 = '1' THEN + IF Burst_counter >= 1 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_2 = '1' THEN + IF Burst_counter >= 2 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_4 = '1' THEN + IF Burst_counter >= 4 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_8 = '1' THEN + IF Burst_counter >= 8 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + END IF; + END; + + BEGIN + WAIT ON Sys_clk; + IF Sys_clk'event AND Sys_clk = '1' THEN + -- Internal Pipeline + Command(0) := Command(1); + Command(1) := Command(2); + Command(2) := Command(3); + Command(3) := NOP; + + Col_addr(0) := Col_addr(1); + Col_addr(1) := Col_addr(2); + Col_addr(2) := Col_addr(3); + Col_addr(3) := (OTHERS => '0'); + + Bank_addr(0) := Bank_addr(1); + Bank_addr(1) := Bank_addr(2); + Bank_addr(2) := Bank_addr(3); + Bank_addr(3) := "00"; + + Bank_precharge(0) := Bank_precharge(1); + Bank_precharge(1) := Bank_precharge(2); + Bank_precharge(2) := Bank_precharge(3); + Bank_precharge(3) := "00"; + + A10_precharge(0) := A10_precharge(1); + A10_precharge(1) := A10_precharge(2); + A10_precharge(2) := A10_precharge(3); + A10_precharge(3) := '0'; + + -- Dqm pipeline for Read + Dqm_reg0 := Dqm_reg1; + Dqm_reg1 := Dqm; + + -- Read or Write with Auto Precharge Counter + IF Auto_precharge (0) = '1' THEN + Count_precharge (0) := Count_precharge (0) + 1; + END IF; + IF Auto_precharge (1) = '1' THEN + Count_precharge (1) := Count_precharge (1) + 1; + END IF; + IF Auto_precharge (2) = '1' THEN + Count_precharge (2) := Count_precharge (2) + 1; + END IF; + IF Auto_precharge (3) = '1' THEN + Count_precharge (3) := Count_precharge (3) + 1; + END IF; + + -- Read or Write Interrupt Counter + IF RW_interrupt_write (0) = '1' THEN + RW_interrupt_counter (0) := RW_interrupt_counter (0) + 1; + END IF; + IF RW_interrupt_write (1) = '1' THEN + RW_interrupt_counter (1) := RW_interrupt_counter (1) + 1; + END IF; + IF RW_interrupt_write (2) = '1' THEN + RW_interrupt_counter (2) := RW_interrupt_counter (2) + 1; + END IF; + IF RW_interrupt_write (3) = '1' THEN + RW_interrupt_counter (3) := RW_interrupt_counter (3) + 1; + END IF; + + -- tMRD Counter + MRD_chk := MRD_chk + 1; + + -- Auto Refresh + IF Aref_enable = '1' THEN + -- Auto Refresh to Auto Refresh + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT ((NOW - RP_chk0 >= tRP) OR (NOW - RP_chk1 >= tRP) OR + (NOW - RP_chk2 >= tRP) OR (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT (Pc_b0 ='1' AND Pc_b1 = '1' AND Pc_b2 ='1' AND Pc_b3 = '1') + REPORT "All banks must be Precharge before Auto Refresh" + SEVERITY WARNING; + + -- Load Mode Register to Auto Refresh + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Auto Refresh" + SEVERITY WARNING; + + -- Record current tRFC time + RFC_chk := NOW; + END IF; + + -- Load Mode Register + IF Mode_reg_enable = '1' THEN + -- Register Mode + Mode_reg <= Addr; + + -- Precharge to Load Mode Register + ASSERT (Pc_b0 ='1' AND Pc_b1 = '1' AND Pc_b2 ='1' AND Pc_b3 = '1') + REPORT "All banks must be Precharge before Load Mode Register" + SEVERITY WARNING; + + -- Precharge to Load Mode Register + ASSERT ((NOW - RP_chk0 >= tRP) OR (NOW - RP_chk1 >= tRP) OR + (NOW - RP_chk2 >= tRP) OR (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Load Mode Register" + SEVERITY WARNING; + + -- Auto Refresh to Load Mode Register + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Load Mode Register" + SEVERITY WARNING; + + -- Load Mode Register to Load Mode Register + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Load Mode Register" + SEVERITY WARNING; + + -- Record current tMRD time + MRD_chk := 0; + END IF; + + -- Active Block (Latch Bank and Row Address) + IF Active_enable = '1' THEN + -- Activate an OPEN bank can corrupt data + ASSERT ((Ba = "00" AND Act_b0 = '0') OR (Ba = "01" AND Act_b1 = '0') OR + (Ba = "10" AND Act_b2 = '0') OR (Ba = "11" AND Act_b3 = '0')) + REPORT "Bank is already activated - data can be corrupted" + SEVERITY WARNING; + + -- Activate Bank 0 + IF Ba = "00" AND Pc_b0 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk0 >= tRC) + REPORT "tRC violation during Activate Bank 0" + SEVERITY WARNING; + + -- Precharge to Activate + ASSERT (NOW - RP_chk0 >= tRP) + REPORT "tRP violation during Activate Bank 0" + SEVERITY WARNING; + + -- Record variables for checking violation + Act_b0 := '1'; + Pc_b0 := '0'; + B0_row_addr := Addr; + RAS_chk0 := NOW; + RC_chk0 := NOW; + RCD_chk0 := NOW; + END IF; + + -- Activate Bank 1 + IF Ba = "01" AND Pc_b1 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk1 >= tRC) + REPORT "tRC violation during Activate Bank 1" + SEVERITY WARNING; + + -- Precharge to Activate + ASSERT (NOW - RP_chk1 >= tRP) + REPORT "tRP violation during Activate Bank 1" + SEVERITY WARNING; + + -- Record variables for checking violation + Act_b1 := '1'; + Pc_b1 := '0'; + B1_row_addr := Addr; + RAS_chk1 := NOW; + RC_chk1 := NOW; + RCD_chk1 := NOW; + END IF; + + -- Activate Bank 2 + IF Ba = "10" AND Pc_b2 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk2 >= tRC) + REPORT "tRC violation during Activate Bank 2" + SEVERITY WARNING; + + -- Precharge to Activate + ASSERT (NOW - RP_chk2 >= tRP) + REPORT "tRP violation during Activate Bank 2" + SEVERITY WARNING; + + -- Record variables for checking violation + Act_b2 := '1'; + Pc_b2 := '0'; + B2_row_addr := Addr; + RAS_chk2 := NOW; + RC_chk2 := NOW; + RCD_chk2 := NOW; + END IF; + + -- Activate Bank 3 + IF Ba = "11" AND Pc_b3 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk3 >= tRC) + REPORT "tRC violation during Activate Bank 3" + SEVERITY WARNING; + + -- Precharge to Activate + ASSERT (NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Activate Bank 3" + SEVERITY WARNING; + + -- Record variables for checking violation + Act_b3 := '1'; + Pc_b3 := '0'; + B3_row_addr := Addr; + RAS_chk3 := NOW; + RC_chk3 := NOW; + RCD_chk3 := NOW; + END IF; + + -- Activate to Activate (different bank) + IF (Prev_bank /= Ba) THEN + ASSERT (NOW - RRD_chk >= tRRD) + REPORT "tRRD violation during Activate" + SEVERITY WARNING; + END IF; + + -- Auto Refresh to Activate + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Activate" + SEVERITY WARNING; + + -- Load Mode Register to Activate + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Activate" + SEVERITY WARNING; + + -- Record variable for checking violation + RRD_chk := NOW; + Prev_Bank := Ba; + END IF; + + -- Precharge Block + IF Prech_enable = '1' THEN + -- Load Mode Register to Precharge + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Precharge" + SEVERITY WARNING; + + -- Precharge Bank 0 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN + Act_b0 := '0'; + Pc_b0 := '1'; + RP_chk0 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk0 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chkm(0) >= tWRm) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 1 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN + Act_b1 := '0'; + Pc_b1 := '1'; + RP_chk1 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk1 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chkm(1) >= tWRm) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 2 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN + Act_b2 := '0'; + Pc_b2 := '1'; + RP_chk2 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk2 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chkm(2) >= tWRm) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 3 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN + Act_b3 := '0'; + Pc_b3 := '1'; + RP_chk3 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk3 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chkm(3) >= tWRm) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Terminate a Write Immediately (if same bank or all banks) + IF (Data_in_enable = '1' AND (Bank = Ba OR Addr(10) = '1')) THEN + Data_in_enable := '0'; + END IF; + + -- Precharge Command Pipeline for READ + IF CAS_latency_3 = '1' THEN + Command(2) := PRECH; + Bank_precharge(2) := Ba; + A10_precharge(2) := Addr(10); + ELSIF CAS_latency_2 = '1' THEN + Command(1) := PRECH; + Bank_precharge(1) := Ba; + A10_precharge(1) := Addr(10); + END IF; + END IF; + + -- Burst Terminate + IF Burst_term = '1' THEN + -- Terminate a Write immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Terminate a Read depend on CAS Latency + IF CAS_latency_3 = '1' THEN + Command(2) := BST; + ELSIF CAS_latency_2 = '1' THEN + Command(1) := BST; + END IF; + END IF; + + -- Read Command + IF Read_enable = '1' THEN + -- Activate to Read + ASSERT ((Ba="00" AND Act_b0='1') OR (Ba="01" AND Act_b1='1') OR + (Ba="10" AND Act_b2='1') OR (Ba="11" AND Act_b3='1')) + REPORT "Bank is not Activated for Read" + SEVERITY WARNING; + + -- Activate to Read + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Read" + SEVERITY WARNING; + + -- CAS Latency Pipeline + IF Cas_latency_3 = '1' THEN + Command(2) := READ; + Col_addr (2) := Addr(col_bits - 1 DOWNTO 0); + Bank_addr (2) := Ba; + ELSIF Cas_latency_2 = '1' THEN + Command(1) := READ; + Col_addr (1) := Addr(col_bits - 1 DOWNTO 0); + Bank_addr (1) := Ba; + ELSIF Cas_latency_1 = '1' THEN + Command(0) := READ; + Col_addr (0) := Addr(col_bits - 1 DOWNTO 0); + Bank_addr (0) := Ba; + END IF; + + -- Read Terminate Write Immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + -- Interrupt a Write with Auto Precharge + IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_write(CONV_INTEGER(RW_Interrupt_Bank)) := '1'; + RW_interrupt_counter (CONV_INTEGER(RW_Interrupt_Bank)) := 0; + ASSERT FALSE REPORT "Read interrupt a Write with Auto Precharge." SEVERITY NOTE; + END IF; + END IF; + + -- Read Terminate Read after CL - 1 + IF (Data_out_enable = '1' AND ((Cas_latency_2 = '1' AND ((Burst_length_2 = '1' AND Burst_counter < 1) OR + (Burst_length_4 = '1' AND Burst_counter < 3) OR + (Burst_length_8 = '1' AND Burst_counter < 7))) OR + (Cas_latency_3 = '1' AND ((Burst_length_4 = '1' AND Burst_counter < 2) OR + (Burst_length_8 = '1' AND Burst_counter < 6))))) THEN + -- Interrupt a Read with Auto Precharge + IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_read(CONV_INTEGER(RW_Interrupt_Bank)) := '1'; + ASSERT FALSE REPORT "Read interrupt a Read with Auto Precharge." SEVERITY NOTE; + END IF; + END IF; + + -- Auto Precharge + IF Addr(10) = '1' THEN + Auto_precharge (CONV_INTEGER(Ba)) := '1'; + Count_precharge (CONV_INTEGER(Ba)) := 0; + RW_Interrupt_Bank := Ba; + Read_precharge (CONV_INTEGER(Ba)) := '1'; + END IF; + END IF; + + -- Write Command + IF Write_enable = '1' THEN + -- Activate to Write + ASSERT ((Ba="00" AND Act_b0='1') OR (Ba="01" AND Act_b1='1') OR + (Ba="10" AND Act_b2='1') OR (Ba="11" AND Act_b3='1')) + REPORT "Bank is not Activated for Write" + SEVERITY WARNING; + + -- Activate to Write + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Write" + SEVERITY WARNING; + + -- Latch write command, bank, column + Command(0) := WRITE; + Col_addr (0) := Addr(col_bits - 1 DOWNTO 0); + Bank_addr (0) := Ba; + + -- Write Terminate Write Immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + + -- Interrupt a Write with Auto Precharge + IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_write(CONV_INTEGER(RW_Interrupt_Bank)) := '1'; + RW_interrupt_counter (CONV_INTEGER(RW_Interrupt_Bank)) := 0; + ASSERT FALSE REPORT "Write interrupt a Write with Auto Precharge." SEVERITY NOTE; + END IF; + END IF; + + -- Write Terminate Read Immediately + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + + -- Interrupt a Read with Auto Precharge + IF Auto_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(CONV_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_read(CONV_INTEGER(RW_Interrupt_Bank)) := '1'; + ASSERT FALSE REPORT "Write interrupt a Read with Auto Precharge." SEVERITY NOTE; + END IF; + END IF; + + -- Auto Precharge + IF Addr(10) = '1' THEN + Auto_precharge (CONV_INTEGER(Ba)) := '1'; + Count_precharge (CONV_INTEGER(Ba)) := 0; + RW_Interrupt_Bank := Ba; + Write_precharge (CONV_INTEGER(Ba)) := '1'; + END IF; + END IF; + + -- Write with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet tRAS requirement + -- and 2. tWR cycle(s) after last valid data + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + -- + -- Note: Model is starting the internal precharge 1 cycle after they meet all the + -- requirement but tRP will be compensate for the time after the 1 cycle. + IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR + (RW_interrupt_write(0) = '1' AND RW_interrupt_counter(0) >= 1)) THEN + Auto_precharge(0) := '0'; + Write_precharge(0) := '0'; + RW_interrupt_write(0) := '0'; + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW + tWRa; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR + (RW_interrupt_write(1) = '1' AND RW_interrupt_counter(1) >= 1)) THEN + Auto_precharge(1) := '0'; + Write_precharge(1) := '0'; + RW_interrupt_write(1) := '0'; + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW + tWRa; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR + (RW_interrupt_write(2) = '1' AND RW_interrupt_counter(2) >= 1)) THEN + Auto_precharge(2) := '0'; + Write_precharge(2) := '0'; + RW_interrupt_write(2) := '0'; + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW + tWRa; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR + (RW_interrupt_write(0) = '1' AND RW_interrupt_counter(3) >= 1)) THEN + Auto_precharge(3) := '0'; + Write_precharge(3) := '0'; + RW_interrupt_write(3) := '0'; + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW + tWRa; + END IF; + END IF; + + -- Read with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet minimum tRAS requirement + -- and 2. CL - 1 cycle(s) before last valid data + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR + (RW_interrupt_read(0) = '1')) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Auto_precharge(0) := '0'; + Read_precharge(0) := '0'; + RW_interrupt_read(0) := '0'; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR + (RW_interrupt_read(1) = '1')) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Auto_precharge(1) := '0'; + Read_precharge(1) := '0'; + RW_interrupt_read(1) := '0'; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR + (RW_interrupt_read(2) = '1')) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Auto_precharge(2) := '0'; + Read_precharge(2) := '0'; + RW_interrupt_read(2) := '0'; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR + (RW_interrupt_read(3) = '1')) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Auto_precharge(3) := '0'; + Read_precharge(3) := '0'; + RW_interrupt_read(3) := '0'; + END IF; + END IF; + + -- Internal Precharge or Bst + IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks + IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + + IF Data_out_enable = '0' THEN + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH; + END IF; + + -- Detect Read or Write Command + IF Command(0) = READ THEN + Bank := Bank_addr (0); + Col := Col_addr (0); + Col_brst := Col_addr (0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '0'; + Data_out_enable := '1'; + ELSIF Command(0) = WRITE THEN + Bank := Bank_addr(0); + Col := Col_addr(0); + Col_brst := Col_addr(0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '1'; + Data_out_enable := '0'; + END IF; + + -- DQ (Driver / Receiver) + Row_index := CONV_INTEGER (Row); + Col_index := CONV_INTEGER (Col); + + IF Data_in_enable = '1' THEN + IF Dqm /= "1111" THEN + -- Initialize Memory + Init_mem (Bank, Row_index); + + -- Array Buffer + CASE Bank IS + WHEN "00" => Dq_temp := Bank0 (Row_index) (Col_index); + WHEN "01" => Dq_temp := Bank1 (Row_index) (Col_index); + WHEN "10" => Dq_temp := Bank2 (Row_index) (Col_index); + WHEN OTHERS => Dq_temp := Bank3 (Row_index) (Col_index); + END CASE; + + -- Dqm Operation + IF Dqm (0) = '0' THEN + Dq_temp ( 7 DOWNTO 0) := Dq ( 7 DOWNTO 0); + END IF; + IF Dqm (1) = '0' THEN + Dq_temp (15 DOWNTO 8) := Dq (15 DOWNTO 8); + END IF; + IF Dqm (2) = '0' THEN + Dq_temp (23 DOWNTO 16) := Dq (23 DOWNTO 16); + END IF; + IF Dqm (3) = '0' THEN + Dq_temp (31 DOWNTO 24) := Dq (31 DOWNTO 24); + END IF; + + -- Write to Memory + CASE Bank IS + WHEN "00" => Bank0 (Row_index) (Col_index) := Dq_temp; + WHEN "01" => Bank1 (Row_index) (Col_index) := Dq_temp; + WHEN "10" => Bank2 (Row_index) (Col_index) := Dq_temp; + WHEN OTHERS => Bank3 (Row_index) (Col_index) := Dq_temp; + END CASE; + + -- Record tWR for manual precharge + WR_chkm(CONV_INTEGER(Bank)) := NOW; + END IF; + + -- Advance Burst Counter + Burst_decode; + + ELSIF Data_out_enable = '1' THEN + IF Dqm_reg0 /= "1111" THEN + -- Initialize Memory + Init_mem (Bank, Row_index); + + -- Array Buffer + CASE Bank IS + WHEN "00" => Dq_temp := Bank0 (Row_index) (Col_index); + WHEN "01" => Dq_temp := Bank1 (Row_index) (Col_index); + WHEN "10" => Dq_temp := Bank2 (Row_index) (Col_index); + WHEN OTHERS => Dq_temp := Bank3 (Row_index) (Col_index); + END CASE; + + -- Dqm Operation + IF Dqm_reg0 (0) = '1' THEN + Dq_temp ( 7 DOWNTO 0) := (OTHERS => 'Z'); + END IF; + IF Dqm_reg0 (1) = '1' THEN + Dq_temp (15 DOWNTO 8) := (OTHERS => 'Z'); + END IF; + IF Dqm_reg0 (2) = '1' THEN + Dq_temp (23 DOWNTO 16) := (OTHERS => 'Z'); + END IF; + IF Dqm_reg0 (3) = '1' THEN + Dq_temp (31 DOWNTO 24) := (OTHERS => 'Z'); + END IF; + + -- Output + Dq <= TRANSPORT Dq_temp AFTER tAC; + ELSE + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ; + END IF; + + -- Advance Burst Counter + Burst_decode; + END IF; + END IF; + + END PROCESS; + + -- Clock timing checks + Clock_check : PROCESS + VARIABLE Clk_low, Clk_high : TIME := 0 ns; + BEGIN + WAIT ON Clk; + IF (Clk = '1' AND NOW >= 10 ns) THEN + ASSERT (NOW - Clk_low >= tCL) + REPORT "tCL violation" + SEVERITY WARNING; + ASSERT (NOW - Clk_high >= tCK) + REPORT "tCK violation" + SEVERITY WARNING; + Clk_high := NOW; + ELSIF (Clk = '0' AND NOW /= 0 ns) THEN + ASSERT (NOW - Clk_high >= tCH) + REPORT "tCH violation" + SEVERITY WARNING; + Clk_low := NOW; + END IF; + END PROCESS; + + -- Setup timing checks + Setup_check : PROCESS + BEGIN + WAIT ON Clk; + IF Clk = '1' THEN + ASSERT(Cke'LAST_EVENT >= tCKS) + REPORT "CKE Setup time violation -- tCKS" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tCMS) + REPORT "CS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tCMS) + REPORT "CAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tCMS) + REPORT "RAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tCMS) + REPORT "WE# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT >= tCMS) + REPORT "Dqm Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tAS) + REPORT "ADDR Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tAS) + REPORT "BA Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Dq'LAST_EVENT >= tDS) + REPORT "Dq Setup time violation -- tDS" + SEVERITY WARNING; + END IF; + END PROCESS; + + -- Hold timing checks + Hold_check : PROCESS + BEGIN + WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH); + IF Clk'DELAYED (tCKH) = '1' THEN + ASSERT(Cke'LAST_EVENT > tCKH) + REPORT "CKE Hold time violation -- tCKH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tCMH) = '1' THEN + ASSERT(Cs_n'LAST_EVENT > tCMH) + REPORT "CS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT > tCMH) + REPORT "CAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT > tCMH) + REPORT "RAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT > tCMH) + REPORT "WE# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT > tCMH) + REPORT "Dqm Hold time violation -- tCMH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tAH) = '1' THEN + ASSERT(Addr'LAST_EVENT > tAH) + REPORT "ADDR Hold time violation -- tAH" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT > tAH) + REPORT "BA Hold time violation -- tAH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tDH) = '1' THEN + ASSERT(Dq'LAST_EVENT > tDH) + REPORT "Dq Hold time violation -- tDH" + SEVERITY WARNING; + END IF; + END PROCESS; + +END behave; Index: sdram_ctrl/tags/V10/test_bench/cpu_simulator.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/cpu_simulator.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/cpu_simulator.vhd (revision 8) @@ -0,0 +1,72 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY cpu_simulator IS + PORT(clk, reset: in std_logic; + + address : out std_logic_vector(21 downto 0); + writedata : out std_logic_vector(31 downto 0); + byteenable : out std_logic_vector(3 downto 0); + write : out std_logic; + read : out std_logic; + readdata : in std_logic_vector(31 downto 0); + waitrequest : in std_logic; + readdatavalid : in std_logic + ); +END cpu_simulator; + +ARCHITECTURE behaviour OF cpu_simulator IS + signal counter: unsigned(3 downto 0); + type vector is + record + address: integer; + writedata: integer; + byteenable: std_logic_vector(3 downto 0); + write: std_logic; + read: std_logic; + end record; + type script is array(0 to (2**counter'length)-1) of vector; + signal wave_form: script:=( + (0,0,"1111",'1','0'), + (1,1,"1111",'1','0'), + (2,2,"1111",'1','0'), + (3,3,"1111",'1','0'), + (1024,1024,"1111",'0','1'), + (1025,1025,"1111",'0','1'), + (1026,1026,"1111",'0','1'), + (1027,1027,"1111",'0','1'), + (1024,1024,"1111",'1','0'), + (1025,1025,"1111",'1','0'), + (1026,1026,"1111",'1','0'), + (1027,1027,"1111",'1','0'), + (0,0,"1111",'0','1'), + (1,1,"1111",'0','1'), + (2,2,"1111",'0','1'), + (3,3,"1111",'0','1') + ); +BEGIN + process(clk,reset) + begin + if reset='1' + then + counter<=(others=>'0'); + address<=(others=>'0'); + writedata<=(others=>'0'); + byteenable<=(others=>'0'); + write<='0'; + read<='0'; + elsif rising_edge(clk) + then + if waitrequest='0' + then + counter<=counter+1; + address<=std_logic_vector(to_unsigned(wave_form(to_integer(counter)).address,address'length)); + writedata<=std_logic_vector(to_unsigned(wave_form(to_integer(counter)).writedata,writedata'length)); + byteenable<=wave_form(to_integer(counter)).byteenable; + write<=wave_form(to_integer(counter)).write; + read<=wave_form(to_integer(counter)).read; + end if; + end if; + end process; +END behaviour; \ No newline at end of file Index: sdram_ctrl/tags/V10/test_bench/pll.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/pll.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/pll.vhd (revision 8) @@ -0,0 +1,256 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 5.1 Build 213 01/19/2006 SP 1 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + e0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + extclk0_divide_by : NATURAL; + extclk0_duty_cycle : NATURAL; + extclk0_multiply_by : NATURAL; + extclk0_phase_shift : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + extclk : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire4 <= sub_wire3(0); + e0 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => 2, + clk0_duty_cycle => 50, + clk0_multiply_by => 11, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + extclk0_divide_by => 2, + extclk0_duty_cycle => 50, + extclk0_multiply_by => 11, + extclk0_phase_shift => "5682", + inclk0_input_frequency => 41666, + intended_device_family => "Cyclone", + invalid_lock_multiplier => 5, + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + valid_lock_multiplier => 1 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2, + extclk => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "504.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "deg" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "132.000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK6 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK6 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA6 STRING "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: EXTCLK0_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: EXTCLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: EXTCLK0_MULTIPLY_BY NUMERIC "11" +-- Retrieval info: CONSTANT: EXTCLK0_PHASE_SHIFT STRING "5682" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +-- Retrieval info: USED_PORT: e0 0 0 0 0 OUTPUT VCC "e0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: e0 0 0 0 0 @extclk 0 0 1 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE Index: sdram_ctrl/tags/V10/test_bench/old/nios.dat =================================================================== --- sdram_ctrl/tags/V10/test_bench/old/nios.dat (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/old/nios.dat (revision 8) @@ -0,0 +1 @@ + ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ ÿÿÿ \ No newline at end of file Index: sdram_ctrl/tags/V10/test_bench/old/Hello_LED_sdram_0.dat =================================================================== --- sdram_ctrl/tags/V10/test_bench/old/Hello_LED_sdram_0.dat (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/old/Hello_LED_sdram_0.dat (revision 8) @@ -0,0 +1,49 @@ +@00000000 00400034 +@00000001 08400804 +@00000002 0800683A +@00000003 00000000 +@00000004 00000000 +@00000005 00000000 +@00000006 00000000 +@00000007 00000000 +@00000008 06C04034 +@00000009 DEC00004 +@0000000A 06800074 +@0000000B D6A03104 +@0000000C 00000340 +@0000000D DEFFFD04 +@0000000E DF000215 +@0000000F D839883A +@00000010 00800084 +@00000011 E0800005 +@00000012 E0000045 +@00000013 E0800003 +@00000014 1080204C +@00000015 1005003A +@00000016 1000031E +@00000017 E0800043 +@00000018 1080005C +@00000019 E0800045 +@0000001A E0800043 +@0000001B 1005003A +@0000001C 1000041E +@0000001D E0800003 +@0000001E 1004D07A +@0000001F E0800005 +@00000020 00000306 +@00000021 E0800003 +@00000022 1085883A +@00000023 E0800005 +@00000024 00C04034 +@00000025 18C21004 +@00000026 E0800003 +@00000027 18800035 +@00000028 E0000115 +@00000029 E0C00117 +@0000002A 008000F4 +@0000002B 10834FC4 +@0000002C 10FFE616 +@0000002D E0800117 +@0000002E 10800044 +@0000002F E0800115 +@00000030 003FF806 Index: sdram_ctrl/tags/V10/test_bench/old/cpu_simulator_file_based.vhd =================================================================== --- sdram_ctrl/tags/V10/test_bench/old/cpu_simulator_file_based.vhd (nonexistent) +++ sdram_ctrl/tags/V10/test_bench/old/cpu_simulator_file_based.vhd (revision 8) @@ -0,0 +1,79 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY cpu_simulator IS + PORT(clk, reset: in std_logic; + + address : out std_logic_vector(21 downto 0); + writedata : out std_logic_vector(31 downto 0); + byteenable : out std_logic_vector(3 downto 0); + write : out std_logic; + read : out std_logic; + readdata : in std_logic_vector(31 downto 0); + waitrequest : in std_logic; + readdatavalid : in std_logic + ); +END cpu_simulator; + +ARCHITECTURE behaviour OF cpu_simulator IS + signal address: std_logic_vector(21 downto 0); + signal writedata: std_logic_vector(31 downto 0); + signal byteenable: std_logic_vector(3 downto 0); + signal write: std_logic; + signal read: std_logic; + +BEGIN + process(clk,reset) + variable service: std_logic_vector(7 downto 0); + variable b0,b1,b2,b3,b4,b5,b6,b7: BYTE; + begin + if reset='1' + then + file_close(NIOS); + file_open(NIOS, FILES_PATH&"nios.dat", READ_MODE); + elsif rising_edge(clk) + then + if waitrequest='0' + then + if Endfile(NIOS) + then + file_close(NIOS); + file_open(NIOS, FILES_PATH&"nios.dat", READ_MODE); + else + Read(NIOS,b0); + Read(NIOS,b1); + Read(NIOS,b2); + Read(NIOS,b3); + Read(NIOS,b4); + Read(NIOS,b5); + Read(NIOS,b6); + Read(NIOS,b7); + service:=char2std_logic_vector(b0); + address<=service(5 downto 0)&char2std_logic_vector(b1)&char2std_logic_vector(b2); + writedata<=char2std_logic_vector(b3)&char2std_logic_vector(b4)&char2std_logic_vector(b5)&char2std_logic_vector(b6); + service:=char2std_logic_vector(b7); + byteenable<=not service(7 downto 4); + write<=service(3); + read<=service(2); + end if; + end if; + end if; + end process; + + process(clk,reset) + begin + if reset='1' + then + readed<=(others=>'0'); + new_data<='0'; + elsif rising_edge(clk) + then + new_data<=readdatavalid; + if readdatavalid='1' + then + readed<=readdata; + end if; + end if; + end process; +END behaviour; \ No newline at end of file Index: sdram_ctrl/tags/V10/test_bench/old/Count_Binary_sdram_0.dat =================================================================== --- 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sdram_ctrl/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##