OpenCores
URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

Subversion Repositories soc_maker

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    from Rev 7 to Rev 8
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Rev 7 → Rev 8

/soc_maker/trunk/lib/soc_maker/parameter.rb
61,7 → 61,8
attr_accessor :visible
attr_accessor :editable
attr_accessor :description
attr_accessor :choice
 
def initialize( type, options = {} )
init_with( { 'type' => type }.merge( options ) )
end
90,7 → 91,7
@visible = coder[ 'visible' ] || true
@editable = coder[ 'editable' ] || false
@description = coder[ 'description' ] || ''
@choice = coder[ 'choice' ] || []
end
 
102,7 → 103,8
o.max == self.max &&
o.visible == self.visible &&
o.editable == self.editable &&
o.description == self.description
o.description == self.description &&
o.choice == self.choice
end
 
 
/soc_maker/trunk/lib/soc_maker/hdl_coder.rb
135,7 → 135,7
def entity_port_str( core )
port_string = ""
 
core.ports do |port_name, port_dir, port_len, is_last |
core.ports do |port_name, port_dir, port_len, port_default, is_last |
# The string we are add in every iteration looks for example like
# myportname1 : out std_logic_vector( 6-1 downto 0 )
144,7 → 144,6
#
port_string << port_name.to_s << " : "
 
puts port_name.to_s + ": dir: " + port_dir.to_s + ", len: " + port_len.to_s
 
 
# port direction
186,7 → 185,7
end
@inst_part << "generic map( \n#{generic_str} )\n" if generic_str.size > 0
port_str = ""
inst.ports do |port_name, dir, length, is_last|
inst.ports do |port_name, dir, length, default, is_last|
port_str << "#{port_name} => #{inst_name}_#{port_name}"
port_str << "," unless is_last
port_str << "\n"
200,7 → 199,22
end
 
def add_ifc_default_assignment( inst, inst_name, ifc_name, default )
 
 
tmp = ""
inst.ports( ifc_name.to_s ) do |port_name, dir, length, default, is_last|
if dir == 1 # assign default value only if it is an input
if length > 1
tmp << "#{inst_name}_#{port_name} <= ( others => '#{default}' );\n"
else
tmp << "#{inst_name}_#{port_name} <= '#{default}';\n"
end
end
end
@asgn_part << tmp
 
end
def add_ifc_connection( ifc_spec, ifc_name, length, src_inst, dst_inst, src_ifc, dst_ifc )
 
226,8 → 240,10
# assignment
#
#
ifc_spec.ports.each do |port_name, port_dir|
if port_dir == 0
ifc_spec.ports.each do |port_name, port_setup|
 
 
if port_setup[ :dir ] == 0
src_inst_sel = src_inst
dst_inst_sel = dst_inst
src_ifc_sel = src_ifc
249,26 → 265,27
 
# combine all sources
tmp = "#{port_tmp_name} <= "
assigned = false
 
# loop over instances
src_inst_sel.each_with_index do |(inst_name, inst), i|
( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name )
if port != nil
tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & " if port[ :len ] < length[ port_name ]
if port[ :len ] < length[ port_name ]
tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & "
end
tmp << "#{inst_name}_#{tmp_name}"
tmp << " and \n" unless i == src_inst_sel.size-1
assigned = true
else
puts "#{port_tmp_name}: #{length[port_name] > 1}"
if length[ port_name ] > 1
tmp << "( others => '0' )"
else
tmp << "'0'"
end
end
end
tmp << ";\n"
@asgn_part << tmp if assigned
@asgn_part << tmp
 
 
puts src_inst_sel.size
puts tmp
 
 
tmp = ""
assigned = false
# assign to destination
284,6 → 301,19
end
end
@asgn_part << tmp if assigned
puts "NOT ASSIGNED DST" if not assigned
else
# puts "ifc #{ifc_name} port #{port_name.to_s} is not assigned"
# p src_ifc
# p dst_ifc
# tmp = ""
# dst_inst_sel.each_with_index do |(inst_name, inst), i|
# p inst_name
# p port_name
# ( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name )
# tmp << "#{inst_name}_#{tmp_name} <= ( others => 'X' );\n"
# end
# @asgn_part << tmp;
end
 
end
/soc_maker/trunk/lib/soc_maker/core_inst.rb
78,11 → 78,15
 
end
 
def ports
puts "HELP" + @defn.name
p @ports
@ports.each_with_index do |(name, port_def), i|
yield( name.to_s, port_def[ :dir ], port_def[ :len ], i==@ports.size-1 )
def ports( *args )
if args.size == 0
@ports.each_with_index do |(name, port_def), i|
yield( name.to_s, port_def[ :dir ], port_def[ :len ], port_def[ :default ], i==@ports.size-1 )
end
elsif args.size == 1
@ifcs[ args.first.to_sym ].each do |name, port_def, i|
yield( name.to_s, port_def[ :dir ], port_def[ :len ], port_def[ :default ], i==@ports.size-1 )
end
end
end
 
116,6 → 120,8
 
 
# TODO do we need this?
#
#
# def implements_port?( ifc_name, port_spec_name )
# @defn.implements_port?( ifc_name, port_spec_name )
# end
161,9 → 167,16
# end
# end
# end
#
# TODO merge these two loops and create one hash
###
#
# create our own ports hash
#
@ports ||= {}
@defn.ports do |port_name, port_dir, port_len, is_last |
@defn.ports do |port_name, port_dir, port_len, default, is_last |
if port_len.is_a?( String )
param_match = SOCMaker::conf[ :length_regex ].match( port_len )
170,17 → 183,41
if param_match and @params[ port_len.to_sym ] != nil
tmp =@params[ port_len.to_sym ]
tmp = tmp.to_i if tmp.is_a?( String )
@ports[ port_name.to_sym ] = { len: tmp, dir: port_dir }
@ports[ port_name.to_sym ] = { len: tmp, dir: port_dir, default: default }
else
SOCMaker::logger.error( "Failed to evaluate #{port_len} for port #{port_name}" )
end
else
@ports[ port_name.to_sym ] = { len: port_len, dir: port_dir }
@ports[ port_name.to_sym ] = { len: port_len, dir: port_dir, default: default }
end
end
 
lerr_if( @defn == nil, 'Core not found in lib',
field: 'cores' )
@ifcs ||= {}
@defn.interfaces.keys.each do |ifc_name|
@ifcs[ ifc_name ] = {}
@defn.ports( ifc_name ) do |port_name, port_dir, port_len, default, is_last |
if port_len.is_a?( String )
param_match = SOCMaker::conf[ :length_regex ].match( port_len )
if param_match and @params[ port_len.to_sym ] != nil
tmp =@params[ port_len.to_sym ]
tmp = tmp.to_i if tmp.is_a?( String )
@ifcs[ ifc_name ][ port_name.to_sym ] = { len: tmp, dir: port_dir, default: default }
else
SOCMaker::logger.error( "Failed to evaluate #{port_len} for port #{port_name}" )
end
else
@ifcs[ ifc_name ][ port_name.to_sym ] = { len: port_len, dir: port_dir, default: default }
end
#
#puts "#{port_def_ref}, #{port_name}, #{port_dir}, #{port_default}"
end
end
# lerr_if( @defn == nil, 'Core not found in lib',
# field: 'cores' )
 
@defn.consistency_check
271,17 → 308,6
SOCMaker::logger.proc( "START of creating top-level '" + file_name + "'" )
 
 
 
# SOCMaker::logger.proc( "verifying first ..." )
#
# # TODO: this is a fix, that the parameters in core_inst.ports are updated.
# # A good approach for verifying, which checks the whole consistency, needs
# # to be done
# @defn.cores.each do |inst_name, inst|
# inst.verify
# end
 
 
#
# Create a unique list of cores and
# add for each core a component statement (vhdl only).
317,7 → 343,9
coder )
end
assign_unused_to_default( coder )
 
#
# Write content to the file
337,6 → 365,43
 
 
#
# Assign default values for unused interfaces.
# This is just a helper function and is used by gen_toplevel
#
# +coder+:: A HDL coder, which is used to create the auto-generated HDL.
#
def assign_unused_to_default( coder )
 
 
# iterate over all instances
# and check all interfaces
@defn.cores.each do |inst_name, inst|
 
inst.defn.interfaces.each do |ifc_name, ifc|
#
# Get the interface specification by using the 1st source entry
# and searching for the core-definition.
#
ifc_spec = SOCMaker::lib.get_ifc( ifc.name, ifc.version )
 
if !@defn.ifc_in_use?( inst_name, ifc_name )
 
default_tmp = {};
ifc_spec.ports.each do |_name,_port|
default_tmp[ _name ] = _port[ :default ]
end
 
coder.add_ifc_default_assignment( inst, inst_name, ifc_name, default_tmp )
end
end
end
end
 
 
 
#
# This function is called during the toplevel generation
# for each connection.
#
419,6 → 484,8
o.params == self.params
end
 
# TODO
# private: assign_unused_to_default, :gen_toplevel_con
 
end # CoreInst
end # SOCMaker
/soc_maker/trunk/lib/soc_maker/err.rb
64,7 → 64,7
SOCMaker::logger.error( "StructureError raised: " + message + " (#{name},#{field})" )
end
def to_s
"->#{@name}:#{@field}"
"#{super} -> #{@name}:#{@field}"
end
end
 
76,7 → 76,7
SOCMaker::logger.error( "LibError raised: " + message + " (#{requested})" )
end
def to_s
"->#{@name}"
"#{super} -> #{@name}:#{@field}"
end
end
 
97,7 → 97,7
SOCMaker::logger.error( "ValueError raised: " + message + " (#{name},#{field})" )
end
def to_s
"->#{@name}:#{@field}"
"#{super} -> #{@name}:#{@field}"
end
end
 
/soc_maker/trunk/lib/soc_maker/component.rb
219,7 → 219,20
 
 
def consistency_check
@interfaces.values.each_with_index do | ifc, i_ifc; ifc_def|
# get interface definition
ifc_def = SOCMaker::lib.get_ifc( ifc.name, ifc.version )
 
 
# check, if all mandatory ports are implemented by this interface
ifc_def.ports.each do | port_name, port |
perr_if( port[ :mandatory ] == true &&
ifc.ports.select{ |key,port_def| port_def.defn.to_sym == port_name }.size == 0,
"Mandatory port #{port_name} is not implemented in interface #{ifc.name}" )
end
end
 
end
 
 
232,7 → 245,6
 
 
 
 
def generics
@inst_parameters.each_with_index do |(name, val), i|
yield( name.to_s, val.type, val.default, i == @inst_parameters.size-1 )
259,6 → 271,14
# - info if last
# as argument
#
# An xor mechanism between port_dir and ifc=>dir is used
# to determine the direction of a port, for example:
# If the interface is declared as input (1) and a port is declared as input (1)
# the resulting direction will be an output 1^1 = 0.
# But if the overall interface direction is an output (0) and a port is declared
# as input, the resulting direction will an input 0^1 = 1.
# This allows to define a port-direction in the interface definition,
# and toggle the directions on core-definition level.
#
#
def ports( *args )
273,26 → 293,15
ifc.ports.each_with_index do |(port_name, port_def), i_port; port_dir|
 
# the reference to the port in the definition
defn_ref = port_def.defn
port_dir = ifc_def.ports[ defn_ref.to_sym ]
perr_if( port_dir == nil,
"Can't find #{defn_ref} in interface " +
"definition #{ifc_def.name} version " +
ifc_def.version + "==>>" + ifc_def.to_yaml )
# An xor mechanism between port_dir and ifc=>dir is used
# to determine the direction of a port, for example:
# If the interface is declared as input (1) and a port is declared as input (1)
# the resulting direction will be an output 1^1 = 0.
# But if the overall interface direction is an output (0) and a port is declared
# as input, the resulting direction will an input 0^1 = 1.
# This allows to define a port-direction in the interface definition,
# and toggle the directions on core-definition level.
 
# (name, direction, length, is_last)
defn_ref = port_def.defn.to_sym
perr_if( !ifc_def.ports.has_key?( defn_ref ),
"Can't find #{port_def} in" +
"interface definition #{ifc_def.name} " +
"version #{ifc_def.version}" )
yield( port_name.to_s,
port_dir ^ ifc.dir,
ifc_def.ports[ defn_ref ][:dir] ^ ifc.dir,
port_def.len,
ifc_def.ports[ defn_ref ][ :default ],
( (i_port == ifc.ports.size-1 ) and (i_ifc == @interfaces.size-1 ) ) )
end
end
301,24 → 310,29
 
# get interface (input is the name as string )
ifc = @interfaces[ args.first.to_sym ]
ifc_def = SOCMaker::lib.get_ifc( ifc.name, ifc.version )
 
ifc_def = SOCMaker::lib.get_ifc( ifc.name, ifc.version )
ifc.ports.each do |port_name, port_def; port_dir|
port_def = port_def.defn
port_dir = ifc_def.ports[ port_def.to_sym ]
if port_dir == nil
perr_if( port_dir==nil,
"Can't find #{port_def} in" +
"interface definition #{ifc_def.name} " +
"version #{ifc_def.version}" )
end
yield( port_def.to_s,
port_name.to_s,
port_dir ^ ifc.dir )
# loop over all ports of this interface
ifc.ports.each_with_index do |(port_name, port_def),i_port; port_dir|
defn_ref = port_def.defn.to_sym
perr_if( !ifc_def.ports.has_key?( defn_ref ),
"Can't find #{defn_ref} in" +
"interface definition #{ifc_def.name} " +
"version #{ifc_def.version}" )
yield( port_name.to_s,
ifc_def.ports[ defn_ref ][:dir] ^ ifc.dir,
port_def.len,
ifc_def.ports[ defn_ref ][ :default ],
( (i_port == ifc.ports.size-1 ) )
)
#yield( port_def.to_s,
#port_name.to_s,
#port_dir ^ ifc.dir,
#port_default )
end
 
else
 
# TODO
end
 
end
381,3 → 395,4
 
# vim: noai:ts=2:sw=2
 
# vim: noai:ts=2:sw=2
/soc_maker/trunk/lib/soc_maker/soc_def.rb
273,6 → 273,7
SOCMaker::logger.proc( "START of copying all HDL files" )
 
 
#
# Create a unique list of cores and
# for every core, create a directory and copy files
293,32 → 294,43
FileUtils.cp( file_path, dst_path )
end
 
 
#
# handle the static parameters
# (search and replace in pakckage/include files)
core_def.static_parameters.each do |file, param|
core_def.static_parameters.each do |file, sparam|
token_val_map = {}
param.parameters.each do |n,p|
sparam.parameters.each do |n,sparam_entry|
if @static[ core_inst.type.to_sym ] != nil and
@static[ core_inst.type.to_sym ][ n ] != nil
# use value defined in soc-spec
token_val_map[ p.token ] = @static[ core_inst.type.to_sym ][ n ]
tmp = @static[ core_inst.type.to_sym ][ n ]
else
# use default value from core-spec
token_val_map[ p.token ] = p.default
tmp = sparam_entry.default
end
 
if sparam_entry.type == "enum"
token_val_map[ sparam_entry.token ] = sparam_entry.choice[ tmp ]
elsif sparam_entry.type == "bool"
if tmp == true
token_val_map[ sparam_entry.token ] = sparam_entry.choice
else
token_val_map[ sparam_entry.token ] = ""
end
else
token_val_map[ sparam_entry.token ] = tmp
end
 
 
end
# create file paths
src_path = File.join( core_def.dir, param.path )
src_path = File.join( core_def.dir, sparam.path )
dst_dir = get_and_ensure_dst_dir!( core_def.name )
dst_path = File.join( dst_dir, param.file_dst )
dst_path = File.join( dst_dir, sparam.file_dst )
# process each line of input file
328,7 → 340,7
File.open( src_path ) do |src_f|
SOCMaker::logger.proc( "create #{dst_path} from #{ src_path} " )
while line = src_f.gets
token_val_map.each { |token, val| line = line.sub( Regexp.new( token.to_s ), val.to_s ) }
token_val_map.each { |token, val| line = line.sub( Regexp.new( '\b' + token.to_s + '\b' ), val.to_s ) }
dst_f.puts line
end
end
/soc_maker/trunk/lib/soc_maker/core_def.rb
74,19 → 74,23
def init_with( coder )
super( coder )
 
serr_if( coder[ 'hdlfiles' ] == nil,
'No hdlfiles field found',
instance: @name,
fiel: 'hdlfiles' )
@hdlfiles = coder[ 'hdlfiles' ]
# TODO: this was removed because we want to
# support cores, which have a config-file only
# (where config and implementation is in one file)
 
# serr_if( coder[ 'hdlfiles' ] == nil,
# 'No hdlfiles field found',
# instance: @name,
# fiel: 'hdlfiles' )
@hdlfiles = coder[ 'hdlfiles' ] || {}
serr_if( !@hdlfiles.is_a?( Hash ),
'HDL file def. != Hash',
instance: @name,
field: 'hdlfiles' )
serr_if( @hdlfiles.size == 0,
'No HDL files are given',
instance: @name,
field: 'hdlfiles' )
# serr_if( @hdlfiles.size == 0,
# 'No HDL files are given',
# instance: @name,
# field: 'hdlfiles' )
 
@hdlfiles.each do |file_name, defn |
serr_if( defn == nil,
112,6 → 116,11
 
 
#
# TODO this also exists in component.rb
# might this be removed?
# If yes, make sure, that the 'default' stuff
# is also done in component.rb!!!
#
# Iterates over interface list.
# For each interface, all ports are processed.
# For each port within each interface, we lookup the port defn
123,68 → 132,70
#
#
#
def ports( *args )
#def ports( *args )
 
 
if args.size == 0
@interfaces.values.each_with_index do | ifc, i_ifc; ifc_def|
#if args.size == 0
#@interfaces.values.each_with_index do | ifc, i_ifc; ifc_def|
# get interface definition
ifc_def = SOCMaker::lib.get_ifc( ifc.name, ifc.version )
## get interface definition
#ifc_def = SOCMaker::lib.get_ifc( ifc.name, ifc.version )
 
# loop over ports in this interface
ifc.ports.each_with_index do |(port_name, port_def), i_port; port_dir|
## loop over ports in this interface
#ifc.ports.each_with_index do |(port_name, port_def), i_port; port_dir|
 
# the reference to the port in the definition
defn_ref = port_def.defn
port_dir = ifc_def.ports[ defn_ref.to_sym ]
perr_if( port_dir == nil,
"Can't find #{defn_ref} in interface " +
"definition #{ifc_def.name} version " +
ifc_def.version + "==>>" + ifc_def.to_yaml )
## the reference to the port in the definition
#defn_ref = port_def.defn
#port_dir = ifc_def.ports[ defn_ref.to_sym ][ :dir ]
#port_default = ifc_def.ports[ defn_ref.to_sym ][ :default ]
#perr_if( port_dir == nil,
#"Can't find #{defn_ref} in interface " +
#"definition #{ifc_def.name} version " +
#ifc_def.version + "==>>" + ifc_def.to_yaml )
# An xor mechanism between port_dir and ifc=>dir is used
# to determine the direction of a port, for example:
# If the interface is declared as input (1) and a port is declared as input (1)
# the resulting direction will be an output 1^1 = 0.
# But if the overall interface direction is an output (0) and a port is declared
# as input, the resulting direction will an input 0^1 = 1.
# This allows to define a port-direction in the interface definition,
# and toggle the directions on core-definition level.
## An xor mechanism between port_dir and ifc=>dir is used
## to determine the direction of a port, for example:
## If the interface is declared as input (1) and a port is declared as input (1)
## the resulting direction will be an output 1^1 = 0.
## But if the overall interface direction is an output (0) and a port is declared
## as input, the resulting direction will an input 0^1 = 1.
## This allows to define a port-direction in the interface definition,
## and toggle the directions on core-definition level.
 
# (name, direction, length, is_last)
yield( port_name.to_s,
port_dir ^ ifc.dir,
port_def.len,
( (i_port == ifc.ports.size-1 ) and (i_ifc == @interfaces.size-1 ) ) )
end
end
## (name, direction, length, is_last)
#yield( port_name.to_s,
#port_dir ^ ifc.dir,
#port_def.len,
#port_default,
#( (i_port == ifc.ports.size-1 ) and (i_ifc == @interfaces.size-1 ) ) )
#end
#end
 
# elsif args.size == 1
## elsif args.size == 1
 
# # get interface (input is the name as string )
# ifc = @interfaces[ args.first.to_sym ]
## # get interface (input is the name as string )
## ifc = @interfaces[ args.first.to_sym ]
 
# ifc_def = SOCMaker::lib.get_ifc( ifc.name, ifc.version )
# ifc.ports.each do |port_name, port_def; port_dir|
# port_def = port_def.defn
# port_dir = ifc_def.ports[ port_def.to_sym ]
# if port_dir == nil
# perr_if( port_dir==nil,
# "Can't find #{port_def} in" +
# "interface definition #{ifc_def.name} " +
# "version #{ifc_def.version}" )
# end
# yield( port_def.to_s,
# port_name.to_s,
# port_dir ^ ifc.dir )
# end
## ifc_def = SOCMaker::lib.get_ifc( ifc.name, ifc.version )
## ifc.ports.each do |port_name, port_def; port_dir|
## port_def = port_def.defn
## port_dir = ifc_def.ports[ port_def.to_sym ]
## if port_dir == nil
## perr_if( port_dir==nil,
## "Can't find #{port_def} in" +
## "interface definition #{ifc_def.name} " +
## "version #{ifc_def.version}" )
## end
## yield( port_def.to_s,
## port_name.to_s,
## port_dir ^ ifc.dir )
## end
 
else
#else
 
end
#end
 
end
#end
 
 
# this is a core_def and doesn't have
194,7 → 205,7
end
 
def consistency_check
 
super
end
 
 
/soc_maker/trunk/lib/soc_maker/ifc_spc.rb
82,12 → 82,27
field: "name" )
 
@ports = coder[ 'ports' ] || {}
@ports.each do |pname, port_dir|
verr_if( !port_dir.is_a?( Fixnum ) ||
( port_dir != 0 && port_dir != 1 ),
"Port direction value is neither 0 nor 1",
@ports.each do |pname, port|
 
verr_if( !port.is_a?( Hash ),
"Port field must be organized as a hash",
instance: @name,
field: "ports" )
 
verr_if( !port.has_key?( :dir ),
"No port direction specified for #{pname}",
instance: @name,
field: "ports" )
field: "ports" )
 
verr_if( !port[ :dir ].is_a?( Fixnum ) ||
( port[ :dir ] != 0 && port[ :dir ] != 1 ),
"Port direction value for #{pname} is neither 0 nor 1",
instance: @name,
field: "ports" )
 
port[ :mandatory ] = true if !port.has_key?( :mandatory )
port[ :default ] ||= '0'
 
end
end
/soc_maker/trunk/spec/core_def_spec.rb
502,4 → 502,5
end
 
 
 
# vim: noai:ts=2:sw=2
/soc_maker/trunk/spec/ifc_spc_spec.rb
51,9 → 51,12
name: core_ifc
version: '1'
ports:
:sig_a: 1
:sig_b: 1
:sig_c: 0
:sig_a:
:dir: 1
:sig_b:
:dir: 1
:sig_c:
:dir: 0
"""
 
IFC_YAML_INVALID = """
/soc_maker/trunk/spec/test_soc.yaml
46,7 → 46,12
:inst_d: SOCM_INST
type: core_Brel1
params: {}
static: {}
 
static:
:core_Arel1:
:p1: 11
:pv1: 0
 
cons:
:a_new_con:
:rule: or
/soc_maker/trunk/spec/core_inst_spec.rb
134,24 → 134,6
( o2 == o1 ).should be == false
end
 
 
 
it "should create valid vhdl output with our test library" do
SOCMaker::conf[ :build_dir ] = 'spec/tmp_build2'
SOCMaker::conf[ :hdl_dir ] = 'b'
coder = SOCMaker::VHDLCoder.new
SOCMaker::lib.refresh( './spec/test_soc_lib' )
soc = SOCMaker::from_f( './spec/test_soc.yaml' );
SOCMaker::lib.add_core( soc )
soc_inst = SOCMaker::CoreInst.new( 'test_socv1' )
soc_inst.consistency_check
soc_inst.gen_toplevel( coder );
#soc.copy_files
#p soc.cons
#puts soc.to_yaml
end
 
it "should call coder functions for each core-def. (stub-version)" do
SOCMaker::lib.clear
176,6 → 158,7
coder.stub( :filename ){ |x| x + ".vhd" }
 
coder.stub( :add_ifc_default_assignment )
 
coder.stub( :add_ifc_connection )
 
197,10 → 180,13
SOCMaker::lib.add_core( core_a )
SOCMaker::lib.add_core( core_b )
ifc_spc = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: 1, port_b: 0 } )
ifc_spc = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: { dir: 1}, port_b: { dir: 0 } } )
SOCMaker::lib.add_ifc( ifc_spc )
ifc_def_1 = SOCMaker::IfcDef.new( "myifc", "v1", 0, { a: SOCMaker::IfcPort.new( "port_a", 1 ) } )
ifc_def_0 = SOCMaker::IfcDef.new( "myifc", "v1", 1, { b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
ifc_def_1 = SOCMaker::IfcDef.new( "myifc", "v1", 0, { a: SOCMaker::IfcPort.new( "port_a", 1 ),
b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
ifc_def_0 = SOCMaker::IfcDef.new( "myifc", "v1", 1, { a: SOCMaker::IfcPort.new( "port_a", 1 ),
b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
core_a.interfaces[ :ifc_a ] = ifc_def_0
249,6 → 235,24
end
 
 
 
 
it "should create valid vhdl output with our test library" do
SOCMaker::conf[ :build_dir ] = 'spec/tmp_build2'
SOCMaker::conf[ :hdl_dir ] = 'b'
coder = SOCMaker::VHDLCoder.new
SOCMaker::lib.refresh( './spec/test_soc_lib' )
soc = SOCMaker::from_f( './spec/test_soc.yaml' );
SOCMaker::lib.add_core( soc )
soc_inst = SOCMaker::CoreInst.new( 'test_socv1' )
soc_inst.consistency_check
soc_inst.gen_toplevel( coder );
soc.copy_files
#p soc.cons
#puts soc.to_yaml
end
 
end
 
# vim: noai:ts=2:sw=2
/soc_maker/trunk/spec/test_soc_lib/ifcs/core_AB_ifc/top_ifc.yaml
2,6 → 2,8
name: top_ifc
version: "1"
ports:
:sig_1: 1
:sig_2: 1
:sig_1:
:dir: 1
:sig_2:
:dir: 1
 
/soc_maker/trunk/spec/test_soc_lib/ifcs/core_AB_ifc/core_AB_ifc.yaml
2,6 → 2,14
name: core_AB_ifc
version: "1"
ports:
:sig_a: 1
:sig_b: 1
:sig_c: 0
:sig_a:
:dir: 1
:mandatory: true
:sig_b:
:dir: 1
:mandatory: true
:default: '1'
:sig_c:
:dir: 0
:mandatory: false
:default: 'X'
/soc_maker/trunk/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg3.v.src
0,0 → 1,6
 
 
TOK_V1
 
 
 
/soc_maker/trunk/spec/test_soc_lib/cores/core_A_rel1/00_core_a.yaml
24,6 → 24,20
:sig_con1c: SOCM_PORT
defn: sig_c
len: 1
:ifc02: SOCM_IFC
name: core_AB_ifc
dir: 1
version: "1"
ports:
:sig_con1ax: SOCM_PORT
defn: sig_a
len: param1
:sig_con1bx: SOCM_PORT
defn: sig_b
len: param2
:sig_con1cx: SOCM_PORT
defn: sig_c
len: 1
 
 
hdlfiles:
/soc_maker/trunk/spec/test_soc_lib/cores/core_A_rel1/01_core_a.yaml
11,7 → 11,7
max: 100
visible: true
editable: true
default: 3
default: 22
description: Some setup
:p3: SOCM_SENTRY
token: TOK_XYZ
37,4 → 37,21
default: 5
description: More setup
 
 
:core_a_pkg3.v.src: SOCM_SPARAM
dir: .
path: ./core_a_pkg3.v.src
file_dst: core_a_pkg3.v
parameters:
:pv1: SOCM_SENTRY
token: TOK_V1
type: enum
min: 0
max: 100
visible: true
editable: true
default: 5
description: More setup
choice:
- "`define SEL_1"
- "`define SEL_2"
- "`define SEL_3"
/soc_maker/trunk/spec/soc_def_spec.rb
235,8 → 235,8
 
it "should raise an ProcessingError if the ifc.-version is wrong" do
 
ifc_spc1 = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: 1, port_b: 0 } )
ifc_spc2 = SOCMaker::IfcSpc.new( "myifc", "v2", 'ports' => { port_a: 1, port_b: 0 } )
ifc_spc1 = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: {dir:1}, port_b: {dir:0} } )
ifc_spc2 = SOCMaker::IfcSpc.new( "myifc", "v2", 'ports' => { port_a: {dir:1}, port_b: {dir:0} } )
ifc_def_1 = SOCMaker::IfcDef.new( "myifc", "v1", 0, { a: SOCMaker::IfcPort.new( "port_a", 1 ) } )
ifc_def_0 = SOCMaker::IfcDef.new( "myifc", "v2", 1, { b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
file = { "file.vhd".to_sym => SOCMaker::HDLFile.new( "./file.vhd" ) }
262,9 → 262,15
 
it "should add a connection entry" do
 
ifc_spc = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: 1, port_b: 0 } )
ifc_def_1 = SOCMaker::IfcDef.new( "myifc", "v1", 0, { a: SOCMaker::IfcPort.new( "port_a", 1 ) } )
ifc_def_0 = SOCMaker::IfcDef.new( "myifc", "v1", 1, { b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
ifc_spc = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: {dir:1}, port_b: {dir:0} } )
 
ifc_def_1 = SOCMaker::IfcDef.new( "myifc", "v1", 0, { a: SOCMaker::IfcPort.new( "port_a", 1 ),
b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
 
ifc_def_0 = SOCMaker::IfcDef.new( "myifc", "v1", 1, { a: SOCMaker::IfcPort.new( "port_a", 1 ),
b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
 
 
file = { "file.vhd".to_sym => SOCMaker::HDLFile.new( "./file.vhd" ) }
core_a = SOCMaker::CoreDef.new( "core_a", "v1", file, "top" )
core_b = SOCMaker::CoreDef.new( "core_b", "v1", file, "top" )
291,9 → 297,14
 
it "should add a connection entry, which connects the toplevel's port" do
 
ifc_spc = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: 1, port_b: 0 } )
ifc_def_1 = SOCMaker::IfcDef.new( "myifc", "v1", 0, { a: SOCMaker::IfcPort.new( "port_a", 1 ) } )
ifc_def_0 = SOCMaker::IfcDef.new( "myifc", "v1", 1, { b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
ifc_spc = SOCMaker::IfcSpc.new( "myifc", "v1", 'ports' => { port_a: {dir:1}, port_b: {dir:0} } )
 
ifc_def_1 = SOCMaker::IfcDef.new( "myifc", "v1", 0, { a: SOCMaker::IfcPort.new( "port_a", 1 ),
b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
 
ifc_def_0 = SOCMaker::IfcDef.new( "myifc", "v1", 1, { a: SOCMaker::IfcPort.new( "port_a", 1 ),
b: SOCMaker::IfcPort.new( "port_b", 1 ) } )
 
file = { "file.vhd".to_sym => SOCMaker::HDLFile.new( "./file.vhd" ) }
core_a = SOCMaker::CoreDef.new( "core_a", "v1", file, "top" )
core_a.interfaces[ :ifc_a ] = ifc_def_0
/soc_maker/trunk/spec/component_spec.rb
180,8 → 180,8
it 'should iterate over all ports' do
 
SOCMaker::lib.clear
ifc_s1 = SOCMaker::IfcSpc.new( "i1", "v1", 'ports' => { p1: 1, p2: 1, p3: 0 } )
ifc_s2 = SOCMaker::IfcSpc.new( "i2", "v1", 'ports' => { x1: 1, x2: 0 } )
ifc_s1 = SOCMaker::IfcSpc.new( "i1", "v1", 'ports' => { p1:{dir:1}, p2:{dir:1}, p3:{dir:0} } )
ifc_s2 = SOCMaker::IfcSpc.new( "i2", "v1", 'ports' => { x1:{dir:1}, x2:{dir:0} } )
SOCMaker::lib.add_ifc( ifc_s1 )
SOCMaker::lib.add_ifc( ifc_s2 )
 
203,7 → 203,7
r_len = []
r_is_last = []
 
c.ports do |arg_name,arg_dir,arg_len,arg_is_last|
c.ports do |arg_name,arg_dir,arg_len,arg_default,arg_is_last|
r_name << arg_name
r_dir << arg_dir
r_len << arg_len
215,22 → 215,47
r_is_last.should be == [ false, false, false, false, true ]
 
 
r_def = []
#r_def = []
r_name = []
r_dir = []
 
c.ports( "i1" ) do |arg_name,arg_def,arg_dir|
r_def << arg_def
c.ports( "i1" ) do |arg_name,arg_dir, arg_default, arg_is_last|
#r_def << arg_def
r_name << arg_name
r_dir << arg_dir
end
r_def.should be == %w[ m_p1 m_p2 m_p3 ]
r_name.should be == %w[ p1 p2 p3 ]
#r_def.should be == %w[ m_p1 m_p2 m_p3 ]
r_name.should be == %w[ m_p1 m_p2 m_p3 ]
r_dir.should be == [ 1, 1, 0, ]
 
end
 
end
 
 
describe SOCMaker::Component, "consistency_check" do
 
 
it "should throw an error if an incomplete interface is used" do
file = { "file.vhd".to_sym => SOCMaker::HDLFile.new( "./file.vhd" ) }
 
# three (auto) mandatory ports
ifc_s1 = SOCMaker::IfcSpc.new( "i1", "v1", 'ports' => { p1: { dir: 1}, p2: {dir: 1}, p3: {dir:0} } )
 
# interface implementaiton with only two of the three ports
p1 = SOCMaker::IfcPort.new( "p1", 1 )
p2 = SOCMaker::IfcPort.new( "p2", 2 )
ifc_d1 = SOCMaker::IfcDef.new( "i1", "v1", 0, { m_p1: p1, m_p2: p2 } )
c = SOCMaker::Component.new( "acore", "v1", "top",
{ 'interfaces' => { i1: ifc_d1 } } )
 
 
expect{ c.consistency_check }.
to raise_error( SOCMaker::ERR::ProcessingError )
end
 
end
 
# vim: noai:ts=2:sw=2
/soc_maker/trunk/core_lib/interfaces/clk_rst/single.yaml
2,5 → 2,6
name: single
version: "1"
ports:
:single: 0
:single:
:dir: 0
 
/soc_maker/trunk/core_lib/interfaces/clk_rst/rst.yaml
2,4 → 2,5
name: rst
version: "1"
ports:
:rst: 0
:rst:
:dir: 0
/soc_maker/trunk/core_lib/interfaces/clk_rst/clk.yaml
2,4 → 2,5
name: clk
version: "1"
ports:
:clk: 0
:clk:
:dir: 0
/soc_maker/trunk/core_lib/interfaces/jtag/jtag.yaml
2,8 → 2,12
name: jtag
version: "1"
ports:
:tck: 1
:tdi: 1
:tdo: 0
:rst: 1
:tck:
:dir: 1
:tdi:
:dir: 1
:tdo:
:dir: 0
:rst:
:dir: 1
 
/soc_maker/trunk/core_lib/interfaces/jtag/jtag_tap.yaml
2,12 → 2,21
name: jtag_tap
version: "1"
ports:
:tck: 0
:tdi: 0
:tdo: 1
:rst: 0
:shift: 0
:pause: 0
:update: 0
:capture: 0
:select: 0
:tck:
:dir: 0
:tdi:
:dir: 0
:tdo:
:dir: 1
:rst:
:dir: 0
:shift:
:dir: 0
:pause:
:dir: 0
:update:
:dir: 0
:capture:
:dir: 0
:select:
:dir: 0
/soc_maker/trunk/core_lib/interfaces/debug/debug.yaml
2,15 → 2,31
name: debug
version: "1"
ports:
:dbg_stall: 0
:dbg_ewt: 0
:dbg_lss: 1
:dbg_iso: 1
:dbg_wpo: 1
:dbg_bpo: 1
:dbg_stb: 0
:dbg_we: 0
:dbg_adr: 0
:dbg_dat_i: 1
:dbg_dat_o: 0
:dbg_ack: 1
:dbg_stall:
:dir: 0
:dbg_ewt:
:dir: 0
:mandatory: false
:dbg_lss:
:dir: 1
:mandatory: false
:dbg_iso:
:dir: 1
:mandatory: false
:dbg_wpo:
:dir: 1
:mandatory: false
:dbg_bpo:
:dir: 1
:dbg_stb:
:dir: 0
:dbg_we:
:dir: 0
:dbg_adr:
:dir: 0
:dbg_dat_i:
:dir: 1
:dbg_dat_o:
:dir: 0
:dbg_ack:
:dir: 1
/soc_maker/trunk/core_lib/interfaces/power/or_power.yaml
2,14 → 2,24
name: or_power_management
version: "1"
ports:
:pm_cpustall: 0
:pm_clksd: 1
:pm_dc_gate: 1
:pm_ic_gate: 1
:pm_dmmu_gate: 1
:pm_immu_gate: 1
:pm_tt_gate: 1
:pm_cpu_gate: 1
:pm_wakeup: 1
:pm_lvolt: 1
:pm_cpustall:
:dir: 0
:pm_clksd:
:dir: 1
:pm_dc_gate:
:dir: 1
:pm_ic_gate:
:dir: 1
:pm_dmmu_gate:
:dir: 1
:pm_immu_gate:
:dir: 1
:pm_tt_gate:
:dir: 1
:pm_cpu_gate:
:dir: 1
:pm_wakeup:
:dir: 1
:pm_lvolt:
:dir: 1
 
/soc_maker/trunk/core_lib/interfaces/wishbone/wishbone_ma_b3.yaml
2,23 → 2,53
name: wishbone_ma
version: "b3"
ports:
:clk: 0
:rst: 0
:dat_i: 1
:dat_o: 0
:tgd_i: 1
:tgd_o: 0
:adr: 1
:cyc: 1
:err: 0
:lock: 1
:rty: 0
:sel: 1
:stb: 1
:tga: 1
:tgc: 1
:we: 1
:ack: 0
:cab: 1
:cti: 1
:bte: 1
:clk:
:dir: 0
:rst:
:dir: 0
:dat_i:
:dir: 1
:dat_o:
:dir: 0
:tgd_i:
:dir: 1
:mandatory: false
:tgd_o:
:dir: 0
:mandatory: false
:adr:
:dir: 1
:cyc:
:dir: 1
:err:
:dir: 0
:mandatory: false
:lock:
:dir: 1
:mandatory: false
:rty:
:dir: 0
:mandatory: false
:sel:
:dir: 1
:stb:
:dir: 1
:tga:
:dir: 1
:mandatory: false
:tgc:
:dir: 1
:mandatory: false
:we:
:dir: 1
:ack:
:dir: 0
:cab:
:dir: 1
:mandatory: false
:cti:
:dir: 1
:mandatory: false
:bte:
:dir: 1
:mandatory: false
/soc_maker/trunk/core_lib/interfaces/wishbone/wishbone_sl_b3.yaml
2,22 → 2,50
name: wishbone_sl
version: "b3"
ports:
:clk: 0
:rst: 0
:dat_i: 1
:dat_o: 0
:tgd_i: 1
:tgd_o: 0
:ack: 1
:adr: 0
:cyc: 0
:err: 1
:lock: 0
:rty: 1
:sel: 0
:stb: 0
:tga: 0
:tgc: 0
:we: 0
:bte: 0
:cti: 0
:clk:
:dir: 0
:rst:
:dir: 0
:dat_i:
:dir: 1
:dat_o:
:dir: 0
:tgd_i:
:dir: 1
:mandatory: false
:tgd_o:
:dir: 0
:mandatory: false
:ack:
:dir: 1
:adr:
:dir: 0
:cyc:
:dir: 0
:err:
:dir: 1
:mandatory: false
:lock:
:dir: 0
:mandatory: false
:rty:
:dir: 1
:mandatory: false
:sel:
:dir: 0
:stb:
:dir: 0
:tga:
:dir: 0
:mandatory: false
:tgc:
:dir: 0
:mandatory: false
:we:
:dir: 0
:bte:
:dir: 0
:mandatory: false
:cti:
:dir: 0
:mandatory: false
/soc_maker/trunk/core_lib/inc.yaml
4,8 → 4,10
- cores/wb_connect
- cores/adv_debug_sys
- cores/ram_wb
- cores/uart16550
- interfaces/clk_rst
- interfaces/debug
- interfaces/power
- interfaces/wishbone
- interfaces/jtag
- interfaces/uart
/soc_maker/trunk/core_lib/cores/or1200_rel2/02_or1200_files.yaml
375,13 → 375,16
type: vhdl
path: rtl/verilog/or1200_xcv_ram32x8d.v
 
:defines: SOCM_HDL_FILE
use_syn: true
use_sys_sim: true
use_mod_sim: true
type: vhdl
path: rtl/verilog/or1200_defines.v
# Please note: the defines is automatically created
# see or1200_defines.v.in
 
# :defines: SOCM_HDL_FILE
# use_syn: true
# use_sys_sim: true
# use_mod_sim: true
# type: vhdl
# path: rtl/verilog/or1200_defines.v
 
:ic_fsm: SOCM_HDL_FILE
use_syn: true
use_sys_sim: true
/soc_maker/trunk/core_lib/cores/or1200_rel2/03_or1200_sparam.yaml
0,0 → 1,188
static_parameters:
:or1200_defines: SOCM_SPARAM
dir: .
path: ./or1200_defines.v.in
file_dst: rtl/verilog/or1200_defines.v
parameters:
 
:VCD_DUMP: SOCM_SENTRY
token: TOK_VCD_DUMP
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_VCD_DUMP"
 
:VERBOSE: SOCM_SENTRY
token: TOK_VERBOSE
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_VERBOSE"
 
:ASIC: SOCM_SENTRY
token: TOK_ASIC
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_ASIC"
 
:ASIC_MEM_CHOICE: SOCM_SENTRY
token: TOK_ASIC_MEM_CHOICE
type: enum
visible: true
editable: true
default: 0
choice:
- "`define OR1200_ARTISAN_SSP"
- "`define OR1200_ARTISAN_SDP"
- "`define OR1200_ARTISAN_STP"
- "`define OR1200_VIRTUALSILICON_SSP"
- "`define OR1200_VIRTUALSILICON_STP_T1"
- "`define OR1200_VIRTUALSILICON_STP_T2"
 
:ASIC_NO_DC: SOCM_SENTRY
token: TOK_ASIC_NO_DC
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_NO_DC"
 
:ASIC_NO_IC: SOCM_SENTRY
token: TOK_ASIC_NO_IC
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_NO_IC"
 
:ASIC_NO_DMMU: SOCM_SENTRY
token: TOK_ASIC_NO_DMMU
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_NO_DMMU"
 
:ASIC_NO_IMMU: SOCM_SENTRY
token: TOK_ASIC_NO_IMMU
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_NO_IMMU"
 
:ASIC_MUL_CHOICE: SOCM_SENTRY
token: TOK_ASIC_MUL_CHOICE
type: enum
visible: true
editable: true
default: 0
choice:
- "`define OR1200_ASIC_MULTP2_32X32"
- "`define OR1200_GENERIC_MULTP2_32X32"
 
:ASIC_IC_CHOICE: SOCM_SENTRY
token: TOK_ASIC_IC_CHOICE
type: enum
visible: true
editable: true
default: 0
choice:
- "`define OR1200_IC_1W_512B"
- "`define OR1200_IC_1W_4KB"
- "`define OR1200_IC_1W_8KB"
 
:ASIC_DC_CHOICE: SOCM_SENTRY
token: TOK_ASIC_DC_CHOICE
type: enum
visible: true
editable: true
default: 0
choice:
- "`define OR1200_DC_1W_4KB"
- "`define OR1200_DC_1W_8KB"
 
:FPGA_MEM_CHOICE: SOCM_SENTRY
token: TOK_FPGA_MEM_CHOICE
type: enum
visible: true
editable: true
default: 0
choice:
- " "
- "`define OR1200_ALTERA_LPM"
- "`define OR1200_XILINX_RAMB16"
- "`define OR1200_XILINX_RAMB4"
- "`define OR1200_XILINX_RAM32X1D"
- "`define OR1200_USE_RAM16X1D_FOR_RAM32X1D"
 
 
:FPGA_NO_DC: SOCM_SENTRY
token: TOK_FPGA_NO_DC
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_NO_DC"
 
:FPGA_NO_IC: SOCM_SENTRY
token: TOK_FPGA_NO_IC
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_NO_IC"
 
:FPGA_NO_DMMU: SOCM_SENTRY
token: TOK_FPGA_NO_DMMU
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_NO_DMMU"
 
:FPGA_NO_IMMU: SOCM_SENTRY
token: TOK_FPGA_NO_IMMU
type: bool
visible: true
editable: true
default: false
choice: "`define OR1200_NO_IMMU"
 
:FPGA_MUL_CHOICE: SOCM_SENTRY
token: TOK_FPGA_MUL_CHOICE
type: enum
visible: true
editable: true
default: 0
choice:
- "`define OR1200_ASIC_MULTP2_32X32"
- "`define OR1200_GENERIC_MULTP2_32X32"
 
:FPGA_IC_CHOICE: SOCM_SENTRY
token: TOK_FPGA_IC_CHOICE
type: enum
visible: true
editable: true
default: 0
choice:
- "`define OR1200_IC_1W_512B"
- "`define OR1200_IC_1W_4KB"
- "`define OR1200_IC_1W_8KB"
 
:FPGA_DC_CHOICE: SOCM_SENTRY
token: TOK_FPGA_DC_CHOICE
type: enum
visible: true
editable: true
default: 0
choice:
- "`define OR1200_DC_1W_4KB"
- "`define OR1200_DC_1W_8KB"
 
 
/soc_maker/trunk/core_lib/cores/or1200_rel2/or1200_defines.v.in
0,0 → 1,1799
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's definitions ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Parameters of the OR1200 core ////
//// ////
//// To Do: ////
//// - add parameters that are missing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Modified for SOC-Maker as config-define ////
//// 28. Jul., 2014, feddischson@opencores.org ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.44 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.43 2005/01/07 09:23:39 andreje
// l.ff1 and l.cmov instructions added
//
// Revision 1.42 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.41 2004/05/09 20:03:20 lampret
// By default l.cust5 insns are disabled
//
// Revision 1.40 2004/05/09 19:49:04 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.39 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.38 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.35.4.6 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.35.4.5 2004/01/15 06:46:38 markom
// interface to debug changed; no more opselect; stb-ack protocol
//
// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
//
// Revision 1.35.4.3 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
// Static exception prefix.
//
// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.35 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.34 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.33 2003/04/07 20:56:07 lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
//
// Revision 1.32 2003/04/07 01:26:57 lampret
// RFRAM defines comments updated. Altera LPM option added.
//
// Revision 1.31 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.30 2002/10/28 15:09:22 mohor
// Previous check-in was done by mistake.
//
// Revision 1.29 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
//
// Revision 1.28 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.27 2002/09/16 03:13:23 lampret
// Removed obsolete comment.
//
// Revision 1.26 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.25 2002/09/07 19:16:10 lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.24 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.23 2002/09/04 00:50:34 lampret
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
//
// Revision 1.22 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.21 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.20 2002/08/18 21:59:45 lampret
// Disable SB until it is tested
//
// Revision 1.19 2002/08/18 19:53:08 lampret
// Added store buffer.
//
// Revision 1.18 2002/08/15 06:04:11 lampret
// Fixed Xilinx trace buffer address. REported by Taylor Su.
//
// Revision 1.17 2002/08/12 05:31:44 lampret
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
//
// Revision 1.16 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.15 2002/06/08 16:20:21 lampret
// Added defines for enabling generic FF based memory macro for register file.
//
// Revision 1.14 2002/03/29 16:24:06 lampret
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
//
// Revision 1.13 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.12 2002/03/28 19:25:42 lampret
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
//
// Revision 1.11 2002/03/28 19:13:17 lampret
// Updated defines.
//
// Revision 1.10 2002/03/14 00:30:24 lampret
// Added alternative for critical path in DU.
//
// Revision 1.9 2002/03/11 01:26:26 lampret
// Fixed async loop. Changed multiplier type for ASIC.
//
// Revision 1.8 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.7 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.6 2002/01/19 14:10:22 lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.5 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.4 2002/01/14 09:44:12 lampret
// Default ASIC configuration does not sample WB inputs.
//
// Revision 1.3 2002/01/08 00:51:08 lampret
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
//
// Revision 1.2 2002/01/03 21:23:03 lampret
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.20 2001/12/04 05:02:36 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.19 2001/11/27 19:46:57 lampret
// Now FPGA and ASIC target are separate.
//
// Revision 1.18 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.17 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.16 2001/11/20 21:30:38 lampret
// Added OR1200_REGISTERED_INPUTS.
//
// Revision 1.15 2001/11/19 14:29:48 simons
// Cashes disabled.
//
// Revision 1.14 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.13 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.12 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.11 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.8 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/17 08:01:19 lampret
// IC enable/disable.
//
// Revision 1.2 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
 
//
// Dump VCD
//
//`define OR1200_VCD_DUMP
TOK_VCD_DUMP
 
//
// Generate debug messages during simulation
//
//`define OR1200_VERBOSE
TOK_VERBOSE
 
 
// `define OR1200_ASIC
TOK_ASIC
 
////////////////////////////////////////////////////////
//
// Typical configuration for an ASIC
//
`ifdef OR1200_ASIC
 
//
// Target ASIC memories
//
//`define OR1200_ARTISAN_SSP
//`define OR1200_ARTISAN_SDP
//`define OR1200_ARTISAN_STP
//`define OR1200_VIRTUALSILICON_SSP
//`define OR1200_VIRTUALSILICON_STP_T1
//`define OR1200_VIRTUALSILICON_STP_T2
TOK_ASIC_MEM_CHOICE
 
 
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
TOK_ASIC_NO_DC
 
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
TOK_ASIC_NO_IC
 
 
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
TOK_ASIC_NO_DMMU
 
 
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
TOK_ASIC_NO_IMMU
 
 
//
// Select between ASIC optimized and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
//`define OR1200_GENERIC_MULTP2_32X32
TOK_ASIC_MUL_CHOICE
 
 
//
// Size/type of insn/data cache if implemented
//
// `define OR1200_IC_1W_512B
// `define OR1200_IC_1W_4KB
// `define OR1200_IC_1W_8KB
TOK_ASIC_IC_CHOICE
 
// `define OR1200_DC_1W_4KB
// `define OR1200_DC_1W_8KB
TOK_ASIC_DC_CHOICE
 
 
`else
 
 
/////////////////////////////////////////////////////////
//
// Typical configuration for an FPGA
//
 
//
// Target FPGA memories
//
//`define OR1200_ALTERA_LPM
//`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
TOK_FPGA_MEM_CHOICE
 
 
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
TOK_FPGA_NO_DC
 
 
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
TOK_FPGA_NO_IC
 
 
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
TOK_FPGA_NO_DMMU
 
 
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
TOK_FPGA_NO_IMMU
 
 
//
// Select between ASIC and generic multiplier
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
//
//`define OR1200_ASIC_MULTP2_32X32
//`define OR1200_GENERIC_MULTP2_32X32
TOK_FPGA_MUL_CHOICE
 
 
//
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
//
//`define OR1200_IC_1W_512B
//`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
TOK_FPGA_IC_CHOICE
 
//`define OR1200_DC_1W_4KB
//`define OR1200_DC_1W_8KB
TOK_FPGA_DC_CHOICE
 
 
`endif
 
 
//////////////////////////////////////////////////////////
//
// Do not change below unless you know what you are doing
//
 
//
// Enable RAM BIST
//
// At the moment this only works for Virtual Silicon
// single port RAMs. For other RAMs it has not effect.
// Special wrapper for VS RAMs needs to be provided
// with scan flops to facilitate bist scan.
//
//`define OR1200_BIST
 
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
//
`define OR1200_REGISTERED_OUTPUTS
 
//
// Register OR1200 WISHBONE inputs
//
// (must be undefined/disabled)
//
//`define OR1200_REGISTERED_INPUTS
 
//
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
//
 
//
// WISHBONE retry counter range
//
// 2^value range for retry counter. Retry counter
// is activated whenever *wb_rty_i is asserted and
// until retry counter expires, corresponding
// WISHBONE interface is deactivated.
//
// To disable retry counters and *wb_rty_i all together,
// undefine this macro.
//
//`define OR1200_WB_RETRY 7
 
//
// WISHBONE Consecutive Address Burst
//
// This was used prior to WISHBONE B3 specification
// to identify bursts. It is no longer needed but
// remains enabled for compatibility with old designs.
//
// To remove *wb_cab_o ports undefine this macro.
//
// `define OR1200_WB_CAB
 
//
// WISHBONE B3 compatible interface
//
// This follows the WISHBONE B3 specification.
// It is not enabled by default because most
// designs still don't use WB b3.
//
// To enable *wb_cti_o/*wb_bte_o ports,
// define this macro.
//
//`define OR1200_WB_B3
 
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
 
//
// Enables default statement in some case blocks
// and disables Synopsys synthesis directive full_case
//
// By default it is enabled. When disabled it
// can increase clock frequency.
//
`define OR1200_CASE_DEFAULT
 
//
// Operand width / register file address width
//
// (DO NOT CHANGE)
//
`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5
 
//
// l.add/l.addi/l.and and optional l.addc/l.addic
// also set (compare) flag when result of their
// operation equals zero
//
// At the time of writing this, default or32
// C/C++ compiler doesn't generate code that
// would benefit from this optimization.
//
// By default this optimization is disabled to
// save area.
//
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
 
//
// Implement l.addc/l.addic instructions
//
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// to save area.
//
`define OR1200_IMPL_ADDC
 
//
// Implement carry bit SR[CY]
//
// By default implementation of SR[CY] is enabled
// to be compliant with the simulator. However
// SR[CY] is explicitly only used by l.addc/l.addic
// instructions and if these two insns are not
// implemented there is not much point having SR[CY].
//
`define OR1200_IMPL_CY
 
//
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area and increase clock frequency. or32 C/C++
// compiler can use soft library for division.
//
// To implement divide, multiplier needs to be implemented.
//
//`define OR1200_IMPL_DIV
 
//
// Implement rotate in the ALU
//
// At the time of writing this, or32
// C/C++ compiler doesn't generate rotate
// instructions. However or32 assembler
// can assemble code that uses rotate insn.
// This means that rotate instructions
// must be used manually inserted.
//
// By default implementation of rotate
// is disabled to save area and increase
// clock frequency.
//
//`define OR1200_IMPL_ALU_ROTATE
 
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
 
//
// Implement multiplier
//
// By default multiplier is implemented
//
`define OR1200_MULT_IMPLEMENTED
 
//
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier needs to be
// implemented.
//
`define OR1200_MAC_IMPLEMENTED
 
//
// Low power, slower multiplier
//
// Select between low-power (larger) multiplier
// and faster multiplier. The actual difference
// is only AND logic that prevents distribution
// of operands into the multiplier when instruction
// in execution is not multiply instruction
//
//`define OR1200_LOWPWR_MULT
 
//
// Clock ratio RISC clock versus WB clock
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
//
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
// and use clmode to set ratio
//
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// clmode to set ratio
//
`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
 
//
// Type of register file RAM
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
//`define OR1200_RFRAM_TWOPORT
//
// Memory macro dual port (see or1200_dpram_32x32.v)
//`define OR1200_RFRAM_DUALPORT
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
`define OR1200_RFRAM_GENERIC
 
//
// Type of mem2reg aligner to implement.
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// circuit, however with today tools it will
// most probably give you slower circuit.
//
`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2
 
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH 4
`define OR1200_ALUOP_NOP 4'd4
/* Order defined by arith insns that have two source operands both in regs
(see binutils/include/opcode/or32.h) */
`define OR1200_ALUOP_ADD 4'd0
`define OR1200_ALUOP_ADDC 4'd1
`define OR1200_ALUOP_SUB 4'd2
`define OR1200_ALUOP_AND 4'd3
`define OR1200_ALUOP_OR 4'd4
`define OR1200_ALUOP_XOR 4'd5
`define OR1200_ALUOP_MUL 4'd6
`define OR1200_ALUOP_CUST5 4'd7
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_IMM 4'd11
`define OR1200_ALUOP_MOVHI 4'd12
`define OR1200_ALUOP_COMP 4'd13
`define OR1200_ALUOP_MTSR 4'd14
`define OR1200_ALUOP_MFSR 4'd15
`define OR1200_ALUOP_CMOV 4'd14
`define OR1200_ALUOP_FF1 4'd15
//
// MACOPs
//
`define OR1200_MACOP_WIDTH 2
`define OR1200_MACOP_NOP 2'b00
`define OR1200_MACOP_MAC 2'b01
`define OR1200_MACOP_MSB 2'b10
 
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH 2
`define OR1200_SHROTOP_NOP 2'd0
`define OR1200_SHROTOP_SLL 2'd0
`define OR1200_SHROTOP_SRL 2'd1
`define OR1200_SHROTOP_SRA 2'd2
`define OR1200_SHROTOP_ROR 2'd3
 
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 2
`define OR1200_ONE_CYCLE 2'd0
`define OR1200_TWO_CYCLES 2'd1
 
// Operand MUX selects
`define OR1200_SEL_WIDTH 2
`define OR1200_SEL_RF 2'd0
`define OR1200_SEL_IMM 2'd1
`define OR1200_SEL_EX_FORW 2'd2
`define OR1200_SEL_WB_FORW 2'd3
 
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH 3
`define OR1200_BRANCHOP_NOP 3'd0
`define OR1200_BRANCHOP_J 3'd1
`define OR1200_BRANCHOP_JR 3'd2
`define OR1200_BRANCHOP_BAL 3'd3
`define OR1200_BRANCHOP_BF 3'd4
`define OR1200_BRANCHOP_BNF 3'd5
`define OR1200_BRANCHOP_RFE 3'd6
 
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH 4
`define OR1200_LSUOP_NOP 4'b0000
`define OR1200_LSUOP_LBZ 4'b0010
`define OR1200_LSUOP_LBS 4'b0011
`define OR1200_LSUOP_LHZ 4'b0100
`define OR1200_LSUOP_LHS 4'b0101
`define OR1200_LSUOP_LWZ 4'b0110
`define OR1200_LSUOP_LWS 4'b0111
`define OR1200_LSUOP_LD 4'b0001
`define OR1200_LSUOP_SD 4'b1000
`define OR1200_LSUOP_SB 4'b1010
`define OR1200_LSUOP_SH 4'b1100
`define OR1200_LSUOP_SW 4'b1110
 
// FETCHOPs
`define OR1200_FETCHOP_WIDTH 1
`define OR1200_FETCHOP_NOP 1'b0
`define OR1200_FETCHOP_LW 1'b1
 
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define OR1200_RFWBOP_WIDTH 3
`define OR1200_RFWBOP_NOP 3'b000
`define OR1200_RFWBOP_ALU 3'b001
`define OR1200_RFWBOP_LSU 3'b011
`define OR1200_RFWBOP_SPRS 3'b101
`define OR1200_RFWBOP_LR 3'b111
 
// Compare instructions
`define OR1200_COP_SFEQ 3'b000
`define OR1200_COP_SFNE 3'b001
`define OR1200_COP_SFGT 3'b010
`define OR1200_COP_SFGE 3'b011
`define OR1200_COP_SFLT 3'b100
`define OR1200_COP_SFLE 3'b101
`define OR1200_COP_X 3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH 4
 
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE 4'h0 // idle bus
`define OR1200_ITAG_NI 4'h1 // normal insn
`define OR1200_ITAG_BE 4'hb // Bus error exception
`define OR1200_ITAG_PE 4'hc // Page fault exception
`define OR1200_ITAG_TE 4'hd // TLB miss exception
 
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE 4'h0 // idle bus
`define OR1200_DTAG_ND 4'h1 // normal data
`define OR1200_DTAG_AE 4'ha // Alignment exception
`define OR1200_DTAG_BE 4'hb // Bus error exception
`define OR1200_DTAG_PE 4'hc // Page fault exception
`define OR1200_DTAG_TE 4'hd // TLB miss exception
 
 
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
 
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS 7:6
 
// ALU instructions multicycle field in machine word
`define OR1200_ALUMCYC_POS 9:8
 
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J 6'b000000
`define OR1200_OR32_JAL 6'b000001
`define OR1200_OR32_BNF 6'b000011
`define OR1200_OR32_BF 6'b000100
`define OR1200_OR32_NOP 6'b000101
`define OR1200_OR32_MOVHI 6'b000110
`define OR1200_OR32_XSYNC 6'b001000
`define OR1200_OR32_RFE 6'b001001
/* */
`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011
/* */
`define OR1200_OR32_LWZ 6'b100001
`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111
`define OR1200_OR32_ADDIC 6'b101000
`define OR1200_OR32_ANDI 6'b101001
`define OR1200_OR32_ORI 6'b101010
`define OR1200_OR32_XORI 6'b101011
`define OR1200_OR32_MULI 6'b101100
`define OR1200_OR32_MFSPR 6'b101101
`define OR1200_OR32_SH_ROTI 6'b101110
`define OR1200_OR32_SFXXI 6'b101111
/* */
`define OR1200_OR32_MTSPR 6'b110000
`define OR1200_OR32_MACMSB 6'b110001
/* */
`define OR1200_OR32_SW 6'b110101
`define OR1200_OR32_SB 6'b110110
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
//`define OR1200_OR32_CUST5 6'b111100
 
 
/////////////////////////////////////////////////////
//
// Exceptions
//
 
//
// Exception vectors per OR1K architecture:
// 0xPPPPP100 - reset
// 0xPPPPP200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPPPPPNVV - exception N
//
// P represents exception prefix
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
 
//
// PPPPP and VV parts
//
// Sum of these two defines needs to be 28
//
`define OR1200_EXCEPT_EPH0_P 20'h00000
`define OR1200_EXCEPT_EPH1_P 20'hF0000
`define OR1200_EXCEPT_V 8'h00
 
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
 
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
 
 
/////////////////////////////////////////////////////
//
// SPR groups
//
 
// Bits that define the group
`define OR1200_SPR_GROUP_BITS 15:11
 
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH 5
 
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
 
// List of groups
`define OR1200_SPR_GROUP_SYS 5'd00
`define OR1200_SPR_GROUP_DMMU 5'd01
`define OR1200_SPR_GROUP_IMMU 5'd02
`define OR1200_SPR_GROUP_DC 5'd03
`define OR1200_SPR_GROUP_IC 5'd04
`define OR1200_SPR_GROUP_MAC 5'd05
`define OR1200_SPR_GROUP_DU 5'd06
`define OR1200_SPR_GROUP_PM 5'd08
`define OR1200_SPR_GROUP_PIC 5'd09
`define OR1200_SPR_GROUP_TT 5'd10
 
 
/////////////////////////////////////////////////////
//
// System group
//
 
//
// System registers
//
`define OR1200_SPR_CFGR 7'd0
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
`define OR1200_SPR_NPC 11'd16
`define OR1200_SPR_SR 11'd17
`define OR1200_SPR_PPC 11'd18
`define OR1200_SPR_EPCR 11'd32
`define OR1200_SPR_EEAR 11'd48
`define OR1200_SPR_ESR 11'd64
 
//
// SR bits
//
`define OR1200_SR_WIDTH 16
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
`define OR1200_SR_IME 6
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Unused
`define OR1200_SR_OV 11 // Unused
`define OR1200_SR_OVE 12 // Unused
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_CID 31:28 // Unimplemented
 
//
// Bits that define offset inside the group
//
`define OR1200_SPROFS_BITS 10:0
 
//
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b0
 
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
 
// Define it if you want PM implemented
`define OR1200_PM_IMPLEMENTED
 
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
 
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
 
// PM group
`define OR1200_SPRGRP_PM 5'd8
 
// Define if PMR can be read/written at any address inside PM group
`define OR1200_PM_PARTIAL_DECODING
 
// Define if reading PMR is allowed
`define OR1200_PM_READREGS
 
// Define if unused PMR bits should be zero
`define OR1200_PM_UNUSED_ZERO
 
 
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
 
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
 
//
// Define if you want HW Breakpoints
// (if HW breakpoints are not implemented
// only default software trapping is
// possible with l.trap insn - this is
// however already enough for use
// with or32 gdb)
//
//`define OR1200_DU_HWBKPTS
 
// Number of DVR/DCR pairs if HW breakpoints enabled
`define OR1200_DU_DVRDCR_PAIRS 8
 
// Define if you want trace buffer
//`define OR1200_DU_TB_IMPLEMENTED
 
//
// Address offsets of DU registers inside DU group
//
// To not implement a register, doq not define its address
//
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0 11'd0
`define OR1200_DU_DVR1 11'd1
`define OR1200_DU_DVR2 11'd2
`define OR1200_DU_DVR3 11'd3
`define OR1200_DU_DVR4 11'd4
`define OR1200_DU_DVR5 11'd5
`define OR1200_DU_DVR6 11'd6
`define OR1200_DU_DVR7 11'd7
`define OR1200_DU_DCR0 11'd8
`define OR1200_DU_DCR1 11'd9
`define OR1200_DU_DCR2 11'd10
`define OR1200_DU_DCR3 11'd11
`define OR1200_DU_DCR4 11'd12
`define OR1200_DU_DCR5 11'd13
`define OR1200_DU_DCR6 11'd14
`define OR1200_DU_DCR7 11'd15
`endif
`define OR1200_DU_DMR1 11'd16
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DMR2 11'd17
`define OR1200_DU_DWCR0 11'd18
`define OR1200_DU_DWCR1 11'd19
`endif
`define OR1200_DU_DSR 11'd20
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1xx
`define OR1200_DU_TBIM 11'h2xx
`define OR1200_DU_TBAR 11'h3xx
`define OR1200_DU_TBTS 11'h4xx
`endif
 
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 10:0
 
// DCR bits
`define OR1200_DU_DCR_DP 0
`define OR1200_DU_DCR_CC 3:1
`define OR1200_DU_DCR_SC 4
`define OR1200_DU_DCR_CT 7:5
 
// DMR1 bits
`define OR1200_DU_DMR1_CW0 1:0
`define OR1200_DU_DMR1_CW1 3:2
`define OR1200_DU_DMR1_CW2 5:4
`define OR1200_DU_DMR1_CW3 7:6
`define OR1200_DU_DMR1_CW4 9:8
`define OR1200_DU_DMR1_CW5 11:10
`define OR1200_DU_DMR1_CW6 13:12
`define OR1200_DU_DMR1_CW7 15:14
`define OR1200_DU_DMR1_CW8 17:16
`define OR1200_DU_DMR1_CW9 19:18
`define OR1200_DU_DMR1_CW10 21:20
`define OR1200_DU_DMR1_ST 22
`define OR1200_DU_DMR1_BT 23
`define OR1200_DU_DMR1_DXFW 24
`define OR1200_DU_DMR1_ETE 25
 
// DMR2 bits
`define OR1200_DU_DMR2_WCE0 0
`define OR1200_DU_DMR2_WCE1 1
`define OR1200_DU_DMR2_AWTC 12:2
`define OR1200_DU_DMR2_WGB 23:13
 
// DWCR bits
`define OR1200_DU_DWCR_COUNT 15:0
`define OR1200_DU_DWCR_MATCH 31:16
 
// DSR bits
`define OR1200_DU_DSR_WIDTH 14
`define OR1200_DU_DSR_RSTE 0
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
`define OR1200_DU_DSR_SCE 11
`define OR1200_DU_DSR_BE 12
`define OR1200_DU_DSR_TE 13
 
// DRR bits
`define OR1200_DU_DRR_RSTE 0
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
`define OR1200_DU_DRR_SCE 11
`define OR1200_DU_DRR_BE 12
`define OR1200_DU_DRR_TE 13
 
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
 
// Define if unused DU registers bits should be zero
`define OR1200_DU_UNUSED_ZERO
 
// Define if IF/LSU status is not needed by devel i/f
`define OR1200_DU_STATUS_UNIMPLEMENTED
 
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
 
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
 
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 20
 
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
 
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
 
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
 
// Define if reading PIC registers is allowed
`define OR1200_PIC_READREGS
 
// Define if unused PIC register bits should be zero
`define OR1200_PIC_UNUSED_ZERO
 
 
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
 
// Define it if you want TT implemented
`define OR1200_TT_IMPLEMENTED
 
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
 
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
 
// Define if you want these TT registers to be implemented
`define OR1200_TT_TTMR
`define OR1200_TT_TTCR
 
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
 
// Define if reading TT registers is allowed
`define OR1200_TT_READREGS
 
 
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
 
//
// Shift {MACHI,MACLO} into destination register when executing l.macrc
//
// According to architecture manual there is no shift, so default value is 0.
//
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
// dest_GPR = {MACHI,MACLO}[59:28]
`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility
 
 
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
 
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR 7
 
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS 0
`define OR1200_DTLBMR_CID_BITS 4:1
`define OR1200_DTLBMR_RES_BITS 11:5
`define OR1200_DTLBMR_VPN_BITS 31:13
 
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS 0
`define OR1200_DTLBTR_CI_BITS 1
`define OR1200_DTLBTR_WBC_BITS 2
`define OR1200_DTLBTR_WOM_BITS 3
`define OR1200_DTLBTR_A_BITS 4
`define OR1200_DTLBTR_D_BITS 5
`define OR1200_DTLBTR_URE_BITS 6
`define OR1200_DTLBTR_UWE_BITS 7
`define OR1200_DTLBTR_SRE_BITS 8
`define OR1200_DTLBTR_SWE_BITS 9
`define OR1200_DTLBTR_RES_BITS 11:10
`define OR1200_DTLBTR_PPN_BITS 31:13
 
//
// DTLB configuration
//
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
 
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_DMMU_CI dcpu_adr_i[31]
 
 
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
 
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR 7
 
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS 0
`define OR1200_ITLBMR_CID_BITS 4:1
`define OR1200_ITLBMR_RES_BITS 11:5
`define OR1200_ITLBMR_VPN_BITS 31:13
 
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS 0
`define OR1200_ITLBTR_CI_BITS 1
`define OR1200_ITLBTR_WBC_BITS 2
`define OR1200_ITLBTR_WOM_BITS 3
`define OR1200_ITLBTR_A_BITS 4
`define OR1200_ITLBTR_D_BITS 5
`define OR1200_ITLBTR_SXE_BITS 6
`define OR1200_ITLBTR_UXE_BITS 7
`define OR1200_ITLBTR_RES_BITS 11:8
`define OR1200_ITLBTR_PPN_BITS 31:13
 
//
// ITLB configuration
//
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
 
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_IMMU_CI 1'b0
 
 
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_ICLS 4
 
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
`define OR1200_ICTAG_W 21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE 13 // 8192
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
`define OR1200_ICTAG_W 20
`endif
 
 
/////////////////////////////////////////////////
//
// Data cache (DC)
//
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_DCLS 4
 
// Define to perform store refill (potential performance penalty)
// `define OR1200_DC_STORE_REFILL
 
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE 12 // 4096
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
`define OR1200_DCTAG_W 21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE 13 // 8192
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
`define OR1200_DCTAG_W 20
`endif
 
/////////////////////////////////////////////////
//
// Store buffer (SB)
//
 
//
// Store buffer
//
// It will improve performance by "caching" CPU stores
// using store buffer. This is most important for function
// prologues because DC can only work in write though mode
// and all stores would have to complete external WB writes
// to memory.
// Store buffer is between DC and data BIU.
// All stores will be stored into store buffer and immediately
// completed by the CPU, even though actual external writes
// will be performed later. As a consequence store buffer masks
// all data bus errors related to stores (data bus errors
// related to loads are delivered normally).
// All pending CPU loads will wait until store buffer is empty to
// ensure strict memory model. Right now this is necessary because
// we don't make destinction between cached and cache inhibited
// address space, so we simply empty store buffer until loads
// can begin.
//
// It makes design a bit bigger, depending what is the number of
// entries in SB FIFO. Number of entries can be changed further
// down.
//
//`define OR1200_SB_IMPLEMENTED
 
//
// Number of store buffer entries
//
// Verified number of entries are 4 and 8 entries
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
// always match 2**OR1200_SB_LOG.
// To disable store buffer, undefine
// OR1200_SB_IMPLEMENTED.
//
`define OR1200_SB_LOG 2 // 2 or 3
`define OR1200_SB_ENTRIES 4 // 4 or 8
 
 
/////////////////////////////////////////////////
//
// Quick Embedded Memory (QMEM)
//
 
//
// Quick Embedded Memory
//
// Instantiation of dedicated insn/data memory (RAM or ROM).
// Insn fetch has effective throughput 1insn / clock cycle.
// Data load takes two clock cycles / access, data store
// takes 1 clock cycle / access (if there is no insn fetch)).
// Memory instantiation is shared between insn and data,
// meaning if insn fetch are performed, data load/store
// performance will be lower.
//
// Main reason for QMEM is to put some time critical functions
// into this memory and to have predictable and fast access
// to these functions. (soft fpu, context switch, exception
// handlers, stack, etc)
//
// It makes design a bit bigger and slower. QMEM sits behind
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
//
`define OR1200_QMEM_IMPLEMENTED
 
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
`define OR1200_QMEM_IADDR 32'h0080_0000
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
`define OR1200_QMEM_DADDR 32'h0080_0000
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
 
//
// QMEM interface byte-select capability
//
// To enable qmem_sel* ports, define this macro.
//
//`define OR1200_QMEM_BSEL
 
//
// QMEM interface acknowledge
//
// To enable qmem_ack port, define this macro.
//
//`define OR1200_QMEM_ACK
 
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
//
//
// VR, UPR and configuration registers are optional. If
// implemented, operating system can automatically figure
// out how to use the processor because it knows
// what units are available in the processor and how they
// are configured.
//
// This section must be last in or1200_defines.v file so
// that all units are already configured and thus
// configuration registers are properly set.
//
 
// Define if you want configuration registers implemented
`define OR1200_CFGR_IMPLEMENTED
 
// Define if you want full address decode inside SYS group
`define OR1200_SYS_FULL_DECODE
 
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR 4'h0
`define OR1200_SPRGRP_SYS_UPR 4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
 
// VR fields
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_RES1_BITS 15:6
`define OR1200_VR_CFG_BITS 23:16
`define OR1200_VR_VER_BITS 31:24
 
// VR values
`define OR1200_VR_REV 6'h01
`define OR1200_VR_RES1 10'h000
`define OR1200_VR_CFG 8'h00
`define OR1200_VR_VER 8'h12
 
// UPR fields
`define OR1200_UPR_UP_BITS 0
`define OR1200_UPR_DCP_BITS 1
`define OR1200_UPR_ICP_BITS 2
`define OR1200_UPR_DMP_BITS 3
`define OR1200_UPR_IMP_BITS 4
`define OR1200_UPR_MP_BITS 5
`define OR1200_UPR_DUP_BITS 6
`define OR1200_UPR_PCUP_BITS 7
`define OR1200_UPR_PMP_BITS 8
`define OR1200_UPR_PICP_BITS 9
`define OR1200_UPR_TTP_BITS 10
`define OR1200_UPR_RES1_BITS 23:11
`define OR1200_UPR_CUP_BITS 31:24
 
// UPR values
`define OR1200_UPR_UP 1'b1
`ifdef OR1200_NO_DC
`define OR1200_UPR_DCP 1'b0
`else
`define OR1200_UPR_DCP 1'b1
`endif
`ifdef OR1200_NO_IC
`define OR1200_UPR_ICP 1'b0
`else
`define OR1200_UPR_ICP 1'b1
`endif
`ifdef OR1200_NO_DMMU
`define OR1200_UPR_DMP 1'b0
`else
`define OR1200_UPR_DMP 1'b1
`endif
`ifdef OR1200_NO_IMMU
`define OR1200_UPR_IMP 1'b0
`else
`define OR1200_UPR_IMP 1'b1
`endif
`define OR1200_UPR_MP 1'b1 // MAC always present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_DUP 1'b1
`else
`define OR1200_UPR_DUP 1'b0
`endif
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PMP 1'b1
`else
`define OR1200_UPR_PMP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PICP 1'b1
`else
`define OR1200_UPR_PICP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_TTP 1'b1
`else
`define OR1200_UPR_TTP 1'b0
`endif
`define OR1200_UPR_RES1 13'h0000
`define OR1200_UPR_CUP 8'h00
 
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS 3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS 5
`define OR1200_CPUCFGR_OB64S_BITS 6
`define OR1200_CPUCFGR_OF32S_BITS 7
`define OR1200_CPUCFGR_OF64S_BITS 8
`define OR1200_CPUCFGR_OV64S_BITS 9
`define OR1200_CPUCFGR_RES1_BITS 31:10
 
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF 4'h0
`define OR1200_CPUCFGR_HGF 1'b0
`define OR1200_CPUCFGR_OB32S 1'b1
`define OR1200_CPUCFGR_OB64S 1'b0
`define OR1200_CPUCFGR_OF32S 1'b0
`define OR1200_CPUCFGR_OF64S 1'b0
`define OR1200_CPUCFGR_OV64S 1'b0
`define OR1200_CPUCFGR_RES1 22'h000000
 
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS 1:0
`define OR1200_DMMUCFGR_NTS_BITS 4:2
`define OR1200_DMMUCFGR_NAE_BITS 7:5
`define OR1200_DMMUCFGR_CRI_BITS 8
`define OR1200_DMMUCFGR_PRI_BITS 9
`define OR1200_DMMUCFGR_TEIRI_BITS 10
`define OR1200_DMMUCFGR_HTR_BITS 11
`define OR1200_DMMUCFGR_RES1_BITS 31:12
 
// DMMUCFGR values
`ifdef OR1200_NO_DMMU
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_RES1 20'h00000
`else
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
 
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS 1:0
`define OR1200_IMMUCFGR_NTS_BITS 4:2
`define OR1200_IMMUCFGR_NAE_BITS 7:5
`define OR1200_IMMUCFGR_CRI_BITS 8
`define OR1200_IMMUCFGR_PRI_BITS 9
`define OR1200_IMMUCFGR_TEIRI_BITS 10
`define OR1200_IMMUCFGR_HTR_BITS 11
`define OR1200_IMMUCFGR_RES1_BITS 31:12
 
// IMMUCFGR values
`ifdef OR1200_NO_IMMU
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_RES1 20'h00000
`else
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
 
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS 2:0
`define OR1200_DCCFGR_NCS_BITS 6:3
`define OR1200_DCCFGR_CBS_BITS 7
`define OR1200_DCCFGR_CWS_BITS 8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS 10
`define OR1200_DCCFGR_CBPRI_BITS 11
`define OR1200_DCCFGR_CBLRI_BITS 12
`define OR1200_DCCFGR_CBFRI_BITS 13
`define OR1200_DCCFGR_CBWBRI_BITS 14
`define OR1200_DCCFGR_RES1_BITS 31:15
 
// DCCFGR values
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_RES1 17'h00000
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
`define OR1200_DCCFGR_RES1 17'h00000
`endif
 
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS 2:0
`define OR1200_ICCFGR_NCS_BITS 6:3
`define OR1200_ICCFGR_CBS_BITS 7
`define OR1200_ICCFGR_CWS_BITS 8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS 10
`define OR1200_ICCFGR_CBPRI_BITS 11
`define OR1200_ICCFGR_CBLRI_BITS 12
`define OR1200_ICCFGR_CBFRI_BITS 13
`define OR1200_ICCFGR_CBWBRI_BITS 14
`define OR1200_ICCFGR_RES1_BITS 31:15
 
// ICCFGR values
`ifdef OR1200_NO_IC
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`endif
 
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS 2:0
`define OR1200_DCFGR_WPCI_BITS 3
`define OR1200_DCFGR_RES1_BITS 31:4
 
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI 1'b1
`else
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`else
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 28'h0000000
/soc_maker/trunk/core_lib/cores/ram_wb/ram_wb_b3.v.in
0,0 → 1,259
//`include "synthesis-defines.v"
module ram_wb_b3(
wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
 
wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
 
wb_clk_i, wb_rst_i);
 
parameter dw = 32;
parameter aw = 32;
 
input [aw-1:0] wb_adr_i;
input [1:0] wb_bte_i;
input [2:0] wb_cti_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
output [dw-1:0] wb_dat_o;
input wb_clk_i;
input wb_rst_i;
 
// Memory parameters
// parameter mem_size_bytes = 32'h0000_5000; // 20KBytes
// parameter mem_adr_width = 15; //(log2(mem_size_bytes));
parameter mem_size_kbytes = TOK_MEM_SIZE ; // 20KBytes
parameter mem_adr_width = TOK_MEM_ADR_WIDTH ; //(log2(mem_size_bytes));
parameter bytes_per_dw = (dw/8);
parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
parameter mem_words = (mem_size_kbytes * 1024/bytes_per_dw);
 
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
 
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
wire [31:0] wr_data;
 
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
wire wb_b3_trans_start, wb_b3_trans_stop;
// Register to use for counting the addresses when doing burst accesses
reg [mem_adr_width-adr_width_for_num_word_bytes-1:0] burst_adr_counter;
reg [2:0] wb_cti_i_r;
reg [1:0] wb_bte_i_r;
wire using_burst_adr;
wire burst_access_wrong_wb_adr;
 
// Wire to indicate addressing error
wire addr_err;
// Logic to detect if there's a burst access going on
assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans;
assign wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
 
// Burst address generation logic
always @(/*AUTOSENSE*/wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or adr)
if (wb_b3_trans_start)
// Kick off burst_adr_counter, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
burst_adr_counter = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
// Incrementing burst
begin
if (wb_bte_i_r == 2'b00) // Linear burst
burst_adr_counter = adr + 1;
if (wb_bte_i_r == 2'b01) // 4-beat wrap burst
burst_adr_counter[1:0] = adr[1:0] + 1;
if (wb_bte_i_r == 2'b10) // 8-beat wrap burst
burst_adr_counter[2:0] = adr[2:0] + 1;
if (wb_bte_i_r == 2'b11) // 16-beat wrap burst
burst_adr_counter[3:0] = adr[3:0] + 1;
end // if ((wb_cti_i_r == 3'b010) & wb_ack_o_r)
 
always @(posedge wb_clk_i)
wb_bte_i_r <= wb_bte_i;
 
// Register it locally
always @(posedge wb_clk_i)
wb_cti_i_r <= wb_cti_i;
 
assign using_burst_adr = wb_b3_trans;
assign burst_access_wrong_wb_adr = (using_burst_adr &
(adr != wb_adr_i[mem_adr_width-1:2]));
 
// Address registering logic
always@(posedge wb_clk_i)
if(wb_rst_i)
adr <= 0;
else if (using_burst_adr)
adr <= burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr <= wb_adr_i[mem_adr_width-1:2];
 
/* Memory initialisation.
If not Verilator model, always do load, otherwise only load when called
from SystemC testbench.
*/
// synthesis translate_off
parameter memory_file = "sram.vmem";
 
`ifdef verilator
task do_readmemh;
// verilator public
$readmemh(memory_file, mem);
endtask // do_readmemh
`else
initial
begin
$readmemh(memory_file, mem);
end
 
`endif // !`ifdef verilator
//synthesis translate_on
assign wb_rty_o = 0;
 
// mux for data to ram, RMW on part sel != 4'hf
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we;
assign ram_we = wb_we_i & wb_ack_o;
 
assign wb_dat_o = mem[adr];
// Write logic
always @ (posedge wb_clk_i)
begin
if (ram_we)
mem[adr] <= wr_data;
end
// Ack Logic
reg wb_ack_o_r;
 
assign wb_ack_o = wb_ack_o_r & wb_stb_i &
!(burst_access_wrong_wb_adr | addr_err);
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) // We have bus
begin
if (addr_err & wb_stb_i)
begin
wb_ack_o_r <= 1;
end
else if (wb_cti_i == 3'b000)
begin
// Classic cycle acks
if (wb_stb_i)
begin
if (!wb_ack_o_r)
wb_ack_o_r <= 1;
else
wb_ack_o_r <= 0;
end
end // if (wb_cti_i == 3'b000)
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010))
begin
// Increment/constant address bursts
if (wb_stb_i)
wb_ack_o_r <= 1;
else
wb_ack_o_r <= 0;
end
else if (wb_cti_i == 3'b111)
begin
// End of cycle
if (!wb_ack_o_r)
wb_ack_o_r <= wb_stb_i;
else
wb_ack_o_r <= 0;
end
end // if (wb_cyc_i)
else
wb_ack_o_r <= 0;
 
 
//
// Error signal generation
//
// Error when out of bounds of memory - skip top nibble of address in case
// this is mapped somewhere other than 0x0.
assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-4:mem_adr_width]);
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr | addr_err);
 
//
// Access functions
//
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
 
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
 
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
mem[addr] = data;
endfunction // set_mem32
endmodule // ram_wb_b3
 
soc_maker/trunk/core_lib/cores/ram_wb/ram_wb_b3.v.in Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: soc_maker/trunk/core_lib/cores/ram_wb/ram_wb.yaml =================================================================== --- soc_maker/trunk/core_lib/cores/ram_wb/ram_wb.yaml (revision 7) +++ soc_maker/trunk/core_lib/cores/ram_wb/ram_wb.yaml (revision 8) @@ -6,7 +6,7 @@ licensefile: author: authormail: -vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb@655 rtl +vccmd: toplevel: ram_wb_b3 interfaces: @@ -58,9 +58,24 @@ len: 1 defn: rst -hdlfiles: - :ram_wb_b3: SOCM_HDL_FILE - use_syn: true - use_sim: true - type: verilog - path: rtl/ram_wb_b3.v +static_parameters: + :ram_wb_b3: SOCM_SPARAM + dir: . + path: ./ram_wb_b3.v.in + file_dst: ram_wb_b3.v + parameters: + + :MEM_SIZE: SOCM_SENTRY + token: TOK_MEM_SIZE + type: integer + visible: true + editable: true + default: 20 + + :MEM_ADR_WIDTH: SOCM_SENTRY + token: TOK_MEM_ADR_WIDTH + type: integer + visible: true + editable: true + default: 15 +
/soc_maker/trunk/examples/or1200_test/or1200_test.rb
1,4 → 1,4
require_relative '../lib/soc_maker'
require_relative '../../lib/soc_maker'
 
options = {}
options[ :libpath ] = "./core_lib/"
37,7 → 37,7
'tck_i' => SOCMaker::IfcPort.new( 'tck', 1 ),
'tdi_i' => SOCMaker::IfcPort.new( 'tdi', 1 ),
'tdo_o' => SOCMaker::IfcPort.new( 'tdo' ,1 ),
'debug_rst_i' => SOCMaker::IfcPort.new( 'rst', 1 ),
'debug_rst_i' => SOCMaker::IfcPort.new( 'rst', 1 ),
'shift_dr_i' => SOCMaker::IfcPort.new( 'shift', 1 ),
'pause_dr_i' => SOCMaker::IfcPort.new( 'pause', 1 ),
'update_dr_i' => SOCMaker::IfcPort.new( 'update', 1 ),
44,29 → 44,80
'capture_dr_i' => SOCMaker::IfcPort.new( 'capture', 1 ),
'debug_select_i' => SOCMaker::IfcPort.new( 'select', 1 ) } )
 
soc.interfaces[ 'uart_ifc'.to_sym ] = SOCMaker::IfcDef.new( 'uart', '1', 1, {
'stx_pad_o' => SOCMaker::IfcPort.new( 'stx_pad', 1 ),
'srx_pad_i' => SOCMaker::IfcPort.new( 'srx_pad', 1 ),
'rts_pad_o' => SOCMaker::IfcPort.new( 'rts_pad', 1 ),
'cts_pad_i' => SOCMaker::IfcPort.new( 'cts_pad', 1 ),
'dtr_pad_o' => SOCMaker::IfcPort.new( 'dtr_pad', 1 ),
'dsr_pad_i' => SOCMaker::IfcPort.new( 'dsr_pad', 1 ),
'ri_pad_i' => SOCMaker::IfcPort.new( 'ri_pad' , 1 ),
'dcd_pad_i' => SOCMaker::IfcPort.new( 'dcd_pad', 1 ) } )
 
 
soc.add_core( 'or1200', 'rel2', 'cpu' )
soc.add_core( 'wb_connect', '1', 'wb_bus' )
soc.add_core( 'adv_debug_sys', 'ads_3', 'dbg' )
soc.add_core( 'ram_wb', 'b3', 'ram' )
soc.add_core( 'ram_wb', 'b3', 'ram1' )
soc.add_core( 'ram_wb', 'b3', 'ram2' )
soc.add_core( 'uart16550', 'rel4', 'uart' )
soc.consistency_check
 
 
#
# Setup the CPU
#
soc.set_sparam( 'or1200rel2', 'VCD_DUMP', false )
soc.set_sparam( 'or1200rel2', 'VERBOSE', false )
soc.set_sparam( 'or1200rel2', 'ASIC' , false )
 
soc.set_sparam( 'or1200rel2', 'ASIC_MEM_CHOICE', 0 )
soc.set_sparam( 'or1200rel2', 'ASIC_NO_DC', true )
soc.set_sparam( 'or1200rel2', 'ASIC_NO_IC', true )
soc.set_sparam( 'or1200rel2', 'ASIC_NO_DMMU', true )
soc.set_sparam( 'or1200rel2', 'ASIC_NO_IMMU', true )
soc.set_sparam( 'or1200rel2', 'ASIC_MUL_CHOICE', 0 )
soc.set_sparam( 'or1200rel2', 'ASIC_IC_CHOICE', 0 )
soc.set_sparam( 'or1200rel2', 'ASIC_DC_CHOICE', 0 )
 
 
soc.set_sparam( 'or1200rel2', 'FPGA_MEM_CHOICE', 0 )
soc.set_sparam( 'or1200rel2', 'FPGA_NO_DC', true )
soc.set_sparam( 'or1200rel2', 'FPGA_NO_IC', true )
soc.set_sparam( 'or1200rel2', 'FPGA_NO_DMMU', true )
soc.set_sparam( 'or1200rel2', 'FPGA_NO_IMMU', true )
soc.set_sparam( 'or1200rel2', 'FPGA_MUL_CHOICE', 1 )
soc.set_sparam( 'or1200rel2', 'FPGA_IC_CHOICE', 0 )
soc.set_sparam( 'or1200rel2', 'FPGA_DC_CHOICE', 0 )
 
#
# Setup the on-chip memory
#
soc.set_sparam( 'ram_wbb3', 'MEM_SIZE', 20 )
soc.set_sparam( 'ram_wbb3', 'MEM_ADR_WIDTH', 17 )
 
 
#
#
#
 
soc.add_connection( 'or1200_test', 'clk_ifc', 'cpu', 'clk', 'con_main_clk' )
soc.add_connection( 'or1200_test', 'rst_ifc', 'cpu', 'rst', 'con_main_rst' )
soc.add_connection( 'or1200_test', 'clk_ifc', 'wb_bus', 'clk', 'con_main_clk' )
soc.add_connection( 'or1200_test', 'rst_ifc', 'wb_bus', 'rst', 'con_main_rst' )
 
soc.add_connection( 'wb_bus', 'i0', 'cpu', 'wb_instruction', 'con_instruction' )
soc.add_connection( 'wb_bus', 'i1', 'cpu', 'wb_data', 'con_data' )
soc.add_connection( 'wb_bus', 'i2', 'dbg', 'wb_ifc', 'con_wb_debug' )
soc.add_connection( 'wb_bus', 't1', 'ram', 'wb_ifc', 'con_ram' )
soc.add_connection( 'wb_bus', 'i3', 'dbg', 'wb_ifc', 'con_wb_debug' )
soc.add_connection( 'wb_bus', 'i4', 'cpu', 'wb_data', 'con_data' )
soc.add_connection( 'wb_bus', 'i5', 'cpu', 'wb_instruction', 'con_instruction' )
soc.add_connection( 'wb_bus', 't0', 'ram1', 'wb_ifc', 'con_ram1' )
soc.add_connection( 'wb_bus', 't1', 'ram2', 'wb_ifc', 'con_ram2' )
soc.add_connection( 'wb_bus', 't2', 'uart', 'wb_ifc', 'con_uart' )
 
soc.add_connection( 'dbg', 'cpu0_dbg', 'cpu', 'ext_debug', 'con_debug' )
 
soc.add_connection( 'or1200_test', 'clk_ifc', 'dbg', 'cpu0_dbg_clk', 'con_main_clk' )
soc.add_connection( 'or1200_test', 'jtag_ifc', 'dbg', 'jtag', 'con_jtag' )
soc.add_connection( 'or1200_test', 'jtag_ifc', 'dbg', 'jtag', 'con_jtag_top' )
soc.add_connection( 'or1200_test', 'uart_ifc', 'uart', 'uart_ifc', 'con_uart_top' )
 
soc_inst.consistency_check
soc_inst.gen_toplevel

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