URL
https://opencores.org/ocsvn/spi/spi/trunk
Subversion Repositories spi
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/bench/verilog/tb_spi_top.v
338,6 → 338,32
else |
$display("status: %t transfer completed: 0xf7b3d591 != 0x%x 0x01234567 != 0x%x nok", $time, i_spi_slave.data, q); |
|
i_wb_master.wb_write(0, SPI_TX_L, 32'hffeeddcc); |
i_wb_master.wb_write(0, SPI_TX_H, 32'hbbaa9988); |
i_wb_master.wb_write(0, SPI_CTRL, 32'he06); // ass, set 64 bit transfer, ie, lsb, rx negedge, tx negedge |
i_wb_master.wb_write(0, SPI_CTRL, 32'he07); // set 64 bit transfer, start transfer |
|
$display("status: %t generate transfer: 64 bit (0xffeeddccbbaa9988), ass, msb first, tx negedge, rx negedge", $time); |
|
// Check interrupt signal |
while (!int) |
@(posedge clk); |
|
i_wb_master.wb_read(1, SPI_RX_H, q); |
|
@(posedge clk); |
if (int) |
$display("status: %t transfer completed: interrupt still active nok", $time, i_spi_slave.data, q); |
|
if (i_spi_slave.data == 32'h119955dd && q == 32'hffeeddcc) |
$display("status: %t transfer completed: 0x119955dd == 0x%x 0xffeeddcc == 0x%x ok", $time, i_spi_slave.data, q); |
else if (i_spi_slave.data == 32'h119955dd) |
$display("status: %t transfer completed: 0x119955dd == 0x%x 0xffeeddcc != 0x%x nok", $time, i_spi_slave.data, q); |
else if (q == 32'h119955dd) |
$display("status: %t transfer completed: 0x119955dd != 0x%x 0xffeeddcc == 0x%x nok", $time, i_spi_slave.data, q); |
else |
$display("status: %t transfer completed: 0x119955dd != 0x%x 0xffeeddcc != 0x%x nok", $time, i_spi_slave.data, q); |
|
$display("\n\nstatus: %t Testbench done", $time); |
|
#25000; // wait 25us |
/trunk/bench/verilog/spi_slave_model.v
60,7 → 60,7
begin |
if (rst) |
data <= #Tp 32'b0; |
else |
else if (!ss) |
data <= #Tp {data[30:0], mosi}; |
end |
|
/trunk/rtl/verilog/spi_top.v
91,6 → 91,7
wire go; // go |
wire lsb; // lsb first on line |
wire ie; // interrupt enable |
wire ass; // automatic slave select |
wire spi_divider_sel; // divider register select |
wire spi_ctrl_sel; // ctrl register select |
wire spi_tx_sel_l; // tx_l register select |
185,6 → 186,7
ctrl[`SPI_CTRL_CHAR_LEN] <= #Tp wb_dat_i[`SPI_CTRL_CHAR_LEN]; |
ctrl[`SPI_CTRL_LSB] <= #Tp wb_dat_i[`SPI_CTRL_LSB]; |
ctrl[`SPI_CTRL_IE] <= #Tp wb_dat_i[`SPI_CTRL_IE]; |
ctrl[`SPI_CTRL_ASS] <= #Tp wb_dat_i[`SPI_CTRL_ASS]; |
end |
else if(tip && last_bit && pos_edge) |
ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; |
196,6 → 198,7
assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; |
assign lsb = ctrl[`SPI_CTRL_LSB]; |
assign ie = ctrl[`SPI_CTRL_IE]; |
assign ass = ctrl[`SPI_CTRL_ASS]; |
|
// Slave select register |
always @(posedge wb_clk_i or posedge wb_rst_i) |
206,7 → 209,7
ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; |
end |
|
assign ss_pad_o = ~ss; |
assign ss_pad_o = ~((ss & tip & ass) | (ss & !ass)); |
|
spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .enable(tip), .last_clk(last_bit), |
.divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), |
/trunk/rtl/verilog/spi_defines.v
78,11 → 78,12
// |
// Number of bits in ctrl register |
// |
`define SPI_CTRL_BIT_NB 11 |
`define SPI_CTRL_BIT_NB 12 |
|
// |
// Control register bit position |
// |
`define SPI_CTRL_ASS 11 |
`define SPI_CTRL_IE 10 |
`define SPI_CTRL_LSB 9 |
`define SPI_CTRL_CHAR_LEN 8:3 |
/trunk/doc/spi.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/doc/src/spi.doc
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream