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https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
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/srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap_fsm.v
1,5 → 1,6
module port_ring_tap_fsm |
#(parameter rdp_sz = 64, |
parameter pdp_sz = 64, |
parameter portnum = 0) |
( |
input clk, |
7,24 → 8,23
|
output reg lfli_drdy, |
output reg lprx_drdy, |
output reg[rdp_sz-1:0] lptx_data, |
output reg[pdp_sz-1:0] lptx_data, |
output reg lptx_srdy, |
output reg lri_drdy, |
output reg[rdp_sz-1:0] lro_data, |
output reg lro_srdy, |
|
input [rdp_sz-1:0] lfli_data, |
input [`NUM_PORTS-1:0] lfli_data, |
input lfli_srdy, |
input [rdp_sz-1:0] lprx_data, |
input [pdp_sz-1:0] lprx_data, |
input lprx_srdy, |
input lptx_drdy, |
input [rdp_sz-1:0] lri_data, |
input lri_srdy, |
input lro_drdy |
// End of automatics |
); |
|
reg [6:0] state, nxt_state; |
reg [4:0] state, nxt_state; |
|
wire [`NUM_PORTS-1:0] port_mask; |
reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec; |
31,17 → 31,26
|
assign port_mask = 1 << portnum; |
|
parameter s_idle = 0, |
s_rcmd = 1, |
s_rfwd = 2, |
s_rcopy = 3, |
s_rsink = 4, |
s_tcmd = 5, |
s_tdata = 6; |
localparam s_idle = 0, |
s_rfwd = 1, |
s_rcopy = 2, |
s_rsink = 3, |
s_tdata = 4; |
localparam ns_idle = 1, |
ns_rfwd = 2, |
ns_rcopy = 4, |
ns_rsink = 8, |
ns_tdata = 16; |
|
always @* |
begin |
lro_data = lri_data; |
lptx_data = lri_data; |
lfli_drdy = 0; |
lprx_drdy = 0; |
lptx_srdy = 0; |
lri_drdy = 0; |
lro_srdy = 0; |
|
case (1'b1) |
state[s_idle] : |
48,6 → 57,20
begin |
if (lfli_srdy) |
begin |
if (lfli_data != 0) |
begin |
lro_data = 0; |
lro_data[`PRW_PVEC] = 1; |
lro_data[`PRW_DATA] = lfli_data; |
if (lro_drdy) |
begin |
lfli_drdy = 1; |
lro_srdy = 1; |
nxt_state = ns_tdata; |
end |
end |
else |
lfli_drdy = 1; |
end |
else if (lri_srdy) |
begin |
86,10 → 109,84
end // if (lri_srdy) |
end // case: state[s_idle] |
|
// transmit data from port on to the ring |
state[s_tdata] : |
begin |
lro_data = lprx_data; |
lro_data[`PRW_PVEC] = 0; |
if (lro_drdy & lprx_srdy) |
begin |
lprx_drdy = 1; |
lro_srdy = 1; |
if ((lprx_data[`PRW_PCC] == `PCC_EOP) | |
(lprx_data[`PRW_PCC] == `PCC_BADEOP)) |
nxt_state = ns_idle; |
end |
end // case: state[s_tdata] |
|
// data on ring is for our port as well as further ports |
// copy ring data to our TX buffer as well as on the ring |
state[s_rcopy] : |
begin |
lro_data = lri_data; |
lptx_data = lri_data[`PFW_SZ-1:0]; |
if (lri_srdy & lro_drdy & lptx_drdy) |
begin |
lri_drdy = 1; |
lro_srdy = 1; |
lptx_srdy = 1; |
if ((lri_data[`PRW_PCC] == `PCC_EOP) | |
(lri_data[`PRW_PCC] == `PCC_BADEOP)) |
nxt_state = ns_idle; |
end |
end |
|
// data on ring is not for our port, copy from ring in to ring out |
state[s_rfwd] : |
begin |
lro_data = lri_data; |
if (lri_srdy & lro_drdy) |
begin |
lri_drdy = 1; |
lro_srdy = 1; |
if ((lri_data[`PRW_PCC] == `PCC_EOP) | |
(lri_data[`PRW_PCC] == `PCC_BADEOP)) |
nxt_state = ns_idle; |
end |
end |
|
// data on ring is for our port and we are the last port |
// copy ring data to our TX buffer but do not copy to ring |
state[s_rcopy] : |
begin |
lptx_data = lri_data[`PFW_SZ-1:0]; |
if (lri_srdy & lptx_drdy) |
begin |
lri_drdy = 1; |
lptx_srdy = 1; |
if ((lri_data[`PRW_PCC] == `PCC_EOP) | |
(lri_data[`PRW_PCC] == `PCC_BADEOP)) |
nxt_state = ns_idle; |
end |
end |
|
default : nxt_state = ns_idle; |
endcase // case (1'b1) |
end // always @ * |
|
|
always @(posedge clk) |
begin |
if (reset) |
begin |
state <= #1 1; |
/*AUTORESET*/ |
end |
else |
begin |
state <= #1 nxt_state; |
end |
end // always @ (posedge clk) |
|
|
|
endmodule // port_ring_tap_fsm |
/srdydrdy_lib/trunk/examples/bridge/rtl/port_clocking.v
0,0 → 1,20
module port_clocking |
(input clk, |
input reset, |
input gmii_rx_clk, |
output gmii_rx_reset |
); |
|
// if this were a testable design, clock muxing logic would go here as well |
|
reg rx_sync1, rx_sync2; |
|
always @(posedge gmii_rx_clk) |
begin |
rx_sync1 <= #1 reset; |
rx_sync2 <= #1 rx_sync1; |
end |
|
assign gmii_rx_reset = reset | rx_sync2; |
|
endmodule // port_clocking |
/srdydrdy_lib/trunk/examples/bridge/rtl/basic_hashfunc.v
8,13 → 8,14
module basic_hashfunc |
#(parameter input_sz=48, |
parameter table_sz=1024, |
parameter fsz=clogb2(table_sz)) |
parameter fsz=$clog2(table_sz)) |
( |
input [input_sz-1:0] hf_in, |
output reg [fsz-1:0] hf_out); |
|
//localparam folds = (input_sz/fsz) + ( (input_sz%fsz) == 0) ? 0 : 1; |
localparam folds = num_folds(input_sz, fsz); |
// const function not supported by Icarus Verilog |
//localparam folds = num_folds(input_sz, fsz); |
localparam folds = 5; |
|
wire [folds*fsz-1:0] tmp_array; |
|
47,6 → 48,7
end |
endfunction |
|
/* -----\/----- EXCLUDED -----\/----- |
function integer clogb2; |
input [31:0] depth; |
integer i; |
56,5 → 58,6
i = i >> 1; |
end |
endfunction // for |
-----/\----- EXCLUDED -----/\----- */ |
|
endmodule // hashfunc |
/srdydrdy_lib/trunk/examples/bridge/rtl/concentrator.v
0,0 → 1,121
module concentrator |
(input clk, |
input reset, |
input [7:0] c_data, |
input [1:0] c_code, |
input c_srdy, // To sdin of sd_input.v |
input p_drdy, // To sdout of sd_output.v |
output c_drdy, // From sdin of sd_input.v |
output reg [`PFW_SZ-1:0] p_data, // From sdout of sd_output.v |
output reg p_srdy, |
output reg p_commit, |
output reg p_abort |
// End of automatics |
); |
|
wire [`PFW_SZ-1:0] ic_data; // From body of template_body_1i1o.v |
wire ic_drdy; // From sdout of sd_output.v |
wire ic_srdy; // From body of template_body_1i1o.v |
wire [7:0] ip_data; // From sdin of sd_input.v |
wire [1:0] ip_code; |
reg ip_drdy; |
wire ip_srdy; // From sdin of sd_input.v |
|
reg [`PFW_SZ-1:0] nxt_p_data; |
reg [1:0] nxt_pkt_code, pkt_code; |
reg nxt_p_srdy; |
reg [2:0] count, nxt_count; |
reg nxt_p_abort, nxt_p_commit; |
|
sd_input #(8+2) sdin |
( |
// Outputs |
.c_drdy (c_drdy), |
.ip_srdy (ip_srdy), |
.ip_data ({ip_code,ip_data}), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (c_srdy), |
.c_data ({c_code,c_data}), |
.ip_drdy (ip_drdy)); |
|
always @* |
begin |
nxt_p_data = p_data; |
nxt_p_srdy = p_srdy; |
nxt_pkt_code = pkt_code; |
nxt_p_data = p_data; |
nxt_count = count; |
nxt_p_commit = p_commit; |
nxt_p_abort = 0; |
|
if (p_srdy) |
begin |
if (p_drdy) |
begin |
nxt_p_srdy = 0; |
ip_drdy = 1; |
nxt_pkt_code = `PCC_DATA; |
nxt_count = 0; |
|
if (ip_srdy) |
begin |
nxt_count = 1; |
if (ip_code != `PCC_DATA) |
nxt_pkt_code = ip_code; |
nxt_p_data[63:56] = ip_data; |
end |
end |
end |
else if (ip_srdy) |
begin |
ip_drdy = 1; |
if (ip_code != `PCC_DATA) |
nxt_pkt_code = ip_code; |
|
nxt_count = count + 1; |
case (count) |
0 : nxt_p_data[63:56] = ip_data; |
1 : nxt_p_data[55:48] = ip_data; |
2 : nxt_p_data[47:40] = ip_data; |
3 : nxt_p_data[39:32] = ip_data; |
4 : nxt_p_data[31:24] = ip_data; |
5 : nxt_p_data[23:16] = ip_data; |
6 : nxt_p_data[15: 8] = ip_data; |
7 : nxt_p_data[ 7: 0] = ip_data; |
endcase // case (count) |
if ((count == 7) | (ip_code == `PCC_BADEOP) | (ip_code == `PCC_EOP)) |
begin |
if ((ip_code == `PCC_BADEOP) || (pkt_code == `PCC_BADEOP)) |
begin |
nxt_p_abort = 1; |
end |
else |
nxt_p_srdy = 1; |
end |
end |
end // always @ * |
|
always @(posedge clk) |
begin |
if (reset) |
begin |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
p_abort <= 1'h0; |
p_commit <= 1'h0; |
p_data <= {(1+(`PFW_SZ-1)){1'b0}}; |
p_srdy <= 1'h0; |
// End of automatics |
end |
else |
begin |
p_commit <= #1 nxt_p_commit; |
p_abort <= #1 nxt_p_abort; |
p_srdy <= #1 nxt_p_srdy; |
p_data <= #1 nxt_p_data; |
end // else: !if(reset) |
end |
|
endmodule // template_1i1o |
/srdydrdy_lib/trunk/examples/bridge/rtl/egr_oflow.v
0,0 → 1,92
module egr_oflow |
#(parameter drop_thr=`TX_FIFO_DEPTH-10) |
( |
input clk, |
input reset, |
|
input c_srdy, |
output reg c_drdy, |
input [`PFW_SZ-1:0] c_data, |
|
input [`TX_USG_SZ-1:0] tx_usage, |
|
output reg p_srdy, |
input p_drdy, |
output [`PFW_SZ-1:0] p_data, |
output reg p_commit, |
output reg p_abort |
); |
|
reg state, nxt_state; |
|
localparam s_idle = 0, s_packet = 1, s_flush = 2; |
|
assign p_data = c_data; |
|
always @* |
begin |
c_drdy = 0; |
p_srdy = 0; |
p_commit = 0; |
p_abort = 0; |
|
case (state) |
s_idle : |
begin |
if (c_srdy & p_drdy & (c_data[`PRW_PCC] == `PCC_SOP)) |
begin |
nxt_state = s_packet; |
c_drdy = 1; |
p_srdy = 1; |
end |
else if (c_srdy) |
begin |
c_drdy = 1; |
end |
end // case: state[s_idle] |
|
s_packet : |
begin |
if (c_srdy & (c_data[`PRW_PCC] == `PCC_BADEOP)) |
begin |
c_drdy = 1; |
p_abort = 1; |
nxt_state = s_idle; |
end |
else if (c_srdy & p_drdy & (c_data[`PRW_PCC] == `PCC_EOP)) |
begin |
p_srdy = 1; |
c_drdy = 1; |
p_commit = 1; |
nxt_state = s_idle; |
end |
else if (tx_usage >= drop_thr) |
begin |
c_drdy = 1; |
nxt_state = s_idle; |
p_abort = 1; |
end |
else if (c_srdy & p_drdy) |
begin |
p_srdy = 1; |
c_drdy = 1; |
end |
end // case: state[s_packet] |
|
default : nxt_state = s_idle; |
endcase // case (1'b1) |
end // always @ * |
|
always @(posedge clk) |
begin |
if (reset) |
begin |
state <= #1 s_idle; |
end |
else |
begin |
state <= #1 nxt_state; |
end |
end // always @ (posedge clk) |
|
endmodule // egr_oflow |
/srdydrdy_lib/trunk/examples/bridge/rtl/bridge.vh
33,6 → 33,17
`define PCC_EOP 2'b10 // End of packet |
`define PCC_BADEOP 2'b11 // End of packet w/ error |
|
// Packet FIFO Word |
// uses same field definitions as Packet Ring Word, but no PVEC bit |
`define PFW_SZ 69 |
|
// Port FIFO sizes |
`define RX_FIFO_DEPTH 64 |
`define TX_FIFO_DEPTH 256 |
|
`define RX_USG_SZ $clog2(`RX_FIFO_DEPTH)+1 |
`define TX_USG_SZ $clog2(`TX_FIFO_DEPTH)+1 |
|
// Packet Ring Word |
|
`define PRW_SZ 70 |
40,3 → 51,7
`define PRW_PCC 65:64 // packet control code |
`define PRW_VALID 68:66 // # of valid bytes modulo 8 |
`define PRW_PVEC 69 // indicates this is port vector word |
|
// GMII definitions |
`define GMII_PRE 8'h55 |
`define GMII_SFD 8'hD5 |
/srdydrdy_lib/trunk/examples/bridge/rtl/port_macro.v
0,0 → 1,299
module port_macro |
(input clk, |
input reset, |
|
input [`PRW_SZ-1:0] ri_data, // To ring_tap of port_ring_tap.v |
output [`PRW_SZ-1:0] ro_data, // From ring_tap of port_ring_tap.v |
input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v |
/*AUTOINPUT*/ |
// Beginning of automatic inputs (from unused autoinst inputs) |
input fli_srdy, // To ring_tap of port_ring_tap.v |
input gmii_rx_clk, // To port_clocking of port_clocking.v, ... |
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v |
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v |
input p2f_drdy, // To pkt_parse of pkt_parse.v |
input ri_srdy, // To ring_tap of port_ring_tap.v |
input ro_drdy, // To ring_tap of port_ring_tap.v |
// End of automatics |
|
output fli_drdy, // From ring_tap of port_ring_tap.v |
output gmii_tx_dv, // From tx_gmii of sd_tx_gigmac.v |
output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v |
output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v |
output p2f_srdy, // From pkt_parse of pkt_parse.v |
output ri_drdy, // From ring_tap of port_ring_tap.v |
output ro_srdy // From ring_tap of port_ring_tap.v |
); |
|
wire [`RX_USG_SZ-1:0] rx_usage; |
wire [`TX_USG_SZ-1:0] tx_usage; |
wire [`PFW_SZ-1:0] prx_data; // From fifo_rx of sd_fifo_b.v |
wire [`PFW_SZ-1:0] ptx_data; // From fifo_tx of sd_fifo_b.v |
wire [`PFW_SZ-1:0] rttx_data; // From ring_tap of port_ring_tap.v |
wire [1:0] rxg_code; // From rx_sync_fifo of sd_fifo_s.v |
wire [7:0] rxg_data; // From rx_sync_fifo of sd_fifo_s.v |
wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v |
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire crx_abort; // From con of concentrator.v |
wire crx_commit; // From con of concentrator.v |
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v |
wire crx_drdy; // From fifo_rx of sd_fifo_b.v |
wire crx_srdy; // From con of concentrator.v |
wire ctx_abort; // From oflow of egr_oflow.v |
wire ctx_commit; // From oflow of egr_oflow.v |
wire ctx_drdy; // From fifo_tx of sd_fifo_b.v |
wire ctx_srdy; // From oflow of egr_oflow.v |
wire gmii_rx_reset; // From port_clocking of port_clocking.v |
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v |
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v |
wire pdo_drdy; // From con of concentrator.v |
wire pdo_srdy; // From pkt_parse of pkt_parse.v |
wire prx_drdy; // From ring_tap of port_ring_tap.v |
wire prx_srdy; // From fifo_rx of sd_fifo_b.v |
wire ptx_drdy; // From dst of distributor.v |
wire ptx_srdy; // From fifo_tx of sd_fifo_b.v |
wire rttx_drdy; // From oflow of egr_oflow.v |
wire rttx_srdy; // From ring_tap of port_ring_tap.v |
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v |
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v |
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v |
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v |
wire rxg_drdy; // From pkt_parse of pkt_parse.v |
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v |
wire [1:0] txg_code; // From dst of distributor.v |
wire [7:0] txg_data; // From dst of distributor.v |
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v |
wire txg_srdy; // From dst of distributor.v |
// End of automatics |
|
|
port_clocking port_clocking |
(/*AUTOINST*/ |
// Outputs |
.gmii_rx_reset (gmii_rx_reset), |
// Inputs |
.clk (clk), |
.reset (reset), |
.gmii_rx_clk (gmii_rx_clk)); |
|
/* sd_rx_gigmac AUTO_TEMPLATE |
( |
.clk (gmii_rx_clk), |
.reset (gmii_rx_reset), |
.rxg_\(.*\) (rxc_rxg_\1[]), |
); |
*/ |
sd_rx_gigmac rx_gigmac |
(/*AUTOINST*/ |
// Outputs |
.rxg_srdy (rxc_rxg_srdy), // Templated |
.rxg_code (rxc_rxg_code[1:0]), // Templated |
.rxg_data (rxc_rxg_data[7:0]), // Templated |
// Inputs |
.clk (gmii_rx_clk), // Templated |
.reset (gmii_rx_reset), // Templated |
.gmii_rx_dv (gmii_rx_dv), |
.gmii_rxd (gmii_rxd[7:0]), |
.rxg_drdy (rxc_rxg_drdy)); // Templated |
|
/* sd_fifo_s AUTO_TEMPLATE |
( |
.c_clk (gmii_rx_clk), |
.c_reset (gmii_rx_reset), |
.c_data ({rxc_rxg_code,rxc_rxg_data}), |
.p_data ({rxg_code,rxg_data}), |
.p_clk (clk), |
.p_reset (reset), |
.c_\(.*\) (rxc_rxg_\1[]), |
.p_\(.*\) (rxg_\1[]), |
); |
*/ |
sd_fifo_s #(8+2,16,1) rx_sync_fifo |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (rxc_rxg_drdy), // Templated |
.p_srdy (rxg_srdy), // Templated |
.p_data ({rxg_code,rxg_data}), // Templated |
// Inputs |
.c_clk (gmii_rx_clk), // Templated |
.c_reset (gmii_rx_reset), // Templated |
.c_srdy (rxc_rxg_srdy), // Templated |
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (rxg_drdy)); // Templated |
|
pkt_parse pkt_parse |
(/*AUTOINST*/ |
// Outputs |
.rxg_drdy (rxg_drdy), |
.p2f_srdy (p2f_srdy), |
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]), |
.pdo_srdy (pdo_srdy), |
.pdo_code (pdo_code[1:0]), |
.pdo_data (pdo_data[7:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.rxg_srdy (rxg_srdy), |
.rxg_code (rxg_code[1:0]), |
.rxg_data (rxg_data[7:0]), |
.p2f_drdy (p2f_drdy), |
.pdo_drdy (pdo_drdy)); |
|
/* concentrator AUTO_TEMPLATE |
( |
.c_\(.*\) (pdo_\1[]), |
.p_\(.*\) (crx_\1[]), |
); |
*/ |
concentrator con |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (pdo_drdy), // Templated |
.p_data (crx_data[`PFW_SZ-1:0]), // Templated |
.p_srdy (crx_srdy), // Templated |
.p_commit (crx_commit), // Templated |
.p_abort (crx_abort), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_data (pdo_data[7:0]), // Templated |
.c_code (pdo_code[1:0]), // Templated |
.c_srdy (pdo_srdy), // Templated |
.p_drdy (crx_drdy)); // Templated |
|
/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)" |
( |
.p_abort (1'b0), |
.p_commit (1'b0), |
.usage (@_usage), |
.c_\(.*\) (c@_\1), |
.p_\(.*\) (p@_\1), |
); |
*/ |
sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (crx_drdy), // Templated |
.p_srdy (prx_srdy), // Templated |
.p_data (prx_data), // Templated |
.usage (rx_usage), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (crx_srdy), // Templated |
.c_commit (crx_commit), // Templated |
.c_abort (crx_abort), // Templated |
.c_data (crx_data), // Templated |
.p_drdy (prx_drdy), // Templated |
.p_commit (1'b0), // Templated |
.p_abort (1'b0)); // Templated |
|
sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (ctx_drdy), // Templated |
.p_srdy (ptx_srdy), // Templated |
.p_data (ptx_data), // Templated |
.usage (tx_usage), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (ctx_srdy), // Templated |
.c_commit (ctx_commit), // Templated |
.c_abort (ctx_abort), // Templated |
.c_data (ctx_data), // Templated |
.p_drdy (ptx_drdy), // Templated |
.p_commit (1'b0), // Templated |
.p_abort (1'b0)); // Templated |
|
/* port_ring_tap AUTO_TEMPLATE |
( |
.ro_data (ro_data[`PRW_SZ-1:0]), |
.ri_data (ri_data[`PRW_SZ-1:0]), |
.prx_\(.*\) (prx_\1), |
.ptx_\(.*\) (rttx_\1), |
); |
*/ |
port_ring_tap ring_tap |
(/*AUTOINST*/ |
// Outputs |
.ri_drdy (ri_drdy), |
.prx_drdy (prx_drdy), // Templated |
.ro_srdy (ro_srdy), |
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated |
.ptx_srdy (rttx_srdy), // Templated |
.ptx_data (rttx_data), // Templated |
.fli_drdy (fli_drdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.ri_srdy (ri_srdy), |
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated |
.prx_srdy (prx_srdy), // Templated |
.prx_data (prx_data), // Templated |
.ro_drdy (ro_drdy), |
.ptx_drdy (rttx_drdy), // Templated |
.fli_srdy (fli_srdy), |
.fli_data (fli_data[`NUM_PORTS-1:0])); |
|
/* egr_oflow AUTO_TEMPLATE |
( |
.c_\(.*\) (rttx_\1[]), |
.p_\(.*\) (ctx_\1[]), |
); |
*/ |
egr_oflow oflow |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (rttx_drdy), // Templated |
.p_srdy (ctx_srdy), // Templated |
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated |
.p_commit (ctx_commit), // Templated |
.p_abort (ctx_abort), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (rttx_srdy), // Templated |
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated |
.tx_usage (tx_usage[`TX_USG_SZ-1:0]), |
.p_drdy (ctx_drdy)); // Templated |
|
/* distributor AUTO_TEMPLATE |
( |
.p_\(.*\) (txg_\1[]), |
); |
*/ |
distributor dst |
(/*AUTOINST*/ |
// Outputs |
.ptx_drdy (ptx_drdy), |
.p_srdy (txg_srdy), // Templated |
.p_code (txg_code[1:0]), // Templated |
.p_data (txg_data[7:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.ptx_srdy (ptx_srdy), |
.ptx_data (ptx_data[`PFW_SZ-1:0]), |
.p_drdy (txg_drdy)); // Templated |
|
sd_tx_gigmac tx_gmii |
(/*AUTOINST*/ |
// Outputs |
.gmii_tx_dv (gmii_tx_dv), |
.gmii_txd (gmii_txd[7:0]), |
.txg_drdy (txg_drdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.txg_srdy (txg_srdy), |
.txg_code (txg_code[1:0]), |
.txg_data (txg_data[7:0])); |
|
endmodule // port_macro |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks") |
// End: |
/srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap.v
2,7 → 2,8
// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX) |
|
module port_ring_tap |
#(parameter rdp_sz = 64, |
#(parameter rdp_sz = `PRW_SZ, |
parameter pdp_sz = `PFW_SZ, |
parameter portnum = 0) |
( |
input clk, |
14,7 → 15,7
|
input prx_srdy, |
output prx_drdy, |
input [rdp_sz-1:0] prx_data, |
input [pdp_sz-1:0] prx_data, |
|
output ro_srdy, |
input ro_drdy, |
22,7 → 23,7
|
output ptx_srdy, |
input ptx_drdy, |
output [rdp_sz-1:0] ptx_data, |
output [pdp_sz-1:0] ptx_data, |
|
input fli_srdy, |
output fli_drdy, |
29,12 → 30,29
input [`NUM_PORTS-1:0] fli_data |
); |
|
wire [`PRW_SZ-1:0] lri_data; // From tc_ri of sd_input.v |
wire [`NUM_PORTS-1:0] lfli_data; // From tc_fli of sd_input.v |
wire [`PFW_SZ-1:0] lprx_data; // From tc_prx of sd_input.v |
wire [`PFW_SZ-1:0] lptx_data; // From fsm of port_ring_tap_fsm.v |
wire [`PRW_SZ-1:0] lro_data; // From fsm of port_ring_tap_fsm.v |
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire lfli_drdy; // From fsm of port_ring_tap_fsm.v |
wire lfli_srdy; // From tc_fli of sd_input.v |
wire lprx_drdy; // From fsm of port_ring_tap_fsm.v |
wire lprx_srdy; // From tc_prx of sd_input.v |
wire lptx_drdy; // From tc_ptx of sd_output.v |
wire lptx_srdy; // From fsm of port_ring_tap_fsm.v |
wire lri_drdy; // From fsm of port_ring_tap_fsm.v |
wire lri_srdy; // From tc_ri of sd_input.v |
wire lro_drdy; // From tc_ro of sd_output.v |
wire lro_srdy; // From fsm of port_ring_tap_fsm.v |
// End of automatics |
|
/* sd_input AUTO_TEMPLATE "tc_\(.*\)" |
( |
.c_\(.*\) (@_\1[]), |
.ip_\(.*\) (l@_\1[]), |
.c_\(.*\) (@_\1), |
.ip_\(.*\) (l@_\1), |
); |
*/ |
|
41,74 → 59,96
sd_input #(rdp_sz) tc_ri |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (ri_drdy), // Templated |
.ip_srdy (lri_srdy), // Templated |
.ip_data (lri_data[width-1:0]), // Templated |
.c_drdy (ri_drdy), // Templated |
.ip_srdy (lri_srdy), // Templated |
.ip_data (lri_data), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (ri_srdy), // Templated |
.c_data (ri_data[width-1:0]), // Templated |
.ip_drdy (lri_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.c_srdy (ri_srdy), // Templated |
.c_data (ri_data), // Templated |
.ip_drdy (lri_drdy)); // Templated |
|
sd_input #(rdp_sz) tc_prx |
sd_input #(pdp_sz) tc_prx |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (prx_drdy), // Templated |
.ip_srdy (lprx_srdy), // Templated |
.ip_data (lprx_data[width-1:0]), // Templated |
.c_drdy (prx_drdy), // Templated |
.ip_srdy (lprx_srdy), // Templated |
.ip_data (lprx_data), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (prx_srdy), // Templated |
.c_data (prx_data[width-1:0]), // Templated |
.ip_drdy (lprx_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.c_srdy (prx_srdy), // Templated |
.c_data (prx_data), // Templated |
.ip_drdy (lprx_drdy)); // Templated |
|
sd_input #(`NUM_PORTS) tc_fli |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (fli_drdy), // Templated |
.ip_srdy (lfli_srdy), // Templated |
.ip_data (lfli_data[width-1:0]), // Templated |
.c_drdy (fli_drdy), // Templated |
.ip_srdy (lfli_srdy), // Templated |
.ip_data (lfli_data), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (fli_srdy), // Templated |
.c_data (fli_data[width-1:0]), // Templated |
.ip_drdy (lfli_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.c_srdy (fli_srdy), // Templated |
.c_data (fli_data), // Templated |
.ip_drdy (lfli_drdy)); // Templated |
|
port_ring_tap_fsm #(rdp_sz, pdp_sz, portnum) fsm |
(/*AUTOINST*/ |
// Outputs |
.lfli_drdy (lfli_drdy), |
.lprx_drdy (lprx_drdy), |
.lptx_data (lptx_data[pdp_sz-1:0]), |
.lptx_srdy (lptx_srdy), |
.lri_drdy (lri_drdy), |
.lro_data (lro_data[rdp_sz-1:0]), |
.lro_srdy (lro_srdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.lfli_data (lfli_data[`NUM_PORTS-1:0]), |
.lfli_srdy (lfli_srdy), |
.lprx_data (lprx_data[pdp_sz-1:0]), |
.lprx_srdy (lprx_srdy), |
.lptx_drdy (lptx_drdy), |
.lri_data (lri_data[rdp_sz-1:0]), |
.lri_srdy (lri_srdy), |
.lro_drdy (lro_drdy)); |
|
/* sd_output AUTO_TEMPLATE "tc_\(.*\)" |
( |
.ic_\(.*\) (l@_\1[]), |
.p_\(.*\) (@_\1[]), |
.ic_\(.*\) (l@_\1), |
.p_\(.*\) (@_\1), |
); |
*/ |
|
sd_output #(rdp_sz) tc_ptx |
sd_output #(pdp_sz) tc_ptx |
(/*AUTOINST*/ |
// Outputs |
.ic_drdy (lptx_drdy), // Templated |
.p_srdy (ptx_srdy), // Templated |
.p_data (ptx_data[width-1:0]), // Templated |
.ic_drdy (lptx_drdy), // Templated |
.p_srdy (ptx_srdy), // Templated |
.p_data (ptx_data), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.ic_srdy (lptx_srdy), // Templated |
.ic_data (lptx_data[width-1:0]), // Templated |
.p_drdy (ptx_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.ic_srdy (lptx_srdy), // Templated |
.ic_data (lptx_data), // Templated |
.p_drdy (ptx_drdy)); // Templated |
|
sd_output #(rdp_sz) tc_ro |
(/*AUTOINST*/ |
// Outputs |
.ic_drdy (lro_drdy), // Templated |
.p_srdy (ro_srdy), // Templated |
.p_data (ro_data[width-1:0]), // Templated |
.ic_drdy (lro_drdy), // Templated |
.p_srdy (ro_srdy), // Templated |
.p_data (ro_data), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.ic_srdy (lro_srdy), // Templated |
.ic_data (lro_data[width-1:0]), // Templated |
.p_drdy (ro_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.ic_srdy (lro_srdy), // Templated |
.ic_data (lro_data), // Templated |
.p_drdy (ro_drdy)); // Templated |
|
endmodule // port_ring_tap |
// Local Variables: |
/srdydrdy_lib/trunk/examples/bridge/rtl/sd_tx_gigmac.v
0,0 → 1,133
// mock-up of RX portion of gigabit ethernet MAC |
// performs packet reception and creates internal |
// packet codes, as well as checking CRC on incoming |
// packets. |
|
// If output is not ready while receiving data, |
// truncates the packet and makes it an error packet. |
|
module sd_tx_gigmac |
( |
input clk, |
input reset, |
output reg gmii_tx_dv, |
output reg [7:0] gmii_txd, |
|
input txg_srdy, |
output txg_drdy, |
input [1:0] txg_code, |
input [7:0] txg_data |
); |
|
wire ip_srdy; |
reg ip_drdy; |
wire [1:0] ip_code; |
wire [7:0] ip_data; |
reg [3:0] count, nxt_count; |
|
reg [7:0] nxt_gmii_txd; |
reg nxt_gmii_tx_dv; |
reg [3:0] state, nxt_state; |
|
localparam s_idle = 0, s_preamble = 1, s_payload = 2, s_ipg = 3; |
localparam ns_idle = 1, ns_preamble = 2, ns_payload = 4, ns_ipg = 8; |
|
sd_input #(8+2) in_hold |
( |
// Outputs |
.c_drdy (txg_drdy), |
.ip_srdy (ip_srdy), |
.ip_data ({ip_code,ip_data}), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (txg_srdy), |
.c_data ({txg_code,txg_data}), |
.ip_drdy (ip_drdy)); |
|
always @* |
begin |
ip_drdy = 0; |
nxt_count = count; |
nxt_gmii_tx_dv = 0; |
nxt_gmii_txd = gmii_txd; |
|
case (1'b1) |
state[s_idle] : |
begin |
if (ip_srdy & (ip_code == `PCC_SOP)) |
begin |
nxt_gmii_tx_dv = 1; |
nxt_gmii_txd = `GMII_PRE; |
nxt_count = 1; |
nxt_state = ns_preamble; |
end |
else |
begin |
ip_drdy = 1; |
end // else: !if(ip_srdy & (ip_code == `PCC_SOP)) |
end // case: state[s_idle] |
|
state[s_preamble] : |
begin |
nxt_count = count + 1; |
nxt_gmii_tx_dv = 1; |
if (count == 6) |
nxt_gmii_txd = `GMII_SFD; |
else |
nxt_gmii_txd = `GMII_PRE; |
|
if (count == 7) |
nxt_state = ns_payload; |
end // case: state[s_preamble] |
|
state[s_payload] : |
begin |
ip_drdy = 1; |
|
if (!ip_srdy | ((ip_code == `PCC_EOP) | (ip_code == `PCC_BADEOP))) |
begin |
nxt_gmii_tx_dv = 0; |
nxt_count = 0; |
nxt_state = ns_ipg; |
end |
end // case: state[s_payload] |
|
state[s_ipg] : |
begin |
nxt_gmii_tx_dv = 0; |
ip_drdy = 0; |
nxt_count = count + 1; |
if (count == 11) |
nxt_state = ns_idle; |
end |
|
default : nxt_state = ns_idle; |
endcase // case (1'b1) |
end // always @ * |
|
always @(posedge clk) |
begin |
if (reset) |
begin |
state <= #1 1; |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
count <= 4'h0; |
gmii_tx_dv <= 1'h0; |
gmii_txd <= 8'h0; |
// End of automatics |
end |
else |
begin |
state <= #1 nxt_state; |
count <= #1 nxt_count; |
gmii_tx_dv <= #1 nxt_gmii_tx_dv; |
gmii_txd <= #1 nxt_gmii_txd; |
end // else: !if(reset) |
end // always @ (posedge clk) |
|
endmodule // sd_rx_gigmac |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks") |
// End: |
/srdydrdy_lib/trunk/examples/bridge/rtl/pkt_parse.v
0,0 → 1,164
// packet parser |
// |
// Takes input packet on rxg interface and copies packet to pdo |
// interface, without changing packet data. If packet is too |
// short to be parsed, converts packet to an error code. |
// |
// If packet parses correctly and is not an error packet, sends |
// a parse result to the FIB for lookup. Otherwise aborts the |
// packet so it is flushed from the packet FIFO. |
module pkt_parse |
(input clk, |
input reset, |
|
input rxg_srdy, |
output rxg_drdy, |
input [1:0] rxg_code, |
input [7:0] rxg_data, |
|
output reg p2f_srdy, |
input p2f_drdy, |
output reg [`PAR_DATA_SZ-1:0] p2f_data, |
|
output pdo_srdy, |
input pdo_drdy, |
output [1:0] pdo_code, |
output [7:0] pdo_data |
); |
|
wire lp_srdy; |
reg lp_drdy; |
wire [1:0] lp_code; |
wire [7:0] lp_data; |
reg lc_srdy; |
wire lc_drdy; |
reg [1:0] lc_code; |
|
reg [3:0] count, nxt_count; |
reg nxt_p2f_srdy; |
reg [`PAR_DATA_SZ-1:0] nxt_p2f_data; |
|
sd_input #(8+2) rxg_in |
( |
// Outputs |
.c_drdy (rxg_drdy), |
.ip_srdy (lp_srdy), |
.ip_data ({lp_code,lp_data}), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (rxg_srdy), |
.c_data ({rxg_code,rxg_data}), |
.ip_drdy (lp_drdy)); |
|
always @* |
begin |
nxt_p2f_srdy = p2f_srdy; |
nxt_p2f_data = p2f_data; |
nxt_count = count; |
lc_code = lp_code; |
|
if (p2f_srdy) |
begin |
lp_drdy = 0; |
lc_srdy = 0; |
if (p2f_drdy) |
nxt_p2f_srdy = 0; |
end |
else if (lp_srdy & lc_drdy) |
begin |
lp_drdy = 1; |
lc_srdy = 1; |
|
case (count) |
0, 1, 2, 3, 4, 5 : |
begin |
if (count == 0) |
nxt_p2f_data = 0; |
|
if ((lp_code == `PCC_EOP) || (lp_code == `PCC_BADEOP)) |
begin |
lc_code = `PCC_BADEOP; |
nxt_count = 0; |
end |
else |
begin |
nxt_p2f_data[`PAR_MACDA] = { p2f_data[`PAR_MACDA] << 8, lp_data }; |
nxt_count = count + 1; |
end |
end // case: 0, 1, 2, 3, 4, 5 |
|
6, 7, 8, 9, 10, 11 : |
begin |
if ((lp_code == `PCC_EOP) || (lp_code == `PCC_BADEOP)) |
begin |
lc_code = `PCC_BADEOP; |
nxt_count = 0; |
end |
else |
begin |
nxt_p2f_data[`PAR_MACSA] = { p2f_data[`PAR_MACSA] << 8, lp_data }; |
nxt_count = count + 1; |
end |
end // case: 6, 7, 8, 9, 10, 11 |
|
// done with parsing, wait for packet EOP |
12 : |
begin |
if (lp_code == `PCC_EOP) |
begin |
nxt_p2f_srdy = 1; |
nxt_count = 0; |
end |
else if (lp_code == `PCC_BADEOP) |
nxt_count = 0; |
end |
|
default : nxt_count = 0; |
endcase // case (count) |
end |
else |
begin |
lp_drdy = 0; |
lc_srdy = 0; |
end // else: !if(lp_srdy & lc_drdy) |
end // always @ * |
|
always @(posedge clk) |
begin |
if (reset) |
begin |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
count <= 4'h0; |
p2f_data <= {(1+(`PAR_DATA_SZ-1)){1'b0}}; |
p2f_srdy <= 1'h0; |
// End of automatics |
end |
else |
begin |
p2f_srdy <= #1 nxt_p2f_srdy; |
p2f_data <= #1 nxt_p2f_data; |
count <= #1 nxt_count; |
end |
end |
|
sd_output #(8+2) par_out |
( |
// Outputs |
.ic_drdy (lc_drdy), |
.p_srdy (pdo_srdy), |
.p_data ({pdo_code,pdo_data}), |
// Inputs |
.clk (clk), |
.reset (reset), |
.ic_srdy (lc_srdy), |
.ic_data ({lp_code,lp_data}), |
.p_drdy (pdo_drdy)); |
|
endmodule // pkt_parse |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks") |
// End: |
|
|
/srdydrdy_lib/trunk/examples/bridge/rtl/bridge_ex1.v
0,0 → 1,217
// Top level for bridge example |
// |
// 4-port bridge has 4 GMII interfaces, each one of which has its own RX clock |
// Port macros contain all packet buffering, and ring interface to communicate |
// with other port macros. |
// FIB block receives requests from all ports and sends results back to the |
// same port containing forwarding information. |
|
module bridge_ex1 |
(input clk, |
input reset, |
/*AUTOINPUT*/ |
// Beginning of automatic inputs (from unused autoinst inputs) |
input gmii_rx_clk_0, // To p0 of port_macro.v |
input gmii_rx_clk_1, // To p1 of port_macro.v |
input gmii_rx_clk_2, // To p2 of port_macro.v |
input gmii_rx_clk_3, // To p3 of port_macro.v |
input gmii_rx_dv_0, // To p0 of port_macro.v |
input gmii_rx_dv_1, // To p1 of port_macro.v |
input gmii_rx_dv_2, // To p2 of port_macro.v |
input gmii_rx_dv_3, // To p3 of port_macro.v |
input [7:0] gmii_rxd_0, // To p0 of port_macro.v |
input [7:0] gmii_rxd_1, // To p1 of port_macro.v |
input [7:0] gmii_rxd_2, // To p2 of port_macro.v |
input [7:0] gmii_rxd_3, // To p3 of port_macro.v |
// End of automatics |
/*AUTOOUTPUT*/ |
// Beginning of automatic outputs (from unused autoinst outputs) |
output gmii_tx_dv_0, // From p0 of port_macro.v |
output gmii_tx_dv_1, // From p1 of port_macro.v |
output gmii_tx_dv_2, // From p2 of port_macro.v |
output gmii_tx_dv_3, // From p3 of port_macro.v |
output [7:0] gmii_txd_0, // From p0 of port_macro.v |
output [7:0] gmii_txd_1, // From p1 of port_macro.v |
output [7:0] gmii_txd_2, // From p2 of port_macro.v |
output [7:0] gmii_txd_3 // From p3 of port_macro.v |
// End of automatics |
); |
|
wire [`PRW_SZ-1:0] ri_data_0; |
wire [`PRW_SZ-1:0] ri_data_1; |
wire [`PRW_SZ-1:0] ri_data_2; |
wire [`PRW_SZ-1:0] ri_data_3; |
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire [`NUM_PORTS-1:0] flo_data; // From fib_lookup of fib_lookup.v |
wire [3:0] flo_drdy; // From p0 of port_macro.v, ... |
wire [`NUM_PORTS-1:0] flo_srdy; // From fib_lookup of fib_lookup.v |
wire [`PAR_DATA_SZ-1:0] p2f_data_0; // From p0 of port_macro.v |
wire [`PAR_DATA_SZ-1:0] p2f_data_1; // From p1 of port_macro.v |
wire [`PAR_DATA_SZ-1:0] p2f_data_2; // From p2 of port_macro.v |
wire [`PAR_DATA_SZ-1:0] p2f_data_3; // From p3 of port_macro.v |
wire [`NUM_PORTS-1:0] p2f_drdy; // From fib_arb of sd_rrslow.v |
wire [3:0] p2f_srdy; // From p0 of port_macro.v, ... |
wire [`PAR_DATA_SZ-1:0] ppi_data; // From fib_arb of sd_rrslow.v |
wire ppi_drdy; // From fib_lookup of fib_lookup.v |
wire ppi_srdy; // From fib_arb of sd_rrslow.v |
wire ri_drdy_0; // From p0 of port_macro.v |
wire ri_drdy_1; // From p1 of port_macro.v |
wire ri_drdy_2; // From p2 of port_macro.v |
wire ri_drdy_3; // From p3 of port_macro.v |
wire ri_srdy_0; // From p3 of port_macro.v |
wire ri_srdy_1; // From p0 of port_macro.v |
wire ri_srdy_2; // From p1 of port_macro.v |
wire ri_srdy_3; // From p2 of port_macro.v |
// End of automatics |
|
/* port_macro AUTO_TEMPLATE |
( |
.clk (clk), |
.reset (reset), |
.ri_data (ri_data_@), |
.ro_\(.*\) (ri_\1_@"(% (+ 1 @) 4)"), |
.p2f_srdy (p2f_srdy[@]), |
.p2f_drdy (p2f_drdy[@]), |
.fli_srdy (flo_srdy[@]), |
.fli_drdy (flo_drdy[@]), |
.fli_data (flo_data), |
.\(.*\) (\1_@[]), |
); |
*/ |
port_macro p0 |
(/*AUTOINST*/ |
// Outputs |
.ro_data (ri_data_1), // Templated |
.fli_drdy (flo_drdy[0]), // Templated |
.gmii_tx_dv (gmii_tx_dv_0), // Templated |
.gmii_txd (gmii_txd_0[7:0]), // Templated |
.p2f_data (p2f_data_0[`PAR_DATA_SZ-1:0]), // Templated |
.p2f_srdy (p2f_srdy[0]), // Templated |
.ri_drdy (ri_drdy_0), // Templated |
.ro_srdy (ri_srdy_1), // Templated |
// Inputs |
.clk (clk), // Templated |
.reset (reset), // Templated |
.ri_data (ri_data_0), // Templated |
.fli_data (flo_data), // Templated |
.fli_srdy (flo_srdy[0]), // Templated |
.gmii_rx_clk (gmii_rx_clk_0), // Templated |
.gmii_rx_dv (gmii_rx_dv_0), // Templated |
.gmii_rxd (gmii_rxd_0[7:0]), // Templated |
.p2f_drdy (p2f_drdy[0]), // Templated |
.ri_srdy (ri_srdy_0), // Templated |
.ro_drdy (ri_drdy_1)); // Templated |
|
port_macro p1 |
(/*AUTOINST*/ |
// Outputs |
.ro_data (ri_data_2), // Templated |
.fli_drdy (flo_drdy[1]), // Templated |
.gmii_tx_dv (gmii_tx_dv_1), // Templated |
.gmii_txd (gmii_txd_1[7:0]), // Templated |
.p2f_data (p2f_data_1[`PAR_DATA_SZ-1:0]), // Templated |
.p2f_srdy (p2f_srdy[1]), // Templated |
.ri_drdy (ri_drdy_1), // Templated |
.ro_srdy (ri_srdy_2), // Templated |
// Inputs |
.clk (clk), // Templated |
.reset (reset), // Templated |
.ri_data (ri_data_1), // Templated |
.fli_data (flo_data), // Templated |
.fli_srdy (flo_srdy[1]), // Templated |
.gmii_rx_clk (gmii_rx_clk_1), // Templated |
.gmii_rx_dv (gmii_rx_dv_1), // Templated |
.gmii_rxd (gmii_rxd_1[7:0]), // Templated |
.p2f_drdy (p2f_drdy[1]), // Templated |
.ri_srdy (ri_srdy_1), // Templated |
.ro_drdy (ri_drdy_2)); // Templated |
|
port_macro p2 |
(/*AUTOINST*/ |
// Outputs |
.ro_data (ri_data_3), // Templated |
.fli_drdy (flo_drdy[2]), // Templated |
.gmii_tx_dv (gmii_tx_dv_2), // Templated |
.gmii_txd (gmii_txd_2[7:0]), // Templated |
.p2f_data (p2f_data_2[`PAR_DATA_SZ-1:0]), // Templated |
.p2f_srdy (p2f_srdy[2]), // Templated |
.ri_drdy (ri_drdy_2), // Templated |
.ro_srdy (ri_srdy_3), // Templated |
// Inputs |
.clk (clk), // Templated |
.reset (reset), // Templated |
.ri_data (ri_data_2), // Templated |
.fli_data (flo_data), // Templated |
.fli_srdy (flo_srdy[2]), // Templated |
.gmii_rx_clk (gmii_rx_clk_2), // Templated |
.gmii_rx_dv (gmii_rx_dv_2), // Templated |
.gmii_rxd (gmii_rxd_2[7:0]), // Templated |
.p2f_drdy (p2f_drdy[2]), // Templated |
.ri_srdy (ri_srdy_2), // Templated |
.ro_drdy (ri_drdy_3)); // Templated |
|
port_macro p3 |
(/*AUTOINST*/ |
// Outputs |
.ro_data (ri_data_0), // Templated |
.fli_drdy (flo_drdy[3]), // Templated |
.gmii_tx_dv (gmii_tx_dv_3), // Templated |
.gmii_txd (gmii_txd_3[7:0]), // Templated |
.p2f_data (p2f_data_3[`PAR_DATA_SZ-1:0]), // Templated |
.p2f_srdy (p2f_srdy[3]), // Templated |
.ri_drdy (ri_drdy_3), // Templated |
.ro_srdy (ri_srdy_0), // Templated |
// Inputs |
.clk (clk), // Templated |
.reset (reset), // Templated |
.ri_data (ri_data_3), // Templated |
.fli_data (flo_data), // Templated |
.fli_srdy (flo_srdy[3]), // Templated |
.gmii_rx_clk (gmii_rx_clk_3), // Templated |
.gmii_rx_dv (gmii_rx_dv_3), // Templated |
.gmii_rxd (gmii_rxd_3[7:0]), // Templated |
.p2f_drdy (p2f_drdy[3]), // Templated |
.ri_srdy (ri_srdy_3), // Templated |
.ro_drdy (ri_drdy_0)); // Templated |
|
/* sd_rrslow AUTO_TEMPLATE |
( |
.p_data (ppi_data[`PAR_DATA_SZ-1:0]), |
.c_data ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}), |
.c_srdy (p2f_srdy[`NUM_PORTS-1:0]), |
.c_drdy (p2f_drdy[`NUM_PORTS-1:0]), |
.c_\(.*\) (p2f_\1[]), |
.p_\(.*\) (ppi_\1[]), |
); |
*/ |
sd_rrslow #(`PAR_DATA_SZ,`NUM_PORTS,0) fib_arb |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (p2f_drdy[`NUM_PORTS-1:0]), // Templated |
.p_data (ppi_data[`PAR_DATA_SZ-1:0]), // Templated |
.p_srdy (ppi_srdy), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_data ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}), // Templated |
.c_srdy (p2f_srdy[`NUM_PORTS-1:0]), // Templated |
.p_drdy (ppi_drdy)); // Templated |
|
fib_lookup fib_lookup |
(/*AUTOINST*/ |
// Outputs |
.flo_data (flo_data[`NUM_PORTS-1:0]), |
.flo_srdy (flo_srdy[`NUM_PORTS-1:0]), |
.ppi_drdy (ppi_drdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.ppi_data (ppi_data[`PAR_DATA_SZ-1:0]), |
.flo_drdy (flo_drdy[`NUM_PORTS-1:0]), |
.ppi_srdy (ppi_srdy)); |
|
endmodule // bridge_ex1 |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks") |
// End: |
/srdydrdy_lib/trunk/examples/bridge/rtl/distributor.v
0,0 → 1,96
module distributor |
#(parameter width=8) |
(input clk, |
input reset, |
|
input ptx_srdy, |
output ptx_drdy, |
input [`PFW_SZ-1:0] ptx_data, |
|
output p_srdy, |
input p_drdy, |
output [1:0] p_code, |
output [7:0] p_data |
); |
|
wire [width-1:0] ic_data; // From body of template_body_1i1o.v |
wire ic_drdy; // From sdout of sd_output.v |
wire ic_srdy; // From body of template_body_1i1o.v |
wire [width-1:0] ip_data; // From sdin of sd_input.v |
wire ip_drdy; // From body of template_body_1i1o.v |
wire ip_srdy; // From sdin of sd_input.v |
// End of automatics |
|
sd_input #(width) sdin |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (c_drdy), |
.ip_srdy (ip_srdy), |
.ip_data (ip_data[width-1:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (c_srdy), |
.c_data (c_data[width-1:0]), |
.ip_drdy (ip_drdy)); |
|
template_body_1i1o #(width) body |
(/*AUTOINST*/ |
// Outputs |
.ic_data (ic_data[width-1:0]), |
.ic_srdy (ic_srdy), |
.ip_drdy (ip_drdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.ic_drdy (ic_drdy), |
.ip_data (ip_data[width-1:0]), |
.ip_srdy (ip_srdy)); |
|
sd_output #(width) sdout |
(/*AUTOINST*/ |
// Outputs |
.ic_drdy (ic_drdy), |
.p_srdy (p_srdy), |
.p_data (p_data[width-1:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.ic_srdy (ic_srdy), |
.ic_data (ic_data[width-1:0]), |
.p_drdy (p_drdy)); |
|
endmodule // template_1i1o |
|
module template_body_1i1o |
#(parameter width=8) |
(input clk, |
input reset, |
output reg [width-1:0] ic_data, |
output reg ic_srdy, |
output reg ip_drdy, |
input ic_drdy, |
input [width-1:0] ip_data, |
input ip_srdy |
); |
|
always @* |
begin |
ic_data = ip_data; |
if (ip_srdy & ip_drdy) |
begin |
ic_srdy = 1; |
ip_drdy = 1; |
end |
else |
begin |
ic_srdy = 0; |
ip_drdy = 0; |
end |
end |
|
endmodule // template_body_1i1o |
|
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks") |
// End: |
/srdydrdy_lib/trunk/examples/bridge/env/run
0,0 → 1,5
#!/bin/bash |
|
iverilog -f bridge.vf |
./a.out |
|
/srdydrdy_lib/trunk/examples/bridge/env/gmii_driver.v
0,0 → 1,114
// Send an ethernet packet over GMII |
|
module gmii_driver |
(output reg [7:0] rxd, |
output reg rx_dv, |
output reg rx_clk); |
|
integer startup_skew; |
|
reg [7:0] rxbuf [0:2048]; |
reg [31:0] crc32_result; |
|
// begin start clock with random skew amount |
initial |
begin |
startup_skew = {$random} % 200; |
rx_clk = 0; |
rx_dv = 0; |
rxd = 0; |
repeat (startup_skew) #0.1; |
forever rx_clk = #4 ~rx_clk; |
end |
|
// Copied from: http://www.mindspring.com/~tcoonan/gencrc.v |
// |
// Generate a (DOCSIS) CRC32. |
// |
// Uses the GLOBAL variables: |
// |
// Globals referenced: |
// parameter CRC32_POLY = 32'h04C11DB7; |
// reg [ 7:0] crc32_packet[0:255]; |
// integer crc32_length; |
// |
// Globals modified: |
// reg [31:0] crc32_result; |
// |
localparam CRC32_POLY = 32'h04C11DB7; |
task gencrc32; |
input [31:09] crc32_length; |
integer cbyte, cbit; |
reg msb; |
reg [7:0] current_cbyte; |
reg [31:0] temp; |
begin |
crc32_result = 32'hffffffff; |
for (cbyte = 0; cbyte < crc32_length; cbyte = cbyte + 1) begin |
current_cbyte = rxbuf[cbyte]; |
for (cbit = 0; cbit < 8; cbit = cbit + 1) begin |
msb = crc32_result[31]; |
crc32_result = crc32_result << 1; |
if (msb != current_cbyte[cbit]) begin |
crc32_result = crc32_result ^ CRC32_POLY; |
crc32_result[0] = 1; |
end |
end |
end |
|
// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit. |
// |
// Mirror: |
for (cbit = 0; cbit < 32; cbit = cbit + 1) |
temp[31-cbit] = crc32_result[cbit]; |
|
// Swap and Complement: |
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]}; |
end |
endtask |
|
task send_packet; |
input [47:0] da, sa; |
input [15:0] length; |
integer p; |
begin |
{ rxbuf[0],rxbuf[1],rxbuf[2],rxbuf[3],rxbuf[4],rxbuf[5] } = da; |
{ rxbuf[6],rxbuf[7],rxbuf[8],rxbuf[9],rxbuf[10],rxbuf[11] } = sa; |
for (p=12; p<length; p=p+1) |
rxbuf[p] = $random; |
|
gencrc32 (length); |
{ rxbuf[length-4], rxbuf[length-3], |
rxbuf[length-2], rxbuf[length-1] } = crc32_result; |
|
$display ("%m : Sending packet DA=%x SA=%x of length %0d", da, sa, length); |
repeat (7) |
begin |
@(posedge rx_clk); |
rx_dv <= #1 1; |
rxd <= #1 `GMII_PRE; |
end |
|
@(posedge rx_clk); |
rxd <= #1 `GMII_SFD; |
|
p = 0; |
while (p < length) |
begin |
@(posedge rx_clk); |
rxd <= #1 rxbuf[p]; |
p = p + 1; |
end |
|
// complete 12B inter frame gap |
repeat (12) |
begin |
@(posedge rx_clk); |
rx_dv <= #1 0; |
rxd <= #1 0; |
end |
end |
endtask // send_packet |
|
|
endmodule // gmii_driver |
/srdydrdy_lib/trunk/examples/bridge/env/bridge.vf
0,0 → 1,25
../rtl/bridge.vh |
|
env_top.v |
gmii_driver.v |
|
../rtl/basic_hashfunc.v |
../rtl/bridge_ex1.v |
../rtl/concentrator.v |
../rtl/distributor.v |
../rtl/egr_oflow.v |
../rtl/fib_lookup_fsm.v |
../rtl/fib_lookup.v |
../rtl/pkt_parse.v |
../rtl/port_clocking.v |
../rtl/port_macro.v |
../rtl/port_ring_tap_fsm.v |
../rtl/port_ring_tap.v |
../rtl/sd_rx_gigmac.v |
../rtl/sd_tx_gigmac.v |
+libext+.v |
-y ../../../rtl/verilog/buffers |
-y ../../../rtl/verilog/closure |
-y ../../../rtl/verilog/forks |
-y ../../../rtl/verilog/memory |
|
/srdydrdy_lib/trunk/examples/bridge/env/env_top.v
0,0 → 1,120
`timescale 1ns/1ps |
|
module env_top; |
|
reg clk, reset; |
|
initial |
begin |
clk = 0; |
forever clk = #4 ~clk; |
end |
|
initial |
begin |
$dumpfile ("env_top.vcd"); |
$dumpvars; |
reset = 1; |
#200; |
reset = 0; |
#200; |
|
fork |
driver0.send_packet (1, 2, 20); |
driver1.send_packet (2, 3, 64); |
driver2.send_packet (3, 4, 64); |
driver3.send_packet (4, 1, 64); |
join |
|
#500; |
$finish; |
end |
|
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire gmii_rx_clk_0; // From driver0 of gmii_driver.v |
wire gmii_rx_clk_1; // From driver1 of gmii_driver.v |
wire gmii_rx_clk_2; // From driver2 of gmii_driver.v |
wire gmii_rx_clk_3; // From driver3 of gmii_driver.v |
wire gmii_rx_dv_0; // From driver0 of gmii_driver.v |
wire gmii_rx_dv_1; // From driver1 of gmii_driver.v |
wire gmii_rx_dv_2; // From driver2 of gmii_driver.v |
wire gmii_rx_dv_3; // From driver3 of gmii_driver.v |
wire [7:0] gmii_rxd_0; // From driver0 of gmii_driver.v |
wire [7:0] gmii_rxd_1; // From driver1 of gmii_driver.v |
wire [7:0] gmii_rxd_2; // From driver2 of gmii_driver.v |
wire [7:0] gmii_rxd_3; // From driver3 of gmii_driver.v |
wire gmii_tx_dv_0; // From bridge of bridge_ex1.v |
wire gmii_tx_dv_1; // From bridge of bridge_ex1.v |
wire gmii_tx_dv_2; // From bridge of bridge_ex1.v |
wire gmii_tx_dv_3; // From bridge of bridge_ex1.v |
wire [7:0] gmii_txd_0; // From bridge of bridge_ex1.v |
wire [7:0] gmii_txd_1; // From bridge of bridge_ex1.v |
wire [7:0] gmii_txd_2; // From bridge of bridge_ex1.v |
wire [7:0] gmii_txd_3; // From bridge of bridge_ex1.v |
// End of automatics |
|
/* gmii_driver AUTO_TEMPLATE |
( |
.\(.*\) (gmii_\1_@[]), |
); |
*/ |
gmii_driver driver0 |
(/*AUTOINST*/ |
// Outputs |
.rxd (gmii_rxd_0[7:0]), // Templated |
.rx_dv (gmii_rx_dv_0), // Templated |
.rx_clk (gmii_rx_clk_0)); // Templated |
|
gmii_driver driver1 |
(/*AUTOINST*/ |
// Outputs |
.rxd (gmii_rxd_1[7:0]), // Templated |
.rx_dv (gmii_rx_dv_1), // Templated |
.rx_clk (gmii_rx_clk_1)); // Templated |
|
gmii_driver driver2 |
(/*AUTOINST*/ |
// Outputs |
.rxd (gmii_rxd_2[7:0]), // Templated |
.rx_dv (gmii_rx_dv_2), // Templated |
.rx_clk (gmii_rx_clk_2)); // Templated |
|
gmii_driver driver3 |
(/*AUTOINST*/ |
// Outputs |
.rxd (gmii_rxd_3[7:0]), // Templated |
.rx_dv (gmii_rx_dv_3), // Templated |
.rx_clk (gmii_rx_clk_3)); // Templated |
|
bridge_ex1 bridge |
(/*AUTOINST*/ |
// Outputs |
.gmii_tx_dv_0 (gmii_tx_dv_0), |
.gmii_tx_dv_1 (gmii_tx_dv_1), |
.gmii_tx_dv_2 (gmii_tx_dv_2), |
.gmii_tx_dv_3 (gmii_tx_dv_3), |
.gmii_txd_0 (gmii_txd_0[7:0]), |
.gmii_txd_1 (gmii_txd_1[7:0]), |
.gmii_txd_2 (gmii_txd_2[7:0]), |
.gmii_txd_3 (gmii_txd_3[7:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.gmii_rx_clk_0 (gmii_rx_clk_0), |
.gmii_rx_clk_1 (gmii_rx_clk_1), |
.gmii_rx_clk_2 (gmii_rx_clk_2), |
.gmii_rx_clk_3 (gmii_rx_clk_3), |
.gmii_rx_dv_0 (gmii_rx_dv_0), |
.gmii_rx_dv_1 (gmii_rx_dv_1), |
.gmii_rx_dv_2 (gmii_rx_dv_2), |
.gmii_rx_dv_3 (gmii_rx_dv_3), |
.gmii_rxd_0 (gmii_rxd_0[7:0]), |
.gmii_rxd_1 (gmii_rxd_1[7:0]), |
.gmii_rxd_2 (gmii_rxd_2[7:0]), |
.gmii_rxd_3 (gmii_rxd_3[7:0])); |
|
endmodule // env_top |
// Local Variables: |
// verilog-library-directories:("." "../rtl") |
// End: |