OpenCores
URL https://opencores.org/ocsvn/twofish/twofish/trunk

Subversion Repositories twofish

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Rev 7 → Rev 8

/trunk/vhdl/twofish.vhd
5332,7 → 5332,7
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
--
-- twofish encryption round with 128 bit key input
-- twofish encryption round with 192 bit key input
--
 
library ieee;
5432,7 → 5432,7
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
--
-- twofish decryption round with 128 bit key input
-- twofish decryption round with 192 bit key input
--
 
library ieee;
5525,3 → 5525,2480
-- --
-- =============================================== --
-- =============================================== --
 
 
--
-- reed solomon for 256bits key
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity reed_solomon256 is
port (
in_rs256 : in std_logic_vector(255 downto 0);
out_Sfirst_rs256,
out_Ssecond_rs256,
out_Sthird_rs256,
out_Sfourth_rs256 : out std_logic_vector(31 downto 0)
);
end reed_solomon256;
 
architecture rs_256_arch of reed_solomon256 is
 
-- declaring all components necessary for reed solomon
-- 01
component mul01
port (
in_mul01 : in std_logic_vector(7 downto 0);
out_mul01 : out std_logic_vector(7 downto 0)
);
end component;
 
-- a4
component mula4
port (
in_mula4 : in std_logic_vector(7 downto 0);
out_mula4 : out std_logic_vector(7 downto 0)
);
end component;
 
-- 55
component mul55
port (
in_mul55 : in std_logic_vector(7 downto 0);
out_mul55 : out std_logic_vector(7 downto 0)
);
end component;
 
-- 87
component mul87
port (
in_mul87 : in std_logic_vector(7 downto 0);
out_mul87 : out std_logic_vector(7 downto 0)
);
end component;
 
-- 5a
component mul5a
port (
in_mul5a : in std_logic_vector(7 downto 0);
out_mul5a : out std_logic_vector(7 downto 0)
);
end component;
 
-- 58
component mul58
port (
in_mul58 : in std_logic_vector(7 downto 0);
out_mul58 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- db
component muldb
port (
in_muldb : in std_logic_vector(7 downto 0);
out_muldb : out std_logic_vector(7 downto 0)
);
end component;
 
-- 9e
component mul9e
port (
in_mul9e : in std_logic_vector(7 downto 0);
out_mul9e : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- 56
component mul56
port (
in_mul56 : in std_logic_vector(7 downto 0);
out_mul56 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- 82
component mul82
port (
in_mul82 : in std_logic_vector(7 downto 0);
out_mul82 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- f3
component mulf3
port (
in_mulf3 : in std_logic_vector(7 downto 0);
out_mulf3 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- 1e
component mul1e
port (
in_mul1e : in std_logic_vector(7 downto 0);
out_mul1e : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- c6
component mulc6
port (
in_mulc6 : in std_logic_vector(7 downto 0);
out_mulc6 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- 68
component mul68
port (
in_mul68 : in std_logic_vector(7 downto 0);
out_mul68 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- e5
component mule5
port (
in_mule5 : in std_logic_vector(7 downto 0);
out_mule5 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- 02
component mul02
port (
in_mul02 : in std_logic_vector(7 downto 0);
out_mul02 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- a1
component mula1
port (
in_mula1 : in std_logic_vector(7 downto 0);
out_mula1 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- fc
component mulfc
port (
in_mulfc : in std_logic_vector(7 downto 0);
out_mulfc : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- c1
component mulc1
port (
in_mulc1 : in std_logic_vector(7 downto 0);
out_mulc1 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- 47
component mul47
port (
in_mul47 : in std_logic_vector(7 downto 0);
out_mul47 : out std_logic_vector(7 downto 0)
);
end component;
 
 
 
-- ae
component mulae
port (
in_mulae : in std_logic_vector(7 downto 0);
out_mulae : out std_logic_vector(7 downto 0)
);
end component;
 
 
 
-- 3d
component mul3d
port (
in_mul3d : in std_logic_vector(7 downto 0);
out_mul3d : out std_logic_vector(7 downto 0)
);
end component;
 
 
 
-- 19
component mul19
port (
in_mul19 : in std_logic_vector(7 downto 0);
out_mul19 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- 03
component mul03
port (
in_mul03 : in std_logic_vector(7 downto 0);
out_mul03 : out std_logic_vector(7 downto 0)
);
end component;
 
 
-- declaring internal signals
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,
m16, m17, m18, m19, m20, m21, m22, m23, m24, m25, m26, m27, m28, m29, m30, m31 : std_logic_vector(7 downto 0);
signal s00,s01,s02,s03,s10,s11,s12,s13, s20, s21, s22, s23, s30, s31, s32, s33 : std_logic_vector(7 downto 0);
 
signal m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e,
m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5,
m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19,
m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03 : std_logic_vector(7 downto 0);
 
signal m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e,
m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5,
m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19,
m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03 : std_logic_vector(7 downto 0);
 
signal m16_01,m17_a4,m18_55,m19_87,m20_5a,m21_58,m22_db,m23_9e,
m16_a4,m17_56,m18_82,m19_f3,m20_1e,m21_c6,m22_68,m23_e5,
m16_02,m17_a1,m18_fc,m19_c1,m20_47,m21_ae,m22_3d,m23_19,
m16_a4_1,m17_55,m18_87,m19_5a,m20_58,m21_db,m22_9e,m23_03 : std_logic_vector(7 downto 0);
 
signal m24_01,m25_a4,m26_55,m27_87,m28_5a,m29_58,m30_db,m31_9e,
m24_a4,m25_56,m26_82,m27_f3,m28_1e,m29_c6,m30_68,m31_e5,
m24_02,m25_a1,m26_fc,m27_c1,m28_47,m29_ae,m30_3d,m31_19,
m24_a4_1,m25_55,m26_87,m27_5a,m28_58,m29_db,m30_9e,m31_03 : std_logic_vector(7 downto 0);
 
 
-- begin architecture description
begin
 
-- first, we separate the input to the respective m
-- for s0j j=0..3
m0 <= in_rs256(7 downto 0);
m1 <= in_rs256(15 downto 8);
m2 <= in_rs256(23 downto 16);
m3 <= in_rs256(31 downto 24);
m4 <= in_rs256(39 downto 32);
m5 <= in_rs256(47 downto 40);
m6 <= in_rs256(55 downto 48);
m7 <= in_rs256(63 downto 56);
 
-- for s1j j=0..3
m8 <= in_rs256(71 downto 64);
m9 <= in_rs256(79 downto 72);
m10 <= in_rs256(87 downto 80);
m11 <= in_rs256(95 downto 88);
m12 <= in_rs256(103 downto 96);
m13 <= in_rs256(111 downto 104);
m14 <= in_rs256(119 downto 112);
m15 <= in_rs256(127 downto 120);
 
-- for s2j j=0..3
m16 <= in_rs256(135 downto 128);
m17 <= in_rs256(143 downto 136);
m18 <= in_rs256(151 downto 144);
m19 <= in_rs256(159 downto 152);
m20 <= in_rs256(167 downto 160);
m21 <= in_rs256(175 downto 168);
m22 <= in_rs256(183 downto 176);
m23 <= in_rs256(191 downto 184);
 
-- for s3j j=0..3
m24 <= in_rs256(199 downto 192);
m25 <= in_rs256(207 downto 200);
m26 <= in_rs256(215 downto 208);
m27 <= in_rs256(223 downto 216);
m28 <= in_rs256(231 downto 224);
m29 <= in_rs256(239 downto 232);
m30 <= in_rs256(247 downto 240);
m31 <= in_rs256(255 downto 248);
 
-- after separating signals, we drive them to multipliers
-- the first line of m0..7 forms s00
m0_with_01: mul01
port map (
in_mul01 => m0,
out_mul01 => m0_01
);
 
m1_with_a4: mula4
port map (
in_mula4 => m1,
out_mula4 => m1_a4
);
 
m2_with_55: mul55
port map (
in_mul55 => m2,
out_mul55 => m2_55
);
 
m3_with_87: mul87
port map (
in_mul87 => m3,
out_mul87 => m3_87
);
 
m4_with_5a: mul5a
port map (
in_mul5a => m4,
out_mul5a => m4_5a
);
 
m5_with_58: mul58
port map (
in_mul58 => m5,
out_mul58 => m5_58
);
 
m6_with_db: muldb
port map (
in_muldb => m6,
out_muldb => m6_db
);
 
m7_with_9e: mul9e
port map (
in_mul9e => m7,
out_mul9e => m7_9e
);
 
-- the second row creates s01
m0_with_a4: mula4
port map (
in_mula4 => m0,
out_mula4 => m0_a4
);
 
m1_with_56: mul56
port map (
in_mul56 => m1,
out_mul56 => m1_56
);
 
m2_with_82: mul82
port map (
in_mul82 => m2,
out_mul82 => m2_82
);
m3_with_f3: mulf3
port map (
in_mulf3 => m3,
out_mulf3 => m3_f3
);
 
m4_with_1e: mul1e
port map (
in_mul1e => m4,
out_mul1e => m4_1e
);
 
m5_with_c6: mulc6
port map (
in_mulc6 => m5,
out_mulc6 => m5_c6
);
 
m6_with_68: mul68
port map (
in_mul68 => m6,
out_mul68 => m6_68
);
 
m7_with_e5: mule5
port map (
in_mule5 => m7,
out_mule5 => m7_e5
);
 
-- the third row creates s02
m0_with_02: mul02
port map (
in_mul02 => m0,
out_mul02 => m0_02
);
 
m1_with_a1: mula1
port map (
in_mula1 => m1,
out_mula1 => m1_a1
);
 
m2_with_fc: mulfc
port map (
in_mulfc => m2,
out_mulfc => m2_fc
);
 
m3_with_c1: mulc1
port map (
in_mulc1 => m3,
out_mulc1 => m3_c1
);
 
m4_with_47: mul47
port map (
in_mul47 => m4,
out_mul47 => m4_47
);
 
m5_with_ae: mulae
port map (
in_mulae => m5,
out_mulae => m5_ae
);
 
m6_with_3d: mul3d
port map (
in_mul3d => m6,
out_mul3d => m6_3d
);
 
m7_with_19: mul19
port map (
in_mul19 => m7,
out_mul19 => m7_19
);
 
-- the fourth row creates s03
m0_with_a4_1: mula4
port map (
in_mula4 => m0,
out_mula4 => m0_a4_1
);
 
m1_with_55: mul55
port map (
in_mul55 => m1,
out_mul55 => m1_55
);
 
m2_with_87: mul87
port map (
in_mul87 => m2,
out_mul87 => m2_87
);
 
m3_with_5a: mul5a
port map (
in_mul5a => m3,
out_mul5a => m3_5a
);
 
m4_with_58: mul58
port map (
in_mul58 => m4,
out_mul58 => m4_58
);
 
m5_with_db: muldb
port map (
in_muldb => m5,
out_muldb => m5_db
);
 
m6_with_9e: mul9e
port map (
in_mul9e => m6,
out_mul9e => m6_9e
);
 
m7_with_03: mul03
port map (
in_mul03 => m7,
out_mul03 => m7_03
);
 
 
-- we create the s1,j j=0..3
-- the first row of m8..15 creates the s10
m8_with_01: mul01
port map (
in_mul01 => m8,
out_mul01 => m8_01
);
 
m9_with_a4: mula4
port map (
in_mula4 => m9,
out_mula4 => m9_a4
);
 
m10_with_55: mul55
port map (
in_mul55 => m10,
out_mul55 => m10_55
);
 
m11_with_87: mul87
port map (
in_mul87 => m11,
out_mul87 => m11_87
);
 
m12_with_5a: mul5a
port map (
in_mul5a => m12,
out_mul5a => m12_5a
);
 
m13_with_58: mul58
port map (
in_mul58 => m13,
out_mul58 => m13_58
);
 
m14_with_db: muldb
port map (
in_muldb => m14,
out_muldb => m14_db
);
 
m15_with_9e: mul9e
port map (
in_mul9e => m15,
out_mul9e => m15_9e
);
 
-- the second row creates s11
m8_with_a4: mula4
port map (
in_mula4 => m8,
out_mula4 => m8_a4
);
 
m9_with_56: mul56
port map (
in_mul56 => m9,
out_mul56 => m9_56
);
 
m10_with_82: mul82
port map (
in_mul82 => m10,
out_mul82 => m10_82
);
m11_with_f3: mulf3
port map (
in_mulf3 => m11,
out_mulf3 => m11_f3
);
 
m12_with_1e: mul1e
port map (
in_mul1e => m12,
out_mul1e => m12_1e
);
 
m13_with_c6: mulc6
port map (
in_mulc6 => m13,
out_mulc6 => m13_c6
);
 
m14_with_68: mul68
port map (
in_mul68 => m14,
out_mul68 => m14_68
);
 
m15_with_e5: mule5
port map (
in_mule5 => m15,
out_mule5 => m15_e5
);
 
-- the third row creates s12
m8_with_02: mul02
port map (
in_mul02 => m8,
out_mul02 => m8_02
);
 
m9_with_a1: mula1
port map (
in_mula1 => m9,
out_mula1 => m9_a1
);
 
m10_with_fc: mulfc
port map (
in_mulfc => m10,
out_mulfc => m10_fc
);
 
m11_with_c1: mulc1
port map (
in_mulc1 => m11,
out_mulc1 => m11_c1
);
 
m12_with_47: mul47
port map (
in_mul47 => m12,
out_mul47 => m12_47
);
 
m13_with_ae: mulae
port map (
in_mulae => m13,
out_mulae => m13_ae
);
 
m14_with_3d: mul3d
port map (
in_mul3d => m14,
out_mul3d => m14_3d
);
 
m15_with_19: mul19
port map (
in_mul19 => m15,
out_mul19 => m15_19
);
 
-- the fourth row creates s13
m8_with_a4_1: mula4
port map (
in_mula4 => m8,
out_mula4 => m8_a4_1
);
 
m9_with_55: mul55
port map (
in_mul55 => m9,
out_mul55 => m9_55
);
 
m10_with_87: mul87
port map (
in_mul87 => m10,
out_mul87 => m10_87
);
 
m11_with_5a: mul5a
port map (
in_mul5a => m11,
out_mul5a => m11_5a
);
 
m12_with_58: mul58
port map (
in_mul58 => m12,
out_mul58 => m12_58
);
 
m13_with_db: muldb
port map (
in_muldb => m13,
out_muldb => m13_db
);
 
m14_with_9e: mul9e
port map (
in_mul9e => m14,
out_mul9e => m14_9e
);
 
m15_with_03: mul03
port map (
in_mul03 => m15,
out_mul03 => m15_03
);
 
-- we create the s2,j j=0..3
-- the first row of m16..23 creates the s20
m16_with_01: mul01
port map (
in_mul01 => m16,
out_mul01 => m16_01
);
 
m17_with_a4: mula4
port map (
in_mula4 => m17,
out_mula4 => m17_a4
);
 
m18_with_55: mul55
port map (
in_mul55 => m18,
out_mul55 => m18_55
);
 
m19_with_87: mul87
port map (
in_mul87 => m19,
out_mul87 => m19_87
);
 
m20_with_5a: mul5a
port map (
in_mul5a => m20,
out_mul5a => m20_5a
);
 
m21_with_58: mul58
port map (
in_mul58 => m21,
out_mul58 => m21_58
);
 
m22_with_db: muldb
port map (
in_muldb => m22,
out_muldb => m22_db
);
 
m23_with_9e: mul9e
port map (
in_mul9e => m23,
out_mul9e => m23_9e
);
 
-- the second row creates s21
m16_with_a4: mula4
port map (
in_mula4 => m16,
out_mula4 => m16_a4
);
 
m17_with_56: mul56
port map (
in_mul56 => m17,
out_mul56 => m17_56
);
 
m18_with_82: mul82
port map (
in_mul82 => m18,
out_mul82 => m18_82
);
m19_with_f3: mulf3
port map (
in_mulf3 => m19,
out_mulf3 => m19_f3
);
 
m20_with_1e: mul1e
port map (
in_mul1e => m20,
out_mul1e => m20_1e
);
 
m21_with_c6: mulc6
port map (
in_mulc6 => m21,
out_mulc6 => m21_c6
);
 
m22_with_68: mul68
port map (
in_mul68 => m22,
out_mul68 => m22_68
);
 
m23_with_e5: mule5
port map (
in_mule5 => m23,
out_mule5 => m23_e5
);
 
-- the third row creates s22
m16_with_02: mul02
port map (
in_mul02 => m16,
out_mul02 => m16_02
);
 
m17_with_a1: mula1
port map (
in_mula1 => m17,
out_mula1 => m17_a1
);
 
m18_with_fc: mulfc
port map (
in_mulfc => m18,
out_mulfc => m18_fc
);
 
m19_with_c1: mulc1
port map (
in_mulc1 => m19,
out_mulc1 => m19_c1
);
 
m20_with_47: mul47
port map (
in_mul47 => m20,
out_mul47 => m20_47
);
 
m21_with_ae: mulae
port map (
in_mulae => m21,
out_mulae => m21_ae
);
 
m22_with_3d: mul3d
port map (
in_mul3d => m22,
out_mul3d => m22_3d
);
 
m23_with_19: mul19
port map (
in_mul19 => m23,
out_mul19 => m23_19
);
 
-- the fourth row creates s23
m16_with_a4_1: mula4
port map (
in_mula4 => m16,
out_mula4 => m16_a4_1
);
 
m17_with_55: mul55
port map (
in_mul55 => m17,
out_mul55 => m17_55
);
 
m18_with_87: mul87
port map (
in_mul87 => m18,
out_mul87 => m18_87
);
 
m19_with_5a: mul5a
port map (
in_mul5a => m19,
out_mul5a => m19_5a
);
 
m20_with_58: mul58
port map (
in_mul58 => m20,
out_mul58 => m20_58
);
 
m21_with_db: muldb
port map (
in_muldb => m21,
out_muldb => m21_db
);
 
m22_with_9e: mul9e
port map (
in_mul9e => m22,
out_mul9e => m22_9e
);
 
m23_with_03: mul03
port map (
in_mul03 => m23,
out_mul03 => m23_03
);
 
-- we create the s3j j=0..3
-- the first row of m24..31 creates the s30
m24_with_01: mul01
port map (
in_mul01 => m24,
out_mul01 => m24_01
);
 
m25_with_a4: mula4
port map (
in_mula4 => m25,
out_mula4 => m25_a4
);
 
m26_with_55: mul55
port map (
in_mul55 => m26,
out_mul55 => m26_55
);
 
m27_with_87: mul87
port map (
in_mul87 => m27,
out_mul87 => m27_87
);
 
m28_with_5a: mul5a
port map (
in_mul5a => m28,
out_mul5a => m28_5a
);
 
m29_with_58: mul58
port map (
in_mul58 => m29,
out_mul58 => m29_58
);
 
m30_with_db: muldb
port map (
in_muldb => m30,
out_muldb => m30_db
);
 
m31_with_9e: mul9e
port map (
in_mul9e => m31,
out_mul9e => m31_9e
);
 
-- the second row creates s31
m24_with_a4: mula4
port map (
in_mula4 => m24,
out_mula4 => m24_a4
);
 
m25_with_56: mul56
port map (
in_mul56 => m25,
out_mul56 => m25_56
);
 
m26_with_82: mul82
port map (
in_mul82 => m26,
out_mul82 => m26_82
);
m27_with_f3: mulf3
port map (
in_mulf3 => m27,
out_mulf3 => m27_f3
);
 
m28_with_1e: mul1e
port map (
in_mul1e => m28,
out_mul1e => m28_1e
);
 
m29_with_c6: mulc6
port map (
in_mulc6 => m29,
out_mulc6 => m29_c6
);
 
m30_with_68: mul68
port map (
in_mul68 => m30,
out_mul68 => m30_68
);
 
m31_with_e5: mule5
port map (
in_mule5 => m31,
out_mule5 => m31_e5
);
 
-- the third row creates s32
m24_with_02: mul02
port map (
in_mul02 => m24,
out_mul02 => m24_02
);
 
m25_with_a1: mula1
port map (
in_mula1 => m25,
out_mula1 => m25_a1
);
 
m26_with_fc: mulfc
port map (
in_mulfc => m26,
out_mulfc => m26_fc
);
 
m27_with_c1: mulc1
port map (
in_mulc1 => m27,
out_mulc1 => m27_c1
);
 
m28_with_47: mul47
port map (
in_mul47 => m28,
out_mul47 => m28_47
);
 
m29_with_ae: mulae
port map (
in_mulae => m29,
out_mulae => m29_ae
);
 
m30_with_3d: mul3d
port map (
in_mul3d => m30,
out_mul3d => m30_3d
);
 
m31_with_19: mul19
port map (
in_mul19 => m31,
out_mul19 => m31_19
);
 
-- the fourth row creates s33
m24_with_a4_1: mula4
port map (
in_mula4 => m24,
out_mula4 => m24_a4_1
);
 
m25_with_55: mul55
port map (
in_mul55 => m25,
out_mul55 => m25_55
);
 
m26_with_87: mul87
port map (
in_mul87 => m26,
out_mul87 => m26_87
);
 
m27_with_5a: mul5a
port map (
in_mul5a => m27,
out_mul5a => m27_5a
);
 
m28_with_58: mul58
port map (
in_mul58 => m28,
out_mul58 => m28_58
);
 
m29_with_db: muldb
port map (
in_muldb => m29,
out_muldb => m29_db
);
 
m30_with_9e: mul9e
port map (
in_mul9e => m30,
out_mul9e => m30_9e
);
 
m31_with_03: mul03
port map (
in_mul03 => m31,
out_mul03 => m31_03
);
 
-- after getting the results from multipliers
-- we combine them in order to get the additions
s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e;
s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5;
s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19;
s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03;
 
-- after creating s0,j j=0...3 we form the S0
-- little endian
out_Sfirst_rs256 <= s03 & s02 & s01 & s00;
 
s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e;
s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5;
s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19;
s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03;
 
-- after creating s1,j j=0...3 we form the S1
-- little endian
out_Ssecond_rs256 <= s13 & s12 & s11 & s10;
 
s20 <= m16_01 XOR m17_a4 XOR m18_55 XOR m19_87 XOR m20_5a XOR m21_58 XOR m22_db XOR m23_9e;
s21 <= m16_a4 XOR m17_56 XOR m18_82 XOR m19_f3 XOR m20_1e XOR m21_c6 XOR m22_68 XOR m23_e5;
s22 <= m16_02 XOR m17_a1 XOR m18_fc XOR m19_c1 XOR m20_47 XOR m21_ae XOR m22_3d XOR m23_19;
s23 <= m16_a4_1 XOR m17_55 XOR m18_87 XOR m19_5a XOR m20_58 XOR m21_db XOR m22_9e XOR m23_03;
 
-- after creating s2j j=0...3 we form the S2
-- little endian
out_Sthird_rs256 <= s23 & s22 & s21 & s20;
 
s30 <= m24_01 XOR m25_a4 XOR m26_55 XOR m27_87 XOR m28_5a XOR m29_58 XOR m30_db XOR m31_9e;
s31 <= m24_a4 XOR m25_56 XOR m26_82 XOR m27_f3 XOR m28_1e XOR m29_c6 XOR m30_68 XOR m31_e5;
s32 <= m24_02 XOR m25_a1 XOR m26_fc XOR m27_c1 XOR m28_47 XOR m29_ae XOR m30_3d XOR m31_19;
s33 <= m24_a4_1 XOR m25_55 XOR m26_87 XOR m27_5a XOR m28_58 XOR m29_db XOR m30_9e XOR m31_03;
 
-- after creating s3j j=0...3 we form the S3
-- little endian
out_Sfourth_rs256 <= s33 & s32 & s31 & s30;
 
end rs_256_arch;
 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
--
-- h function for 256 bits key
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity h_256 is
port (
in_h256 : in std_logic_vector(7 downto 0);
Mfirst_h256,
Msecond_h256,
Mthird_h256,
Mfourth_h256 : in std_logic_vector(31 downto 0);
out_h256 : out std_logic_vector(31 downto 0)
);
end h_256;
 
architecture h256_arch of h_256 is
 
-- we declare internal signals
signal from_first_row,
to_second_row,
from_second_row,
to_third_row,
from_third_row,
to_fourth_row,
from_fourth_row,
to_fifth_row,
to_mds : std_logic_vector(31 downto 0);
-- we declare all components needed
component q0
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end component;
component q1
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end component;
 
component mds
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end component;
 
-- begin architecture description
begin
-- first row of q
first_q1_1: q1
port map (
in_q1 => in_h256,
out_q1 => from_first_row(7 downto 0)
);
 
first_q0_1: q0
port map (
in_q0 => in_h256,
out_q0 => from_first_row(15 downto 8)
);
 
first_q0_2: q0
port map (
in_q0 => in_h256,
out_q0 => from_first_row(23 downto 16)
);
 
first_q1_2: q1
port map (
in_q1 => in_h256,
out_q1 => from_first_row(31 downto 24)
);
 
-- we perform the XOR of the results of the first row
-- with first M of h (Mfirst_h256)
to_second_row <= from_first_row XOR Mfirst_h256;
 
-- second row of q
second_q1_1: q1
port map (
in_q1 => to_second_row(7 downto 0),
out_q1 => from_second_row(7 downto 0)
);
 
second_q1_2: q1
port map (
in_q1 => to_second_row(15 downto 8),
out_q1 => from_second_row(15 downto 8)
);
 
second_q0_1: q0
port map (
in_q0 => to_second_row(23 downto 16),
out_q0 => from_second_row(23 downto 16)
);
 
second_q0_2: q0
port map (
in_q0 => to_second_row(31 downto 24),
out_q0 => from_second_row(31 downto 24)
);
 
-- we perform the XOR of the results of the second row
-- with second M of h (Msecond_h256)
to_third_row <= from_second_row XOR Msecond_h256;
 
-- third row of q
third_q0_1: q0
port map (
in_q0 => to_third_row(7 downto 0),
out_q0 => from_third_row(7 downto 0)
);
third_q1_1: q1
port map (
in_q1 => to_third_row(15 downto 8),
out_q1 => from_third_row(15 downto 8)
);
third_q0_2: q0
port map (
in_q0 => to_third_row(23 downto 16),
out_q0 => from_third_row(23 downto 16)
);
third_q1_2: q1
port map (
in_q1 => to_third_row(31 downto 24),
out_q1 => from_third_row(31 downto 24)
);
 
-- we perform the XOR of the results of the third row
-- with third M of h (Mthird_h256)
to_fourth_row <= from_third_row XOR Mthird_h256;
 
-- fourth row of q
fourth_q0_1: q0
port map (
in_q0 => to_fourth_row(7 downto 0),
out_q0 => from_fourth_row(7 downto 0)
);
fourth_q0_2: q0
port map (
in_q0 => to_fourth_row(15 downto 8),
out_q0 => from_fourth_row(15 downto 8)
);
fourth_q1_1: q1
port map (
in_q1 => to_fourth_row(23 downto 16),
out_q1 => from_fourth_row(23 downto 16)
);
fourth_q1_2: q1
port map (
in_q1 => to_fourth_row(31 downto 24),
out_q1 => from_fourth_row(31 downto 24)
);
-- we perform the fourth XOR
to_fifth_row <= from_fourth_row XOR Mfourth_h256;
-- the fifth row of q
fifth_q1_1: q1
port map (
in_q1 => to_fifth_row(7 downto 0),
out_q1 => to_mds(7 downto 0)
);
fifth_q0_1: q0
port map (
in_q0 => to_fifth_row(15 downto 8),
out_q0 => to_mds(15 downto 8)
);
fifth_q1_2: q1
port map (
in_q1 => to_fifth_row(23 downto 16),
out_q1 => to_mds(23 downto 16)
);
fifth_q0_2: q0
port map (
in_q0 => to_fifth_row(31 downto 24),
out_q0 => to_mds(31 downto 24)
);
-- mds table
mds_table: mds
port map (
y0 => to_mds(7 downto 0),
y1 => to_mds(15 downto 8),
y2 => to_mds(23 downto 16),
y3 => to_mds(31 downto 24),
z0 => out_h256(7 downto 0),
z1 => out_h256(15 downto 8),
z2 => out_h256(23 downto 16),
z3 => out_h256(31 downto 24)
);
 
end h256_arch;
 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
 
--
-- g function for 256 bits key
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity g_256 is
port (
in_g256,
in_S0_g256,
in_S1_g256,
in_S2_g256,
in_S3_g256 : in std_logic_vector(31 downto 0);
out_g256 : out std_logic_vector(31 downto 0)
);
end g_256;
 
architecture g256_arch of g_256 is
 
-- we declare the internal signals
signal from_first_row,
to_second_row,
from_second_row,
to_third_row,
from_third_row,
to_fourth_row,
from_fourth_row,
to_fifth_row,
to_mds : std_logic_vector(31 downto 0);
 
component q0
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end component;
component q1
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end component;
 
component mds
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end component;
 
-- begin architecture description
begin
 
-- first row of q
first_q1_1: q1
port map (
in_q1 => in_g256(7 downto 0),
out_q1 => from_first_row(7 downto 0)
);
 
first_q0_1: q0
port map (
in_q0 => in_g256(15 downto 8),
out_q0 => from_first_row(15 downto 8)
);
 
first_q0_2: q0
port map (
in_q0 => in_g256(23 downto 16),
out_q0 => from_first_row(23 downto 16)
);
 
first_q1_2: q1
port map (
in_q1 => in_g256(31 downto 24),
out_q1 => from_first_row(31 downto 24)
);
 
-- we perform the XOR of the results of the first row
-- with S0
to_second_row <= from_first_row XOR in_S0_g256;
 
-- second row of q
second_q1_1: q1
port map (
in_q1 => to_second_row(7 downto 0),
out_q1 => from_second_row(7 downto 0)
);
 
second_q1_2: q1
port map (
in_q1 => to_second_row(15 downto 8),
out_q1 => from_second_row(15 downto 8)
);
 
second_q0_1: q0
port map (
in_q0 => to_second_row(23 downto 16),
out_q0 => from_second_row(23 downto 16)
);
 
second_q0_2: q0
port map (
in_q0 => to_second_row(31 downto 24),
out_q0 => from_second_row(31 downto 24)
);
 
-- we perform the XOR of the results of the second row
-- with S1
to_third_row <= from_second_row XOR in_S1_g256;
 
-- third row of q
third_q0_1: q0
port map (
in_q0 => to_third_row(7 downto 0),
out_q0 => from_third_row(7 downto 0)
);
third_q1_1: q1
port map (
in_q1 => to_third_row(15 downto 8),
out_q1 => from_third_row(15 downto 8)
);
third_q0_2: q0
port map (
in_q0 => to_third_row(23 downto 16),
out_q0 => from_third_row(23 downto 16)
);
third_q1_2: q1
port map (
in_q1 => to_third_row(31 downto 24),
out_q1 => from_third_row(31 downto 24)
);
 
-- we perform the XOR of the results of the third row
-- with S2
to_fourth_row <= from_third_row XOR in_S2_g256;
 
-- fourth row of q
fourth_q0_1: q0
port map (
in_q0 => to_fourth_row(7 downto 0),
out_q0 => from_fourth_row(7 downto 0)
);
fourth_q0_2: q0
port map (
in_q0 => to_fourth_row(15 downto 8),
out_q0 => from_fourth_row(15 downto 8)
);
fourth_q1_1: q1
port map (
in_q1 => to_fourth_row(23 downto 16),
out_q1 => from_fourth_row(23 downto 16)
);
fourth_q1_2: q1
port map (
in_q1 => to_fourth_row(31 downto 24),
out_q1 => from_fourth_row(31 downto 24)
);
-- we perform the fourth XOR
to_fifth_row <= from_fourth_row XOR in_S3_g256;
-- the fifth row of q
fifth_q1_1: q1
port map (
in_q1 => to_fifth_row(7 downto 0),
out_q1 => to_mds(7 downto 0)
);
fifth_q0_1: q0
port map (
in_q0 => to_fifth_row(15 downto 8),
out_q0 => to_mds(15 downto 8)
);
fifth_q1_2: q1
port map (
in_q1 => to_fifth_row(23 downto 16),
out_q1 => to_mds(23 downto 16)
);
fifth_q0_2: q0
port map (
in_q0 => to_fifth_row(31 downto 24),
out_q0 => to_mds(31 downto 24)
);
-- mds table
mds_table: mds
port map (
y0 => to_mds(7 downto 0),
y1 => to_mds(15 downto 8),
y2 => to_mds(23 downto 16),
y3 => to_mds(31 downto 24),
z0 => out_g256(7 downto 0),
z1 => out_g256(15 downto 8),
z2 => out_g256(23 downto 16),
z3 => out_g256(31 downto 24)
);
 
end g256_arch;
 
 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
 
--
-- f function with 256 bits key
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity f_256 is
port (
up_in_f256,
low_in_f256,
S0_in_f256,
S1_in_f256,
S2_in_f256,
S3_in_f256,
up_key_f256,
low_key_f256 : in std_logic_vector(31 downto 0);
up_out_f256,
low_out_f256 : out std_logic_vector(31 downto 0)
);
end f_256;
 
architecture f256_arch of f_256 is
 
-- we declare the internal signals
signal from_shift_8,
to_up_pht,
to_low_pht,
to_up_key,
to_low_key,
intermediate_carry1,
intermediate_carry2 : std_logic_vector(31 downto 0);
signal zero : std_logic;
component g_256
port (
in_g256,
in_S0_g256,
in_S1_g256,
in_S2_g256,
in_S3_g256 : in std_logic_vector(31 downto 0);
out_g256 : out std_logic_vector(31 downto 0)
);
end component;
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
 
component adder
port (
in1_adder,
in2_adder,
in_carry_adder : in std_logic;
out_adder,
out_carry_adder : out std_logic
);
end component;
 
-- begin architecture description
begin
 
-- we initialize zero
zero <= '0';
-- upper g_256
upper_g256: g_256
port map (
in_g256 => up_in_f256,
in_S0_g256 => S0_in_f256,
in_S1_g256 => S1_in_f256,
in_S2_g256 => S2_in_f256,
in_S3_g256 => S3_in_f256,
out_g256 => to_up_pht
);
-- left rotation by 8
from_shift_8(31 downto 8) <= low_in_f256(23 downto 0);
from_shift_8(7 downto 0) <= low_in_f256(31 downto 24);
-- lower g256
lower_g256: g_256
port map (
in_g256 => from_shift_8,
in_S0_g256 => S0_in_f256,
in_S1_g256 => S1_in_f256,
in_S2_g256 => S2_in_f256,
in_S3_g256 => S3_in_f256,
out_g256 => to_low_pht
);
-- pht
pht_transform: pht
port map (
up_in_pht => to_up_pht,
down_in_pht => to_low_pht,
up_out_pht => to_up_key,
down_out_pht => to_low_key
);
-- upper adder of 32 bits
up_adder: for i in 0 to 31 generate
first: if (i=0) generate
the_adder: adder
port map (
in1_adder => to_up_key(0),
in2_adder => up_key_f256(0),
in_carry_adder => zero,
out_adder => up_out_f256(0),
out_carry_adder => intermediate_carry1(0)
);
end generate first;
the_rest: if (i>0) generate
the_adders: adder
port map (
in1_adder => to_up_key(i),
in2_adder => up_key_f256(i),
in_carry_adder => intermediate_carry1(i-1),
out_adder => up_out_f256(i),
out_carry_adder => intermediate_carry1(i)
);
end generate the_rest;
end generate up_adder;
 
-- lower adder of 32 bits
low_adder: for i in 0 to 31 generate
first1: if (i=0) generate
the_adder1:adder
port map (
in1_adder => to_low_key(0),
in2_adder => low_key_f256(0),
in_carry_adder => zero,
out_adder => low_out_f256(0),
out_carry_adder => intermediate_carry2(0)
);
end generate first1;
the_rest1: if (i>0) generate
the_adders1: adder
port map (
in1_adder => to_low_key(i),
in2_adder => low_key_f256(i),
in_carry_adder => intermediate_carry2(i-1),
out_adder => low_out_f256(i),
out_carry_adder => intermediate_carry2(i)
);
end generate the_rest1;
end generate low_adder;
 
end f256_arch;
 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
--
-- twofish key scheduler for 256 bits key input
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity twofish_keysched256 is
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end twofish_keysched256;
architecture twofish_keysched256_arch of twofish_keysched256 is
 
-- we declare internal signals
signal to_up_pht,
to_shift_8,
from_shift_8,
to_shift_9,
M0, M1, M2, M3, M4, M5, M6, M7 : std_logic_vector(31 downto 0);
 
signal byte15, byte14, byte13, byte12, byte11, byte10,
byte9, byte8, byte7, byte6, byte5, byte4,
byte3, byte2, byte1, byte0,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23,
byte24, byte25, byte26, byte27,
byte28, byte29, byte30, byte31 : std_logic_vector(7 downto 0);
-- we declare the components to be used
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
 
component h_256
port (
in_h256 : in std_logic_vector(7 downto 0);
Mfirst_h256,
Msecond_h256,
Mthird_h256,
Mfourth_h256 : in std_logic_vector(31 downto 0);
out_h256 : out std_logic_vector(31 downto 0)
);
end component;
 
-- begin architecture description
begin
 
-- we assign the input signal to the respective
-- bytes as is described in the prototype
-- splitting the input
byte31 <= in_key_tk256(7 downto 0);
byte30 <= in_key_tk256(15 downto 8);
byte29 <= in_key_tk256(23 downto 16);
byte28 <= in_key_tk256(31 downto 24);
byte27 <= in_key_tk256(39 downto 32);
byte26 <= in_key_tk256(47 downto 40);
byte25 <= in_key_tk256(55 downto 48);
byte24 <= in_key_tk256(63 downto 56);
byte23 <= in_key_tk256(71 downto 64);
byte22 <= in_key_tk256(79 downto 72);
byte21 <= in_key_tk256(87 downto 80);
byte20 <= in_key_tk256(95 downto 88);
byte19 <= in_key_tk256(103 downto 96);
byte18 <= in_key_tk256(111 downto 104);
byte17 <= in_key_tk256(119 downto 112);
byte16 <= in_key_tk256(127 downto 120);
byte15 <= in_key_tk256(135 downto 128);
byte14 <= in_key_tk256(143 downto 136);
byte13 <= in_key_tk256(151 downto 144);
byte12 <= in_key_tk256(159 downto 152);
byte11 <= in_key_tk256(167 downto 160);
byte10 <= in_key_tk256(175 downto 168);
byte9 <= in_key_tk256(183 downto 176);
byte8 <= in_key_tk256(191 downto 184);
byte7 <= in_key_tk256(199 downto 192);
byte6 <= in_key_tk256(207 downto 200);
byte5 <= in_key_tk256(215 downto 208);
byte4 <= in_key_tk256(223 downto 216);
byte3 <= in_key_tk256(231 downto 224);
byte2 <= in_key_tk256(239 downto 232);
byte1 <= in_key_tk256(247 downto 240);
byte0 <= in_key_tk256(255 downto 248);
 
-- we form the M{0..7}
M0 <= byte3 & byte2 & byte1 & byte0;
M1 <= byte7 & byte6 & byte5 & byte4;
M2 <= byte11 & byte10 & byte9 & byte8;
M3 <= byte15 & byte14 & byte13 & byte12;
M4 <= byte19 & byte18 & byte17 & byte16;
M5 <= byte23 & byte22 & byte21 & byte20;
M6 <= byte27 & byte26 & byte25 & byte24;
M7 <= byte31 & byte30 & byte29 & byte28;
 
-- upper h
upper_h: h_256
port map (
in_h256 => even_in_tk256,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht
);
-- lower h
lower_h: h_256
port map (
in_h256 => odd_in_tk256,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8
);
-- left rotate by 8
from_shift_8(31 downto 8) <= to_shift_8(23 downto 0);
from_shift_8(7 downto 0) <= to_shift_8(31 downto 24);
-- pht transformation
pht_transform: pht
port map (
up_in_pht => to_up_pht,
down_in_pht => from_shift_8,
up_out_pht => out_key_up_tk256,
down_out_pht => to_shift_9
);
-- left rotate by 9
out_key_down_tk256(31 downto 9) <= to_shift_9(22 downto 0);
out_key_down_tk256(8 downto 0) <= to_shift_9(31 downto 23);
 
end twofish_keysched256_arch;
 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
--
-- twofish S key component for 256 bits key
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity twofish_S256 is
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end twofish_S256;
architecture twofish_S256_arch of twofish_S256 is
-- we declare the components to be used
component reed_solomon256
port (
in_rs256 : in std_logic_vector(255 downto 0);
out_Sfirst_rs256,
out_Ssecond_rs256,
out_Sthird_rs256,
out_Sfourth_rs256 : out std_logic_vector(31 downto 0)
);
end component;
signal twofish_key : std_logic_vector(255 downto 0);
signal byte15, byte14, byte13, byte12, byte11, byte10,
byte9, byte8, byte7, byte6, byte5, byte4,
byte3, byte2, byte1, byte0,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23,
byte24, byte25, byte26, byte27,
byte28, byte29, byte30, byte31 : std_logic_vector(7 downto 0);
 
-- begin architecture description
begin
 
-- splitting the input
byte31 <= in_key_ts256(7 downto 0);
byte30 <= in_key_ts256(15 downto 8);
byte29 <= in_key_ts256(23 downto 16);
byte28 <= in_key_ts256(31 downto 24);
byte27 <= in_key_ts256(39 downto 32);
byte26 <= in_key_ts256(47 downto 40);
byte25 <= in_key_ts256(55 downto 48);
byte24 <= in_key_ts256(63 downto 56);
byte23 <= in_key_ts256(71 downto 64);
byte22 <= in_key_ts256(79 downto 72);
byte21 <= in_key_ts256(87 downto 80);
byte20 <= in_key_ts256(95 downto 88);
byte19 <= in_key_ts256(103 downto 96);
byte18 <= in_key_ts256(111 downto 104);
byte17 <= in_key_ts256(119 downto 112);
byte16 <= in_key_ts256(127 downto 120);
byte15 <= in_key_ts256(135 downto 128);
byte14 <= in_key_ts256(143 downto 136);
byte13 <= in_key_ts256(151 downto 144);
byte12 <= in_key_ts256(159 downto 152);
byte11 <= in_key_ts256(167 downto 160);
byte10 <= in_key_ts256(175 downto 168);
byte9 <= in_key_ts256(183 downto 176);
byte8 <= in_key_ts256(191 downto 184);
byte7 <= in_key_ts256(199 downto 192);
byte6 <= in_key_ts256(207 downto 200);
byte5 <= in_key_ts256(215 downto 208);
byte4 <= in_key_ts256(223 downto 216);
byte3 <= in_key_ts256(231 downto 224);
byte2 <= in_key_ts256(239 downto 232);
byte1 <= in_key_ts256(247 downto 240);
byte0 <= in_key_ts256(255 downto 248);
 
-- forming the key
twofish_key <= byte31 & byte30 & byte29 & byte28 & byte27 & byte26 & byte25 & byte24 &
byte23 & byte22 & byte21 & byte20 & byte19 & byte18 & byte17 & byte16 &
byte15 & byte14 & byte13 & byte12 & byte11 & byte10 & byte9 & byte8 & byte7 &
byte6 & byte5 & byte4 & byte3 & byte2 & byte1 & byte0;
 
 
-- the keys S0,1,2,3
produce_S0_S1_S2_S3: reed_solomon256
port map (
in_rs256 => twofish_key,
out_Sfirst_rs256 => out_Sfirst_ts256,
out_Ssecond_rs256 => out_Ssecond_ts256,
out_Sthird_rs256 => out_Sthird_ts256,
out_Sfourth_rs256 => out_Sfourth_ts256
);
 
 
end twofish_S256_arch;
 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
--
-- twofish whitening key scheduler for 256 bits key input
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity twofish_whit_keysched256 is
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end twofish_whit_keysched256;
architecture twofish_whit_keysched256_arch of twofish_whit_keysched256 is
 
-- we declare internal signals
signal to_up_pht_1,
to_shift_8_1,
from_shift_8_1,
to_shift_9_1,
to_up_pht_2,
to_shift_8_2,
from_shift_8_2,
to_shift_9_2,
to_up_pht_3,
to_shift_8_3,
from_shift_8_3,
to_shift_9_3,
to_up_pht_4,
to_shift_8_4,
from_shift_8_4,
to_shift_9_4,
M0, M1, M2, M3, M4, M5, M6, M7 : std_logic_vector(31 downto 0);
 
signal byte15, byte14, byte13, byte12, byte11, byte10,
byte9, byte8, byte7, byte6, byte5, byte4,
byte3, byte2, byte1, byte0,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23,
byte24, byte25, byte26, byte27,
byte28, byte29, byte30, byte31 : std_logic_vector(7 downto 0);
 
signal zero, one, two, three, four, five, six, seven : std_logic_vector(7 downto 0);
-- we declare the components to be used
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
 
component h_256
port (
in_h256 : in std_logic_vector(7 downto 0);
Mfirst_h256,
Msecond_h256,
Mthird_h256,
Mfourth_h256 : in std_logic_vector(31 downto 0);
out_h256 : out std_logic_vector(31 downto 0)
);
end component;
 
-- begin architecture description
begin
 
-- we produce the first eight numbers
zero <= "00000000";
one <= "00000001";
two <= "00000010";
three <= "00000011";
four <= "00000100";
five <= "00000101";
six <= "00000110";
seven <= "00000111";
 
-- we assign the input signal to the respective
-- bytes as is described in the prototype
byte31 <= in_key_twk256(7 downto 0);
byte30 <= in_key_twk256(15 downto 8);
byte29 <= in_key_twk256(23 downto 16);
byte28 <= in_key_twk256(31 downto 24);
byte27 <= in_key_twk256(39 downto 32);
byte26 <= in_key_twk256(47 downto 40);
byte25 <= in_key_twk256(55 downto 48);
byte24 <= in_key_twk256(63 downto 56);
byte23 <= in_key_twk256(71 downto 64);
byte22 <= in_key_twk256(79 downto 72);
byte21 <= in_key_twk256(87 downto 80);
byte20 <= in_key_twk256(95 downto 88);
byte19 <= in_key_twk256(103 downto 96);
byte18 <= in_key_twk256(111 downto 104);
byte17 <= in_key_twk256(119 downto 112);
byte16 <= in_key_twk256(127 downto 120);
byte15 <= in_key_twk256(135 downto 128);
byte14 <= in_key_twk256(143 downto 136);
byte13 <= in_key_twk256(151 downto 144);
byte12 <= in_key_twk256(159 downto 152);
byte11 <= in_key_twk256(167 downto 160);
byte10 <= in_key_twk256(175 downto 168);
byte9 <= in_key_twk256(183 downto 176);
byte8 <= in_key_twk256(191 downto 184);
byte7 <= in_key_twk256(199 downto 192);
byte6 <= in_key_twk256(207 downto 200);
byte5 <= in_key_twk256(215 downto 208);
byte4 <= in_key_twk256(223 downto 216);
byte3 <= in_key_twk256(231 downto 224);
byte2 <= in_key_twk256(239 downto 232);
byte1 <= in_key_twk256(247 downto 240);
byte0 <= in_key_twk256(255 downto 248);
 
-- we form the M{0..7}
M0 <= byte3 & byte2 & byte1 & byte0;
M1 <= byte7 & byte6 & byte5 & byte4;
M2 <= byte11 & byte10 & byte9 & byte8;
M3 <= byte15 & byte14 & byte13 & byte12;
M4 <= byte19 & byte18 & byte17 & byte16;
M5 <= byte23 & byte22 & byte21 & byte20;
M6 <= byte27 & byte26 & byte25 & byte24;
M7 <= byte31 & byte30 & byte29 & byte28;
 
-- we produce the keys for the whitening steps
-- keys K0,1
-- upper h
upper_h1: h_256
port map (
in_h256 => zero,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht_1
);
-- lower h
lower_h1: h_256
port map (
in_h256 => one,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8_1
);
-- left rotate by 8
from_shift_8_1(31 downto 8) <= to_shift_8_1(23 downto 0);
from_shift_8_1(7 downto 0) <= to_shift_8_1(31 downto 24);
-- pht transformation
pht_transform1: pht
port map (
up_in_pht => to_up_pht_1,
down_in_pht => from_shift_8_1,
up_out_pht => out_K0_twk256,
down_out_pht => to_shift_9_1
);
-- left rotate by 9
out_K1_twk256(31 downto 9) <= to_shift_9_1(22 downto 0);
out_K1_twk256(8 downto 0) <= to_shift_9_1(31 downto 23);
 
-- keys K2,3
-- upper h
upper_h2: h_256
port map (
in_h256 => two,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht_2
);
-- lower h
lower_h2: h_256
port map (
in_h256 => three,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8_2
);
-- left rotate by 8
from_shift_8_2(31 downto 8) <= to_shift_8_2(23 downto 0);
from_shift_8_2(7 downto 0) <= to_shift_8_2(31 downto 24);
-- pht transformation
pht_transform2: pht
port map (
up_in_pht => to_up_pht_2,
down_in_pht => from_shift_8_2,
up_out_pht => out_K2_twk256,
down_out_pht => to_shift_9_2
);
-- left rotate by 9
out_K3_twk256(31 downto 9) <= to_shift_9_2(22 downto 0);
out_K3_twk256(8 downto 0) <= to_shift_9_2(31 downto 23);
 
-- keys K4,5
-- upper h
upper_h3: h_256
port map (
in_h256 => four,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht_3
);
-- lower h
lower_h3: h_256
port map (
in_h256 => five,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8_3
);
-- left rotate by 8
from_shift_8_3(31 downto 8) <= to_shift_8_3(23 downto 0);
from_shift_8_3(7 downto 0) <= to_shift_8_3(31 downto 24);
-- pht transformation
pht_transform3: pht
port map (
up_in_pht => to_up_pht_3,
down_in_pht => from_shift_8_3,
up_out_pht => out_K4_twk256,
down_out_pht => to_shift_9_3
);
-- left rotate by 9
out_K5_twk256(31 downto 9) <= to_shift_9_3(22 downto 0);
out_K5_twk256(8 downto 0) <= to_shift_9_3(31 downto 23);
 
-- keys K6,7
-- upper h
upper_h4: h_256
port map (
in_h256 => six,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht_4
);
-- lower h
lower_h4: h_256
port map (
in_h256 => seven,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8_4
);
-- left rotate by 8
from_shift_8_4(31 downto 8) <= to_shift_8_4(23 downto 0);
from_shift_8_4(7 downto 0) <= to_shift_8_4(31 downto 24);
-- pht transformation
pht_transform4: pht
port map (
up_in_pht => to_up_pht_4,
down_in_pht => from_shift_8_4,
up_out_pht => out_K6_twk256,
down_out_pht => to_shift_9_4
);
-- left rotate by 9
out_K7_twk256(31 downto 9) <= to_shift_9_4(22 downto 0);
out_K7_twk256(8 downto 0) <= to_shift_9_4(31 downto 23);
 
end twofish_whit_keysched256_arch;
 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
--
-- twofish encryption round with 256 bit key input
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity twofish_encryption_round256 is
port (
in1_ter256,
in2_ter256,
in3_ter256,
in4_ter256,
in_Sfirst_ter256,
in_Ssecond_ter256,
in_Sthird_ter256,
in_Sfourth_ter256,
in_key_up_ter256,
in_key_down_ter256 : in std_logic_vector(31 downto 0);
out1_ter256,
out2_ter256,
out3_ter256,
out4_ter256 : out std_logic_vector(31 downto 0)
);
end twofish_encryption_round256;
 
architecture twofish_encryption_round256_arch of twofish_encryption_round256 is
-- we declare internal signals
signal to_left_shift,
from_right_shift,
to_xor_with3,
to_xor_with4 : std_logic_vector(31 downto 0);
component f_256
port (
up_in_f256,
low_in_f256,
S0_in_f256,
S1_in_f256,
S2_in_f256,
S3_in_f256,
up_key_f256,
low_key_f256 : in std_logic_vector(31 downto 0);
up_out_f256,
low_out_f256 : out std_logic_vector(31 downto 0)
);
end component;
 
-- begin architecture description
begin
 
-- we declare f_256
function_f: f_256
port map (
up_in_f256 => in1_ter256,
low_in_f256 => in2_ter256,
S0_in_f256 => in_Sfirst_ter256,
S1_in_f256 => in_Ssecond_ter256,
S2_in_f256 => in_Sthird_ter256,
S3_in_f256 => in_Sfourth_ter256,
up_key_f256 => in_key_up_ter256,
low_key_f256 => in_key_down_ter256,
up_out_f256 => to_xor_with3,
low_out_f256 => to_xor_with4
);
-- we perform the exchange
-- in1_ter256 -> out3_ter256
-- in2_ter256 -> out4_ter256
-- in3_ter256 -> out1_ter256
-- in4_ter256 -> out2_ter256
-- we perform the left xor between the upper f function and
-- the third input (input 3)
to_left_shift <= to_xor_with3 XOR in3_ter256;
-- we perform the left side rotation to the right by 1 and
-- we perform the exchange too
out1_ter256(30 downto 0) <= to_left_shift(31 downto 1);
out1_ter256(31) <= to_left_shift(0);
-- we perform the right side rotation to the left by 1
from_right_shift(0) <= in4_ter256(31);
from_right_shift(31 downto 1) <= in4_ter256(30 downto 0);
-- we perform the right xor between the lower f function and
-- the fourth input (input 4)
out2_ter256 <= from_right_shift XOR to_xor_with4;
-- we perform the last exchanges
out3_ter256 <= in1_ter256;
out4_ter256 <= in2_ter256;
 
end twofish_encryption_round256_arch;
 
 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
 
--
-- twofish decryption round with 256 bit key input
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity twofish_decryption_round256 is
port (
in1_tdr256,
in2_tdr256,
in3_tdr256,
in4_tdr256,
in_Sfirst_tdr256,
in_Ssecond_tdr256,
in_Sthird_tdr256,
in_Sfourth_tdr256,
in_key_up_tdr256,
in_key_down_tdr256 : in std_logic_vector(31 downto 0);
out1_tdr256,
out2_tdr256,
out3_tdr256,
out4_tdr256 : out std_logic_vector(31 downto 0)
);
end twofish_decryption_round256;
 
architecture twofish_decryption_round256_arch of twofish_decryption_round256 is
 
signal to_xor_with3,
to_xor_with4,
to_xor_with_up_f,
from_xor_with_down_f : std_logic_vector(31 downto 0);
 
component f_256
port (
up_in_f256,
low_in_f256,
S0_in_f256,
S1_in_f256,
S2_in_f256,
S3_in_f256,
up_key_f256,
low_key_f256 : in std_logic_vector(31 downto 0);
up_out_f256,
low_out_f256 : out std_logic_vector(31 downto 0)
);
end component;
 
begin
 
-- we instantiate f function
function_f: f_256
port map (
up_in_f256 => in1_tdr256,
low_in_f256 => in2_tdr256,
S0_in_f256 => in_Sfirst_tdr256,
S1_in_f256 => in_Ssecond_tdr256,
S2_in_f256 => in_Sthird_tdr256,
S3_in_f256 => in_Sfourth_tdr256,
up_key_f256 => in_key_up_tdr256,
low_key_f256 => in_key_down_tdr256,
up_out_f256 => to_xor_with3,
low_out_f256 => to_xor_with4
);
-- output 1: input3 with upper f
-- we first rotate the input3 by 1 bit leftwise
to_xor_with_up_f(0) <= in3_tdr256(31);
to_xor_with_up_f(31 downto 1) <= in3_tdr256(30 downto 0);
-- we perform the XOR with the upper output of f and the result
-- is ouput 1
out1_tdr256 <= to_xor_with_up_f XOR to_xor_with3;
-- output 2: input4 with lower f
-- we perform the XOR with the lower output of f
from_xor_with_down_f <= in4_tdr256 XOR to_xor_with4;
-- we perform the rotation by 1 bit rightwise and the result
-- is output2
out2_tdr256(31) <= from_xor_with_down_f(0);
out2_tdr256(30 downto 0) <= from_xor_with_down_f(31 downto 1);
-- we assign outputs 3 and 4
out3_tdr256 <= in1_tdr256;
out4_tdr256 <= in2_tdr256;
 
end twofish_decryption_round256_arch;

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