URL
https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk
Subversion Repositories udp_ip_stack
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- This comparison shows the changes necessary to convert path
/
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/udp_ip_stack/trunk/bench/vhdl/IP_complete_nomac_tb.vhd
40,7 → 40,11
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT IP_complete_nomac |
PORT( |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- IP Layer signals |
ip_tx_start : in std_logic; |
ip_tx : in ipv4_tx_type; -- IP tx cxns |
54,6 → 58,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in ip_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
68,7 → 73,7
mac_rx_tvalid : in std_logic; -- indicates tdata is valid |
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data |
mac_rx_tlast : in std_logic -- indicates last byte of the trame |
); |
); |
END COMPONENT; |
|
|
84,6 → 89,8
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0'); |
signal mac_rx_tvalid : std_logic := '0'; |
signal mac_rx_tlast : std_logic := '0'; |
signal control : ip_control_type; |
|
--Outputs |
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission) |
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data |
114,6 → 121,7
reset => reset, |
our_ip_address => our_ip_address, |
our_mac_address => our_mac_address, |
control => control, |
arp_pkt_count => arp_pkt_count, |
mac_tx_tdata => mac_tx_tdata, |
mac_tx_tvalid => mac_tx_tvalid, |
144,6 → 152,7
|
our_ip_address <= x"c0a80509"; -- 192.168.5.9 |
our_mac_address <= x"002320212223"; |
control.arp_controls.clear_cache <= '0'; |
ip_tx_start <= '0'; |
mac_tx_tready <= '0'; |
|
/udp_ip_stack/trunk/bench/vhdl/IPv4_TX_tb.vhd
166,11 → 166,12
ip_tx.hdr.dst_ip_addr <= x"c0123478"; |
ip_tx_start <= '1'; |
wait for clk_period; |
ip_tx_start <= '0'; wait for clk_period; |
ip_tx_start <= '0'; |
arp_req_rslt.got_mac <= '0'; |
arp_req_rslt.got_err <= '0'; |
|
assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start"; |
wait for clk_period; |
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING"; |
|
wait for clk_period*10; -- simulate arp lookup time |
/udp_ip_stack/trunk/bench/vhdl/UDP_complete_nomac_tb.vhd
17,6 → 17,7
-- Revision: |
-- Revision 0.01 - File Created |
-- Revision 0.02 - Added test for IP broadcast tx |
-- Revision 0.03 - Added tests for ARP timeout |
-- Additional Comments: |
-- |
-- Notes: |
41,7 → 42,11
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT UDP_Complete_nomac |
PORT( |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- UDP TX signals |
udp_tx_start : in std_logic; -- indicates req to tx UDP |
udp_txi : in udp_tx_type; -- UDP tx cxns |
58,6 → 63,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in udp_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
77,7 → 83,7
|
|
|
type state_type is (IDLE, DATA_OUT); |
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT); |
type count_mode_type is (RST, INCR, HOLD); |
type set_clr_type is (SET, CLR, HOLD); |
|
93,6 → 99,7
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0'); |
signal mac_rx_tvalid : std_logic := '0'; |
signal mac_rx_tlast : std_logic := '0'; |
signal control : udp_control_type; |
|
--Outputs |
signal udp_rx_start_int : std_logic; |
130,6 → 137,7
signal set_last : std_logic; |
signal set_tx_started : set_clr_type; |
signal set_tx_fin : set_clr_type; |
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0); |
|
|
|
139,7 → 147,12
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: UDP_Complete_nomac PORT MAP ( |
uut: UDP_Complete_nomac |
generic map ( |
CLOCK_FREQ => 10, -- artificially low count to enable pragmatic testing |
ARP_TIMEOUT => 20 |
) |
PORT MAP ( |
udp_tx_start => udp_tx_start_int, |
udp_txi => udp_tx_int, |
udp_tx_result => udp_tx_result, |
152,6 → 165,7
reset => reset, |
our_ip_address => our_ip_address, |
our_mac_address => our_mac_address, |
control => control, |
arp_pkt_count => arp_pkt_count, |
ip_pkt_count => ip_pkt_count, |
mac_tx_tdata => mac_tx_tdata, |
183,6 → 197,7
|
our_ip_address <= x"c0a80509"; -- 192.168.5.9 |
our_mac_address <= x"002320212223"; |
control.ip_controls.arp_controls.clear_cache <= '0'; |
mac_tx_tready <= '0'; |
|
reset <= '1'; |
303,7 → 318,7
assert mac_tx_tvalid = '0' report "T1: tx held on for too long"; |
|
------------ |
-- TEST 2 -- send UDP pkt (same as sample from Java program |
-- TEST 2 -- send UDP pkt (same as sample from Java program) |
------------ |
|
report "T2: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694"; |
409,7 → 424,7
wait for clk_period*20; |
|
------------ |
-- TEST 3 -- send UDP pkt again (same as sample from Java program |
-- TEST 3 -- send UDP pkt again (same as sample from Java program) |
------------ |
|
report "T3: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694"; |
512,12 → 527,10
assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx_hdr.last_error_code indicates error at end of test"; |
assert ip_pkt_count = x"02" report "T3: ip pkt cnt incorrect"; |
|
wait for clk_period*50; |
|
|
|
|
------------ |
-- TEST 4 -- send UDP pkt with src=bc addr to force a broadcast tx in reply |
-- TEST 4 -- send UDP pkt with specific UDP data to force a broadcast tx in reply |
------------ |
|
report "T4: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694"; |
560,10 → 573,10
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- SRC IP |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"c0"; wait for clk_period; |
mac_rx_tdata <= x"a8"; wait for clk_period; |
mac_rx_tdata <= x"05"; wait for clk_period; |
mac_rx_tdata <= x"01"; wait for clk_period; |
-- DST IP |
mac_rx_tdata <= x"c0"; wait for clk_period; |
mac_rx_tdata <= x"a8"; wait for clk_period; |
582,12 → 595,12
mac_rx_tdata <= x"8b"; wait for clk_period; |
mac_rx_tdata <= x"79"; wait for clk_period; |
-- user data |
mac_rx_tdata <= x"68"; wait for clk_period; |
mac_rx_tdata <= x"42"; wait for clk_period; -- First byte 'B' triggers a reply to broadcast addr |
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set |
assert udp_rx_int.hdr.is_valid = '1' report "T4: udp_rx_int.hdr.is_valid not set"; |
assert udp_rx_int.hdr.data_length = x"0005" report "T4: udp_rx_int.hdr.data_length not set correctly"; |
assert udp_rx_int.hdr.src_ip_addr = x"ffffffff" report "T4: udp_rx_int.hdr.src_ip_addr not set correctly"; |
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T4: udp_rx_int.hdr.src_ip_addr not set correctly"; |
assert udp_rx_int.hdr.src_port = x"f49a" report "T4: udp_rx_int.hdr.src_port not set correctly"; |
assert udp_rx_int.hdr.dst_port = x"2694" report "T4: udp_rx_int.hdr.dst_port not set correctly"; |
|
596,7 → 609,7
|
assert ip_rx_hdr.is_valid = '1' report "T4: ip_rx_hdr.is_valid not set"; |
assert ip_rx_hdr.protocol = x"11" report "T4: ip_rx_hdr.protocol not set correctly"; |
assert ip_rx_hdr.src_ip_addr = x"ffffffff" report "T4: ip_rx.hdr.src_ip_addr not set correctly"; |
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T4: ip_rx.hdr.src_ip_addr not set correctly"; |
assert ip_rx_hdr.num_frame_errors = x"00" report "T4: ip_rx.hdr.num_frame_errors not set correctly"; |
assert ip_rx_hdr.last_error_code = x"0" report "T4: ip_rx.hdr.last_error_code not set correctly"; |
|
861,6 → 874,491
assert ip_rx_hdr.last_error_code = x"0" report "T5: ip_rx_hdr.last_error_code indicates error at end of test"; |
assert ip_pkt_count = x"04" report "T5: ip pkt cnt incorrect"; |
|
|
------------ |
-- TEST 6 -- send UDP pkt with data to trigger the sending of a pkt to unknown IP addr to force an ARP timeout |
------------ |
|
report "T6: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694 with data x43 to trig tx to unknown IP"; |
|
mac_rx_tvalid <= '1'; |
-- dst MAC (bc) |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
mac_rx_tdata <= x"20"; wait for clk_period; |
mac_rx_tdata <= x"21"; wait for clk_period; |
mac_rx_tdata <= x"22"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
-- src MAC |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
mac_rx_tdata <= x"18"; wait for clk_period; |
mac_rx_tdata <= x"29"; wait for clk_period; |
mac_rx_tdata <= x"26"; wait for clk_period; |
mac_rx_tdata <= x"7c"; wait for clk_period; |
-- type |
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- ver & HL / service type |
mac_rx_tdata <= x"45"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- total len |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"21"; wait for clk_period; |
-- ID |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"7a"; wait for clk_period; |
-- flags & frag |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- TTL |
mac_rx_tdata <= x"80"; wait for clk_period; |
-- Protocol |
mac_rx_tdata <= x"11"; wait for clk_period; |
-- Header CKS |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- SRC IP |
mac_rx_tdata <= x"c0"; wait for clk_period; |
mac_rx_tdata <= x"a8"; wait for clk_period; |
mac_rx_tdata <= x"05"; wait for clk_period; |
mac_rx_tdata <= x"01"; wait for clk_period; |
-- DST IP |
mac_rx_tdata <= x"c0"; wait for clk_period; |
mac_rx_tdata <= x"a8"; wait for clk_period; |
mac_rx_tdata <= x"05"; wait for clk_period; |
mac_rx_tdata <= x"09"; wait for clk_period; |
-- SRC port |
mac_rx_tdata <= x"f4"; wait for clk_period; |
mac_rx_tdata <= x"9a"; wait for clk_period; |
-- DST port |
mac_rx_tdata <= x"26"; wait for clk_period; |
mac_rx_tdata <= x"94"; wait for clk_period; |
-- length |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"0d"; wait for clk_period; |
-- cks |
mac_rx_tdata <= x"8b"; wait for clk_period; |
mac_rx_tdata <= x"79"; wait for clk_period; |
-- user data |
mac_rx_tdata <= x"43"; wait for clk_period; -- First byte 'C' triggers a reply to unknown addr |
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set |
assert udp_rx_int.hdr.is_valid = '1' report "T6: udp_rx_int.hdr.is_valid not set"; |
assert udp_rx_int.hdr.data_length = x"0005" report "T6: udp_rx_int.hdr.data_length not set correctly"; |
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T6: udp_rx_int.hdr.src_ip_addr not set correctly"; |
assert udp_rx_int.hdr.src_port = x"f49a" report "T6: udp_rx_int.hdr.src_port not set correctly"; |
assert udp_rx_int.hdr.dst_port = x"2694" report "T6: udp_rx_int.hdr.dst_port not set correctly"; |
|
assert udp_rx_start_int = '1' report "T6: udp_rx_start not set"; |
assert udp_rx_int.data.data_in_valid = '1' report "T6: udp_rx_int.data.data_in_valid not set"; |
|
assert ip_rx_hdr.is_valid = '1' report "T6: ip_rx_hdr.is_valid not set"; |
assert ip_rx_hdr.protocol = x"11" report "T6: ip_rx_hdr.protocol not set correctly"; |
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T6: ip_rx.hdr.src_ip_addr not set correctly"; |
assert ip_rx_hdr.num_frame_errors = x"00" report "T6: ip_rx.hdr.num_frame_errors not set correctly"; |
assert ip_rx_hdr.last_error_code = x"0" report "T6: ip_rx.hdr.last_error_code not set correctly"; |
|
-- put the rest of the user data |
mac_rx_tdata <= x"65"; wait for clk_period; |
mac_rx_tdata <= x"6c"; wait for clk_period; |
mac_rx_tdata <= x"6c"; wait for clk_period; |
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period; |
|
assert udp_rx_int.data.data_in_last = '1' report "T6: udp_rx_int.data.data_in_last not set"; |
|
mac_rx_tdata <= x"00"; |
mac_rx_tlast <= '0'; |
mac_rx_tvalid <= '0'; |
wait for clk_period; |
|
report "T6: waiting for mac data tx"; |
wait until mac_tx_tvalid = '1'; |
report "T6: starting mac data tx"; |
wait for clk_period; |
|
-- check the mac data being transmitted is valid ARP request |
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T6: incorrect src mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T6: incorrect src mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"20" report "T6: incorrect src mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"21" report "T6: incorrect src mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"22" report "T6: incorrect src mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T6: incorrect src mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"08" report "T6: incorrect pkt_type 0"; wait for clk_period; |
assert mac_tx_tdata = x"06" report "T6: incorrect pkt type 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T6: incorrect HW type.0"; wait for clk_period; |
assert mac_tx_tdata = x"01" report "T6: incorrect HW type.1"; wait for clk_period; |
assert mac_tx_tdata = x"08" report "T6: incorrect prot.0"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T6: incorrect prot.1"; wait for clk_period; |
assert mac_tx_tdata = x"06" report "T6: incorrect HW size"; wait for clk_period; |
assert mac_tx_tdata = x"04" report "T6: incorrect prot size"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T6: incorrect opcode.0"; wait for clk_period; |
assert mac_tx_tdata = x"01" report "T6: incorrect opcode.1"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T6: incorrect sndr mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T6: incorrect sndr mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"20" report "T6: incorrect sndr mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"21" report "T6: incorrect sndr mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"22" report "T6: incorrect sndr mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T6: incorrect sndr mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"c0" report "T6: incorrect sndr ip 0"; wait for clk_period; |
assert mac_tx_tdata = x"a8" report "T6: incorrect sndr ip 1"; wait for clk_period; |
assert mac_tx_tdata = x"05" report "T6: incorrect sndr ip 2"; wait for clk_period; |
assert mac_tx_tdata = x"09" report "T6: incorrect sndr ip 3"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"c0" report "T6: incorrect trg ip 0"; wait for clk_period; |
assert mac_tx_tdata = x"bb" report "T6: incorrect trg ip 1"; wait for clk_period; |
assert mac_tx_tdata = x"cc" report "T6: incorrect trg ip 2"; |
assert mac_tx_tlast = '0' report "T6: tlast asserted too soon"; |
wait for clk_period; |
|
assert mac_tx_tdata = x"dd" report "T6: incorrect trg ip 3"; |
assert mac_tx_tlast = '1' report "T6: tlast should be set"; |
wait for clk_period; |
|
assert udp_tx_result = IPTX_RESULT_SENDING report "T6: TX should still be in sending phase"; |
|
assert udp_rx_int.data.data_in_valid = '0' report "T6: udp_rx_int.data.data_in_valid not cleared"; |
assert udp_rx_int.data.data_in_last = '0' report "T6: udp_rx_int.data.data_in_last not cleared"; |
assert udp_rx_start_int = '0' report "T6: udp_rx_start not cleared"; |
assert ip_rx_hdr.num_frame_errors = x"00" report "T6: ip_rx_hdr.num_frame_errors non zero at end of test"; |
assert ip_rx_hdr.last_error_code = x"0" report "T6: ip_rx_hdr.last_error_code indicates error at end of test"; |
assert ip_pkt_count = x"05" report "T6: ip pkt cnt incorrect"; |
|
-- check for error on tx as a result of ARP timeout |
|
wait for clk_period*10*20; |
assert udp_tx_result = IPTX_RESULT_ERR report "T6: TX should resulkt in error (arp timeout)"; |
|
wait for clk_period*10; |
|
------------ |
-- TEST 7 -- send UDP pkt again to ensure that we can rx a pkt and tx after a timeout |
------------ |
|
report "T7: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694"; |
|
mac_rx_tvalid <= '1'; |
-- dst MAC (bc) |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
mac_rx_tdata <= x"20"; wait for clk_period; |
mac_rx_tdata <= x"21"; wait for clk_period; |
mac_rx_tdata <= x"22"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
-- src MAC |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
mac_rx_tdata <= x"18"; wait for clk_period; |
mac_rx_tdata <= x"29"; wait for clk_period; |
mac_rx_tdata <= x"26"; wait for clk_period; |
mac_rx_tdata <= x"7c"; wait for clk_period; |
-- type |
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- ver & HL / service type |
mac_rx_tdata <= x"45"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- total len |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"21"; wait for clk_period; |
-- ID |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"7a"; wait for clk_period; |
-- flags & frag |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- TTL |
mac_rx_tdata <= x"80"; wait for clk_period; |
-- Protocol |
mac_rx_tdata <= x"11"; wait for clk_period; |
-- Header CKS |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- SRC IP |
mac_rx_tdata <= x"c0"; wait for clk_period; |
mac_rx_tdata <= x"a8"; wait for clk_period; |
mac_rx_tdata <= x"05"; wait for clk_period; |
mac_rx_tdata <= x"01"; wait for clk_period; |
-- DST IP |
mac_rx_tdata <= x"c0"; wait for clk_period; |
mac_rx_tdata <= x"a8"; wait for clk_period; |
mac_rx_tdata <= x"05"; wait for clk_period; |
mac_rx_tdata <= x"09"; wait for clk_period; |
-- SRC port |
mac_rx_tdata <= x"f4"; wait for clk_period; |
mac_rx_tdata <= x"9a"; wait for clk_period; |
-- DST port |
mac_rx_tdata <= x"26"; wait for clk_period; |
mac_rx_tdata <= x"94"; wait for clk_period; |
-- length |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"0d"; wait for clk_period; |
-- cks |
mac_rx_tdata <= x"8b"; wait for clk_period; |
mac_rx_tdata <= x"79"; wait for clk_period; |
-- user data |
mac_rx_tdata <= x"68"; wait for clk_period; |
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set |
assert udp_rx_int.hdr.is_valid = '1' report "T7: udp_rx_int.hdr.is_valid not set"; |
assert udp_rx_int.hdr.data_length = x"0005" report "T7: udp_rx_int.hdr.data_length not set correctly"; |
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T7: udp_rx_int.hdr.src_ip_addr not set correctly"; |
assert udp_rx_int.hdr.src_port = x"f49a" report "T7: udp_rx_int.hdr.src_port not set correctly"; |
assert udp_rx_int.hdr.dst_port = x"2694" report "T7: udp_rx_int.hdr.dst_port not set correctly"; |
|
assert udp_rx_start_int = '1' report "T7: udp_rx_start not set"; |
assert udp_rx_int.data.data_in_valid = '1' report "T7: udp_rx_int.data.data_in_valid not set"; |
|
assert ip_rx_hdr.is_valid = '1' report "T7: ip_rx_hdr.is_valid not set"; |
assert ip_rx_hdr.protocol = x"11" report "T7: ip_rx_hdr.protocol not set correctly"; |
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T7: ip_rx.hdr.src_ip_addr not set correctly"; |
assert ip_rx_hdr.num_frame_errors = x"00" report "T7: ip_rx.hdr.num_frame_errors not set correctly"; |
assert ip_rx_hdr.last_error_code = x"0" report "T7: ip_rx.hdr.last_error_code not set correctly"; |
|
-- put the rest of the user data |
mac_rx_tdata <= x"65"; wait for clk_period; |
mac_rx_tdata <= x"6c"; wait for clk_period; |
mac_rx_tdata <= x"6c"; wait for clk_period; |
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period; |
|
assert udp_rx_int.data.data_in_last = '1' report "T7: udp_rx_int.data.data_in_last not set"; |
|
mac_rx_tdata <= x"00"; |
mac_rx_tlast <= '0'; |
mac_rx_tvalid <= '0'; |
wait for clk_period; |
|
report "T7: waiting for mac ARP REQ data tx"; |
if mac_tx_tvalid = '0' then |
wait until mac_tx_tvalid = '1'; |
wait for clk_period; |
end if; |
report "T7: starting mac ARP REQ data tx"; |
|
-- check the ARP REQ mac data being transmitted |
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T7: arp incorrect src mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T7: arp incorrect src mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"20" report "T7: arp incorrect src mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"21" report "T7: arp incorrect src mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"22" report "T7: arp incorrect src mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T7: arp incorrect src mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"08" report "T7: arp incorrect pkt_type 0"; wait for clk_period; |
assert mac_tx_tdata = x"06" report "T7: arp incorrect pkt type 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T7: arp incorrect HW type.0"; wait for clk_period; |
assert mac_tx_tdata = x"01" report "T7: arp incorrect HW type.1"; wait for clk_period; |
assert mac_tx_tdata = x"08" report "T7: arp incorrect prot.0"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: arp incorrect prot.1"; wait for clk_period; |
assert mac_tx_tdata = x"06" report "T7: arp incorrect HW size"; wait for clk_period; |
assert mac_tx_tdata = x"04" report "T7: arp incorrect prot size"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: arp incorrect opcode.0"; wait for clk_period; |
assert mac_tx_tdata = x"01" report "T7: arp incorrect opcode.1"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T7: arp incorrect sndr mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T7: arp incorrect sndr mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"20" report "T7: arp incorrect sndr mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"21" report "T7: arp incorrect sndr mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"22" report "T7: arp incorrect sndr mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T7: arp incorrect sndr mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"c0" report "T7: arp incorrect sndr ip 0"; wait for clk_period; |
assert mac_tx_tdata = x"a8" report "T7: arp incorrect sndr ip 1"; wait for clk_period; |
assert mac_tx_tdata = x"05" report "T7: arp incorrect sndr ip 2"; wait for clk_period; |
assert mac_tx_tdata = x"09" report "T7: arp incorrect sndr ip 3"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"c0" report "T7: arp incorrect trg ip 0"; wait for clk_period; |
assert mac_tx_tdata = x"a8" report "T7: arp incorrect trg ip 1"; wait for clk_period; |
assert mac_tx_tdata = x"05" report "T7: arp incorrect trg ip 2"; |
assert mac_tx_tlast = '0' report "T7: arp tlast asserted too soon"; |
wait for clk_period; |
|
assert mac_tx_tdata = x"01" report "T7: arp incorrect trg ip 3"; |
assert mac_tx_tlast = '1' report "T7: arp tlast should be set"; |
wait for clk_period; |
|
assert udp_tx_result = IPTX_RESULT_SENDING report "T7: arp TX should still be in sending phase"; |
|
wait for clk_period*5; |
|
report "T7: feeding in an arp reply: I have c0180501 at mac 021503230454"; |
|
mac_rx_tvalid <= '1'; |
-- dst MAC (bc) |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"ff"; wait for clk_period; |
mac_rx_tdata <= x"ff"; wait for clk_period; |
-- src MAC |
mac_rx_tdata <= x"02"; wait for clk_period; |
mac_rx_tdata <= x"15"; wait for clk_period; |
mac_rx_tdata <= x"03"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
mac_rx_tdata <= x"04"; wait for clk_period; |
mac_rx_tdata <= x"54"; wait for clk_period; |
-- type |
mac_rx_tdata <= x"08"; wait for clk_period; |
mac_rx_tdata <= x"06"; wait for clk_period; |
-- HW type |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"01"; wait for clk_period; |
-- Protocol type |
mac_rx_tdata <= x"08"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
-- HW size |
mac_rx_tdata <= x"06"; wait for clk_period; |
-- protocol size |
mac_rx_tdata <= x"04"; wait for clk_period; |
-- Opcode |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"02"; wait for clk_period; |
-- Sender MAC |
mac_rx_tdata <= x"02"; wait for clk_period; |
mac_rx_tdata <= x"15"; wait for clk_period; |
mac_rx_tdata <= x"03"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
mac_rx_tdata <= x"04"; wait for clk_period; |
mac_rx_tdata <= x"54"; wait for clk_period; |
-- Sender IP |
mac_rx_tdata <= x"c0"; wait for clk_period; |
mac_rx_tdata <= x"a8"; wait for clk_period; |
mac_rx_tdata <= x"05"; wait for clk_period; |
mac_rx_tdata <= x"01"; wait for clk_period; |
-- Target MAC |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
mac_rx_tdata <= x"20"; wait for clk_period; |
mac_rx_tdata <= x"21"; wait for clk_period; |
mac_rx_tdata <= x"22"; wait for clk_period; |
mac_rx_tdata <= x"23"; wait for clk_period; |
-- Target IP |
mac_rx_tdata <= x"c0"; wait for clk_period; |
mac_rx_tdata <= x"a8"; wait for clk_period; |
mac_rx_tdata <= x"05"; wait for clk_period; |
mac_rx_tdata <= x"09"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tlast <= '1'; |
mac_rx_tdata <= x"00"; wait for clk_period; |
mac_rx_tlast <= '0'; |
mac_rx_tvalid <= '0'; |
wait for clk_period; |
|
assert udp_tx_result = IPTX_RESULT_SENDING report "T7: TX should still be sending"; |
|
report "T7: waiting for mac data tx"; |
if mac_tx_tvalid = '0' then |
wait until mac_tx_tvalid = '1'; |
wait for clk_period; |
end if; |
report "T7: starting mac data tx"; |
|
-- check the mac data being transmitted |
assert mac_tx_tdata = x"02" report "T7: incorrect dst mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"15" report "T7: incorrect dst mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"03" report "T7: incorrect dst mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T7: incorrect dst mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"04" report "T7: incorrect dst mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"54" report "T7: incorrect dst mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T7: incorrect src mac 0"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T7: incorrect src mac 1"; wait for clk_period; |
assert mac_tx_tdata = x"20" report "T7: incorrect src mac 2"; wait for clk_period; |
assert mac_tx_tdata = x"21" report "T7: incorrect src mac 3"; wait for clk_period; |
assert mac_tx_tdata = x"22" report "T7: incorrect src mac 4"; wait for clk_period; |
assert mac_tx_tdata = x"23" report "T7: incorrect src mac 5"; wait for clk_period; |
|
assert mac_tx_tdata = x"08" report "T7: incorrect pkt_type 0"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: incorrect pkt type 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"45" report "T7: incorrect ver.hlen"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: incorrect srv type"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: incorrect len 0"; wait for clk_period; |
assert mac_tx_tdata = x"20" report "T7: incorrect len 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T7: incorrect ident 0"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: incorrect ident 1"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: incorrect flag&frag 0"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: incorrect flag&frag 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"80" report "T7: incorrect TTL"; wait for clk_period; |
assert mac_tx_tdata = x"11" report "T7: incorrect protocol"; wait for clk_period; |
assert mac_tx_tdata = x"af" report "T7: incorrect hdr.cks 0"; wait for clk_period; |
assert mac_tx_tdata = x"72" report "T7: incorrect hdr.cks 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"c0" report "T7: incorrect src ip 0"; wait for clk_period; |
assert mac_tx_tdata = x"a8" report "T7: incorrect src ip 1"; wait for clk_period; |
assert mac_tx_tdata = x"05" report "T7: incorrect src ip 2"; wait for clk_period; |
assert mac_tx_tdata = x"09" report "T7: incorrect src ip 3"; wait for clk_period; |
|
assert mac_tx_tdata = x"c0" report "T7: incorrect dst ip 0"; wait for clk_period; |
assert mac_tx_tdata = x"a8" report "T7: incorrect dst ip 1"; wait for clk_period; |
assert mac_tx_tdata = x"05" report "T7: incorrect dst ip 2"; wait for clk_period; |
assert mac_tx_tdata = x"01" report "T7: incorrect dst ip 3"; wait for clk_period; |
|
assert mac_tx_tdata = x"26" report "T7: incorrect src port 0"; wait for clk_period; |
assert mac_tx_tdata = x"94" report "T7: incorrect src port 1"; wait for clk_period; |
assert mac_tx_tdata = x"f4" report "T7: incorrect dst port 0"; wait for clk_period; |
assert mac_tx_tdata = x"9a" report "T7: incorrect dst port 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"00" report "T7: incorrect udp len 0"; wait for clk_period; |
assert mac_tx_tdata = x"0c" report "T7: incorrect udp len 1"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: incorrect udp cks 0"; wait for clk_period; |
assert mac_tx_tdata = x"00" report "T7: incorrect udp cks 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"40" report "T7: incorrect udp data 0"; wait for clk_period; |
assert mac_tx_tdata = x"41" report "T7: incorrect udp data 1"; wait for clk_period; |
|
assert mac_tx_tdata = x"42" report "T7: incorrect udp data 2"; |
assert mac_tx_tlast = '0' report "T7: tlast asserted too soon"; wait for clk_period; |
assert mac_tx_tdata = x"43" report "T7: incorrect udp data 3"; |
assert mac_tx_tlast = '1' report "T7: tlast not asserted"; wait for clk_period; |
|
assert udp_tx_result = IPTX_RESULT_SENT report "T7: TX did not complete"; |
|
assert udp_rx_int.data.data_in_valid = '0' report "T7: udp_rx_int.data.data_in_valid not cleared"; |
assert udp_rx_int.data.data_in_last = '0' report "T7: udp_rx_int.data.data_in_last not cleared"; |
assert udp_rx_start_int = '0' report "T7: udp_rx_start not cleared"; |
assert ip_rx_hdr.num_frame_errors = x"00" report "T7: ip_rx_hdr.num_frame_errors non zero at end of test"; |
assert ip_rx_hdr.last_error_code = x"0" report "T7: ip_rx_hdr.last_error_code indicates error at end of test"; |
assert ip_pkt_count = x"06" report "T7: ip pkt cnt incorrect"; |
|
|
report "--- end of tests ---"; |
wait; |
end process; |
870,12 → 1368,13
-- TX response process - COMB |
tx_proc_combinatorial: process( |
-- inputs |
udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX, |
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result, ip_rx_hdr, |
udp_tx_int.data.data_out_valid, PBTX, |
-- state |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, |
-- controls |
next_state, set_state, set_count, set_hdr, set_tx_start, set_last, |
set_tx_started, set_tx_fin |
set_tx_started, set_tx_fin, first_byte_rx |
) |
begin |
-- set output_followers |
892,6 → 1391,7
set_last <= '0'; |
set_tx_started <= HOLD; |
set_tx_fin <= HOLD; |
first_byte_rx <= (others => '0'); |
|
-- FSM |
case state is |
900,33 → 1400,63
udp_tx_int.data.data_out <= (others => '0'); |
udp_tx_int.data.data_out_valid <= '0'; |
if udp_rx_start_int = '1' or PBTX = '1' then |
if udp_rx_start_int = '1' then |
first_byte_rx <= udp_rx_int.data.data_in; |
else |
first_byte_rx <= x"00"; |
end if; |
set_tx_fin <= CLR; |
set_count <= RST; |
set_hdr <= '1'; |
if udp_rx_int.data.data_in_last = '1' then |
set_tx_started <= SET; |
set_tx_start <= SET; |
next_state <= DATA_OUT; |
set_state <= '1'; |
else |
next_state <= WAIT_RX_DONE; |
set_state <= '1'; |
end if; |
end if; |
|
when WAIT_RX_DONE => |
-- wait until RX pkt fully received |
if udp_rx_int.data.data_in_last = '1' then |
set_tx_started <= SET; |
set_hdr <= '1'; |
set_tx_start <= SET; |
set_tx_fin <= CLR; |
set_count <= RST; |
next_state <= DATA_OUT; |
set_state <= '1'; |
end if; |
|
|
when DATA_OUT => |
if ip_rx_hdr.is_broadcast = '1' then |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"50"; |
if udp_tx_result = UDPTX_RESULT_ERR then |
-- have an error from the IP TX layer, clear down the TX |
set_tx_start <= CLR; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
else |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40"; |
end if; |
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int; |
if udp_tx_data_out_ready_int = '1' then |
set_tx_start <= CLR; |
if unsigned(count) = x"03" then |
set_last <= '1'; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
if udp_tx_result = UDPTX_RESULT_SENDING then |
set_tx_start <= CLR; -- reset out start req as soon as we know we are sending |
end if; |
if ip_rx_hdr.is_broadcast = '1' then |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"50"; |
else |
set_count <= INCR; |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40"; |
end if; |
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int; |
if udp_tx_data_out_ready_int = '1' then |
if unsigned(count) = x"03" then |
set_last <= '1'; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
else |
set_count <= INCR; |
end if; |
end if; |
end if; |
|
end case; |
970,7 → 1500,14
|
-- set tx hdr |
if set_hdr = '1' then |
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; |
-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP |
if first_byte_rx = x"42" then |
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr |
elsif first_byte_rx = x"43" then |
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout |
else |
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender |
end if; |
tx_hdr.dst_port <= udp_rx_int.hdr.src_port; |
tx_hdr.src_port <= udp_rx_int.hdr.dst_port; |
tx_hdr.data_length <= x"0004"; |
/udp_ip_stack/trunk/bench/vhdl/arp_tb.vhd
16,6 → 16,7
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Revision 0.02 - Added tests for ARP timeout |
-- Additional Comments: |
-- |
-- Notes: |
38,7 → 39,11
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT arp |
PORT( |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- lookup request signals |
arp_req_req : in arp_req_req_type; |
arp_req_rslt : out arp_req_rslt_type; |
59,9 → 64,10
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
-- system signals |
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
control : in arp_control_type; |
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received |
); |
); |
END COMPONENT; |
|
|
83,6 → 89,7
signal arp_req_rslt : arp_req_rslt_type; |
signal mac_tx_req : std_logic; |
signal mac_tx_granted : std_logic; |
signal control : arp_control_type; |
|
|
-- Clock period definitions |
91,7 → 98,11
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: arp PORT MAP ( |
uut: arp generic map ( |
CLOCK_FREQ => 10, -- artificially low count to enable pragmatic testing |
ARP_TIMEOUT => 20 |
) |
PORT MAP ( |
-- lookup request mappings |
arp_req_req => arp_req_req, |
arp_req_rslt => arp_req_rslt, |
112,7 → 123,8
data_out => data_out, |
-- system mappings |
our_mac_address => our_mac_address, |
our_ip_address => our_ip_address, |
our_ip_address => our_ip_address, |
control => control, |
req_count => req_count |
); |
|
135,6 → 147,7
our_ip_address <= x"c0a80509"; -- 192.168.5.9 |
our_mac_address <= x"002320212223"; |
mac_tx_granted <= '1'; -- FIXME 0 |
control.clear_cache <= '0'; |
|
reset <= '1'; |
wait for clk_period*10; |
148,7 → 161,7
arp_req_req.ip <= (others => '0'); |
data_out_ready <= '1'; |
|
report "T1: Send an ARP request: who has 192.168.5.8? Tell 192.168.5.1"; |
report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1"; |
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
225,7 → 238,7
data_out_ready <= '1'; |
wait for clk_period*50; |
|
report "T2: Send another ARP request: who has 192.168.5.8? Tell 192.168.5.1, holding off transmitter"; |
report "T2: Send another ARP request: who has 192.168.5.9? Tell 192.168.5.1, holding off transmitter"; |
data_out_ready <= '0'; |
data_in_valid <= '1'; |
-- dst MAC (bc) |
295,25 → 308,32
data_out_ready <= '1'; |
|
wait for clk_period*50; |
|
-- Send a request for the IP that is already cached |
|
report "T3 Send a request for the IP that is already cached"; |
arp_req_req.ip <= x"c0a80501"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T3: should have got mac"; |
assert arp_req_rslt.mac = x"00231829267c" report "T3: incorrect mac"; |
assert arp_req_rslt.got_err = '0' report "T3: should not have got err"; |
arp_req_req.lookup_req <= '0'; |
|
wait for clk_period*50; |
|
-- Send a request for the IP that is not cached |
wait for clk_period; |
wait for clk_period*10; |
|
wait for clk_period*20; |
assert mac_tx_req = '0' report "T3: should not be requesting TX channel"; |
|
report "T4: Request 192.168.5.3 (not cached= and Send an ARP reply: 192.168.5.3 has mac 02:12:03:23:04:54"; |
arp_req_req.ip <= x"c0a80503"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
wait for clk_period*80; |
wait for clk_period*20; |
assert mac_tx_req = '1' report "T4: should be requesting TX channel"; |
wait for clk_period*50; |
-- Send the reply |
data_out_ready <= '1'; |
|
report "T3: Send an ARP reply: 192.168.5.3 has mac 02:12:03:23:04:54"; |
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
375,8 → 395,205
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
data_in_valid <= '0'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T4: should have got mac"; |
assert arp_req_rslt.mac = x"021203230454" report "T4: incorrect mac"; |
assert arp_req_rslt.got_err = '0' report "T4: should not have got err"; |
wait for clk_period*10; |
|
report "T5: Request 192.168.5.4 (not cached), dont send a reply and wait for timeout"; |
arp_req_req.ip <= x"c0a80504"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
wait for clk_period*20; |
assert mac_tx_req = '1' report "T5: should be requesting TX channel"; |
wait for clk_period*200; |
assert arp_req_rslt.got_mac = '0' report "T5: should not have got mac"; |
assert arp_req_rslt.got_err = '1' report "T5: should have got err"; |
|
report "T6: Request 192.168.5.7 (not cached= and Send an ARP reply: 192.168.5.7 has mac 02:15:03:23:04:54"; |
arp_req_req.ip <= x"c0a80507"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '0' report "T6: should not yet have mac"; |
assert arp_req_rslt.got_err = '0' report "T6: should not have got err"; |
|
arp_req_req.lookup_req <= '0'; |
wait for clk_period*20; |
assert mac_tx_req = '1' report "T6: should be requesting TX channel"; |
wait for clk_period*50; |
-- Send the reply |
data_out_ready <= '1'; |
|
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"15"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"04"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"02"; wait for clk_period; |
-- Sender MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"15"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"04"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"07"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"20"; wait for clk_period; |
data_in <= x"21"; wait for clk_period; |
data_in <= x"22"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T6: should have got mac"; |
assert arp_req_rslt.mac = x"021503230454" report "T6: incorrect mac"; |
assert arp_req_rslt.got_err = '0' report "T6: should not have got err"; |
wait for clk_period*10; |
|
report "T7: Request 192.168.5.7 again an expect it to be in the cache"; |
arp_req_req.ip <= x"c0a80507"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T7: should have mac"; |
assert arp_req_rslt.got_err = '0' report "T7: should not have got err"; |
|
arp_req_req.lookup_req <= '0'; |
wait for clk_period*20; |
|
report "T8: Clear the cache, Request 192.168.5.7 again an expect a 'who has' to be sent"; |
control.clear_cache <= '1'; |
wait for clk_period; |
control.clear_cache <= '0'; |
wait for clk_period; |
|
arp_req_req.ip <= x"c0a80507"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '0' report "T8: should not yet have mac"; |
assert arp_req_rslt.got_err = '0' report "T8: should not have got err"; |
|
arp_req_req.lookup_req <= '0'; |
wait for clk_period*20; |
|
|
assert mac_tx_req = '1' report "T8: should be requesting TX channel"; |
wait for clk_period*50; |
-- Send the reply |
data_out_ready <= '1'; |
|
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"15"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"04"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"02"; wait for clk_period; |
-- Sender MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"15"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"55"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"07"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"20"; wait for clk_period; |
data_in <= x"21"; wait for clk_period; |
data_in <= x"22"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T8: should have got mac"; |
assert arp_req_rslt.mac = x"021503235554" report "T8: incorrect mac"; |
assert arp_req_rslt.got_err = '0' report "T8: should not have got err"; |
wait for clk_period*10; |
|
report "--- end of tests ---"; |
wait; |
end process; |
/udp_ip_stack/trunk/rtl/vhdl/arp.vhd
23,7 → 23,8
-- Revision 0.01 - File Created |
-- Revision 0.02 - Added req for mac tx and wait for grant |
-- Revision 0.03 - Added data_out_first |
|
-- Revision 0.04 - Added arp response timeout |
-- Revision 0.05 - Added arp cache reset control |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
32,7 → 33,11
use IEEE.NUMERIC_STD.ALL; |
use work.arp_types.all; |
|
entity arp is |
entity arp is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- lookup request signals |
arp_req_req : in arp_req_req_type; |
54,7 → 59,8
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
-- system signals |
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
control : in arp_control_type; |
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received |
); |
end arp; |
61,7 → 67,7
|
architecture Behavioral of arp is |
|
type req_state_type is (IDLE,LOOKUP,REQUEST,WAIT_REPLY); |
type req_state_type is (IDLE,LOOKUP,REQUEST,WAIT_REPLY,PAUSE1,PAUSE2,PAUSE3); |
type rx_state_type is (IDLE,PARSE,PROCESS_ARP,WAIT_END); |
type rx_event_type is (NO_EVENT,DATA); |
type count_mode_type is (RST,INCR,HOLD); |
85,6 → 91,9
signal mac_addr_valid_reg: std_logic; |
signal send_request_needed : std_logic; |
signal tx_mac_chn_reqd : std_logic; |
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz |
signal timer : unsigned (7 downto 0); -- counts seconds timeout |
signal timeout_reg : std_logic; |
|
signal rx_state : rx_state_type; |
signal rx_count : unsigned (7 downto 0); |
93,7 → 102,7
signal arp_entry : arp_entry_type; -- arp entry store |
signal new_arp_entry : arp_entry_type; |
signal tx_state : tx_state_type; |
signal tx_count : unsigned (7 downto 0); |
signal tx_count : unsigned (7 downto 0); |
|
-- FIXME - remove these debug state signals |
signal arp_err_data : std_logic_vector (7 downto 0); |
110,6 → 119,9
signal set_mac_addr_invalid : std_logic; |
signal set_send_req : std_logic; |
signal clear_send_req : std_logic; |
signal set_timer : count_mode_type; -- timer reset, count, hold control |
signal timer_enable : std_logic; -- enable the timer counting |
signal set_timeout : set_clr_type; -- control the timeout register |
|
|
-- rx control signals |
183,12 → 195,19
-- input signals |
arp_req_req, |
-- state variables |
req_state, req_ip_addr, mac_addr_found, mac_addr_valid_reg, send_request_needed, arp_entry, |
req_state, req_ip_addr, mac_addr_found, mac_addr_valid_reg, send_request_needed, arp_entry, |
freq_scaler, timer, timeout_reg, |
-- control signals |
next_req_state, set_req_state, set_req_ip, set_mac_addr,set_mac_addr_invalid,set_send_req, clear_send_req) |
next_req_state, set_req_state, set_req_ip, set_mac_addr, control, |
set_mac_addr_invalid,set_send_req, clear_send_req, set_timer, timer_enable, set_timeout |
) |
begin |
-- set output followers |
arp_req_rslt.got_err <= '0'; -- errors not returned in this version |
-- set output followers |
if arp_req_req.lookup_req = '1' then |
arp_req_rslt.got_err <= '0'; |
else |
arp_req_rslt.got_err <= timeout_reg; |
end if; |
-- zero time response to lookup request if already in cache |
if arp_req_req.lookup_req = '1' and arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then |
arp_req_rslt.got_mac <= '1'; |
209,16 → 228,26
set_mac_addr_invalid <= '0'; |
set_send_req <= '0'; |
clear_send_req <= '0'; |
set_timer <= INCR; -- default is timer running, unless we hold or reset it |
set_timeout <= HOLD; |
timer_enable <= '0'; |
|
-- combinatorial logic |
if freq_scaler = x"00000000" then |
timer_enable <= '1'; |
end if; |
|
-- REQ FSM |
case req_state is |
when IDLE => |
set_timer <= RST; |
if arp_req_req.lookup_req = '1' then |
-- check if we already have the info in cache |
if arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then |
-- already have this IP |
set_mac_addr <= '1'; |
else |
else |
set_timeout <= CLR; |
next_req_state <= LOOKUP; |
set_req_state <= '1'; |
set_req_ip <= '1'; |
233,10 → 262,11
set_req_state <= '1'; |
set_mac_addr <= '1'; |
else |
-- need to request mac for this IP |
-- need to request mac for this IP |
set_send_req <= '1'; |
set_timer <= RST; |
next_req_state <= REQUEST; |
set_req_state <= '1'; |
set_send_req <= '1'; |
end if; |
|
when REQUEST => |
245,12 → 275,28
set_req_state <= '1'; |
|
when WAIT_REPLY => |
if arp_entry.is_valid = '1' then |
-- have reply, go back to LOOKUP state to see if it is the right one |
next_req_state <= LOOKUP; |
set_req_state <= '1'; |
end if; |
-- TODO: add timeout here |
if arp_entry.is_valid = '1' then |
-- have reply, go back to LOOKUP state to see if it is the right one |
next_req_state <= LOOKUP; |
set_req_state <= '1'; |
end if; |
if timer >= ARP_TIMEOUT then |
set_timeout <= SET; |
next_req_state <= PAUSE1; |
set_req_state <= '1'; |
end if; |
|
when PAUSE1 => |
next_req_state <= PAUSE2; |
set_req_state <= '1'; |
|
when PAUSE2 => |
next_req_state <= PAUSE3; |
set_req_state <= '1'; |
|
when PAUSE3 => |
next_req_state <= IDLE; |
set_req_state <= '1'; |
|
end case; |
end process; |
264,7 → 310,10
req_ip_addr <= (others => '0'); |
mac_addr_found <= (others => '0'); |
mac_addr_valid_reg <= '0'; |
send_request_needed <= '0'; |
send_request_needed <= '0'; |
freq_scaler <= to_unsigned(CLOCK_FREQ,32); |
timer <= (others => '0'); |
timeout_reg <= '0'; |
else |
-- Next req_state processing |
if set_req_state = '1' then |
299,7 → 348,35
else |
mac_addr_found <= mac_addr_found; |
mac_addr_valid_reg <= mac_addr_valid_reg; |
end if; |
end if; |
|
-- freq scaling and 1-sec timer |
if freq_scaler = x"00000000" then |
freq_scaler <= to_unsigned(CLOCK_FREQ,32); |
else |
freq_scaler <= freq_scaler - 1; |
end if; |
|
-- timer processing |
case set_timer is |
when RST => |
timer <= x"00"; |
when INCR => |
if timer_enable = '1' then |
timer <= timer + 1; |
else |
timer <= timer; |
end if; |
when HOLD => |
timer <= timer; |
end case; |
|
-- timeout latching |
case set_timeout is |
when CLR => timeout_reg <= '0'; |
when SET => timeout_reg <= '1'; |
when HOLD => timeout_reg <= timeout_reg; |
end case; |
|
end if; |
end if; |
513,8 → 590,13
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if; |
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if; |
|
-- set arp entry request |
if set_arp_entry_request = '1' then |
-- set arp entry request |
if control.clear_cache = '1' then |
arp_entry.ip <= x"00000000"; |
arp_entry.mac <= x"000000000000"; |
arp_entry.is_valid <= '0'; |
arp_entry.reply_required <= '0'; |
elsif set_arp_entry_request = '1' then |
-- copy info from new entry to arp_entry and set reply required |
arp_entry.mac <= new_arp_entry.mac; |
arp_entry.ip <= new_arp_entry.ip; |
/udp_ip_stack/trunk/rtl/vhdl/UDP_TX.vhd
43,7 → 43,7
end UDP_TX; |
|
architecture Behavioral of UDP_TX is |
type tx_state_type is (IDLE, SEND_UDP_HDR, SEND_USER_DATA); |
type tx_state_type is (IDLE, PAUSE, SEND_UDP_HDR, SEND_USER_DATA); |
|
type count_mode_type is (RST, INCR, HOLD); |
type settable_cnt_type is (RST, SET, INCR, HOLD); |
110,8 → 110,12
ip_tx.hdr.protocol <= x"11"; -- UDP protocol |
ip_tx.hdr.data_length <= total_length; |
ip_tx.hdr.dst_ip_addr <= udp_txi.hdr.dst_ip_addr; |
udp_tx_result <= tx_result_reg; |
|
if udp_tx_start = '1' and ip_tx_start_reg = '0' then |
udp_tx_result <= UDPTX_RESULT_NONE; -- kill the result until have started the IP layer |
else |
udp_tx_result <= tx_result_reg; |
end if; |
|
case udp_tx_state is |
when SEND_USER_DATA => |
ip_tx.data.data_out <= udp_txi.data.data_out; |
141,6 → 145,7
set_tx_result <= '0'; |
set_ip_tx_start <= HOLD; |
tx_count_val <= (others => '0'); |
udp_tx_data_out_ready <= '0'; |
|
-- set temp signals |
total_length <= std_logic_vector(unsigned(udp_txi.hdr.data_length) + 8); -- total length = user data length + header length (bytes) |
161,14 → 166,25
next_tx_result <= UDPTX_RESULT_SENDING; |
set_ip_tx_start <= SET; |
set_tx_result <= '1'; |
next_tx_state <= SEND_UDP_HDR; |
next_tx_state <= PAUSE; |
set_tx_state <= '1'; |
end if; |
end if; |
|
|
when PAUSE => |
-- delay one clock for IP layer to respond to ip_tx_start and remove any tx error result |
next_tx_state <= SEND_UDP_HDR; |
set_tx_state <= '1'; |
|
when SEND_UDP_HDR => |
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx |
if ip_tx_data_out_ready = '1' then |
if ip_tx_result = IPTX_RESULT_ERR then |
set_ip_tx_start <= CLR; |
next_tx_result <= UDPTX_RESULT_ERR; |
set_tx_result <= '1'; |
next_tx_state <= IDLE; |
set_tx_state <= '1'; |
elsif ip_tx_data_out_ready = '1' then |
if tx_count = x"0007" then |
tx_count_val <= x"0001"; |
tx_count_mode <= SET; |
/udp_ip_stack/trunk/rtl/vhdl/ml605/IP_complete.vhd
25,6 → 25,10
use work.arp_types.all; |
|
entity IP_complete is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- IP Layer signals |
ip_tx_start : in std_logic; |
40,6 → 44,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in ip_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
66,7 → 71,11
------------------------------------------------------------------------------ |
|
COMPONENT IP_complete_nomac |
PORT( |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- IP Layer signals |
ip_tx_start : in std_logic; |
ip_tx : in ipv4_tx_type; -- IP tx cxns |
80,6 → 89,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in ip_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
94,7 → 104,7
mac_rx_tvalid : in std_logic; -- indicates tdata is valid |
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data |
mac_rx_tlast : in std_logic -- indicates last byte of the trame |
); |
); |
END COMPONENT; |
|
|
171,8 → 181,12
-- Instantiate the IP layer |
------------------------------------------------------------------------------ |
|
IP_layer : IP_complete_nomac PORT MAP |
( |
IP_layer : IP_complete_nomac |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT |
) |
PORT MAP ( |
-- IP Layer signals |
ip_tx_start => ip_tx_start, |
ip_tx => ip_tx, |
186,6 → 200,7
reset => reset, |
our_ip_address => our_ip_address, |
our_mac_address => our_mac_address, |
control => control, |
-- status signals |
arp_pkt_count => arp_pkt_count, |
ip_pkt_count => ip_pkt_count, |
/udp_ip_stack/trunk/rtl/vhdl/ml605/UDP_Complete.vhd
26,6 → 26,10
use work.arp_types.all; |
|
entity UDP_Complete is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- UDP TX signals |
udp_tx_start : in std_logic; -- indicates req to tx UDP |
44,6 → 48,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in udp_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
70,7 → 75,11
------------------------------------------------------------------------------ |
|
COMPONENT UDP_Complete_nomac |
PORT( |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- UDP TX signals |
udp_tx_start : in std_logic; -- indicates req to tx UDP |
udp_txi : in udp_tx_type; -- UDP tx cxns |
87,6 → 96,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in udp_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
185,7 → 195,12
-- Instantiate the UDP layer |
------------------------------------------------------------------------------ |
|
udp_block: UDP_Complete_nomac PORT MAP ( |
udp_block: UDP_Complete_nomac |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT |
) |
PORT MAP ( |
-- UDP TX signals |
udp_tx_start => udp_tx_start, |
udp_txi => udp_txi, |
205,7 → 220,7
-- status signals |
arp_pkt_count => arp_pkt_count, |
ip_pkt_count => ip_pkt_count, |
|
control => control, |
-- MAC Transmitter |
mac_tx_tready => mac_tx_tready_int, |
mac_tx_tvalid => mac_tx_tvalid, |
/udp_ip_stack/trunk/rtl/vhdl/ml605/UDP_integration_example.vhd
40,6 → 40,8
PBTX_LED : out std_logic; |
TX_Started : out std_logic; |
TX_Completed : out std_logic; |
TX_RSLT_0 : out std_logic; |
TX_RSLT_1 : out std_logic; |
reset_leds : in std_logic; |
display : out std_logic_vector(7 downto 0); |
|
66,6 → 68,10
-- Component Declaration for the complete IP layer |
------------------------------------------------------------------------------ |
component UDP_Complete |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- UDP TX signals |
udp_tx_start : in std_logic; -- indicates req to tx UDP |
84,6 → 90,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in udp_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
104,7 → 111,7
end component; |
|
|
type state_type is (IDLE, DATA_OUT); |
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT); |
type count_mode_type is (RST, INCR, HOLD); |
type set_clr_type is (SET, CLR, HOLD); |
|
129,7 → 136,6
signal tx_start_reg : std_logic; |
signal tx_started_reg : std_logic; |
signal tx_fin_reg : std_logic; |
signal udp_rx_start_reg : std_logic; |
|
-- control signals |
signal next_state : state_type; |
140,20 → 146,21
signal set_last : std_logic; |
signal set_tx_started : set_clr_type; |
signal set_tx_fin : set_clr_type; |
signal set_udp_rx_start_reg : set_clr_type; |
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0); |
|
signal control_int : udp_control_type; |
|
begin |
|
process ( |
our_ip, our_mac, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, udp_rx_start_reg, |
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, |
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int, |
reset, tx_started_reg, tx_fin_reg, tx_start_reg |
) |
begin |
-- set up our local addresses |
-- set up our local addresses and default controls |
our_ip <= x"c0a80509"; -- 192.168.5.9 |
our_mac <= x"002320212223"; |
control_int.ip_controls.arp_controls.clear_cache <= '0'; |
|
-- determine RX good and error LEDs |
if udp_rx_int.hdr.is_valid = '1' then |
162,28 → 169,36
UDP_RX <= '0'; |
end if; |
|
UDP_Start <= udp_rx_start_reg; |
UDP_Start <= udp_rx_start_int; |
TX_Started <= tx_start_reg; --tx_started_reg; |
TX_Completed <= tx_fin_reg; |
TX_RSLT_0 <= udp_tx_result_int(0); |
TX_RSLT_1 <= udp_tx_result_int(1); |
|
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0 |
display (7 downto 4) <= ip_pkt_count_int (3 downto 0); |
display (3 downto 0) <= arp_pkt_count_int (3 downto 0); |
|
|
-- display (3 downto 0) <= arp_pkt_count_int (3 downto 0); |
case state is |
when IDLE => display (3 downto 0) <= "0001"; |
when WAIT_RX_DONE => display (3 downto 0) <= "0010"; |
when DATA_OUT => display (3 downto 0) <= "0011"; |
end case; |
|
end process; |
|
-- AUTO TX process - on receipt of any UDP pkt, send a response, |
-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received. |
|
-- TX response process - COMB |
-- TX response process - COMB |
tx_proc_combinatorial: process( |
-- inputs |
udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, |
udp_rx_int, PBTX, reset_leds, |
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int, |
udp_tx_int.data.data_out_valid, PBTX, |
-- state |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, udp_rx_start_reg, |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, |
-- controls |
next_state, set_state, set_count, set_hdr, set_tx_start, set_last, |
set_tx_started, set_tx_fin, set_udp_rx_start_reg, first_byte_rx |
set_tx_started, set_tx_fin, first_byte_rx |
) |
begin |
-- set output_followers |
200,14 → 215,14
set_last <= '0'; |
set_tx_started <= HOLD; |
set_tx_fin <= HOLD; |
set_udp_rx_start_reg <= HOLD; |
first_byte_rx <= (others => '0'); |
udp_tx_int.data.data_out <= (others => '0'); |
udp_tx_int.data.data_out_valid <= '0'; |
|
-- FSM |
case state is |
|
when IDLE => |
udp_tx_int.data.data_out <= (others => '0'); |
udp_tx_int.data.data_out_valid <= '0'; |
if udp_rx_start_int = '1' or PBTX = '1' then |
if udp_rx_start_int = '1' then |
215,34 → 230,58
else |
first_byte_rx <= x"00"; |
end if; |
set_udp_rx_start_reg <= SET; |
set_tx_fin <= CLR; |
set_count <= RST; |
set_hdr <= '1'; |
if udp_rx_int.data.data_in_last = '1' then |
set_tx_started <= SET; |
set_tx_start <= SET; |
next_state <= DATA_OUT; |
set_state <= '1'; |
else |
next_state <= WAIT_RX_DONE; |
set_state <= '1'; |
end if; |
end if; |
|
when WAIT_RX_DONE => |
-- wait until RX pkt fully received |
if udp_rx_int.data.data_in_last = '1' then |
set_tx_started <= SET; |
set_hdr <= '1'; |
set_tx_start <= SET; |
set_tx_fin <= CLR; |
set_count <= RST; |
next_state <= DATA_OUT; |
set_state <= '1'; |
elsif reset_leds = '1' then |
set_udp_rx_start_reg <= CLR; |
set_tx_started <= CLR; |
set_tx_fin <= CLR; |
end if; |
|
|
when DATA_OUT => |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40"; |
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int; |
if udp_tx_data_out_ready_int = '1' then |
set_tx_start <= CLR; |
if unsigned(count) = x"03" then |
set_last <= '1'; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
if udp_tx_result_int = UDPTX_RESULT_ERR then |
-- have an error from the IP TX layer, clear down the TX |
set_tx_start <= CLR; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
else |
if udp_tx_result_int = UDPTX_RESULT_SENDING then |
set_tx_start <= CLR; -- reset out start req as soon as we know we are sending |
end if; |
if ip_rx_hdr_int.is_broadcast = '1' then |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"50"; |
else |
set_count <= INCR; |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40"; |
end if; |
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int; |
if udp_tx_data_out_ready_int = '1' then |
if unsigned(count) = x"03" then |
set_last <= '1'; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
else |
set_count <= INCR; |
end if; |
end if; |
end if; |
|
end case; |
288,9 → 327,11
if set_hdr = '1' then |
-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP |
if first_byte_rx = x"42" then |
tx_hdr.dst_ip_addr <= IP_BC_ADDR; |
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr |
elsif first_byte_rx = x"43" then |
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout |
else |
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; |
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender |
end if; |
tx_hdr.dst_port <= udp_rx_int.hdr.src_port; |
tx_hdr.src_port <= udp_rx_int.hdr.dst_port; |
320,13 → 361,6
when CLR => tx_fin_reg <= '0'; |
when HOLD => tx_fin_reg <= tx_fin_reg; |
end case; |
|
-- set UDP START signal |
case set_udp_rx_start_reg is |
when SET => udp_rx_start_reg <= '1'; |
when CLR => udp_rx_start_reg <= '0'; |
when HOLD => udp_rx_start_reg <= udp_rx_start_reg; |
end case; |
|
|
end if; |
333,13 → 367,17
end if; |
|
end process; |
|
|
|
------------------------------------------------------------------------------ |
-- Instantiate the UDP layer |
------------------------------------------------------------------------------ |
UDP_block : UDP_Complete PORT MAP |
( |
UDP_block : UDP_Complete |
generic map ( |
ARP_TIMEOUT => 30 -- timeout in seconds |
) |
PORT MAP ( |
-- UDP interface |
udp_tx_start => udp_tx_start_int, |
udp_txi => udp_tx_int, |
356,6 → 394,7
reset => reset, |
our_ip_address => our_ip, |
our_mac_address => our_mac, |
control => control_int, |
-- status signals |
arp_pkt_count => arp_pkt_count_int, |
ip_pkt_count => ip_pkt_count_int, |
/udp_ip_stack/trunk/rtl/vhdl/ml605/udp_constraints.ucf
21,7 → 21,13
NET "display[7]" LOC = AD24; |
|
NET PBTX_LED LOC = AD21; |
NET UDP_RX LOC = AH27; |
NET UDP_START LOC = AH28; |
NET TX_RSLT_0 LOC = AE21; |
NET TX_RSLT_1 LOC = AP24; |
|
|
|
#### Module Push_Buttons_4Bit constraints |
NET PBTX LOC = H17; |
NET reset_leds LOC = G26; |
/udp_ip_stack/trunk/rtl/vhdl/arp_types.vhd
25,5 → 25,9
got_err : std_logic; -- indicates that we got an error (prob a timeout) |
end record; |
|
type arp_control_type is |
record |
clear_cache : std_logic; |
end record; |
|
end arp_types; |
/udp_ip_stack/trunk/rtl/vhdl/ipv4_types.vhd
6,6 → 6,7
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use work.axi.all; |
use work.arp_types.all; |
|
package ipv4_types is |
|
59,6 → 60,9
data : axi_in_type; -- rx axi bus |
end record; |
|
type ip_control_type is record |
arp_controls : arp_control_type; |
end record; |
|
------------ |
-- UDP TX -- |
108,5 → 112,9
port_num : STD_LOGIC_VECTOR (15 downto 0); |
end record; |
|
type udp_control_type is record |
ip_controls : ip_control_type; |
end record; |
|
|
end ipv4_types; |
/udp_ip_stack/trunk/rtl/vhdl/IP_complete_nomac.vhd
27,6 → 27,10
use work.arp_types.all; |
|
entity IP_complete_nomac is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- IP Layer signals |
ip_tx_start : in std_logic; |
41,6 → 45,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in ip_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
96,7 → 101,11
END COMPONENT; |
|
COMPONENT arp |
PORT( |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- lookup request signals |
arp_req_req : in arp_req_req_type; |
arp_req_rslt : out arp_req_rslt_type; |
117,9 → 126,10
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
-- system signals |
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
control : in arp_control_type; |
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received |
); |
); |
END COMPONENT; |
|
COMPONENT tx_arbitrator |
226,7 → 236,11
-- Instantiate the ARP layer |
------------------------------------------------------------------------------ |
arp_layer : arp |
Port map( |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT |
) |
Port map( |
-- request signals |
arp_req_req => arp_req_req_int, |
arp_req_rslt => arp_req_rslt_int, |
248,6 → 262,7
-- system signals |
our_mac_address => our_mac_address, |
our_ip_address => our_ip_address, |
control => control.arp_controls, |
req_count => arp_pkt_count |
); |
|
/udp_ip_stack/trunk/rtl/vhdl/IPv4_TX.vhd
251,12 → 251,12
|
when WAIT_MAC => |
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx |
set_mac_lku_req <= CLR; -- clear the request - will have been latched in the ARP layer |
if arp_req_rslt.got_mac = '1' then |
-- save the MAC we got back from the ARP lookup |
tx_mac_value <= arp_req_rslt.mac; |
set_tx_mac <= '1'; |
set_chn_reqd <= SET; |
set_mac_lku_req <= CLR; |
-- check for optimise when already have the channel |
if mac_tx_granted = '1' then |
-- ready to send data |
/udp_ip_stack/trunk/rtl/vhdl/UDP_Complete_nomac.vhd
27,6 → 27,10
use work.arp_types.all; |
|
entity UDP_Complete_nomac is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- UDP TX signals |
udp_tx_start : in std_logic; -- indicates req to tx UDP |
44,6 → 48,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in udp_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
109,6 → 114,10
------------------------------------------------------------------------------ |
|
component IP_complete_nomac |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- IP Layer signals |
ip_tx_start : in std_logic; |
123,6 → 132,7
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in ip_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
157,7 → 167,8
ip_rx_hdr <= ip_rx_int.hdr; |
|
-- Instantiate the UDP TX block |
udp_tx_block: UDP_TX PORT MAP ( |
udp_tx_block: UDP_TX |
PORT MAP ( |
-- UDP Layer signals |
udp_tx_start => udp_tx_start, |
udp_txi => udp_txi, |
189,8 → 200,12
------------------------------------------------------------------------------ |
-- Instantiate the IP layer |
------------------------------------------------------------------------------ |
IP_block : IP_complete_nomac PORT MAP |
( |
IP_block : IP_complete_nomac |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT |
) |
PORT MAP ( |
-- IP interface |
ip_tx_start => ip_tx_start_int, |
ip_tx => ip_tx_int, |
204,6 → 219,7
reset => reset, |
our_ip_address => our_ip_address, |
our_mac_address => our_mac_address, |
control => control.ip_controls, |
-- status signals |
arp_pkt_count => arp_pkt_count, |
ip_pkt_count => ip_pkt_count, |
/udp_ip_stack/trunk/doc/release_notes.txt
1,3 → 1,9
V1.3 - Added ARP timeout and ability to reset the ARP IP/MAC cache |
Migration notes: v1.2 to v1.3 - UDP_complete_nomac and IP_Complete_nomac have generics |
to specify clock rate and ARP timeout, and an additional control input. |
The generics can be left at their default values, the control input should have clear_cache set to '0'. |
|
|
V1.2 - Added handling for receipt of IP pkts with broadcast address ff.ff.ff.ff. Added is_broadcast flag |
to IP RX hdr. |
- Added ability to transmit IP pkts to broadcast address. |
/udp_ip_stack/trunk/doc/src/UDP_IP_Stack.pptx
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/udp_ip_stack/trunk/doc/UDP_IP_Stack.pdf
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