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https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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Rev 7 → Rev 8
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
12,7 → 12,7
clk_b |
); |
parameter DATA_WIDTH = 8; |
parameter ADDR_WIDTH = 11; |
parameter ADDR_WIDTH = 9; |
input [(DATA_WIDTH-1):0] d_a; |
input [(ADDR_WIDTH-1):0] adr_a; |
input [(ADDR_WIDTH-1):0] adr_b; |