OpenCores
URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

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Rev 7 → Rev 8

/virtex7_pcie_dma/trunk/documentation/pictures/dma_core_structure.odg Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/virtex7_pcie_dma/trunk/documentation/pictures/dma_core_structure.pdf
76,30 → 76,38
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/virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_slow_clock.vhd
57,7 → 57,7
entity pcie_slow_clock is
port (
clk : in std_logic;
clk40 : out std_logic;
clkDiv6 : out std_logic;
pll_locked : out std_logic;
reset_n : in std_logic;
reset_out : out std_logic);
85,7 → 85,7
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF clk_wiz_40 : COMPONENT IS "clk_in250,clk_out40,reset,locked";
 
signal clk40_s: std_logic;
signal clkDiv6_s: std_logic;
signal reset_s: std_logic;
signal locked_s: std_logic;
signal reset_cnt: integer range 0 to 15;
95,7 → 95,7
 
reset_s <= not reset_n;
pll_locked <= locked_s;
clk40 <= clk40_s;
clkDiv6 <= clkDiv6_s;
 
clk0 : clk_wiz_40
port map (
103,18 → 103,18
-- Clock in ports
clk_in250 => clk,
-- Clock out ports
clk_out40 => clk40_s,
clk_out40 => clkDiv6_s,
-- Status and control signals
reset => reset_s,
locked => locked_s
);
process(reset_s,locked_s, clk40_s)
process(reset_s,locked_s, clkDiv6_s)
begin
if(reset_s='1' or locked_s = '0') then
reset_cnt <= 0;
reset_out <= '1';
elsif(rising_edge(clk40_s)) then
elsif(rising_edge(clkDiv6_s)) then
if(reset_cnt < 15) then
reset_cnt <= reset_cnt + 1;
reset_out <= '1';
/virtex7_pcie_dma/trunk/firmware/sources/pcie/intr_ctrl.vhd
65,9 → 65,9
cfg_interrupt_msix_int : out std_logic;
cfg_interrupt_msix_sent : in std_logic;
clk : in std_logic;
clk40 : in std_logic;
dma_interrupt_call : in std_logic_vector(1 downto 0);
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 2);
clkDiv6 : in std_logic;
dma_interrupt_call : in std_logic_vector(3 downto 0);
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
interrupt_table_en : in std_logic;
interrupt_vector : in interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
reset : in std_logic);
96,9 → 96,9
begin
 
-- Interrupt vector assignments
interrupt_assign : process (clk40, interrupt_vector)
interrupt_assign : process (clkDiv6, interrupt_vector)
begin
if rising_edge (clk40) then
if rising_edge (clkDiv6) then
for i in 0 to (NUMBER_OF_INTERRUPTS-1) loop
interrupt_vector_s(i).int_vec_add <= interrupt_vector(i).int_vec_add;
interrupt_vector_s(i).int_vec_data <= interrupt_vector(i).int_vec_data;
122,7 → 122,7
s_interrupt_call <= interrupt_call & dma_interrupt_call;
--
-- interrupt controller
intr: process (clk40, reset)
intr: process (clkDiv6, reset)
variable v_cfg_interrupt_msix_int : std_logic := '0';
begin
if(reset = '1') then
130,7 → 130,7
v_cfg_interrupt_msix_int := '0';
s_cfg_interrupt_msix_address <= (others => '0');
s_cfg_interrupt_msix_data <= (others => '0');
elsif(rising_edge(clk40)) then
elsif(rising_edge(clkDiv6)) then
--default:
s_cfg_interrupt_msix_int <= v_cfg_interrupt_msix_int;
v_cfg_interrupt_msix_int := '0';
/virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd
58,13 → 58,15
entity dma_control is
generic(
NUMBER_OF_DESCRIPTORS : integer := 8;
NUMBER_OF_INTERRUPTS : integer := 8);
NUMBER_OF_INTERRUPTS : integer := 8;
SVN_VERSION : integer := 0;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE");
port (
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
clk : in std_logic;
clk40 : in std_logic;
clkDiv6 : in std_logic;
dma_descriptors : out dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
dma_soft_reset : out std_logic;
dma_status : in dma_statuses_type;
79,7 → 81,9
reset_global_soft : out std_logic;
s_axis_cq : in axis_type;
s_axis_r_cq : out axis_r_type;
dma_interrupt_call : out std_logic_vector(1 downto 0));
fifo_full : in std_logic;
fifo_empty : in std_logic;
dma_interrupt_call : out std_logic_vector(3 downto 0));
end entity dma_control;
 
 
101,69 → 105,75
signal dma_descriptors_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_descriptors_40_r_s : dma_descriptors_type(0 to 7);
signal dma_descriptors_40_w_s : dma_descriptors_type(0 to 7);
signal dma_descriptors_w_250_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_descriptors_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_descriptors_40_r_s : dma_descriptors_type(0 to 7);
signal dma_descriptors_40_w_s : dma_descriptors_type(0 to 7);
signal dma_descriptors_w_250_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_status_s : dma_statuses_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_status_40_s : dma_statuses_type(0 to 7);
signal dma_status_s : dma_statuses_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_status_40_s : dma_statuses_type(0 to 7);
 
signal int_vector_s : interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
signal int_vector_40_s : interrupt_vectors_type(0 to 7);
signal int_table_en_s : std_logic_vector(0 downto 0);
signal int_vector_s : interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
signal int_vector_40_s : interrupt_vectors_type(0 to 7);
signal int_table_en_s : std_logic_vector(0 downto 0);
signal register_address_s : std_logic_vector(63 downto 0);
signal address_type_s : std_logic_vector(1 downto 0);
signal dword_count_s : std_logic_vector(10 downto 0);
signal request_type_s : std_logic_vector(3 downto 0);
signal requester_id_s : std_logic_vector(15 downto 0);
signal tag_s : std_logic_vector(7 downto 0);
signal target_function_s : std_logic_vector(7 downto 0);
signal bar_id_s : std_logic_vector(2 downto 0);
signal bar_aperture_s : std_logic_vector(5 downto 0);
signal bar0_valid : std_logic;
signal transaction_class_s : std_logic_vector(2 downto 0);
signal attributes_s : std_logic_vector(2 downto 0);
signal seen_tlast_s : std_logic;
signal register_data_s : std_logic_vector(127 downto 0);
signal register_data_r : std_logic_vector(127 downto 0); --temporary register for read/modify/write
signal register_map_monitor_s : register_map_monitor_type;
signal register_map_control_s : register_map_control_type;
signal tlast_timer_s : std_logic_vector(7 downto 0);
signal register_address_s : std_logic_vector(63 downto 0);
signal address_type_s : std_logic_vector(1 downto 0);
signal dword_count_s : std_logic_vector(10 downto 0);
signal request_type_s : std_logic_vector(3 downto 0);
signal requester_id_s : std_logic_vector(15 downto 0);
signal tag_s : std_logic_vector(7 downto 0);
signal target_function_s : std_logic_vector(7 downto 0);
signal bar_id_s : std_logic_vector(2 downto 0);
signal bar_aperture_s : std_logic_vector(5 downto 0);
signal bar0_valid : std_logic;
signal transaction_class_s : std_logic_vector(2 downto 0);
signal attributes_s : std_logic_vector(2 downto 0);
signal seen_tlast_s : std_logic;
signal register_data_s : std_logic_vector(127 downto 0);
signal register_data_r : std_logic_vector(127 downto 0); --temporary register for read/modify/write
signal register_map_monitor_s : register_map_monitor_type;
signal register_map_control_s : register_map_control_type;
signal tlast_timer_s : std_logic_vector(7 downto 0);
signal register_read_address_250_s: std_logic_vector(31 downto 0);
signal register_read_address_40_s: std_logic_vector(31 downto 0);
signal register_read_enable_250_s: std_logic;
signal register_read_enable1_250_s: std_logic;
signal register_read_enable_40_s: std_logic;
signal register_read_done_250_s: std_logic;
signal register_read_done_40_s: std_logic;
signal register_read_data_250_s: std_logic_vector(127 downto 0);
signal register_read_data_40_s: std_logic_vector(127 downto 0);
signal register_write_address_250_s: std_logic_vector(31 downto 0);
signal register_write_address_40_s: std_logic_vector(31 downto 0);
signal register_write_enable_250_s: std_logic;
signal register_write_enable1_250_s: std_logic;
signal register_write_enable_40_s: std_logic;
signal register_write_done_250_s: std_logic;
signal register_write_done_40_s: std_logic;
signal register_write_data_250_s: std_logic_vector(127 downto 0);
signal register_write_data_40_s: std_logic_vector(127 downto 0);
signal bar0_40_s : std_logic_vector(31 downto 0);
signal bar1_40_s : std_logic_vector(31 downto 0);
signal bar2_40_s : std_logic_vector(31 downto 0);
signal flush_fifo_40_s : std_logic;
signal dma_soft_reset_40_s : std_logic;
signal reset_global_soft_40_s : std_logic;
signal write_interrupt_40_s: std_logic;
signal read_interrupt_40_s : std_logic;
signal write_interrupt_250_s: std_logic;
signal read_interrupt_250_s : std_logic;
signal register_read_address_250_s : std_logic_vector(31 downto 0);
signal register_read_address_40_s : std_logic_vector(31 downto 0);
signal register_read_enable_250_s : std_logic;
signal register_read_enable1_250_s : std_logic;
signal register_read_enable_40_s : std_logic;
signal register_read_done_250_s : std_logic;
signal register_read_done_40_s : std_logic;
signal register_read_data_250_s : std_logic_vector(127 downto 0);
signal register_read_data_40_s : std_logic_vector(127 downto 0);
signal register_write_address_250_s : std_logic_vector(31 downto 0);
signal register_write_address_40_s : std_logic_vector(31 downto 0);
signal register_write_enable_250_s : std_logic;
signal register_write_enable1_250_s : std_logic;
signal register_write_enable_40_s : std_logic;
signal register_write_done_250_s : std_logic;
signal register_write_done_40_s : std_logic;
signal register_write_data_250_s : std_logic_vector(127 downto 0);
signal register_write_data_40_s : std_logic_vector(127 downto 0);
signal bar0_40_s : std_logic_vector(31 downto 0);
signal bar1_40_s : std_logic_vector(31 downto 0);
signal bar2_40_s : std_logic_vector(31 downto 0);
signal fifo_full_interrupt_40_s : std_logic;
signal data_available_interrupt_40_s : std_logic;
signal flush_fifo_40_s : std_logic;
signal dma_soft_reset_40_s : std_logic;
signal reset_global_soft_40_s : std_logic;
signal write_interrupt_40_s : std_logic;
signal read_interrupt_40_s : std_logic;
signal write_interrupt_250_s : std_logic;
signal read_interrupt_250_s : std_logic;
type slv64_arr is array(0 to (NUMBER_OF_DESCRIPTORS -1)) of std_logic_vector(63 downto 0);
signal next_current_address_s : slv64_arr;
signal next_current_address_s : slv64_arr;
signal last_current_address_s : slv64_arr;
signal last_pc_pointer_s : slv64_arr;
signal dma_wait : std_logic_vector(0 to (NUMBER_OF_DESCRIPTORS-1));
--leave 16x8 = 128 bits space per register
 
-- ### BAR0 registers: start
247,7 → 257,7
pipe_descriptors: process(clk, dma_descriptors_s)
begin
for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
dma_descriptors(i).enable <= dma_descriptors_s(i).enable;
dma_descriptors(i).enable <= dma_descriptors_s(i).enable and not dma_wait(i);
dma_descriptors(i).current_address <= dma_descriptors_s(i).current_address;
end loop;
if(rising_edge(clk)) then
257,10 → 267,17
dma_descriptors(i).end_address <= dma_descriptors_s(i).end_address;
dma_descriptors(i).dword_count <= dma_descriptors_s(i).dword_count;
dma_descriptors(i).read_not_write <= dma_descriptors_s(i).read_not_write;
dma_descriptors(i).wrap_around <= dma_descriptors_s(i).wrap_around;
dma_descriptors(i).pc_pointer <= dma_descriptors_s(i).pc_pointer;
dma_descriptors(i).evencycle_dma <= dma_descriptors_s(i).evencycle_dma;
dma_descriptors(i).evencycle_pc <= dma_descriptors_s(i).evencycle_pc;
end loop;
end if;
end process;
 
 
 
comp: process(clk, reset)
variable request_type_v : std_logic_vector(3 downto 0);
variable poisoned_completion_v : std_logic;
272,7 → 289,10
begin
if(reset = '1') then
for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
dma_descriptors_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'));
dma_descriptors_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around => '0', evencycle_dma => '0', evencycle_pc => '0', pc_pointer => (others => '0'));
dma_wait(i) <= '0';
read_interrupt_250_s <= '0';
write_interrupt_250_s <= '0';
end loop;
else
if(rising_edge(clk)) then
324,21 → 344,60
dma_descriptors_s(i).start_address <= dma_descriptors_w_250_s(i).start_address;
dma_descriptors_s(i).read_not_write <= dma_descriptors_w_250_s(i).read_not_write;
dma_descriptors_s(i).dword_count <= dma_descriptors_w_250_s(i).dword_count;
dma_descriptors_s(i).pc_pointer <= dma_descriptors_w_250_s(i).pc_pointer;
dma_descriptors_s(i).wrap_around <= dma_descriptors_w_250_s(i).wrap_around;
last_current_address_s(i) <= dma_descriptors_s(i).current_address;
if(last_current_address_s(i) > dma_descriptors_s(i).current_address) then
dma_descriptors_s(i).evencycle_dma <= not dma_descriptors_s(i).evencycle_dma; --Toggle on wrap around
end if;
last_pc_pointer_s(i) <= dma_descriptors_s(i).pc_pointer;
if(last_pc_pointer_s(i) > dma_descriptors_s(i).pc_pointer) then
dma_descriptors_s(i).evencycle_pc <= not dma_descriptors_s(i).evencycle_pc; --Toggle on wrap around
end if;
next_current_address_s(i) <= (dma_descriptors_s(i).current_address + (dma_descriptors_s(i).dword_count&"00"));
--dma has wrapped around while PC still hasn't, check if we are smaller than write pointer.
if(dma_descriptors_s(i).wrap_around = '1' and ((dma_descriptors_s(i).evencycle_dma xor dma_descriptors_s(i).read_not_write) /= dma_descriptors_s(i).evencycle_pc)) then
if(next_current_address_s(i)<dma_descriptors_s(i).pc_pointer) then
dma_wait(i) <= '0';
else
dma_wait(i) <= '1';
end if;
else
dma_wait(i) <= '0';
end if;
if(dma_descriptors_s(i).enable = '1') then
if(dma_status_s(i).descriptor_done = '1') then
if(next_current_address_s(i)<dma_descriptors_s(i).end_address) then
dma_descriptors_s(i).current_address <= next_current_address_s(i);
--dma has wrapped around while PC still hasn't, check if we are smaller than write pointer.
if(dma_descriptors_s(i).wrap_around = '1' and ((dma_descriptors_s(i).evencycle_dma xor dma_descriptors_s(i).read_not_write) /= dma_descriptors_s(i).evencycle_pc)) then
if(next_current_address_s(i)<dma_descriptors_s(i).pc_pointer) then
dma_descriptors_s(i).current_address <= next_current_address_s(i);
else
dma_descriptors_s(i).current_address <= dma_descriptors_s(i).current_address;
end if;
else
dma_descriptors_s(i).enable <= '0';
if(dma_descriptors_s(i).read_not_write='1') then
read_interrupt_250_s <= '1';
if(next_current_address_s(i)<dma_descriptors_s(i).end_address) then
dma_descriptors_s(i).current_address <= next_current_address_s(i);
else
write_interrupt_250_s <= '1';
dma_descriptors_s(i).enable <= dma_descriptors_s(i).wrap_around;
if(dma_descriptors_s(i).read_not_write='1') then
read_interrupt_250_s <= '1';
else
write_interrupt_250_s <= '1';
end if;
end if;
end if;
--When wrapping around, regardless of the cycle, when the end address has been reached, the current address must be reset to start_address.
if(next_current_address_s(i)=dma_descriptors_s(i).end_address) then
if(dma_descriptors_s(i).wrap_around = '1') then
dma_descriptors_s(i).current_address <= dma_descriptors_s(i).start_address;
end if;
end if;
end if;
else
dma_descriptors_s(i).current_address <= dma_descriptors_s(i).start_address;
633,7 → 692,7
 
regSync40: process(clk40)
regSync40: process(clkDiv6)
variable register_read_address_v : std_logic_vector(31 downto 0);
variable register_read_enable_v : std_logic;
variable register_write_address_v : std_logic_vector(31 downto 0);
646,9 → 705,10
variable dma_status_v : dma_statuses_type(0 to 7);
variable int_vector_v : interrupt_vectors_type(0 to NUMBER_OF_INTERRUPTS-1);
variable int_table_en_v : std_logic_vector(0 downto 0);
variable fifo_full_interrupt_v : std_logic_vector(2 downto 0);
variable data_available_interrupt_v : std_logic_vector(2 downto 0);
begin
if(rising_edge(clk40)) then
if(rising_edge(clkDiv6)) then
register_read_address_40_s <= register_read_address_v;
register_read_enable_40_s <= register_read_enable_v;
register_write_address_40_s <= register_write_address_v;
674,6 → 734,21
read_interrupt_40_s <= read_interrupt_250_s;
write_interrupt_40_s <= write_interrupt_250_s;
if(fifo_full_interrupt_v(2 downto 1) = "01") then --rising edge detected on full flag
fifo_full_interrupt_40_s <= '1';
else
fifo_full_interrupt_40_s <= '0';
end if;
if(data_available_interrupt_v(2 downto 1) = "10") then --falling edge detected on empty flag
data_available_interrupt_40_s <= '1';
else
data_available_interrupt_40_s <= '0';
end if;
fifo_full_interrupt_v := fifo_full_interrupt_v(1 downto 0) & fifo_full;
data_available_interrupt_v := data_available_interrupt_v(1 downto 0) & fifo_empty;
for i in 0 to (NUMBER_OF_DESCRIPTORS - 1) loop
dma_descriptors_v(i) := dma_descriptors_s(i);
dma_status_v(i) := dma_status_s(i);
720,6 → 795,9
end if;
end process;
 
dma_interrupt_call(3) <= fifo_full_interrupt_40_s;
dma_interrupt_call(2) <= data_available_interrupt_40_s;
 
dma_interrupt_call(1) <= write_interrupt_40_s;
dma_interrupt_call(0) <= read_interrupt_40_s;
 
728,7 → 806,7
register_map_monitor_s <= register_map_monitor;
register_map_control <= register_map_control_s;
regrw: process(clk40, reset)
regrw: process(clkDiv6, reset)
begin
if(reset = '1') then
736,7 → 814,7
register_read_done_40_s <= '0';
register_read_data_40_s <= (others => '0');
for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
dma_descriptors_40_w_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'));
dma_descriptors_40_w_s(i) <= (start_address => (others => '0'), dword_count => (others => '0'), read_not_write => '0', enable => '0', current_address => (others => '0'), end_address => (others => '0'),wrap_around => '0', evencycle_dma => '0', evencycle_pc => '0', pc_pointer => (others => '0'));
end loop;
for i in 0 to (NUMBER_OF_INTERRUPTS-1) loop
int_vector_40_s(i) <= (int_vec_add => (others => '0'), int_vec_data => (others => '0'),int_vec_ctrl => (others => '0') );
752,7 → 830,7
------------------------------------------------
---- Application specific registers END 🂱 ----
------------------------------------------------
elsif(rising_edge(clk40)) then
elsif(rising_edge(clkDiv6)) then
register_map_control_s <= register_map_control_s; --store read (PCIe Write) register map
register_read_done_40_s <= '0';
register_read_data_40_s <= register_read_data_40_s;
770,67 → 848,99
if(register_read_address_40_s(31 downto 20) = bar0_40_s(31 downto 20)) then
case(register_read_address_40_s(19 downto 4)&"0000") is
when REG_DESCRIPTOR_0 => register_read_data_40_s <= dma_descriptors_40_r_s( 0).end_address&
dma_descriptors_40_r_s( 0 ).start_address;
when REG_DESCRIPTOR_0a => register_read_data_40_s <= x"00000000000000000000000000000"&
dma_descriptors_40_r_s( 0).start_address;
when REG_DESCRIPTOR_0a => register_read_data_40_s <= dma_descriptors_40_r_s( 0).pc_pointer&
x"000000000000"&"000"&
dma_descriptors_40_r_s( 0).wrap_around&
dma_descriptors_40_r_s( 0).read_not_write&
dma_descriptors_40_r_s( 0).dword_count;
when REG_DESCRIPTOR_1 => register_read_data_40_s <= dma_descriptors_40_r_s( 1).end_address&
dma_descriptors_40_r_s( 1 ).start_address;
when REG_DESCRIPTOR_1a => register_read_data_40_s <= x"00000000000000000000000000000"&
dma_descriptors_40_r_s( 1).start_address;
when REG_DESCRIPTOR_1a => register_read_data_40_s <= dma_descriptors_40_r_s( 1).pc_pointer&
x"000000000000"&"000"&
dma_descriptors_40_r_s( 1).wrap_around&
dma_descriptors_40_r_s( 1).read_not_write&
dma_descriptors_40_r_s( 1).dword_count;
when REG_DESCRIPTOR_2 => register_read_data_40_s <= dma_descriptors_40_r_s( 2).end_address&
dma_descriptors_40_r_s( 2 ).start_address;
when REG_DESCRIPTOR_2a => register_read_data_40_s <= x"00000000000000000000000000000"&
dma_descriptors_40_r_s( 2).start_address;
when REG_DESCRIPTOR_2a => register_read_data_40_s <= dma_descriptors_40_r_s( 2).pc_pointer&
x"000000000000"&"000"&
dma_descriptors_40_r_s( 2).wrap_around&
dma_descriptors_40_r_s( 2).read_not_write&
dma_descriptors_40_r_s( 2).dword_count;
when REG_DESCRIPTOR_3 => register_read_data_40_s <= dma_descriptors_40_r_s( 3).end_address&
dma_descriptors_40_r_s( 3 ).start_address;
when REG_DESCRIPTOR_3a => register_read_data_40_s <= x"00000000000000000000000000000"&
dma_descriptors_40_r_s( 3).start_address;
when REG_DESCRIPTOR_3a => register_read_data_40_s <= dma_descriptors_40_r_s( 3).pc_pointer&
x"000000000000"&"000"&
dma_descriptors_40_r_s( 3).wrap_around&
dma_descriptors_40_r_s( 3).read_not_write&
dma_descriptors_40_r_s( 3).dword_count;
when REG_DESCRIPTOR_4 => register_read_data_40_s <= dma_descriptors_40_r_s( 4).end_address&
dma_descriptors_40_r_s( 4 ).start_address;
when REG_DESCRIPTOR_4a => register_read_data_40_s <= x"00000000000000000000000000000"&
dma_descriptors_40_r_s( 4).start_address;
when REG_DESCRIPTOR_4a => register_read_data_40_s <= dma_descriptors_40_r_s( 4).pc_pointer&
x"000000000000"&"000"&
dma_descriptors_40_r_s( 4).wrap_around&
dma_descriptors_40_r_s( 4).read_not_write&
dma_descriptors_40_r_s( 4).dword_count;
when REG_DESCRIPTOR_5 => register_read_data_40_s <= dma_descriptors_40_r_s( 5).end_address&
dma_descriptors_40_r_s( 5 ).start_address;
when REG_DESCRIPTOR_5a => register_read_data_40_s <= x"00000000000000000000000000000"&
dma_descriptors_40_r_s( 5).start_address;
when REG_DESCRIPTOR_5a => register_read_data_40_s <= dma_descriptors_40_r_s( 5).pc_pointer&
x"000000000000"&"000"&
dma_descriptors_40_r_s( 5).wrap_around&
dma_descriptors_40_r_s( 5).read_not_write&
dma_descriptors_40_r_s( 5).dword_count;
when REG_DESCRIPTOR_6 => register_read_data_40_s <= dma_descriptors_40_r_s( 6).end_address&
dma_descriptors_40_r_s( 6 ).start_address;
when REG_DESCRIPTOR_6a => register_read_data_40_s <= x"00000000000000000000000000000"&
dma_descriptors_40_r_s( 6).start_address;
when REG_DESCRIPTOR_6a => register_read_data_40_s <= dma_descriptors_40_r_s( 6).pc_pointer&
x"000000000000"&"000"&
dma_descriptors_40_r_s( 6).wrap_around&
dma_descriptors_40_r_s( 6).read_not_write&
dma_descriptors_40_r_s( 6).dword_count;
when REG_DESCRIPTOR_7 => register_read_data_40_s <= dma_descriptors_40_r_s( 7).end_address&
dma_descriptors_40_r_s( 7 ).start_address;
when REG_DESCRIPTOR_7a => register_read_data_40_s <= x"00000000000000000000000000000"&
dma_descriptors_40_r_s( 7).start_address;
when REG_DESCRIPTOR_7a => register_read_data_40_s <= dma_descriptors_40_r_s( 7).pc_pointer&
x"000000000000"&"000"&
dma_descriptors_40_r_s( 7).wrap_around&
dma_descriptors_40_r_s( 7).read_not_write&
dma_descriptors_40_r_s( 7).dword_count;
when REG_STATUS_0 => register_read_data_40_s <= x"000000000000000"&"000"&
when REG_STATUS_0 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(0 ).evencycle_pc&
dma_descriptors_40_r_s(0 ).evencycle_dma&
dma_status_40_s(0 ).descriptor_done&
dma_descriptors_40_r_s(0 ).current_address;
when REG_STATUS_1 => register_read_data_40_s <= x"000000000000000"&"000"&
when REG_STATUS_1 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(1 ).evencycle_pc&
dma_descriptors_40_r_s(1 ).evencycle_dma&
dma_status_40_s(1 ).descriptor_done&
dma_descriptors_40_r_s(1 ).current_address;
when REG_STATUS_2 => register_read_data_40_s <= x"000000000000000"&"000"&
when REG_STATUS_2 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(2 ).evencycle_pc&
dma_descriptors_40_r_s(2 ).evencycle_dma&
dma_status_40_s(2 ).descriptor_done&
dma_descriptors_40_r_s(2 ).current_address;
when REG_STATUS_3 => register_read_data_40_s <= x"000000000000000"&"000"&
when REG_STATUS_3 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(3 ).evencycle_pc&
dma_descriptors_40_r_s(3 ).evencycle_dma&
dma_status_40_s(3 ).descriptor_done&
dma_descriptors_40_r_s(3 ).current_address;
when REG_STATUS_4 => register_read_data_40_s <= x"000000000000000"&"000"&
when REG_STATUS_4 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(4 ).evencycle_pc&
dma_descriptors_40_r_s(4 ).evencycle_dma&
dma_status_40_s(4 ).descriptor_done&
dma_descriptors_40_r_s(4 ).current_address;
when REG_STATUS_5 => register_read_data_40_s <= x"000000000000000"&"000"&
when REG_STATUS_5 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(5 ).evencycle_pc&
dma_descriptors_40_r_s(5 ).evencycle_dma&
dma_status_40_s(5 ).descriptor_done&
dma_descriptors_40_r_s(5 ).current_address;
when REG_STATUS_6 => register_read_data_40_s <= x"000000000000000"&"000"&
when REG_STATUS_6 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(6 ).evencycle_pc&
dma_descriptors_40_r_s(6 ).evencycle_dma&
dma_status_40_s(6 ).descriptor_done&
dma_descriptors_40_r_s(6 ).current_address;
when REG_STATUS_7 => register_read_data_40_s <= x"000000000000000"&"000"&
when REG_STATUS_7 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(7 ).evencycle_pc&
dma_descriptors_40_r_s(7 ).evencycle_dma&
dma_status_40_s(7 ).descriptor_done&
dma_descriptors_40_r_s(7 ).current_address;
when REG_BAR0 => register_read_data_40_s <= x"000000000000000000000000"&bar0_40_s;
885,7 → 995,7
---- Application specific registers BEGIN 🂱 ----
------------------------------------------------
-- Control Registers
when REG_BOARD_ID => register_read_data_40_s <= x"0000000000000000"&register_map_control_s.BOARD_ID;
when REG_BOARD_ID => register_read_data_40_s <= x"000000000000"&std_logic_vector(to_unsigned(SVN_VERSION, 16))&x"000000"&BUILD_DATETIME;
when REG_STATUS_LEDS => register_read_data_40_s <= x"000000000000000000000000000000"&register_map_control_s.STATUS_LEDS;
when REG_GENERIC_CONSTANTS => register_read_data_40_s <= x"0000000000000000000000000000"&std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS, 8))&
std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS, 8));
913,35 → 1023,51
case(register_write_address_40_s(19 downto 4)&"0000") is --only check 128 bit addressing
when REG_DESCRIPTOR_0 => dma_descriptors_40_w_s( 0).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 0).start_address <= register_write_data_40_s(63 downto 0);
when REG_DESCRIPTOR_0a => dma_descriptors_40_w_s( 0).read_not_write <= register_write_data_40_s(11);
when REG_DESCRIPTOR_0a => dma_descriptors_40_w_s( 0).pc_pointer <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 0).wrap_around <= register_write_data_40_s(12);
dma_descriptors_40_w_s( 0).read_not_write <= register_write_data_40_s(11);
dma_descriptors_40_w_s( 0).dword_count <= register_write_data_40_s(10 downto 0);
when REG_DESCRIPTOR_1 => dma_descriptors_40_w_s( 1).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 1).start_address <= register_write_data_40_s(63 downto 0);
when REG_DESCRIPTOR_1a => dma_descriptors_40_w_s( 1).read_not_write <= register_write_data_40_s(11);
when REG_DESCRIPTOR_1a => dma_descriptors_40_w_s( 1).pc_pointer <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 1).wrap_around <= register_write_data_40_s(12);
dma_descriptors_40_w_s( 1).read_not_write <= register_write_data_40_s(11);
dma_descriptors_40_w_s( 1).dword_count <= register_write_data_40_s(10 downto 0);
when REG_DESCRIPTOR_2 => dma_descriptors_40_w_s( 2).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 2).start_address <= register_write_data_40_s(63 downto 0);
when REG_DESCRIPTOR_2a => dma_descriptors_40_w_s( 2).read_not_write <= register_write_data_40_s(11);
when REG_DESCRIPTOR_2a => dma_descriptors_40_w_s( 2).pc_pointer <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 2).wrap_around <= register_write_data_40_s(12);
dma_descriptors_40_w_s( 2).read_not_write <= register_write_data_40_s(11);
dma_descriptors_40_w_s( 2).dword_count <= register_write_data_40_s(10 downto 0);
when REG_DESCRIPTOR_3 => dma_descriptors_40_w_s( 3).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 3).start_address <= register_write_data_40_s(63 downto 0);
when REG_DESCRIPTOR_3a => dma_descriptors_40_w_s( 3).read_not_write <= register_write_data_40_s(11);
when REG_DESCRIPTOR_3a => dma_descriptors_40_w_s( 3).pc_pointer <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 3).wrap_around <= register_write_data_40_s(12);
dma_descriptors_40_w_s( 3).read_not_write <= register_write_data_40_s(11);
dma_descriptors_40_w_s( 3).dword_count <= register_write_data_40_s(10 downto 0);
when REG_DESCRIPTOR_4 => dma_descriptors_40_w_s( 4).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 4).start_address <= register_write_data_40_s(63 downto 0);
when REG_DESCRIPTOR_4a => dma_descriptors_40_w_s( 4).read_not_write <= register_write_data_40_s(11);
when REG_DESCRIPTOR_4a => dma_descriptors_40_w_s( 4).pc_pointer <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 4).wrap_around <= register_write_data_40_s(12);
dma_descriptors_40_w_s( 4).read_not_write <= register_write_data_40_s(11);
dma_descriptors_40_w_s( 4).dword_count <= register_write_data_40_s(10 downto 0);
when REG_DESCRIPTOR_5 => dma_descriptors_40_w_s( 5).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 5).start_address <= register_write_data_40_s(63 downto 0);
when REG_DESCRIPTOR_5a => dma_descriptors_40_w_s( 5).read_not_write <= register_write_data_40_s(11);
when REG_DESCRIPTOR_5a => dma_descriptors_40_w_s( 5).pc_pointer <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 5).wrap_around <= register_write_data_40_s(12);
dma_descriptors_40_w_s( 5).read_not_write <= register_write_data_40_s(11);
dma_descriptors_40_w_s( 5).dword_count <= register_write_data_40_s(10 downto 0);
when REG_DESCRIPTOR_6 => dma_descriptors_40_w_s( 6).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 6).start_address <= register_write_data_40_s(63 downto 0);
when REG_DESCRIPTOR_6a => dma_descriptors_40_w_s( 6).read_not_write <= register_write_data_40_s(11);
when REG_DESCRIPTOR_6a => dma_descriptors_40_w_s( 6).pc_pointer <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 6).wrap_around <= register_write_data_40_s(12);
dma_descriptors_40_w_s( 6).read_not_write <= register_write_data_40_s(11);
dma_descriptors_40_w_s( 6).dword_count <= register_write_data_40_s(10 downto 0);
when REG_DESCRIPTOR_7 => dma_descriptors_40_w_s( 7).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 7).start_address <= register_write_data_40_s(63 downto 0);
when REG_DESCRIPTOR_7a => dma_descriptors_40_w_s( 7).read_not_write <= register_write_data_40_s(11);
when REG_DESCRIPTOR_7a => dma_descriptors_40_w_s( 7).pc_pointer <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 7).wrap_around <= register_write_data_40_s(12);
dma_descriptors_40_w_s( 7).read_not_write <= register_write_data_40_s(11);
dma_descriptors_40_w_s( 7).dword_count <= register_write_data_40_s(10 downto 0);
-- REG_STATUS_0 is readonly
-- REG_STATUS_1 is readonly
1001,7 → 1127,7
------------------------------------------------
---- Application specific registers END 🂱 ----
------------------------------------------------
-- test crap far away in BAR 2
 
when others =>
end case;
end if;
/virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_read_write.vhd
172,7 → 172,11
read_not_write => '1',
enable => '0',
current_address => (others => '0'),
end_address => (others => '0'));
end_address => (others => '0'),
wrap_around => '0',
evencycle_dma => '0',
evencycle_pc => '0',
pc_pointer => (others => '0'));
req_tag <= "0000";
active_descriptor_s <= 0;
for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
/virtex7_pcie_dma/trunk/firmware/sources/pcie/DMA_Core.vhd
59,14 → 59,16
entity DMA_Core is
generic(
NUMBER_OF_DESCRIPTORS : integer := 8;
NUMBER_OF_INTERRUPTS : integer := 8);
NUMBER_OF_INTERRUPTS : integer := 8;
SVN_VERSION : integer := 0;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE");
port (
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
clk : in std_logic;
clk40 : in std_logic;
dma_interrupt_call : out STD_LOGIC_VECTOR(1 downto 0);
clkDiv6 : in std_logic;
dma_interrupt_call : out STD_LOGIC_VECTOR(3 downto 0);
fifo_din : out std_logic_vector(255 downto 0);
fifo_dout : in std_logic_vector(255 downto 0);
fifo_empty : in std_logic;
140,13 → 142,15
component dma_control
generic(
NUMBER_OF_DESCRIPTORS : integer := 8;
NUMBER_OF_INTERRUPTS : integer := 8);
NUMBER_OF_INTERRUPTS : integer := 8;
SVN_VERSION : integer := 0;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE");
port (
bar0 : in STD_LOGIC_VECTOR(31 downto 0);
bar1 : in STD_LOGIC_VECTOR(31 downto 0);
bar2 : in STD_LOGIC_VECTOR(31 downto 0);
clk : in STD_LOGIC;
clk40 : in STD_LOGIC;
clkDiv6 : in STD_LOGIC;
dma_descriptors : out dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
dma_soft_reset : out STD_LOGIC;
dma_status : in dma_statuses_type;
161,7 → 165,9
register_map_monitor : in register_map_monitor_type;
register_map_control : out register_map_control_type;
interrupt_table_en : out STD_LOGIC;
dma_interrupt_call : out STD_LOGIC_VECTOR(1 downto 0));
dma_interrupt_call : out STD_LOGIC_VECTOR(3 downto 0);
fifo_empty : in std_logic;
fifo_full : in std_logic);
end component dma_control;
 
begin
203,13 → 209,15
u1: dma_control
generic map(
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS,
NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS)
NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS,
SVN_VERSION => SVN_VERSION,
BUILD_DATETIME => BUILD_DATETIME)
port map(
bar0 => bar0,
bar1 => bar1,
bar2 => bar2,
clk => clk,
clk40 => clk40,
clkDiv6 => clkDiv6,
dma_descriptors => u1_dma_descriptors,
dma_soft_reset => dma_soft_reset,
dma_status => dma_status,
224,6 → 232,8
register_map_monitor => register_map_monitor,
register_map_control => register_map_control,
interrupt_table_en => interrupt_table_en,
dma_interrupt_call => dma_interrupt_call);
dma_interrupt_call => dma_interrupt_call,
fifo_empty => fifo_empty,
fifo_full => fifo_full);
end architecture structure ; -- of DMA_Core
 
/virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_dma_wrap.vhd
59,7 → 59,9
entity pcie_dma_wrap is
generic(
NUMBER_OF_INTERRUPTS : integer := 8;
NUMBER_OF_DESCRIPTORS : integer := 8);
NUMBER_OF_DESCRIPTORS : integer := 8;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
SVN_VERSION : integer := 0);
port (
appreg_clk : out std_logic;
fifo_din : out std_logic_vector(255 downto 0);
71,7 → 73,7
fifo_we : out std_logic;
fifo_wr_clk : out std_logic;
flush_fifo : out std_logic;
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 2);
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
pcie_rxn : in std_logic_vector(7 downto 0);
pcie_rxp : in std_logic_vector(7 downto 0);
pcie_txn : out std_logic_vector(7 downto 0);
118,8 → 120,8
signal cfg_mgmt_read_write_done : std_logic;
signal cfg_mgmt_read_data : std_logic_vector(31 downto 0);
signal interrupt_table_en : std_logic;
signal dma_interrupt_call : STD_LOGIC_VECTOR(1 downto 0);
signal clk40 : std_logic;
signal clkDiv6 : std_logic;
signal dma_interrupt_call : STD_LOGIC_VECTOR(3 downto 0);
 
component pcie_ep_wrap
port (
159,14 → 161,16
component DMA_Core
generic(
NUMBER_OF_DESCRIPTORS : integer := 8;
NUMBER_OF_INTERRUPTS : integer := 8);
NUMBER_OF_INTERRUPTS : integer := 8;
SVN_VERSION : integer := 0;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE");
port (
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
clk : in std_logic;
clk40 : in std_logic;
dma_interrupt_call : out STD_LOGIC_VECTOR(1 downto 0);
clkDiv6 : in std_logic;
dma_interrupt_call : out STD_LOGIC_VECTOR(3 downto 0);
fifo_din : out std_logic_vector(255 downto 0);
fifo_dout : in std_logic_vector(255 downto 0);
fifo_empty : in std_logic;
202,9 → 206,9
cfg_interrupt_msix_int : out std_logic;
cfg_interrupt_msix_sent : in std_logic;
clk : in std_logic;
clk40 : in std_logic;
dma_interrupt_call : in std_logic_vector(1 downto 0);
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 2);
clkDiv6 : in std_logic;
dma_interrupt_call : in std_logic_vector(3 downto 0);
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
interrupt_table_en : in std_logic;
interrupt_vector : in interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
reset : in std_logic);
229,7 → 233,7
component pcie_slow_clock
port (
clk : in std_logic;
clk40 : out std_logic;
clkDiv6 : out std_logic;
pll_locked : out std_logic;
reset_n : in std_logic;
reset_out : out std_logic);
238,7 → 242,7
begin
fifo_rd_clk <= clk;
fifo_wr_clk <= clk;
appreg_clk <= clk40;
appreg_clk <= clkDiv6;
 
u1: pcie_ep_wrap
port map(
277,13 → 281,15
dma0: DMA_Core
generic map(
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS,
NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS)
NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS,
SVN_VERSION => SVN_VERSION,
BUILD_DATETIME => BUILD_DATETIME)
port map(
bar0 => bar0,
bar1 => bar1,
bar2 => bar2,
clk => clk,
clk40 => clk40,
clkDiv6 => clkDiv6,
dma_interrupt_call => dma_interrupt_call,
fifo_din => fifo_din,
fifo_dout => fifo_dout,
319,7 → 325,7
cfg_interrupt_msix_int => cfg_interrupt_msix_int,
cfg_interrupt_msix_sent => cfg_interrupt_msix_sent,
clk => clk,
clk40 => clk40,
clkDiv6 => clkDiv6,
dma_interrupt_call => dma_interrupt_call,
interrupt_call => interrupt_call,
interrupt_table_en => interrupt_table_en,
344,7 → 350,7
u3: pcie_slow_clock
port map(
clk => clk,
clk40 => clk40,
clkDiv6 => clkDiv6,
pll_locked => pll_locked,
reset_n => sys_reset_n,
reset_out => reset_hard);
/virtex7_pcie_dma/trunk/firmware/sources/application/application.vhd
74,7 → 74,7
fifo_we : in std_logic;
fifo_wr_clk : in std_logic;
flush_fifo : in std_logic;
interrupt_call : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 2);
interrupt_call : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
leds : out std_logic_vector(7 downto 0);
pll_locked : in std_logic;
register_map_control : in register_map_control_type; --! contains all read/write registers that control the application. The record members are described in pcie_package.vhd
167,11 → 167,11
end if;
end process;
g0: if(NUMBER_OF_INTERRUPTS>2) generate
interrupt_call(2 downto 2) <= register_map_control_s.INT_TEST_2;
g1: if(NUMBER_OF_INTERRUPTS>3) generate
interrupt_call(3 downto 3) <= register_map_control_s.INT_TEST_3;
interrupt_call(NUMBER_OF_INTERRUPTS-1 downto 4) <= (others => '0');
g0: if(NUMBER_OF_INTERRUPTS>4) generate
interrupt_call(4 downto 4) <= register_map_control_s.INT_TEST_2;
g1: if(NUMBER_OF_INTERRUPTS>5) generate
interrupt_call(5 downto 5) <= register_map_control_s.INT_TEST_3;
interrupt_call(NUMBER_OF_INTERRUPTS-1 downto 6) <= (others => '0');
end generate;
end generate;
/virtex7_pcie_dma/trunk/firmware/sources/shared/virtex7_dma_top.vhd
59,7 → 59,9
entity virtex7_dma_top is
generic(
NUMBER_OF_INTERRUPTS : integer := 8;
NUMBER_OF_DESCRIPTORS : integer := 8);
NUMBER_OF_DESCRIPTORS : integer := 8;
SVN_VERSION : integer := 0;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE");
port (
emcclk : in std_logic; --! emcclk is part of the JTAG high speed programming.
emcclk_out : out std_logic; --! use emcclk_out in order to not optimize emcclk away
87,7 → 89,7
signal fifo_empty : std_logic;
signal fifo_rd_clk : std_logic; --! High speed DMA fifo for the PCIe => PC transfers
signal flush_fifo : std_logic; --! Reset signal for the FIFOs
signal interrupt_call : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 2);
signal interrupt_call : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
signal appreg_clk : std_logic;
signal u1_pll_locked : std_logic;
signal reset_soft : std_logic;
96,7 → 98,9
component pcie_dma_wrap
generic(
NUMBER_OF_INTERRUPTS : integer := 8;
NUMBER_OF_DESCRIPTORS : integer := 8);
NUMBER_OF_DESCRIPTORS : integer := 8;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
SVN_VERSION : integer := 0);
port (
appreg_clk : out std_logic;
fifo_din : out std_logic_vector(255 downto 0);
108,7 → 112,7
fifo_we : out std_logic;
fifo_wr_clk : out std_logic;
flush_fifo : out std_logic;
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 2);
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
pcie_rxn : in std_logic_vector(7 downto 0);
pcie_rxp : in std_logic_vector(7 downto 0);
pcie_txn : out std_logic_vector(7 downto 0);
137,7 → 141,7
fifo_we : in std_logic;
fifo_wr_clk : in std_logic;
flush_fifo : in std_logic;
interrupt_call : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 2);
interrupt_call : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
leds : out std_logic_vector(7 downto 0);
pll_locked : in std_logic;
register_map_control : in register_map_control_type; --! contains all read/write registers that control the application. The record members are described in pcie_package.vhd
156,7 → 160,9
u1: pcie_dma_wrap
generic map(
NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS,
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS)
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS,
BUILD_DATETIME => BUILD_DATETIME,
SVN_VERSION => SVN_VERSION)
port map(
appreg_clk => appreg_clk,
fifo_din => fifo_din,
/virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd
77,6 → 77,10
dword_count : std_logic_vector(10 downto 0);
read_not_write : std_logic; --1 means this is a read descriptor, 0: write descriptor
enable : std_logic; --descriptor is valid
wrap_around : std_logic; --1 means when end is reached, keep enabled and start over
evencycle_dma : std_logic; --For every time the current_address overflows, this bit toggles
evencycle_pc : std_logic; --For every time the pc pointer overflows, this bit toggles.
pc_pointer : std_logic_vector(63 downto 0); --Last address that the PC has read / written. For write: overflow and read until this cycle.
end record;
 
type dma_descriptors_type is array (natural range <>) of dma_descriptor_type;
119,7 → 123,6
---- Application specific registers BEGIN 🂱 ----
------------------------------------------------
type register_map_control_type is record
BOARD_ID : std_logic_vector(63 downto 0);
STATUS_LEDS : std_logic_vector(7 downto 0);
INT_TEST_2 : std_logic_vector(0 downto 0);
INT_TEST_3 : std_logic_vector(0 downto 0);
/virtex7_pcie_dma/trunk/firmware/simulation/pcie_dma_top/wave.do
1,68 → 1,121
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group application /virtex7_dma_top/u0/appreg_clk
add wave -noupdate -expand -group application /virtex7_dma_top/u0/fifo_din
add wave -noupdate -expand -group application /virtex7_dma_top/u0/fifo_dout
add wave -noupdate -expand -group application /virtex7_dma_top/u0/fifo_empty
add wave -noupdate -expand -group application /virtex7_dma_top/u0/fifo_full
add wave -noupdate -expand -group application /virtex7_dma_top/u0/fifo_rd_clk
add wave -noupdate -expand -group application /virtex7_dma_top/u0/fifo_re
add wave -noupdate -expand -group application /virtex7_dma_top/u0/fifo_we
add wave -noupdate -expand -group application /virtex7_dma_top/u0/fifo_wr_clk
add wave -noupdate -expand -group application /virtex7_dma_top/u0/flush_fifo
add wave -noupdate -expand -group application /virtex7_dma_top/u0/interrupt_call
add wave -noupdate -expand -group application /virtex7_dma_top/u0/leds
add wave -noupdate -expand -group application /virtex7_dma_top/u0/pll_locked
add wave -noupdate -expand -group application /virtex7_dma_top/u0/register_map_control
add wave -noupdate -expand -group application /virtex7_dma_top/u0/register_map_monitor
add wave -noupdate -expand -group application /virtex7_dma_top/u0/reset_hard
add wave -noupdate -expand -group application /virtex7_dma_top/u0/reset_soft
add wave -noupdate -expand -group application /virtex7_dma_top/u0/register_map_monitor_s
add wave -noupdate -expand -group application /virtex7_dma_top/u0/register_map_control_s
add wave -noupdate -expand -group application /virtex7_dma_top/u0/s_fifo_we
add wave -noupdate -expand -group application /virtex7_dma_top/u0/s_fifo_full
add wave -noupdate -expand -group application /virtex7_dma_top/u0/s_fifo_din
add wave -noupdate -expand -group application /virtex7_dma_top/u0/cnt
add wave -noupdate -expand -group application /virtex7_dma_top/u0/reset
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/cache_tready
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/clk
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/dma_descriptors
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/dma_soft_reset
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/dma_status
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_din
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_dout
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_empty
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_full
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_re
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_we
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/m_axis_r_rq
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/m_axis_rq
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/reset
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/s_axis_r_rc
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/s_axis_rc
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/rw_state
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/rw_state_slv
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/strip_state
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/strip_state_slv
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/current_descriptor
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_dout_pipe
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_din_pipe
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/req_tag
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/descriptor_done_s
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/s_axis_rc_tlast_pipe
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/s_axis_rc_tvalid_pipe
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_full_pipe
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/receive_word_count
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/active_descriptor_s
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/receive_tags_s
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/receive_tag_status_s
add wave -noupdate -expand -group dma_read_write /virtex7_dma_top/u1/dma0/u0/current_receive_tag_s
add wave -noupdate -group application /virtex7_dma_top/u0/appreg_clk
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_din
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_dout
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_empty
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_full
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_rd_clk
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_re
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_we
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_wr_clk
add wave -noupdate -group application /virtex7_dma_top/u0/flush_fifo
add wave -noupdate -group application /virtex7_dma_top/u0/interrupt_call
add wave -noupdate -group application /virtex7_dma_top/u0/leds
add wave -noupdate -group application /virtex7_dma_top/u0/pll_locked
add wave -noupdate -group application /virtex7_dma_top/u0/register_map_control
add wave -noupdate -group application /virtex7_dma_top/u0/register_map_monitor
add wave -noupdate -group application /virtex7_dma_top/u0/reset_hard
add wave -noupdate -group application /virtex7_dma_top/u0/reset_soft
add wave -noupdate -group application /virtex7_dma_top/u0/register_map_monitor_s
add wave -noupdate -group application /virtex7_dma_top/u0/register_map_control_s
add wave -noupdate -group application /virtex7_dma_top/u0/s_fifo_we
add wave -noupdate -group application /virtex7_dma_top/u0/s_fifo_full
add wave -noupdate -group application /virtex7_dma_top/u0/s_fifo_din
add wave -noupdate -group application /virtex7_dma_top/u0/cnt
add wave -noupdate -group application /virtex7_dma_top/u0/reset
add wave -noupdate -group application /virtex7_dma_top/u0/appreg_clk
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_din
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_dout
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_empty
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_full
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_rd_clk
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_re
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_we
add wave -noupdate -group application /virtex7_dma_top/u0/fifo_wr_clk
add wave -noupdate -group application /virtex7_dma_top/u0/flush_fifo
add wave -noupdate -group application /virtex7_dma_top/u0/interrupt_call
add wave -noupdate -group application /virtex7_dma_top/u0/leds
add wave -noupdate -group application /virtex7_dma_top/u0/pll_locked
add wave -noupdate -group application /virtex7_dma_top/u0/register_map_control
add wave -noupdate -group application /virtex7_dma_top/u0/register_map_monitor
add wave -noupdate -group application /virtex7_dma_top/u0/reset_hard
add wave -noupdate -group application /virtex7_dma_top/u0/reset_soft
add wave -noupdate -group application /virtex7_dma_top/u0/register_map_monitor_s
add wave -noupdate -group application /virtex7_dma_top/u0/register_map_control_s
add wave -noupdate -group application /virtex7_dma_top/u0/s_fifo_we
add wave -noupdate -group application /virtex7_dma_top/u0/s_fifo_full
add wave -noupdate -group application /virtex7_dma_top/u0/s_fifo_din
add wave -noupdate -group application /virtex7_dma_top/u0/cnt
add wave -noupdate -group application /virtex7_dma_top/u0/reset
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/clk
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/pll_locked
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/reset_n
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/reset_out
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/reset_s
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/locked_s
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/reset_cnt
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/clk
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/pll_locked
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/reset_n
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/reset_out
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/reset_s
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/locked_s
add wave -noupdate -group slowclock /virtex7_dma_top/u1/u3/reset_cnt
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_in250
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_out40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/reset
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/locked
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_in250_clk_wiz_40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_out40_clk_wiz_40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clkfbout_buf_clk_wiz_40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clkfbout_clk_wiz_40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_DRDY_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_PSDONE_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_DO_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_in250
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_out40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/reset
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/locked
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_in250_clk_wiz_40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_out40_clk_wiz_40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clkfbout_buf_clk_wiz_40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clkfbout_clk_wiz_40
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_DRDY_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_PSDONE_UNCONNECTED
add wave -noupdate -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_DO_UNCONNECTED
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/bar0
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/bar1
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/bar2
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/clk
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/clk40
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/dma_descriptors
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/clkDiv6
add wave -noupdate -expand -group dma_control -expand -subitemconfig {/virtex7_dma_top/u1/dma0/u1/dma_descriptors(0) -expand} /virtex7_dma_top/u1/dma0/u1/dma_descriptors
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/dma_soft_reset
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/dma_status
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/flush_fifo
76,6 → 129,8
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/reset_global_soft
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/s_axis_cq
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/s_axis_r_cq
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/fifo_full
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/fifo_empty
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/dma_interrupt_call
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/completer_state
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/completer_state_slv
127,6 → 182,8
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/bar0_40_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/bar1_40_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/bar2_40_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/fifo_full_interrupt_40_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/data_available_interrupt_40_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/flush_fifo_40_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/dma_soft_reset_40_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/reset_global_soft_40_s
134,41 → 191,45
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/read_interrupt_40_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/write_interrupt_250_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/read_interrupt_250_s
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/clk
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/clk40
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/pll_locked
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/reset_n
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/reset_out
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/clk40_s
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/reset_s
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/locked_s
add wave -noupdate -expand -group slowclock /virtex7_dma_top/u1/u3/reset_cnt
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_in250
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_out40
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/reset
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/locked
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_in250_clk_wiz_40
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clk_out40_clk_wiz_40
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clkfbout_buf_clk_wiz_40
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/clkfbout_clk_wiz_40
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_DRDY_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_PSDONE_UNCONNECTED
add wave -noupdate -expand -group clk_wiz /virtex7_dma_top/u1/u3/clk0/U0/NLW_mmcm_adv_inst_DO_UNCONNECTED
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/next_current_address_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/last_current_address_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/last_pc_pointer_s
add wave -noupdate -expand -group dma_control /virtex7_dma_top/u1/dma0/u1/dma_wait
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/cache_tready
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/clk
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/dma_descriptors
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/dma_soft_reset
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/dma_status
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_din
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_dout
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_empty
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_full
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_re
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_we
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/m_axis_r_rq
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/m_axis_rq
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/reset
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/s_axis_r_rc
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/s_axis_rc
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/rw_state
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/rw_state_slv
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/strip_state
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/strip_state_slv
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/current_descriptor
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_dout_pipe
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_din_pipe
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/req_tag
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/descriptor_done_s
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/s_axis_rc_tlast_pipe
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/s_axis_rc_tvalid_pipe
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/fifo_full_pipe
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/receive_word_count
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/active_descriptor_s
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/receive_tags_s
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/receive_tag_status_s
add wave -noupdate -group dma_read_write /virtex7_dma_top/u1/dma0/u0/current_receive_tag_s
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
WaveRestoreCursors {{Cursor 1} {1952634 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 269
configure wave -valuecolwidth 449
184,4 → 245,4
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {81548510 ps}
WaveRestoreZoom {1685218 ps} {2184484 ps}
/virtex7_pcie_dma/trunk/firmware/simulation/pcie_dma_top/start.do
152,72 → 152,82
run 102ns
run 800ns
## emulated register writes
write_reg128 64'hfbb00000 128'h00000004560100000000000456000000
write_reg128 64'hfbb00010 128'h00000000000000000000000000000040
write_reg128 64'hfbb00020 128'h00000004560008000000000456000000
write_reg128 64'hfbb00030 128'h00000000000000000000000000000840
write_reg128 64'hfbb00000 128'h0000_0004_5600_0400_0000_0004_5600_0000
write_reg128 64'hfbb00010 128'h0000_0004_5600_0000_0000_0000_0000_1040
write_reg128 64'hfbb00020 128'h0000_0004_5600_0800_0000_0004_5600_0000
write_reg128 64'hfbb00030 128'h0000_0004_5600_0700_0000_0000_0000_1840
#do it another time to see if read works.
write_reg128 64'hfbb00030 128'h00000000000000000000000000000840
#write_reg128 64'hfbb00030 128'h00000000000000000000000000000840
# issue a soft reset
write_reg32 64'hfbb00430 128'h1
#enable descriptor 0
write_reg32 64'hfbb00400 128'h1
#write_reg32 64'hfbb00430 128'h1
#enable descriptor 0 and 1
write_reg32 64'hfbb00400 128'h3
#enable interrupt table
#write_reg32 64'hfba0100 32'h1
 
run 100ns
 
### emulated PCIe read to drive the AXI interface from the Core side
#### emulated PCIe read to drive the AXI interface from the Core side
##
#set dmadataL(0) 160'h131211100f0e0d0c0b0a09080706050403020100
#set dmadataH(0) 96'h1f1e1d1c1b1a191817161514
#set dmadataL(1) 160'h333231302f2e2d2c2b2a29282726252423222120
#set dmadataH(1) 96'h3f3e3d3c3b3a393837363534
#set dmadataL(2) 160'h535251504f4e4d4c4b4a49484746454443424140
#set dmadataH(2) 96'h5f5e5d5c5b5a595857565554
#set dmadataL(3) 160'h737271706f6e6d6c6b6a69686766656463626160
#set dmadataH(3) 96'h7f7e7d7c7b7a797877767574
#set dmadataL(4) 160'h939291908f8e8d8c8b8a89888786858483828180
#set dmadataH(4) 96'h9f9e9d9c9b9a999897969594
#set dmadataL(5) 160'hB3B2B1B0AfAeAdAcAbAaA9A8A7A6A5A4A3A2A1A0
#set dmadataH(5) 96'hBfBeBdBcBbBaB9B8B7B6B5B4
#set dmadataL(6) 160'hD3D2D1D0CfCeCdCcCbCaC9C8C7C6C5C4C3C2C1C0
#set dmadataH(6) 96'hDfDeDdDcDbDaD9D8D7D6D5D4
#set dmadataL(7) 160'hF3F2F1F0EfEeEdEcEbEaE9E8E7E6E5E4E3E2E1E0
#set dmadataH(7) 96'hFfFeFdFcFbFaF9F8F7F6F5F4
#
set dmadataL(0) 160'h131211100f0e0d0c0b0a09080706050403020100
set dmadataH(0) 96'h1f1e1d1c1b1a191817161514
set dmadataL(1) 160'h333231302f2e2d2c2b2a29282726252423222120
set dmadataH(1) 96'h3f3e3d3c3b3a393837363534
set dmadataL(2) 160'h535251504f4e4d4c4b4a49484746454443424140
set dmadataH(2) 96'h5f5e5d5c5b5a595857565554
set dmadataL(3) 160'h737271706f6e6d6c6b6a69686766656463626160
set dmadataH(3) 96'h7f7e7d7c7b7a797877767574
set dmadataL(4) 160'h939291908f8e8d8c8b8a89888786858483828180
set dmadataH(4) 96'h9f9e9d9c9b9a999897969594
set dmadataL(5) 160'hB3B2B1B0AfAeAdAcAbAaA9A8A7A6A5A4A3A2A1A0
set dmadataH(5) 96'hBfBeBdBcBbBaB9B8B7B6B5B4
set dmadataL(6) 160'hD3D2D1D0CfCeCdCcCbCaC9C8C7C6C5C4C3C2C1C0
set dmadataH(6) 96'hDfDeDdDcDbDaD9D8D7D6D5D4
set dmadataL(7) 160'hF3F2F1F0EfEeEdEcEbEaE9E8E7E6E5E4E3E2E1E0
set dmadataH(7) 96'hFfFeFdFcFbFaF9F8F7F6F5F4
#write_dma 12'hABC dmadataL dmadataH 8'h10 8
 
write_dma 12'hABC dmadataL dmadataH 8'h10 8
 
 
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h11 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h12 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h13 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h14 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h15 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h15 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h16 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h17 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h18 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h19 8
#run 100ns
#write_dma 12'hABC dmadataL dmadataH 8'h1A 8
#run 100ns
 
#write_reg32 64'hfbb00400 128'h1
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h11 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h12 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h13 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h14 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h15 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h15 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h16 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h17 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h18 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h19 8
run 100ns
write_dma 12'hABC dmadataL dmadataH 8'h1A 8
run 100ns
 
write_reg32 64'hfbb00400 128'h1
run 100ns
force -freeze sim:/virtex7_dma_top/u1/dma0/u2/m_axis_r_rq.tready 0 0
run 80ns
force -freeze sim:/virtex7_dma_top/u1/dma0/u2/m_axis_r_rq.tready 1 0
run 100ns
#run 12us
write_reg128 64'hfbb00010 128'h0000_0004_5600_0400_0000_0000_0000_1040
run 100ns
write_reg128 64'hfbb00010 128'h0000_0004_5600_0000_0000_0000_0000_1040
run 200ns
write_reg128 64'hfbb00010 128'h0000_0004_5600_0200_0000_0000_0000_1040
run 200ns
write_reg128 64'hfbb00010 128'h0000_0004_5600_0300_0000_0000_0000_1040
run 200ns
write_reg128 64'hfbb00010 128'h0000_0004_5600_0400_0000_0000_0000_1040
 

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