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URL https://opencores.org/ocsvn/wb_dma/wb_dma/trunk

Subversion Repositories wb_dma

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Rev 7 → Rev 8

/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: test_bench_top.v,v 1.2 2001-08-15 05:40:29 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:29 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.1.1.1 2001/03/19 13:11:22 rudi
// Initial Release
//
102,10 → 108,10
wire wb1_ack_i;
wire wb1_err_i;
wire wb1_rty_i;
reg [`CH_COUNT-1:0] req_i;
wire [`CH_COUNT-1:0] ack_o;
reg [`CH_COUNT-1:0] nd_i;
reg [`CH_COUNT-1:0] rest_i;
reg [`WDMA_CH_COUNT-1:0] req_i;
wire [`WDMA_CH_COUNT-1:0] ack_o;
reg [`WDMA_CH_COUNT-1:0] nd_i;
reg [`WDMA_CH_COUNT-1:0] rest_i;
wire inta_o;
wire intb_o;
 
202,7 → 208,7
 
// HERE IS WHERE THE TEST CASES GO ...
 
if(0) // Full Regression Run
if(1) // Full Regression Run
begin
pt10_rd;
pt01_wr;
240,7 → 246,7
// TEST DEVELOPMENT AREA
//
 
hw_dma4(0);
arb_test1;
 
repeat(100) @(posedge clk);
 
268,9 → 274,8
 
always @(posedge clk)
if(wb0_cyc_i | wb1_cyc_i | wb0_ack_i | wb1_ack_i) wd_cnt <= #1 0;
else wd_cnt <= #1 wd_cnt + 1;
else wd_cnt <= #1 wd_cnt + 1;
 
 
always @(wd_cnt)
if(wd_cnt>5000)
begin
291,8 → 296,8
// Module Prototype
 
wb_dma_top u0(
.clk( clk ),
.rst( rst ),
.clk_i( clk ),
.rst_i( rst ),
.wb0s_data_i( wb0s_data_i ),
.wb0s_data_o( wb0s_data_o ),
.wb0_addr_i( wb0_addr_i ),
/trunk/bench/verilog/tests.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tests.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: tests.v,v 1.2 2001-08-15 05:40:29 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:29 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.1.1.1 2001/03/19 13:12:39 rudi
// Initial Release
//
116,7 → 122,6
$display("Total Size: %0d, Chunk Size: %0d, Slave Delay: %0d",
tot_sz, chunk_sz, del);
 
 
ack_cnt_clr = 1;
@(posedge clk);
ack_cnt_clr = 0;
149,8 → 154,6
s0.mem[15] = 32'h0000_0000;
 
 
 
 
m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);
 
m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0020);
159,7 → 162,6
m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
 
m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
//{25'h0000001, 4'b0011, 2'b00, 1'b1});
{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});
 
 
169,12 → 171,9
m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4000);
 
m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
//{25'h0000001, 4'b0011, 2'b00, 1'b1});
{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});
 
 
 
 
for(ii=0;ii<2;ii=ii+1)
begin
repeat(5) @(posedge clk);
237,9 → 236,6
 
end
 
 
 
 
if(ack_cnt != ((tot_sz*4)+(4*2))*2 )
begin
$display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
436,16 → 432,16
s1.fill_mem(1);
 
m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
{17'h00000, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b0});
{17'h00000, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b0});
 
m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
{17'h00000, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b0});
{17'h00000, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b0});
 
m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
{17'h00000, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b0});
{17'h00000, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b0});
 
m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
{17'h00000, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b0});
{17'h00000, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b0});
 
m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);
 
465,17 → 461,22
m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_0180);
m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_4180);
 
 
m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
{15'h0002, 2'b00, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b1});
{12'h000, 3'b010, 1'b0, 1'b0, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b1});
 
//{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});
 
m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
{15'h0002, 2'b00, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b1});
{12'h000, 3'b010, 1'b0, 1'b0, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b1});
 
m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
{15'h0002, 2'b00, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b1});
{12'h000, 3'b010, 1'b0, 1'b0, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b1});
 
 
 
m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
{15'h0002, 2'b00, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b1});
{12'h0000, 3'b010, 1'b0, 1'b0, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b1});
 
repeat(1) @(posedge clk);
 
485,40 → 486,37
finish = 8'hxx;
 
while(ptr!=4)
begin
begin
while(!inta_o) @(posedge clk);
m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0);
 
while(!inta_o) @(posedge clk);
m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0);
if(d0[0]) d0[1:0] = 0;
else
if(d0[1]) d0[1:0] = 1;
else
if(d0[2]) d0[1:0] = 2;
else
if(d0[3]) d0[1:0] = 3;
 
if(d0[0]) d0[1:0] = 0;
else
if(d0[1]) d0[1:0] = 1;
else
if(d0[2]) d0[1:0] = 2;
else
if(d0[3]) d0[1:0] = 3;
case(ptr)
0: finish[7:6] = d0[1:0];
1: finish[5:4] = d0[1:0];
2: finish[3:2] = d0[1:0];
3: finish[1:0] = d0[1:0];
endcase
 
case(ptr)
0: finish[7:6] = d0[1:0];
1: finish[5:4] = d0[1:0];
2: finish[3:2] = d0[1:0];
3: finish[1:0] = d0[1:0];
endcase
case(d0[1:0])
0: m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
1: m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
2: m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
3: m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
endcase
 
case(d0[1:0])
0: m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
1: m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
2: m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
3: m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
endcase
ptr=ptr+1;
repeat(4) @(posedge clk);
end
 
ptr=ptr+1;
repeat(2) @(posedge clk);
 
 
end
 
 
if(finish !== order)
begin
$display("ERROR: Completion Order[%0d] Mismatch: Expected: %b, Got: %b (%0t)",
542,8 → 540,6
end
end
 
 
 
if(ack_cnt != ((tot_sz*4*2)) )
begin
$display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
/trunk/rtl/verilog/wb_dma_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_top.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: wb_dma_top.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.3 2001/06/13 02:26:50 rudi
//
//
69,7 → 75,7
 
`include "wb_dma_defines.v"
 
module wb_dma_top(clk, rst,
module wb_dma_top(clk_i, rst_i,
 
wb0s_data_i, wb0s_data_o, wb0_addr_i, wb0_sel_i, wb0_we_i, wb0_cyc_i,
wb0_stb_i, wb0_ack_o, wb0_err_o, wb0_rty_o,
86,7 → 92,7
inta_o, intb_o
);
 
input clk, rst;
input clk_i, rst_i;
 
// --------------------------------------
// WISHBONE INTERFACE 0
144,10 → 150,10
 
// --------------------------------------
// Misc Signals
input [`CH_COUNT-1:0] dma_req_i;
input [`CH_COUNT-1:0] dma_nd_i;
output [`CH_COUNT-1:0] dma_ack_o;
input [`CH_COUNT-1:0] dma_rest_i;
input [`WDMA_CH_COUNT-1:0] dma_req_i;
input [`WDMA_CH_COUNT-1:0] dma_nd_i;
output [`WDMA_CH_COUNT-1:0] dma_ack_o;
input [`WDMA_CH_COUNT-1:0] dma_rest_i;
output inta_o;
output intb_o;
 
269,10 → 275,10
// Misc Logic
//
 
assign dma_req[`CH_COUNT-1:0] = dma_req_i;
assign dma_nd[`CH_COUNT-1:0] = dma_nd_i;
assign dma_rest[`CH_COUNT-1:0] = dma_rest_i;
assign dma_ack_o = dma_ack[`CH_COUNT-1:0];
assign dma_req[`WDMA_CH_COUNT-1:0] = dma_req_i;
assign dma_nd[`WDMA_CH_COUNT-1:0] = dma_nd_i;
assign dma_rest[`WDMA_CH_COUNT-1:0] = dma_rest_i;
assign dma_ack_o = dma_ack[`WDMA_CH_COUNT-1:0];
 
// --------------------------------------------------
// This should go in to a separate Pass Through Block
293,8 → 299,8
// DMA Register File
 
wb_dma_rf u0(
.clk( clk ),
.rst( rst ),
.clk( clk_i ),
.rst( rst_i ),
.wb_rf_adr( slv0_adr[9:2] ),
.wb_rf_din( slv0_dout ),
.wb_rf_dout( slv0_din ),
574,8 → 580,8
 
// Channel Select
wb_dma_ch_sel u1(
.clk( clk ),
.rst( rst ),
.clk( clk_i ),
.rst( rst_i ),
.req_i( dma_req ),
.ack_o( dma_ack ),
.nd_i( dma_nd ),
849,8 → 855,8
 
// DMA Engine
wb_dma_de u2(
.clk( clk ),
.rst( rst ),
.clk( clk_i ),
.rst( rst_i ),
.mast0_go( mast0_go ),
.mast0_we( mast0_we ),
.mast0_adr( mast0_adr ),
900,8 → 906,8
 
// Wishbone Interface 0
wb_dma_wb_if u3(
.clk( clk ),
.rst( rst ),
.clk( clk_i ),
.rst( rst_i ),
.wbs_data_i( wb0s_data_i ),
.wbs_data_o( wb0s_data_o ),
.wb_addr_i( wb0_addr_i ),
945,8 → 951,8
 
// Wishbone Interface 1
wb_dma_wb_if u4(
.clk( clk ),
.rst( rst ),
.clk( clk_i ),
.rst( rst_i ),
.wbs_data_i( wb1s_data_i ),
.wbs_data_o( wb1s_data_o ),
.wb_addr_i( wb1_addr_i ),
/trunk/rtl/verilog/wb_dma_rf.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_rf.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: wb_dma_rf.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.4 2001/06/14 08:50:46 rudi
//
// Changed name of channel register file module.
258,7 → 264,6
 
assign int_maska = {1'h0, int_maska_r};
assign int_maskb = {1'h0, int_maskb_r};
//assign csr = {24'h0, csr_r[7:1], paused};
assign csr = {31'h0, paused};
 
////////////////////////////////////////////////////////////////////
291,7 → 296,7
8'he: wb_rf_dout <= #1 pointer0;
8'hf: wb_rf_dout <= #1 sw_pointer0;
 
`ifdef HAVE_CH1
`ifdef WDMA_HAVE_CH1
8'h10: wb_rf_dout <= #1 ch1_csr;
8'h11: wb_rf_dout <= #1 ch1_txsz;
8'h12: wb_rf_dout <= #1 ch1_adr0;
302,7 → 307,7
8'h17: wb_rf_dout <= #1 sw_pointer1;
`endif
 
`ifdef HAVE_CH2
`ifdef WDMA_HAVE_CH2
8'h18: wb_rf_dout <= #1 ch2_csr;
8'h19: wb_rf_dout <= #1 ch2_txsz;
8'h1a: wb_rf_dout <= #1 ch2_adr0;
313,7 → 318,7
8'h1f: wb_rf_dout <= #1 sw_pointer2;
`endif
 
`ifdef HAVE_CH3
`ifdef WDMA_HAVE_CH3
8'h20: wb_rf_dout <= #1 ch3_csr;
8'h21: wb_rf_dout <= #1 ch3_txsz;
8'h22: wb_rf_dout <= #1 ch3_adr0;
324,7 → 329,7
8'h27: wb_rf_dout <= #1 sw_pointer3;
`endif
 
`ifdef HAVE_CH4
`ifdef WDMA_HAVE_CH4
8'h28: wb_rf_dout <= #1 ch4_csr;
8'h29: wb_rf_dout <= #1 ch4_txsz;
8'h2a: wb_rf_dout <= #1 ch4_adr0;
335,7 → 340,7
8'h2f: wb_rf_dout <= #1 sw_pointer4;
`endif
 
`ifdef HAVE_CH5
`ifdef WDMA_HAVE_CH5
8'h30: wb_rf_dout <= #1 ch5_csr;
8'h31: wb_rf_dout <= #1 ch5_txsz;
8'h32: wb_rf_dout <= #1 ch5_adr0;
346,7 → 351,7
8'h37: wb_rf_dout <= #1 sw_pointer5;
`endif
 
`ifdef HAVE_CH6
`ifdef WDMA_HAVE_CH6
8'h38: wb_rf_dout <= #1 ch6_csr;
8'h39: wb_rf_dout <= #1 ch6_txsz;
8'h3a: wb_rf_dout <= #1 ch6_adr0;
357,7 → 362,7
8'h3f: wb_rf_dout <= #1 sw_pointer6;
`endif
 
`ifdef HAVE_CH7
`ifdef WDMA_HAVE_CH7
8'h40: wb_rf_dout <= #1 ch7_csr;
8'h41: wb_rf_dout <= #1 ch7_txsz;
8'h42: wb_rf_dout <= #1 ch7_adr0;
368,7 → 373,7
8'h47: wb_rf_dout <= #1 sw_pointer7;
`endif
 
`ifdef HAVE_CH8
`ifdef WDMA_HAVE_CH8
8'h48: wb_rf_dout <= #1 ch8_csr;
8'h49: wb_rf_dout <= #1 ch8_txsz;
8'h4a: wb_rf_dout <= #1 ch8_adr0;
379,7 → 384,7
8'h4f: wb_rf_dout <= #1 sw_pointer8;
`endif
 
`ifdef HAVE_CH9
`ifdef WDMA_HAVE_CH9
8'h50: wb_rf_dout <= #1 ch9_csr;
8'h51: wb_rf_dout <= #1 ch9_txsz;
8'h52: wb_rf_dout <= #1 ch9_adr0;
390,7 → 395,7
8'h57: wb_rf_dout <= #1 sw_pointer9;
`endif
 
`ifdef HAVE_CH10
`ifdef WDMA_HAVE_CH10
8'h58: wb_rf_dout <= #1 ch10_csr;
8'h59: wb_rf_dout <= #1 ch10_txsz;
8'h5a: wb_rf_dout <= #1 ch10_adr0;
401,7 → 406,7
8'h5f: wb_rf_dout <= #1 sw_pointer10;
`endif
 
`ifdef HAVE_CH11
`ifdef WDMA_HAVE_CH11
8'h60: wb_rf_dout <= #1 ch11_csr;
8'h61: wb_rf_dout <= #1 ch11_txsz;
8'h62: wb_rf_dout <= #1 ch11_adr0;
412,7 → 417,7
8'h67: wb_rf_dout <= #1 sw_pointer11;
`endif
 
`ifdef HAVE_CH12
`ifdef WDMA_HAVE_CH12
8'h68: wb_rf_dout <= #1 ch12_csr;
8'h69: wb_rf_dout <= #1 ch12_txsz;
8'h6a: wb_rf_dout <= #1 ch12_adr0;
423,7 → 428,7
8'h6f: wb_rf_dout <= #1 sw_pointer12;
`endif
 
`ifdef HAVE_CH13
`ifdef WDMA_HAVE_CH13
8'h70: wb_rf_dout <= #1 ch13_csr;
8'h71: wb_rf_dout <= #1 ch13_txsz;
8'h72: wb_rf_dout <= #1 ch13_adr0;
434,7 → 439,7
8'h77: wb_rf_dout <= #1 sw_pointer13;
`endif
 
`ifdef HAVE_CH14
`ifdef WDMA_HAVE_CH14
8'h78: wb_rf_dout <= #1 ch14_csr;
8'h79: wb_rf_dout <= #1 ch14_txsz;
8'h7a: wb_rf_dout <= #1 ch14_adr0;
445,7 → 450,7
8'h7f: wb_rf_dout <= #1 sw_pointer14;
`endif
 
`ifdef HAVE_CH15
`ifdef WDMA_HAVE_CH15
8'h80: wb_rf_dout <= #1 ch15_csr;
8'h81: wb_rf_dout <= #1 ch15_txsz;
8'h82: wb_rf_dout <= #1 ch15_adr0;
456,7 → 461,7
8'h87: wb_rf_dout <= #1 sw_pointer15;
`endif
 
`ifdef HAVE_CH16
`ifdef WDMA_HAVE_CH16
8'h88: wb_rf_dout <= #1 ch16_csr;
8'h89: wb_rf_dout <= #1 ch16_txsz;
8'h8a: wb_rf_dout <= #1 ch16_adr0;
467,7 → 472,7
8'h8f: wb_rf_dout <= #1 sw_pointer16;
`endif
 
`ifdef HAVE_CH17
`ifdef WDMA_HAVE_CH17
8'h90: wb_rf_dout <= #1 ch17_csr;
8'h91: wb_rf_dout <= #1 ch17_txsz;
8'h92: wb_rf_dout <= #1 ch17_adr0;
478,7 → 483,7
8'h97: wb_rf_dout <= #1 sw_pointer17;
`endif
 
`ifdef HAVE_CH18
`ifdef WDMA_HAVE_CH18
8'h98: wb_rf_dout <= #1 ch18_csr;
8'h99: wb_rf_dout <= #1 ch18_txsz;
8'h9a: wb_rf_dout <= #1 ch18_adr0;
489,7 → 494,7
8'h9f: wb_rf_dout <= #1 sw_pointer18;
`endif
 
`ifdef HAVE_CH19
`ifdef WDMA_HAVE_CH19
8'ha0: wb_rf_dout <= #1 ch19_csr;
8'ha1: wb_rf_dout <= #1 ch19_txsz;
8'ha2: wb_rf_dout <= #1 ch19_adr0;
500,7 → 505,7
8'ha7: wb_rf_dout <= #1 sw_pointer19;
`endif
 
`ifdef HAVE_CH20
`ifdef WDMA_HAVE_CH20
8'ha8: wb_rf_dout <= #1 ch20_csr;
8'ha9: wb_rf_dout <= #1 ch20_txsz;
8'haa: wb_rf_dout <= #1 ch20_adr0;
511,7 → 516,7
8'haf: wb_rf_dout <= #1 sw_pointer20;
`endif
 
`ifdef HAVE_CH21
`ifdef WDMA_HAVE_CH21
8'hb0: wb_rf_dout <= #1 ch21_csr;
8'hb1: wb_rf_dout <= #1 ch21_txsz;
8'hb2: wb_rf_dout <= #1 ch21_adr0;
522,7 → 527,7
8'hb7: wb_rf_dout <= #1 sw_pointer21;
`endif
 
`ifdef HAVE_CH22
`ifdef WDMA_HAVE_CH22
8'hb8: wb_rf_dout <= #1 ch22_csr;
8'hb9: wb_rf_dout <= #1 ch22_txsz;
8'hba: wb_rf_dout <= #1 ch22_adr0;
533,7 → 538,7
8'hbf: wb_rf_dout <= #1 sw_pointer22;
`endif
 
`ifdef HAVE_CH23
`ifdef WDMA_HAVE_CH23
8'hc0: wb_rf_dout <= #1 ch23_csr;
8'hc1: wb_rf_dout <= #1 ch23_txsz;
8'hc2: wb_rf_dout <= #1 ch23_adr0;
544,7 → 549,7
8'hc7: wb_rf_dout <= #1 sw_pointer23;
`endif
 
`ifdef HAVE_CH24
`ifdef WDMA_HAVE_CH24
8'hc8: wb_rf_dout <= #1 ch24_csr;
8'hc9: wb_rf_dout <= #1 ch24_txsz;
8'hca: wb_rf_dout <= #1 ch24_adr0;
555,7 → 560,7
8'hcf: wb_rf_dout <= #1 sw_pointer24;
`endif
 
`ifdef HAVE_CH25
`ifdef WDMA_HAVE_CH25
8'hd0: wb_rf_dout <= #1 ch25_csr;
8'hd1: wb_rf_dout <= #1 ch25_txsz;
8'hd2: wb_rf_dout <= #1 ch25_adr0;
566,7 → 571,7
8'hd7: wb_rf_dout <= #1 sw_pointer25;
`endif
 
`ifdef HAVE_CH26
`ifdef WDMA_HAVE_CH26
8'hd8: wb_rf_dout <= #1 ch26_csr;
8'hd9: wb_rf_dout <= #1 ch26_txsz;
8'hda: wb_rf_dout <= #1 ch26_adr0;
577,7 → 582,7
8'hdf: wb_rf_dout <= #1 sw_pointer26;
`endif
 
`ifdef HAVE_CH27
`ifdef WDMA_HAVE_CH27
8'he0: wb_rf_dout <= #1 ch27_csr;
8'he1: wb_rf_dout <= #1 ch27_txsz;
8'he2: wb_rf_dout <= #1 ch27_adr0;
588,7 → 593,7
8'he7: wb_rf_dout <= #1 sw_pointer27;
`endif
 
`ifdef HAVE_CH28
`ifdef WDMA_HAVE_CH28
8'he8: wb_rf_dout <= #1 ch28_csr;
8'he9: wb_rf_dout <= #1 ch28_txsz;
8'hea: wb_rf_dout <= #1 ch28_adr0;
599,7 → 604,7
8'hef: wb_rf_dout <= #1 sw_pointer28;
`endif
 
`ifdef HAVE_CH29
`ifdef WDMA_HAVE_CH29
8'hf0: wb_rf_dout <= #1 ch29_csr;
8'hf1: wb_rf_dout <= #1 ch29_txsz;
8'hf2: wb_rf_dout <= #1 ch29_adr0;
610,7 → 615,7
8'hf7: wb_rf_dout <= #1 sw_pointer29;
`endif
 
`ifdef HAVE_CH30
`ifdef WDMA_HAVE_CH30
8'hf8: wb_rf_dout <= #1 ch30_csr;
8'hf9: wb_rf_dout <= #1 ch30_txsz;
8'hfa: wb_rf_dout <= #1 ch30_adr0;
621,7 → 626,7
8'hff: wb_rf_dout <= #1 sw_pointer30;
`endif
 
`ifdef HAVE_CH31
`ifdef WDMA_HAVE_CH31
8'h100: wb_rf_dout <= #1 ch31_csr;
8'h101: wb_rf_dout <= #1 ch31_txsz;
8'h102: wb_rf_dout <= #1 ch31_adr0;
648,7 → 653,7
// ---------------------------------------------------
 
always @(posedge clk or negedge rst)
if(!rst) csr_r <= #1 0;
if(!rst) csr_r <= #1 8'h0;
else
if(csr_we) csr_r <= #1 wb_rf_din[7:0];
 
655,12 → 660,12
// ---------------------------------------------------
// INT_MASK
always @(posedge clk or negedge rst)
if(!rst) int_maska_r <= #1 0;
if(!rst) int_maska_r <= #1 31'h0;
else
if(int_maska_we) int_maska_r <= #1 wb_rf_din[30:0];
 
always @(posedge clk or negedge rst)
if(!rst) int_maskb_r <= #1 0;
if(!rst) int_maskb_r <= #1 31'h0;
else
if(int_maskb_we) int_maskb_r <= #1 wb_rf_din[30:0];
 
684,7 → 689,7
// Channel Register File
//
 
wb_dma_ch_rf #(0, `HAVE_ARS0, `HAVE_ED0, `HAVE_CBUF0) u0(
wb_dma_ch_rf #(0, `WDMA_HAVE_ARS0, `WDMA_HAVE_ED0, `WDMA_HAVE_CBUF0) u0(
.clk( clk ),
.rst( rst ),
.pointer( pointer0 ),
722,8 → 727,8
.ptr_set( ptr_set )
);
 
`ifdef HAVE_CH1
wb_dma_ch_rf #(1, `HAVE_ARS1, `HAVE_ED1, `HAVE_CBUF1) u1(
`ifdef WDMA_HAVE_CH1
wb_dma_ch_rf #(1, `WDMA_HAVE_ARS1, `WDMA_HAVE_ED1, `WDMA_HAVE_CBUF1) u1(
.clk( clk ),
.rst( rst ),
.pointer( pointer1 ),
761,7 → 766,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(1, `HAVE_ARS1, `HAVE_ED1, `HAVE_CBUF1) u1(
wb_dma_ch_rf_dummy #(1, `WDMA_HAVE_ARS1, `WDMA_HAVE_ED1, `WDMA_HAVE_CBUF1) u1(
.clk( clk ),
.rst( rst ),
.pointer( pointer1 ),
801,8 → 806,8
`endif
 
 
`ifdef HAVE_CH2
wb_dma_ch_rf #(2, `HAVE_ARS2, `HAVE_ED2, `HAVE_CBUF2) u2(
`ifdef WDMA_HAVE_CH2
wb_dma_ch_rf #(2, `WDMA_HAVE_ARS2, `WDMA_HAVE_ED2, `WDMA_HAVE_CBUF2) u2(
.clk( clk ),
.rst( rst ),
.pointer( pointer2 ),
840,7 → 845,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(2, `HAVE_ARS2, `HAVE_ED2, `HAVE_CBUF2) u2(
wb_dma_ch_rf_dummy #(2, `WDMA_HAVE_ARS2, `WDMA_HAVE_ED2, `WDMA_HAVE_CBUF2) u2(
.clk( clk ),
.rst( rst ),
.pointer( pointer2 ),
880,8 → 885,8
`endif
 
 
`ifdef HAVE_CH3
wb_dma_ch_rf #(3, `HAVE_ARS3, `HAVE_ED3, `HAVE_CBUF3) u3(
`ifdef WDMA_HAVE_CH3
wb_dma_ch_rf #(3, `WDMA_HAVE_ARS3, `WDMA_HAVE_ED3, `WDMA_HAVE_CBUF3) u3(
.clk( clk ),
.rst( rst ),
.pointer( pointer3 ),
919,7 → 924,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(3, `HAVE_ARS3, `HAVE_ED3, `HAVE_CBUF3) u3(
wb_dma_ch_rf_dummy #(3, `WDMA_HAVE_ARS3, `WDMA_HAVE_ED3, `WDMA_HAVE_CBUF3) u3(
.clk( clk ),
.rst( rst ),
.pointer( pointer3 ),
959,8 → 964,8
`endif
 
 
`ifdef HAVE_CH4
wb_dma_ch_rf #(4, `HAVE_ARS4, `HAVE_ED4, `HAVE_CBUF4) u4(
`ifdef WDMA_HAVE_CH4
wb_dma_ch_rf #(4, `WDMA_HAVE_ARS4, `WDMA_HAVE_ED4, `WDMA_HAVE_CBUF4) u4(
.clk( clk ),
.rst( rst ),
.pointer( pointer4 ),
998,7 → 1003,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(4, `HAVE_ARS4, `HAVE_ED4, `HAVE_CBUF4) u4(
wb_dma_ch_rf_dummy #(4, `WDMA_HAVE_ARS4, `WDMA_HAVE_ED4, `WDMA_HAVE_CBUF4) u4(
.clk( clk ),
.rst( rst ),
.pointer( pointer4 ),
1038,8 → 1043,8
`endif
 
 
`ifdef HAVE_CH5
wb_dma_ch_rf #(5, `HAVE_ARS5, `HAVE_ED5, `HAVE_CBUF5) u5(
`ifdef WDMA_HAVE_CH5
wb_dma_ch_rf #(5, `WDMA_HAVE_ARS5, `WDMA_HAVE_ED5, `WDMA_HAVE_CBUF5) u5(
.clk( clk ),
.rst( rst ),
.pointer( pointer5 ),
1077,7 → 1082,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(5, `HAVE_ARS5, `HAVE_ED5, `HAVE_CBUF5) u5(
wb_dma_ch_rf_dummy #(5, `WDMA_HAVE_ARS5, `WDMA_HAVE_ED5, `WDMA_HAVE_CBUF5) u5(
.clk( clk ),
.rst( rst ),
.pointer( pointer5 ),
1117,8 → 1122,8
`endif
 
 
`ifdef HAVE_CH6
wb_dma_ch_rf #(6, `HAVE_ARS6, `HAVE_ED6, `HAVE_CBUF6) u6(
`ifdef WDMA_HAVE_CH6
wb_dma_ch_rf #(6, `WDMA_HAVE_ARS6, `WDMA_HAVE_ED6, `WDMA_HAVE_CBUF6) u6(
.clk( clk ),
.rst( rst ),
.pointer( pointer6 ),
1156,7 → 1161,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(6, `HAVE_ARS6, `HAVE_ED6, `HAVE_CBUF6) u6(
wb_dma_ch_rf_dummy #(6, `WDMA_HAVE_ARS6, `WDMA_HAVE_ED6, `WDMA_HAVE_CBUF6) u6(
.clk( clk ),
.rst( rst ),
.pointer( pointer6 ),
1196,8 → 1201,8
`endif
 
 
`ifdef HAVE_CH7
wb_dma_ch_rf #(7, `HAVE_ARS7, `HAVE_ED7, `HAVE_CBUF7) u7(
`ifdef WDMA_HAVE_CH7
wb_dma_ch_rf #(7, `WDMA_HAVE_ARS7, `WDMA_HAVE_ED7, `WDMA_HAVE_CBUF7) u7(
.clk( clk ),
.rst( rst ),
.pointer( pointer7 ),
1235,7 → 1240,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(7, `HAVE_ARS7, `HAVE_ED7, `HAVE_CBUF7) u7(
wb_dma_ch_rf_dummy #(7, `WDMA_HAVE_ARS7, `WDMA_HAVE_ED7, `WDMA_HAVE_CBUF7) u7(
.clk( clk ),
.rst( rst ),
.pointer( pointer7 ),
1275,8 → 1280,8
`endif
 
 
`ifdef HAVE_CH8
wb_dma_ch_rf #(8, `HAVE_ARS8, `HAVE_ED8, `HAVE_CBUF8) u8(
`ifdef WDMA_HAVE_CH8
wb_dma_ch_rf #(8, `WDMA_HAVE_ARS8, `WDMA_HAVE_ED8, `WDMA_HAVE_CBUF8) u8(
.clk( clk ),
.rst( rst ),
.pointer( pointer8 ),
1314,7 → 1319,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(8, `HAVE_ARS8, `HAVE_ED8, `HAVE_CBUF8) u8(
wb_dma_ch_rf_dummy #(8, `WDMA_HAVE_ARS8, `WDMA_HAVE_ED8, `WDMA_HAVE_CBUF8) u8(
.clk( clk ),
.rst( rst ),
.pointer( pointer8 ),
1354,8 → 1359,8
`endif
 
 
`ifdef HAVE_CH9
wb_dma_ch_rf #(9, `HAVE_ARS9, `HAVE_ED9, `HAVE_CBUF9) u9(
`ifdef WDMA_HAVE_CH9
wb_dma_ch_rf #(9, `WDMA_HAVE_ARS9, `WDMA_HAVE_ED9, `WDMA_HAVE_CBUF9) u9(
.clk( clk ),
.rst( rst ),
.pointer( pointer9 ),
1393,7 → 1398,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(9, `HAVE_ARS9, `HAVE_ED9, `HAVE_CBUF9) u9(
wb_dma_ch_rf_dummy #(9, `WDMA_HAVE_ARS9, `WDMA_HAVE_ED9, `WDMA_HAVE_CBUF9) u9(
.clk( clk ),
.rst( rst ),
.pointer( pointer9 ),
1433,8 → 1438,8
`endif
 
 
`ifdef HAVE_CH10
wb_dma_ch_rf #(10, `HAVE_ARS10, `HAVE_ED10, `HAVE_CBUF10) u10(
`ifdef WDMA_HAVE_CH10
wb_dma_ch_rf #(10, `WDMA_HAVE_ARS10, `WDMA_HAVE_ED10, `WDMA_HAVE_CBUF10) u10(
.clk( clk ),
.rst( rst ),
.pointer( pointer10 ),
1472,7 → 1477,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(10, `HAVE_ARS10, `HAVE_ED10, `HAVE_CBUF10) u10(
wb_dma_ch_rf_dummy #(10, `WDMA_HAVE_ARS10, `WDMA_HAVE_ED10, `WDMA_HAVE_CBUF10) u10(
.clk( clk ),
.rst( rst ),
.pointer( pointer10 ),
1512,8 → 1517,8
`endif
 
 
`ifdef HAVE_CH11
wb_dma_ch_rf #(11, `HAVE_ARS11, `HAVE_ED11, `HAVE_CBUF11) u11(
`ifdef WDMA_HAVE_CH11
wb_dma_ch_rf #(11, `WDMA_HAVE_ARS11, `WDMA_HAVE_ED11, `WDMA_HAVE_CBUF11) u11(
.clk( clk ),
.rst( rst ),
.pointer( pointer11 ),
1551,7 → 1556,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(11, `HAVE_ARS11, `HAVE_ED11, `HAVE_CBUF11) u11(
wb_dma_ch_rf_dummy #(11, `WDMA_HAVE_ARS11, `WDMA_HAVE_ED11, `WDMA_HAVE_CBUF11) u11(
.clk( clk ),
.rst( rst ),
.pointer( pointer11 ),
1591,8 → 1596,8
`endif
 
 
`ifdef HAVE_CH12
wb_dma_ch_rf #(12, `HAVE_ARS12, `HAVE_ED12, `HAVE_CBUF12) u12(
`ifdef WDMA_HAVE_CH12
wb_dma_ch_rf #(12, `WDMA_HAVE_ARS12, `WDMA_HAVE_ED12, `WDMA_HAVE_CBUF12) u12(
.clk( clk ),
.rst( rst ),
.pointer( pointer12 ),
1630,7 → 1635,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(12, `HAVE_ARS12, `HAVE_ED12, `HAVE_CBUF12) u12(
wb_dma_ch_rf_dummy #(12, `WDMA_HAVE_ARS12, `WDMA_HAVE_ED12, `WDMA_HAVE_CBUF12) u12(
.clk( clk ),
.rst( rst ),
.pointer( pointer12 ),
1670,8 → 1675,8
`endif
 
 
`ifdef HAVE_CH13
wb_dma_ch_rf #(13, `HAVE_ARS13, `HAVE_ED13, `HAVE_CBUF13) u13(
`ifdef WDMA_HAVE_CH13
wb_dma_ch_rf #(13, `WDMA_HAVE_ARS13, `WDMA_HAVE_ED13, `WDMA_HAVE_CBUF13) u13(
.clk( clk ),
.rst( rst ),
.pointer( pointer13 ),
1709,7 → 1714,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(13, `HAVE_ARS13, `HAVE_ED13, `HAVE_CBUF13) u13(
wb_dma_ch_rf_dummy #(13, `WDMA_HAVE_ARS13, `WDMA_HAVE_ED13, `WDMA_HAVE_CBUF13) u13(
.clk( clk ),
.rst( rst ),
.pointer( pointer13 ),
1749,8 → 1754,8
`endif
 
 
`ifdef HAVE_CH14
wb_dma_ch_rf #(14, `HAVE_ARS14, `HAVE_ED14, `HAVE_CBUF14) u14(
`ifdef WDMA_HAVE_CH14
wb_dma_ch_rf #(14, `WDMA_HAVE_ARS14, `WDMA_HAVE_ED14, `WDMA_HAVE_CBUF14) u14(
.clk( clk ),
.rst( rst ),
.pointer( pointer14 ),
1788,7 → 1793,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(14, `HAVE_ARS14, `HAVE_ED14, `HAVE_CBUF14) u14(
wb_dma_ch_rf_dummy #(14, `WDMA_HAVE_ARS14, `WDMA_HAVE_ED14, `WDMA_HAVE_CBUF14) u14(
.clk( clk ),
.rst( rst ),
.pointer( pointer14 ),
1828,8 → 1833,8
`endif
 
 
`ifdef HAVE_CH15
wb_dma_ch_rf #(15, `HAVE_ARS15, `HAVE_ED15, `HAVE_CBUF15) u15(
`ifdef WDMA_HAVE_CH15
wb_dma_ch_rf #(15, `WDMA_HAVE_ARS15, `WDMA_HAVE_ED15, `WDMA_HAVE_CBUF15) u15(
.clk( clk ),
.rst( rst ),
.pointer( pointer15 ),
1867,7 → 1872,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(15, `HAVE_ARS15, `HAVE_ED15, `HAVE_CBUF15) u15(
wb_dma_ch_rf_dummy #(15, `WDMA_HAVE_ARS15, `WDMA_HAVE_ED15, `WDMA_HAVE_CBUF15) u15(
.clk( clk ),
.rst( rst ),
.pointer( pointer15 ),
1907,8 → 1912,8
`endif
 
 
`ifdef HAVE_CH16
wb_dma_ch_rf #(16, `HAVE_ARS16, `HAVE_ED16, `HAVE_CBUF16) u16(
`ifdef WDMA_HAVE_CH16
wb_dma_ch_rf #(16, `WDMA_HAVE_ARS16, `WDMA_HAVE_ED16, `WDMA_HAVE_CBUF16) u16(
.clk( clk ),
.rst( rst ),
.pointer( pointer16 ),
1946,7 → 1951,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(16, `HAVE_ARS16, `HAVE_ED16, `HAVE_CBUF16) u16(
wb_dma_ch_rf_dummy #(16, `WDMA_HAVE_ARS16, `WDMA_HAVE_ED16, `WDMA_HAVE_CBUF16) u16(
.clk( clk ),
.rst( rst ),
.pointer( pointer16 ),
1986,8 → 1991,8
`endif
 
 
`ifdef HAVE_CH17
wb_dma_ch_rf #(17, `HAVE_ARS17, `HAVE_ED17, `HAVE_CBUF17) u17(
`ifdef WDMA_HAVE_CH17
wb_dma_ch_rf #(17, `WDMA_HAVE_ARS17, `WDMA_HAVE_ED17, `WDMA_HAVE_CBUF17) u17(
.clk( clk ),
.rst( rst ),
.pointer( pointer17 ),
2025,7 → 2030,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(17, `HAVE_ARS17, `HAVE_ED17, `HAVE_CBUF17) u17(
wb_dma_ch_rf_dummy #(17, `WDMA_HAVE_ARS17, `WDMA_HAVE_ED17, `WDMA_HAVE_CBUF17) u17(
.clk( clk ),
.rst( rst ),
.pointer( pointer17 ),
2065,8 → 2070,8
`endif
 
 
`ifdef HAVE_CH18
wb_dma_ch_rf #(18, `HAVE_ARS18, `HAVE_ED18, `HAVE_CBUF18) u18(
`ifdef WDMA_HAVE_CH18
wb_dma_ch_rf #(18, `WDMA_HAVE_ARS18, `WDMA_HAVE_ED18, `WDMA_HAVE_CBUF18) u18(
.clk( clk ),
.rst( rst ),
.pointer( pointer18 ),
2104,7 → 2109,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(18, `HAVE_ARS18, `HAVE_ED18, `HAVE_CBUF18) u18(
wb_dma_ch_rf_dummy #(18, `WDMA_HAVE_ARS18, `WDMA_HAVE_ED18, `WDMA_HAVE_CBUF18) u18(
.clk( clk ),
.rst( rst ),
.pointer( pointer18 ),
2144,8 → 2149,8
`endif
 
 
`ifdef HAVE_CH19
wb_dma_ch_rf #(19, `HAVE_ARS19, `HAVE_ED19, `HAVE_CBUF19) u19(
`ifdef WDMA_HAVE_CH19
wb_dma_ch_rf #(19, `WDMA_HAVE_ARS19, `WDMA_HAVE_ED19, `WDMA_HAVE_CBUF19) u19(
.clk( clk ),
.rst( rst ),
.pointer( pointer19 ),
2183,7 → 2188,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(19, `HAVE_ARS19, `HAVE_ED19, `HAVE_CBUF19) u19(
wb_dma_ch_rf_dummy #(19, `WDMA_HAVE_ARS19, `WDMA_HAVE_ED19, `WDMA_HAVE_CBUF19) u19(
.clk( clk ),
.rst( rst ),
.pointer( pointer19 ),
2223,8 → 2228,8
`endif
 
 
`ifdef HAVE_CH20
wb_dma_ch_rf #(20, `HAVE_ARS20, `HAVE_ED20, `HAVE_CBUF20) u20(
`ifdef WDMA_HAVE_CH20
wb_dma_ch_rf #(20, `WDMA_HAVE_ARS20, `WDMA_HAVE_ED20, `WDMA_HAVE_CBUF20) u20(
.clk( clk ),
.rst( rst ),
.pointer( pointer20 ),
2262,7 → 2267,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(20, `HAVE_ARS20, `HAVE_ED20, `HAVE_CBUF20) u20(
wb_dma_ch_rf_dummy #(20, `WDMA_HAVE_ARS20, `WDMA_HAVE_ED20, `WDMA_HAVE_CBUF20) u20(
.clk( clk ),
.rst( rst ),
.pointer( pointer20 ),
2302,8 → 2307,8
`endif
 
 
`ifdef HAVE_CH21
wb_dma_ch_rf #(21, `HAVE_ARS21, `HAVE_ED21, `HAVE_CBUF21) u21(
`ifdef WDMA_HAVE_CH21
wb_dma_ch_rf #(21, `WDMA_HAVE_ARS21, `WDMA_HAVE_ED21, `WDMA_HAVE_CBUF21) u21(
.clk( clk ),
.rst( rst ),
.pointer( pointer21 ),
2341,7 → 2346,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(21, `HAVE_ARS21, `HAVE_ED21, `HAVE_CBUF21) u21(
wb_dma_ch_rf_dummy #(21, `WDMA_HAVE_ARS21, `WDMA_HAVE_ED21, `WDMA_HAVE_CBUF21) u21(
.clk( clk ),
.rst( rst ),
.pointer( pointer21 ),
2381,8 → 2386,8
`endif
 
 
`ifdef HAVE_CH22
wb_dma_ch_rf #(22, `HAVE_ARS22, `HAVE_ED22, `HAVE_CBUF22) u22(
`ifdef WDMA_HAVE_CH22
wb_dma_ch_rf #(22, `WDMA_HAVE_ARS22, `WDMA_HAVE_ED22, `WDMA_HAVE_CBUF22) u22(
.clk( clk ),
.rst( rst ),
.pointer( pointer22 ),
2420,7 → 2425,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(22, `HAVE_ARS22, `HAVE_ED22, `HAVE_CBUF22) u22(
wb_dma_ch_rf_dummy #(22, `WDMA_HAVE_ARS22, `WDMA_HAVE_ED22, `WDMA_HAVE_CBUF22) u22(
.clk( clk ),
.rst( rst ),
.pointer( pointer22 ),
2460,8 → 2465,8
`endif
 
 
`ifdef HAVE_CH23
wb_dma_ch_rf #(23, `HAVE_ARS23, `HAVE_ED23, `HAVE_CBUF23) u23(
`ifdef WDMA_HAVE_CH23
wb_dma_ch_rf #(23, `WDMA_HAVE_ARS23, `WDMA_HAVE_ED23, `WDMA_HAVE_CBUF23) u23(
.clk( clk ),
.rst( rst ),
.pointer( pointer23 ),
2499,7 → 2504,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(23, `HAVE_ARS23, `HAVE_ED23, `HAVE_CBUF23) u23(
wb_dma_ch_rf_dummy #(23, `WDMA_HAVE_ARS23, `WDMA_HAVE_ED23, `WDMA_HAVE_CBUF23) u23(
.clk( clk ),
.rst( rst ),
.pointer( pointer23 ),
2539,8 → 2544,8
`endif
 
 
`ifdef HAVE_CH24
wb_dma_ch_rf #(24, `HAVE_ARS24, `HAVE_ED24, `HAVE_CBUF24) u24(
`ifdef WDMA_HAVE_CH24
wb_dma_ch_rf #(24, `WDMA_HAVE_ARS24, `WDMA_HAVE_ED24, `WDMA_HAVE_CBUF24) u24(
.clk( clk ),
.rst( rst ),
.pointer( pointer24 ),
2578,7 → 2583,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(24, `HAVE_ARS24, `HAVE_ED24, `HAVE_CBUF24) u24(
wb_dma_ch_rf_dummy #(24, `WDMA_HAVE_ARS24, `WDMA_HAVE_ED24, `WDMA_HAVE_CBUF24) u24(
.clk( clk ),
.rst( rst ),
.pointer( pointer24 ),
2618,8 → 2623,8
`endif
 
 
`ifdef HAVE_CH25
wb_dma_ch_rf #(25, `HAVE_ARS25, `HAVE_ED25, `HAVE_CBUF25) u25(
`ifdef WDMA_HAVE_CH25
wb_dma_ch_rf #(25, `WDMA_HAVE_ARS25, `WDMA_HAVE_ED25, `WDMA_HAVE_CBUF25) u25(
.clk( clk ),
.rst( rst ),
.pointer( pointer25 ),
2657,7 → 2662,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(25, `HAVE_ARS25, `HAVE_ED25, `HAVE_CBUF25) u25(
wb_dma_ch_rf_dummy #(25, `WDMA_HAVE_ARS25, `WDMA_HAVE_ED25, `WDMA_HAVE_CBUF25) u25(
.clk( clk ),
.rst( rst ),
.pointer( pointer25 ),
2697,8 → 2702,8
`endif
 
 
`ifdef HAVE_CH26
wb_dma_ch_rf #(26, `HAVE_ARS26, `HAVE_ED26, `HAVE_CBUF26) u26(
`ifdef WDMA_HAVE_CH26
wb_dma_ch_rf #(26, `WDMA_HAVE_ARS26, `WDMA_HAVE_ED26, `WDMA_HAVE_CBUF26) u26(
.clk( clk ),
.rst( rst ),
.pointer( pointer26 ),
2736,7 → 2741,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(26, `HAVE_ARS26, `HAVE_ED26, `HAVE_CBUF26) u26(
wb_dma_ch_rf_dummy #(26, `WDMA_HAVE_ARS26, `WDMA_HAVE_ED26, `WDMA_HAVE_CBUF26) u26(
.clk( clk ),
.rst( rst ),
.pointer( pointer26 ),
2776,8 → 2781,8
`endif
 
 
`ifdef HAVE_CH27
wb_dma_ch_rf #(27, `HAVE_ARS27, `HAVE_ED27, `HAVE_CBUF27) u27(
`ifdef WDMA_HAVE_CH27
wb_dma_ch_rf #(27, `WDMA_HAVE_ARS27, `WDMA_HAVE_ED27, `WDMA_HAVE_CBUF27) u27(
.clk( clk ),
.rst( rst ),
.pointer( pointer27 ),
2815,7 → 2820,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(27, `HAVE_ARS27, `HAVE_ED27, `HAVE_CBUF27) u27(
wb_dma_ch_rf_dummy #(27, `WDMA_HAVE_ARS27, `WDMA_HAVE_ED27, `WDMA_HAVE_CBUF27) u27(
.clk( clk ),
.rst( rst ),
.pointer( pointer27 ),
2855,8 → 2860,8
`endif
 
 
`ifdef HAVE_CH28
wb_dma_ch_rf #(28, `HAVE_ARS28, `HAVE_ED28, `HAVE_CBUF28) u28(
`ifdef WDMA_HAVE_CH28
wb_dma_ch_rf #(28, `WDMA_HAVE_ARS28, `WDMA_HAVE_ED28, `WDMA_HAVE_CBUF28) u28(
.clk( clk ),
.rst( rst ),
.pointer( pointer28 ),
2894,7 → 2899,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(28, `HAVE_ARS28, `HAVE_ED28, `HAVE_CBUF28) u28(
wb_dma_ch_rf_dummy #(28, `WDMA_HAVE_ARS28, `WDMA_HAVE_ED28, `WDMA_HAVE_CBUF28) u28(
.clk( clk ),
.rst( rst ),
.pointer( pointer28 ),
2934,8 → 2939,8
`endif
 
 
`ifdef HAVE_CH29
wb_dma_ch_rf #(29, `HAVE_ARS29, `HAVE_ED29, `HAVE_CBUF29) u29(
`ifdef WDMA_HAVE_CH29
wb_dma_ch_rf #(29, `WDMA_HAVE_ARS29, `WDMA_HAVE_ED29, `WDMA_HAVE_CBUF29) u29(
.clk( clk ),
.rst( rst ),
.pointer( pointer29 ),
2973,7 → 2978,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(29, `HAVE_ARS29, `HAVE_ED29, `HAVE_CBUF29) u29(
wb_dma_ch_rf_dummy #(29, `WDMA_HAVE_ARS29, `WDMA_HAVE_ED29, `WDMA_HAVE_CBUF29) u29(
.clk( clk ),
.rst( rst ),
.pointer( pointer29 ),
3013,8 → 3018,8
`endif
 
 
`ifdef HAVE_CH30
wb_dma_ch_rf #(30, `HAVE_ARS30, `HAVE_ED30, `HAVE_CBUF30) u30(
`ifdef WDMA_HAVE_CH30
wb_dma_ch_rf #(30, `WDMA_HAVE_ARS30, `WDMA_HAVE_ED30, `WDMA_HAVE_CBUF30) u30(
.clk( clk ),
.rst( rst ),
.pointer( pointer30 ),
3052,7 → 3057,7
.ptr_set( ptr_set )
);
`else
wb_dma_ch_rf_dummy #(30, `HAVE_ARS30, `HAVE_ED30, `HAVE_CBUF30) u30(
wb_dma_ch_rf_dummy #(30, `WDMA_HAVE_ARS30, `WDMA_HAVE_ED30, `WDMA_HAVE_CBUF30) u30(
.clk( clk ),
.rst( rst ),
.pointer( pointer30 ),
/trunk/rtl/verilog/wb_dma_de.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_de.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: wb_dma_de.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.3 2001/06/13 02:26:48 rudi
//
//
232,7 → 238,7
wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable
wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable
wire ptr_valid = pointer[0];
wire use_ed = csr[`USE_ED];
wire use_ed = csr[`WDMA_USE_ED];
 
reg mast0_drdy_r;
reg paused;
480,7 → 486,7
begin
if(pause_req) next_state = PAUSE;
else
if(de_start & !csr[`ERR])
if(de_start & !csr[`WDMA_ERR])
begin
if(use_ed & !ptr_valid) next_state = LD_DESC1;
else next_state = READ;
527,7 → 533,7
de_txsz_we = 1'b1;
de_adr0_we = 1'b1;
de_adr1_we = 1'b1;
if(use_ed & csr[`WRB] & nd)
if(use_ed & csr[`WDMA_WRB] & nd)
begin
m0_we = 1'b1;
m0_go = 1'b1;
/trunk/rtl/verilog/wb_dma_pri_enc_sub.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_pri_enc_sub.v,v 1.1 2001-08-07 08:00:43 rudi Exp $
// $Id: wb_dma_pri_enc_sub.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-08-07 08:00:43 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,11 → 47,16
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/07 08:00:43 rudi
//
//
// Split up priority encoder modules to separate files
//
//
//
//
//
//
 
`include "wb_dma_defines.v"
 
67,7 → 72,7
 
reg [7:0] pri_out;
 
`ifdef PRI_8
`ifdef WDMA_PRI_8
always @(valid or pri_in)
if(!valid) pri_out = 8'b0000_0001;
else
86,7 → 91,7
if(pri_in==3'h6) pri_out = 8'b0100_0000;
else pri_out = 8'b1000_0000;
`else
`ifdef PRI_4
`ifdef WDMA_PRI_4
always @(valid or pri_in)
if(!valid) pri_out = 8'b0000_0001;
else
/trunk/rtl/verilog/wb_dma_ch_pri_enc.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_ch_pri_enc.v,v 1.2 2001-08-07 08:00:43 rudi Exp $
// $Id: wb_dma_ch_pri_enc.v,v 1.3 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-08-07 08:00:43 $
// $Revision: 1.2 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/07 08:00:43 rudi
//
//
// Split up priority encoder modules to separate files
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
110,7 → 115,7
wire [7:0] pri_out_tmp;
reg [2:0] pri_out;
 
`ifdef HAVE_CH1
`ifdef WDMA_HAVE_CH1
wb_dma_pri_enc_sub u0(
.valid( valid[0] ),
.pri_in( pri0 ),
127,7 → 132,7
assign pri1_out = 0;
`endif
 
`ifdef HAVE_CH2
`ifdef WDMA_HAVE_CH2
wb_dma_pri_enc_sub u2(
.valid( valid[2] ),
.pri_in( pri2 ),
137,7 → 142,7
assign pri2_out = 0;
`endif
 
`ifdef HAVE_CH3
`ifdef WDMA_HAVE_CH3
wb_dma_pri_enc_sub u3(
.valid( valid[3] ),
.pri_in( pri3 ),
147,7 → 152,7
assign pri3_out = 0;
`endif
 
`ifdef HAVE_CH4
`ifdef WDMA_HAVE_CH4
wb_dma_pri_enc_sub u4(
.valid( valid[4] ),
.pri_in( pri4 ),
157,7 → 162,7
assign pri4_out = 0;
`endif
 
`ifdef HAVE_CH5
`ifdef WDMA_HAVE_CH5
wb_dma_pri_enc_sub u5(
.valid( valid[5] ),
.pri_in( pri5 ),
167,7 → 172,7
assign pri5_out = 0;
`endif
 
`ifdef HAVE_CH6
`ifdef WDMA_HAVE_CH6
wb_dma_pri_enc_sub u6(
.valid( valid[6] ),
.pri_in( pri6 ),
177,7 → 182,7
assign pri6_out = 0;
`endif
 
`ifdef HAVE_CH7
`ifdef WDMA_HAVE_CH7
wb_dma_pri_enc_sub u7(
.valid( valid[7] ),
.pri_in( pri7 ),
187,7 → 192,7
assign pri7_out = 0;
`endif
 
`ifdef HAVE_CH8
`ifdef WDMA_HAVE_CH8
wb_dma_pri_enc_sub u8(
.valid( valid[8] ),
.pri_in( pri8 ),
197,7 → 202,7
assign pri8_out = 0;
`endif
 
`ifdef HAVE_CH9
`ifdef WDMA_HAVE_CH9
wb_dma_pri_enc_sub u9(
.valid( valid[9] ),
.pri_in( pri9 ),
207,7 → 212,7
assign pri9_out = 0;
`endif
 
`ifdef HAVE_CH10
`ifdef WDMA_HAVE_CH10
wb_dma_pri_enc_sub u10(
.valid( valid[10] ),
.pri_in( pri10 ),
217,7 → 222,7
assign pri10_out = 0;
`endif
 
`ifdef HAVE_CH11
`ifdef WDMA_HAVE_CH11
wb_dma_pri_enc_sub u11(
.valid( valid[11] ),
.pri_in( pri11 ),
227,7 → 232,7
assign pri11_out = 0;
`endif
 
`ifdef HAVE_CH12
`ifdef WDMA_HAVE_CH12
wb_dma_pri_enc_sub u12(
.valid( valid[12] ),
.pri_in( pri12 ),
237,7 → 242,7
assign pri12_out = 0;
`endif
 
`ifdef HAVE_CH13
`ifdef WDMA_HAVE_CH13
wb_dma_pri_enc_sub u13(
.valid( valid[13] ),
.pri_in( pri13 ),
247,7 → 252,7
assign pri13_out = 0;
`endif
 
`ifdef HAVE_CH14
`ifdef WDMA_HAVE_CH14
wb_dma_pri_enc_sub u14(
.valid( valid[14] ),
.pri_in( pri14 ),
257,7 → 262,7
assign pri14_out = 0;
`endif
 
`ifdef HAVE_CH15
`ifdef WDMA_HAVE_CH15
wb_dma_pri_enc_sub u15(
.valid( valid[15] ),
.pri_in( pri15 ),
267,7 → 272,7
assign pri15_out = 0;
`endif
 
`ifdef HAVE_CH16
`ifdef WDMA_HAVE_CH16
wb_dma_pri_enc_sub u16(
.valid( valid[16] ),
.pri_in( pri16 ),
277,7 → 282,7
assign pri16_out = 0;
`endif
 
`ifdef HAVE_CH17
`ifdef WDMA_HAVE_CH17
wb_dma_pri_enc_sub u17(
.valid( valid[17] ),
.pri_in( pri17 ),
287,7 → 292,7
assign pri17_out = 0;
`endif
 
`ifdef HAVE_CH18
`ifdef WDMA_HAVE_CH18
wb_dma_pri_enc_sub u18(
.valid( valid[18] ),
.pri_in( pri18 ),
297,7 → 302,7
assign pri18_out = 0;
`endif
 
`ifdef HAVE_CH19
`ifdef WDMA_HAVE_CH19
wb_dma_pri_enc_sub u19(
.valid( valid[19] ),
.pri_in( pri19 ),
307,7 → 312,7
assign pri19_out = 0;
`endif
 
`ifdef HAVE_CH20
`ifdef WDMA_HAVE_CH20
wb_dma_pri_enc_sub u20(
.valid( valid[20] ),
.pri_in( pri20 ),
317,7 → 322,7
assign pri20_out = 0;
`endif
 
`ifdef HAVE_CH21
`ifdef WDMA_HAVE_CH21
wb_dma_pri_enc_sub u21(
.valid( valid[21] ),
.pri_in( pri21 ),
327,7 → 332,7
assign pri21_out = 0;
`endif
 
`ifdef HAVE_CH22
`ifdef WDMA_HAVE_CH22
wb_dma_pri_enc_sub u22(
.valid( valid[22] ),
.pri_in( pri22 ),
337,7 → 342,7
assign pri22_out = 0;
`endif
 
`ifdef HAVE_CH23
`ifdef WDMA_HAVE_CH23
wb_dma_pri_enc_sub u23(
.valid( valid[23] ),
.pri_in( pri23 ),
347,7 → 352,7
assign pri23_out = 0;
`endif
 
`ifdef HAVE_CH24
`ifdef WDMA_HAVE_CH24
wb_dma_pri_enc_sub u24(
.valid( valid[24] ),
.pri_in( pri24 ),
357,7 → 362,7
assign pri24_out = 0;
`endif
 
`ifdef HAVE_CH25
`ifdef WDMA_HAVE_CH25
wb_dma_pri_enc_sub u25(
.valid( valid[25] ),
.pri_in( pri25 ),
367,7 → 372,7
assign pri25_out = 0;
`endif
 
`ifdef HAVE_CH26
`ifdef WDMA_HAVE_CH26
wb_dma_pri_enc_sub u26(
.valid( valid[26] ),
.pri_in( pri26 ),
377,7 → 382,7
assign pri26_out = 0;
`endif
 
`ifdef HAVE_CH27
`ifdef WDMA_HAVE_CH27
wb_dma_pri_enc_sub u27(
.valid( valid[27] ),
.pri_in( pri27 ),
387,7 → 392,7
assign pri27_out = 0;
`endif
 
`ifdef HAVE_CH28
`ifdef WDMA_HAVE_CH28
wb_dma_pri_enc_sub u28(
.valid( valid[28] ),
.pri_in( pri28 ),
397,7 → 402,7
assign pri28_out = 0;
`endif
 
`ifdef HAVE_CH29
`ifdef WDMA_HAVE_CH29
wb_dma_pri_enc_sub u29(
.valid( valid[29] ),
.pri_in( pri29 ),
407,7 → 412,7
assign pri29_out = 0;
`endif
 
`ifdef HAVE_CH30
`ifdef WDMA_HAVE_CH30
wb_dma_pri_enc_sub u30(
.valid( valid[30] ),
.pri_in( pri30 ),
427,7 → 432,7
pri28_out | pri29_out | pri30_out;
 
always @(posedge clk)
`ifdef PRI_8
`ifdef WDMA_PRI_8
if(pri_out_tmp[7]) pri_out <= #1 3'h7;
else
if(pri_out_tmp[6]) pri_out <= #1 3'h6;
441,7 → 446,7
if(pri_out_tmp[2]) pri_out <= #1 3'h2;
else
`endif
`ifdef PRI_4
`ifdef WDMA_PRI_4
if(pri_out_tmp[3]) pri_out <= #1 3'h3;
else
if(pri_out_tmp[2]) pri_out <= #1 3'h2;
/trunk/rtl/verilog/wb_dma_wb_slv.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_wb_slv.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: wb_dma_wb_slv.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
120,7 → 126,7
// Misc Logic
//
 
assign rf_sel = `REG_SEL ;
assign rf_sel = `WDMA_REG_SEL ;
 
////////////////////////////////////////////////////////////////////
//
/trunk/rtl/verilog/wb_dma_ch_sel.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_ch_sel.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: wb_dma_ch_sel.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.4 2001/06/14 08:52:00 rudi
//
//
236,7 → 242,7
// Aliases
//
 
`ifdef PRI_8
`ifdef WDMA_PRI_8
assign pri0 = ch0_csr[15:13];
assign pri1 = ch1_csr[15:13];
assign pri2 = ch2_csr[15:13];
269,7 → 275,7
assign pri29 = ch29_csr[15:13];
assign pri30 = ch30_csr[15:13];
`else
`ifdef PRI_4
`ifdef WDMA_PRI_4
assign pri0 = {1'b0, ch0_csr[14:13]};
assign pri1 = {1'b0, ch1_csr[14:13]};
assign pri2 = {1'b0, ch2_csr[14:13]};
350,37 → 356,37
always @(posedge clk)
req_r <= #1 req_i & ~ack_o;
 
assign valid[0] = ch0_csr[`CH_EN] & (ch0_csr[`MODE] ? (req_r[0] & !ack_o[0]) : 1'b1);
assign valid[1] = ch1_csr[`CH_EN] & (ch1_csr[`MODE] ? (req_r[1] & !ack_o[1]) : 1'b1);
assign valid[2] = ch2_csr[`CH_EN] & (ch2_csr[`MODE] ? (req_r[2] & !ack_o[2]) : 1'b1);
assign valid[3] = ch3_csr[`CH_EN] & (ch3_csr[`MODE] ? (req_r[3] & !ack_o[3]) : 1'b1);
assign valid[4] = ch4_csr[`CH_EN] & (ch4_csr[`MODE] ? (req_r[4] & !ack_o[4]) : 1'b1);
assign valid[5] = ch5_csr[`CH_EN] & (ch5_csr[`MODE] ? (req_r[5] & !ack_o[5]) : 1'b1);
assign valid[6] = ch6_csr[`CH_EN] & (ch6_csr[`MODE] ? (req_r[6] & !ack_o[6]) : 1'b1);
assign valid[7] = ch7_csr[`CH_EN] & (ch7_csr[`MODE] ? (req_r[7] & !ack_o[7]) : 1'b1);
assign valid[8] = ch8_csr[`CH_EN] & (ch8_csr[`MODE] ? (req_r[8] & !ack_o[8]) : 1'b1);
assign valid[9] = ch9_csr[`CH_EN] & (ch9_csr[`MODE] ? (req_r[9] & !ack_o[9]) : 1'b1);
assign valid[10] = ch10_csr[`CH_EN] & (ch10_csr[`MODE] ? (req_r[10] & !ack_o[10]) : 1'b1);
assign valid[11] = ch11_csr[`CH_EN] & (ch11_csr[`MODE] ? (req_r[11] & !ack_o[11]) : 1'b1);
assign valid[12] = ch12_csr[`CH_EN] & (ch12_csr[`MODE] ? (req_r[12] & !ack_o[12]) : 1'b1);
assign valid[13] = ch13_csr[`CH_EN] & (ch13_csr[`MODE] ? (req_r[13] & !ack_o[13]) : 1'b1);
assign valid[14] = ch14_csr[`CH_EN] & (ch14_csr[`MODE] ? (req_r[14] & !ack_o[14]) : 1'b1);
assign valid[15] = ch15_csr[`CH_EN] & (ch15_csr[`MODE] ? (req_r[15] & !ack_o[15]) : 1'b1);
assign valid[16] = ch16_csr[`CH_EN] & (ch16_csr[`MODE] ? (req_r[16] & !ack_o[16]) : 1'b1);
assign valid[17] = ch17_csr[`CH_EN] & (ch17_csr[`MODE] ? (req_r[17] & !ack_o[17]) : 1'b1);
assign valid[18] = ch18_csr[`CH_EN] & (ch18_csr[`MODE] ? (req_r[18] & !ack_o[18]) : 1'b1);
assign valid[19] = ch19_csr[`CH_EN] & (ch19_csr[`MODE] ? (req_r[19] & !ack_o[19]) : 1'b1);
assign valid[20] = ch20_csr[`CH_EN] & (ch20_csr[`MODE] ? (req_r[20] & !ack_o[20]) : 1'b1);
assign valid[21] = ch21_csr[`CH_EN] & (ch21_csr[`MODE] ? (req_r[21] & !ack_o[21]) : 1'b1);
assign valid[22] = ch22_csr[`CH_EN] & (ch22_csr[`MODE] ? (req_r[22] & !ack_o[22]) : 1'b1);
assign valid[23] = ch23_csr[`CH_EN] & (ch23_csr[`MODE] ? (req_r[23] & !ack_o[23]) : 1'b1);
assign valid[24] = ch24_csr[`CH_EN] & (ch24_csr[`MODE] ? (req_r[24] & !ack_o[24]) : 1'b1);
assign valid[25] = ch25_csr[`CH_EN] & (ch25_csr[`MODE] ? (req_r[25] & !ack_o[25]) : 1'b1);
assign valid[26] = ch26_csr[`CH_EN] & (ch26_csr[`MODE] ? (req_r[26] & !ack_o[26]) : 1'b1);
assign valid[27] = ch27_csr[`CH_EN] & (ch27_csr[`MODE] ? (req_r[27] & !ack_o[27]) : 1'b1);
assign valid[28] = ch28_csr[`CH_EN] & (ch28_csr[`MODE] ? (req_r[28] & !ack_o[28]) : 1'b1);
assign valid[29] = ch29_csr[`CH_EN] & (ch29_csr[`MODE] ? (req_r[29] & !ack_o[29]) : 1'b1);
assign valid[30] = ch30_csr[`CH_EN] & (ch30_csr[`MODE] ? (req_r[30] & !ack_o[30]) : 1'b1);
assign valid[0] = ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1);
assign valid[1] = ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1);
assign valid[2] = ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1);
assign valid[3] = ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1);
assign valid[4] = ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1);
assign valid[5] = ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1);
assign valid[6] = ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1);
assign valid[7] = ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1);
assign valid[8] = ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1);
assign valid[9] = ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1);
assign valid[10] = ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1);
assign valid[11] = ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1);
assign valid[12] = ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1);
assign valid[13] = ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1);
assign valid[14] = ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1);
assign valid[15] = ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1);
assign valid[16] = ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1);
assign valid[17] = ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1);
assign valid[18] = ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1);
assign valid[19] = ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1);
assign valid[20] = ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1);
assign valid[21] = ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1);
assign valid[22] = ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1);
assign valid[23] = ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1);
assign valid[24] = ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1);
assign valid[25] = ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1);
assign valid[26] = ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1);
assign valid[27] = ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1);
assign valid[28] = ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1);
assign valid[29] = ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1);
assign valid[30] = ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1);
 
always @(posedge clk)
ndr_r <= #1 nd_i & req_i;
399,97 → 405,97
 
// Ack outputs for HW handshake mode
always @(posedge clk)
ack_o[0] <= #1 (ch_sel == 5'h0) & ch0_csr[`MODE] & de_ack;
ack_o[0] <= #1 (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[1] <= #1 (ch_sel == 5'h1) & ch1_csr[`MODE] & de_ack;
ack_o[1] <= #1 (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[2] <= #1 (ch_sel == 5'h2) & ch2_csr[`MODE] & de_ack;
ack_o[2] <= #1 (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[3] <= #1 (ch_sel == 5'h3) & ch3_csr[`MODE] & de_ack;
ack_o[3] <= #1 (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[4] <= #1 (ch_sel == 5'h4) & ch4_csr[`MODE] & de_ack;
ack_o[4] <= #1 (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[5] <= #1 (ch_sel == 5'h5) & ch5_csr[`MODE] & de_ack;
ack_o[5] <= #1 (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[6] <= #1 (ch_sel == 5'h6) & ch6_csr[`MODE] & de_ack;
ack_o[6] <= #1 (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[7] <= #1 (ch_sel == 5'h7) & ch7_csr[`MODE] & de_ack;
ack_o[7] <= #1 (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[8] <= #1 (ch_sel == 5'h8) & ch8_csr[`MODE] & de_ack;
ack_o[8] <= #1 (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[9] <= #1 (ch_sel == 5'h9) & ch9_csr[`MODE] & de_ack;
ack_o[9] <= #1 (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[10] <= #1 (ch_sel == 5'ha) & ch10_csr[`MODE] & de_ack;
ack_o[10] <= #1 (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[11] <= #1 (ch_sel == 5'hb) & ch11_csr[`MODE] & de_ack;
ack_o[11] <= #1 (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[12] <= #1 (ch_sel == 5'hc) & ch12_csr[`MODE] & de_ack;
ack_o[12] <= #1 (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[13] <= #1 (ch_sel == 5'hd) & ch13_csr[`MODE] & de_ack;
ack_o[13] <= #1 (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[14] <= #1 (ch_sel == 5'he) & ch14_csr[`MODE] & de_ack;
ack_o[14] <= #1 (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[15] <= #1 (ch_sel == 5'hf) & ch15_csr[`MODE] & de_ack;
ack_o[15] <= #1 (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[16] <= #1 (ch_sel == 5'h10) & ch16_csr[`MODE] & de_ack;
ack_o[16] <= #1 (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[17] <= #1 (ch_sel == 5'h11) & ch17_csr[`MODE] & de_ack;
ack_o[17] <= #1 (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[18] <= #1 (ch_sel == 5'h12) & ch18_csr[`MODE] & de_ack;
ack_o[18] <= #1 (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[19] <= #1 (ch_sel == 5'h13) & ch19_csr[`MODE] & de_ack;
ack_o[19] <= #1 (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[20] <= #1 (ch_sel == 5'h14) & ch20_csr[`MODE] & de_ack;
ack_o[20] <= #1 (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[21] <= #1 (ch_sel == 5'h15) & ch21_csr[`MODE] & de_ack;
ack_o[21] <= #1 (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[22] <= #1 (ch_sel == 5'h16) & ch22_csr[`MODE] & de_ack;
ack_o[22] <= #1 (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[23] <= #1 (ch_sel == 5'h17) & ch23_csr[`MODE] & de_ack;
ack_o[23] <= #1 (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[24] <= #1 (ch_sel == 5'h18) & ch24_csr[`MODE] & de_ack;
ack_o[24] <= #1 (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[25] <= #1 (ch_sel == 5'h19) & ch25_csr[`MODE] & de_ack;
ack_o[25] <= #1 (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[26] <= #1 (ch_sel == 5'h1a) & ch26_csr[`MODE] & de_ack;
ack_o[26] <= #1 (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[27] <= #1 (ch_sel == 5'h1b) & ch27_csr[`MODE] & de_ack;
ack_o[27] <= #1 (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[28] <= #1 (ch_sel == 5'h1c) & ch28_csr[`MODE] & de_ack;
ack_o[28] <= #1 (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[29] <= #1 (ch_sel == 5'h1d) & ch29_csr[`MODE] & de_ack;
ack_o[29] <= #1 (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack;
 
always @(posedge clk)
ack_o[30] <= #1 (ch_sel == 5'h1e) & ch30_csr[`MODE] & de_ack;
ack_o[30] <= #1 (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack;
 
// Channel Select
always @(posedge clk or negedge rst)
1236,7 → 1242,7
.advance( next_ch )
);
 
`ifdef PRI_4
`ifdef WDMA_PRI_4
// RR Arbiter for priority 2
wb_dma_ch_arb u3(
.clk( clk ),
1255,7 → 1261,7
);
`endif
 
`ifdef PRI_8
`ifdef WDMA_PRI_8
// RR Arbiter for priority 2
wb_dma_ch_arb u3(
.clk( clk ),
1307,7 → 1313,7
`endif
 
// Ground unused outputs
`ifdef PRI_8
`ifdef WDMA_PRI_8
// Do nothing
`else
assign gnt_p4 = 0;
1314,7 → 1320,7
assign gnt_p5 = 0;
assign gnt_p6 = 0;
assign gnt_p7 = 0;
`ifdef PRI_4
`ifdef WDMA_PRI_4
// Do nothing
`else
assign gnt_p2 = 0;
/trunk/rtl/verilog/wb_dma_defines.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_defines.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: wb_dma_defines.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
65,147 → 71,148
`timescale 1ns / 10ps
 
// Identify how many channels are in this implementation
`define CH_COUNT 4
`define WDMA_CH_COUNT 4
 
`define HAVE_CH1 1
`define HAVE_CH2 1
`define HAVE_CH3 1
`define WDMA_HAVE_CH1 1
`define WDMA_HAVE_CH2 1
`define WDMA_HAVE_CH3 1
 
/*
`define HAVE_CH4 1
`define HAVE_CH5 1
`define HAVE_CH6 1
`define HAVE_CH7 1
`define HAVE_CH8 1
`define HAVE_CH9 1
`define HAVE_CH10 1
`define HAVE_CH11 1
`define HAVE_CH12 1
`define HAVE_CH13 1
`define HAVE_CH14 1
`define HAVE_CH15 1
`define HAVE_CH16 1
`define HAVE_CH17 1
`define HAVE_CH18 1
`define HAVE_CH19 1
`define HAVE_CH20 1
`define HAVE_CH21 1
`define HAVE_CH22 1
`define HAVE_CH23 1
`define HAVE_CH24 1
`define HAVE_CH25 1
`define HAVE_CH26 1
`define HAVE_CH27 1
`define HAVE_CH28 1
`define HAVE_CH29 1
`define HAVE_CH30 1
`define WDMA_HAVE_CH4 1
`define WDMA_HAVE_CH5 1
`define WDMA_HAVE_CH6 1
`define WDMA_HAVE_CH7 1
`define WDMA_HAVE_CH8 1
`define WDMA_HAVE_CH9 1
`define WDMA_HAVE_CH10 1
`define WDMA_HAVE_CH11 1
`define WDMA_HAVE_CH12 1
`define WDMA_HAVE_CH13 1
`define WDMA_HAVE_CH14 1
`define WDMA_HAVE_CH15 1
`define WDMA_HAVE_CH16 1
`define WDMA_HAVE_CH17 1
`define WDMA_HAVE_CH18 1
`define WDMA_HAVE_CH19 1
`define WDMA_HAVE_CH20 1
`define WDMA_HAVE_CH21 1
`define WDMA_HAVE_CH22 1
`define WDMA_HAVE_CH23 1
`define WDMA_HAVE_CH24 1
`define WDMA_HAVE_CH25 1
`define WDMA_HAVE_CH26 1
`define WDMA_HAVE_CH27 1
`define WDMA_HAVE_CH28 1
`define WDMA_HAVE_CH29 1
`define WDMA_HAVE_CH30 1
*/
 
`define HAVE_ARS0 1
`define HAVE_ARS1 1
`define HAVE_ARS2 1
`define HAVE_ARS3 1
`define HAVE_ARS4 1
`define HAVE_ARS5 1
`define HAVE_ARS6 1
`define HAVE_ARS7 1
`define HAVE_ARS8 1
`define HAVE_ARS9 1
`define HAVE_ARS10 1
`define HAVE_ARS11 1
`define HAVE_ARS12 1
`define HAVE_ARS13 1
`define HAVE_ARS14 1
`define HAVE_ARS15 1
`define HAVE_ARS16 1
`define HAVE_ARS17 1
`define HAVE_ARS18 1
`define HAVE_ARS19 1
`define HAVE_ARS20 1
`define HAVE_ARS21 1
`define HAVE_ARS22 1
`define HAVE_ARS23 1
`define HAVE_ARS24 1
`define HAVE_ARS25 1
`define HAVE_ARS26 1
`define HAVE_ARS27 1
`define HAVE_ARS28 1
`define HAVE_ARS29 1
`define HAVE_ARS30 1
`define WDMA_HAVE_ARS0 1
`define WDMA_HAVE_ARS1 1
`define WDMA_HAVE_ARS2 1
`define WDMA_HAVE_ARS3 1
`define WDMA_HAVE_ARS4 1
`define WDMA_HAVE_ARS5 1
`define WDMA_HAVE_ARS6 1
`define WDMA_HAVE_ARS7 1
`define WDMA_HAVE_ARS8 1
`define WDMA_HAVE_ARS9 1
`define WDMA_HAVE_ARS10 1
`define WDMA_HAVE_ARS11 1
`define WDMA_HAVE_ARS12 1
`define WDMA_HAVE_ARS13 1
`define WDMA_HAVE_ARS14 1
`define WDMA_HAVE_ARS15 1
`define WDMA_HAVE_ARS16 1
`define WDMA_HAVE_ARS17 1
`define WDMA_HAVE_ARS18 1
`define WDMA_HAVE_ARS19 1
`define WDMA_HAVE_ARS20 1
`define WDMA_HAVE_ARS21 1
`define WDMA_HAVE_ARS22 1
`define WDMA_HAVE_ARS23 1
`define WDMA_HAVE_ARS24 1
`define WDMA_HAVE_ARS25 1
`define WDMA_HAVE_ARS26 1
`define WDMA_HAVE_ARS27 1
`define WDMA_HAVE_ARS28 1
`define WDMA_HAVE_ARS29 1
`define WDMA_HAVE_ARS30 1
 
`define HAVE_ED0 1
`define HAVE_ED1 1
`define HAVE_ED2 1
`define HAVE_ED3 1
`define HAVE_ED4 1
`define HAVE_ED5 1
`define HAVE_ED6 1
`define HAVE_ED7 1
`define HAVE_ED8 1
`define HAVE_ED9 1
`define HAVE_ED10 1
`define HAVE_ED11 1
`define HAVE_ED12 1
`define HAVE_ED13 1
`define HAVE_ED14 1
`define HAVE_ED15 1
`define HAVE_ED16 1
`define HAVE_ED17 1
`define HAVE_ED18 1
`define HAVE_ED19 1
`define HAVE_ED20 1
`define HAVE_ED21 1
`define HAVE_ED22 1
`define HAVE_ED23 1
`define HAVE_ED24 1
`define HAVE_ED25 1
`define HAVE_ED26 1
`define HAVE_ED27 1
`define HAVE_ED28 1
`define HAVE_ED29 1
`define HAVE_ED30 1
`define WDMA_HAVE_ED0 1
`define WDMA_HAVE_ED1 1
`define WDMA_HAVE_ED2 1
`define WDMA_HAVE_ED3 1
`define WDMA_HAVE_ED4 1
`define WDMA_HAVE_ED5 1
`define WDMA_HAVE_ED6 1
`define WDMA_HAVE_ED7 1
`define WDMA_HAVE_ED8 1
`define WDMA_HAVE_ED9 1
`define WDMA_HAVE_ED10 1
`define WDMA_HAVE_ED11 1
`define WDMA_HAVE_ED12 1
`define WDMA_HAVE_ED13 1
`define WDMA_HAVE_ED14 1
`define WDMA_HAVE_ED15 1
`define WDMA_HAVE_ED16 1
`define WDMA_HAVE_ED17 1
`define WDMA_HAVE_ED18 1
`define WDMA_HAVE_ED19 1
`define WDMA_HAVE_ED20 1
`define WDMA_HAVE_ED21 1
`define WDMA_HAVE_ED22 1
`define WDMA_HAVE_ED23 1
`define WDMA_HAVE_ED24 1
`define WDMA_HAVE_ED25 1
`define WDMA_HAVE_ED26 1
`define WDMA_HAVE_ED27 1
`define WDMA_HAVE_ED28 1
`define WDMA_HAVE_ED29 1
`define WDMA_HAVE_ED30 1
 
`define HAVE_CBUF0 1
`define HAVE_CBUF1 1
`define HAVE_CBUF2 1
`define HAVE_CBUF3 1
`define HAVE_CBUF4 1
`define HAVE_CBUF5 1
`define HAVE_CBUF6 1
`define HAVE_CBUF7 1
`define HAVE_CBUF8 1
`define HAVE_CBUF9 1
`define HAVE_CBUF10 1
`define HAVE_CBUF11 1
`define HAVE_CBUF12 1
`define HAVE_CBUF13 1
`define HAVE_CBUF14 1
`define HAVE_CBUF15 1
`define HAVE_CBUF16 1
`define HAVE_CBUF17 1
`define HAVE_CBUF18 1
`define HAVE_CBUF19 1
`define HAVE_CBUF20 1
`define HAVE_CBUF21 1
`define HAVE_CBUF22 1
`define HAVE_CBUF23 1
`define HAVE_CBUF24 1
`define HAVE_CBUF25 1
`define HAVE_CBUF26 1
`define HAVE_CBUF27 1
`define HAVE_CBUF28 1
`define HAVE_CBUF29 1
`define HAVE_CBUF30 1
`define WDMA_HAVE_CBUF0 1
`define WDMA_HAVE_CBUF1 1
`define WDMA_HAVE_CBUF2 1
`define WDMA_HAVE_CBUF3 1
`define WDMA_HAVE_CBUF4 1
`define WDMA_HAVE_CBUF5 1
`define WDMA_HAVE_CBUF6 1
`define WDMA_HAVE_CBUF7 1
`define WDMA_HAVE_CBUF8 1
`define WDMA_HAVE_CBUF9 1
`define WDMA_HAVE_CBUF10 1
`define WDMA_HAVE_CBUF11 1
`define WDMA_HAVE_CBUF12 1
`define WDMA_HAVE_CBUF13 1
`define WDMA_HAVE_CBUF14 1
`define WDMA_HAVE_CBUF15 1
`define WDMA_HAVE_CBUF16 1
`define WDMA_HAVE_CBUF17 1
`define WDMA_HAVE_CBUF18 1
`define WDMA_HAVE_CBUF19 1
`define WDMA_HAVE_CBUF20 1
`define WDMA_HAVE_CBUF21 1
`define WDMA_HAVE_CBUF22 1
`define WDMA_HAVE_CBUF23 1
`define WDMA_HAVE_CBUF24 1
`define WDMA_HAVE_CBUF25 1
`define WDMA_HAVE_CBUF26 1
`define WDMA_HAVE_CBUF27 1
`define WDMA_HAVE_CBUF28 1
`define WDMA_HAVE_CBUF29 1
`define WDMA_HAVE_CBUF30 1
 
// The two define statements below select the number of priorities
// that the DMA engine supports.
// if PRI_8 is defined, 8 levels of priorities are supported. If PRI_4
// is defined then 4 levels of priorities are supported. If neither is
// defined then two levels of priorities are supported.
// PRI_4 and PRI_8 should never be both defined at the same time.
//`define PRI_8 1
`define PRI_4 1
// if WDMA_PRI_8 is defined, 8 levels of priorities are supported. If
// WDMA_PRI_4 is defined then 4 levels of priorities are supported.
// If neither is defined then two levels of priorities are supported.
// WDMA_PRI_4 and WDMA_PRI_8 should never be both defined at the same
// time.
 
//`define WDMA_PRI_8 1
`define WDMA_PRI_4 1
 
// This define selects how the slave interface determines if
// the internal register file or pass through mode are selected.
216,23 → 223,22
// the higher will be the initial delay when pass-through mode is selected.
// Here we look at the top 8 address bit. If they are all 1, the
// register file is selected. Use this with caution !!!
`define REG_SEL (wb_addr_i[31:24] == 8'hff)
`define WDMA_REG_SEL (wb_addr_i[31:24] == 8'hff)
 
 
// CSR Bits
`define CH_EN 0
`define DST_SEL 1
`define SRC_SEL 2
`define INC_DST 3
`define INC_SRC 4
`define MODE 5
`define ARS 6
`define USE_ED 7
`define WRB 8
`define STOP 9
`define BUSY 10
`define DONE 11
`define ERR 12
`define ED_EOL 20
`define WDMA_CH_EN 0
`define WDMA_DST_SEL 1
`define WDMA_SRC_SEL 2
`define WDMA_INC_DST 3
`define WDMA_INC_SRC 4
`define WDMA_MODE 5
`define WDMA_ARS 6
`define WDMA_USE_ED 7
`define WDMA_WRB 8
`define WDMA_STOP 9
`define WDMA_BUSY 10
`define WDMA_DONE 11
`define WDMA_ERR 12
`define WDMA_ED_EOL 20
 
 
/trunk/rtl/verilog/wb_dma_ch_rf.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_dma_ch_rf.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
// $Id: wb_dma_ch_rf.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
//
// $Date: 2001-07-29 08:57:02 $
// $Revision: 1.1 $
// $Date: 2001-08-15 05:40:30 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.3 2001/06/14 08:50:01 rudi
//
// Changed Module Name to match file name.
199,7 → 205,7
ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable};
assign ch_txsz = {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r};
 
assign ch_enable = ch_csr_r[0] & (HAVE_CBUF ? !ch_dis : 1'b1);
assign ch_enable = ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1);
 
////////////////////////////////////////////////////////////////////
//
219,7 → 225,7
assign sw_pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
 
assign ch_done_we = (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
(ch_csr[`USE_ED] ? ch_eol : !ch_csr[`ARS]);
(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
assign chunk_done_we = (ch_sel==CH_NO) & dma_done;
assign ch_err_we = (ch_sel==CH_NO) & dma_err;
assign ch_csr_dewe = de_csr_we & (ch_sel==CH_NO);
233,7 → 239,7
always @(posedge clk)
ch_rl <= #1 HAVE_ARS & (
(rest_en & dma_rest) |
((ch_sel==CH_NO) & dma_done_all & ch_csr[`ARS] & !ch_csr[`USE_ED])
((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
);
 
// ---------------------------------------------------
256,7 → 262,7
else
if(HAVE_ED)
begin
if(ch_csr_dewe) ch_eol <= #1 de_csr[`ED_EOL];
if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
else
if(ch_done_we) ch_eol <= #1 1'b0;
end
287,7 → 293,7
if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];
else
begin
if(ch_done_we) ch_csr_r[`CH_EN] <= #1 1'b0;
if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
end
 
295,7 → 301,7
always @(posedge clk or negedge rst)
if(!rst) ch_done <= #1 1'b0;
else
if(ch_csr_we) ch_done <= #1 !wb_rf_din[`CH_EN];
if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
else
if(ch_done_we) ch_done <= #1 1'b1;
 
305,7 → 311,7
 
// stop bit
always @(posedge clk)
ch_stop <= #1 ch_csr_we & wb_rf_din[`STOP];
ch_stop <= #1 ch_csr_we & wb_rf_din[`WDMA_STOP];
 
// error bit
always @(posedge clk or negedge rst)
371,13 → 377,7
{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
 
// txsz shadow register
/*
always @(posedge clk)
if((ch_txsz_we | (rest_en & ch_txsz_dewe & de_fetch_descr) )
& HAVE_ARS) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
*/
 
always @(posedge clk)
if(HAVE_ARS)
begin
 
387,9 → 387,6
ch_txsz_s[11:0] <= #1 de_txsz[11:0];
end
 
 
 
 
// Infinite Size indicator
always @(posedge clk)
if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];
404,13 → 401,7
if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;
 
// Adr0 shadow register
/*
always @(posedge clk)
if((ch_adr0_we | (rest_en & ch_adr0_dewe & de_fetch_descr) )
& HAVE_ARS) ch_adr0_s <= #1 wb_rf_din[31:2];
*/
 
always @(posedge clk)
if(HAVE_ARS)
begin
if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];
419,7 → 410,6
ch_adr0_s <= #1 de_adr0[31:2];
end
 
 
// ---------------------------------------------------
// AM0
always @(posedge clk or negedge rst)
437,13 → 427,7
if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;
 
// Adr1 shadow register
/*
always @(posedge clk)
if((ch_adr1_we | (rest_en & ch_adr1_dewe & de_fetch_descr) )
& HAVE_ARS) ch_adr1_s <= #1 wb_rf_din[31:2];
*/
 
always @(posedge clk)
if(HAVE_ARS)
begin
if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];
/trunk/doc/dma_doc.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/sim/rtl_sim/bin/Makefile
2,7 → 2,7
all: sim
 
SHELL = /bin/sh
MS="-s"
MS=-s
 
##########################################################################
#
58,12 → 58,12
$(_TARGETS_) $(_TB_)
 
simw:
@$(MAKE) -s sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES"
@$(MAKE) $(MS) sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES"
 
sim:
@echo ""
@echo "----- Running NCVLOG ... ----------"
$(MAKE) $(MS) vlog \
@$(MAKE) $(MS) vlog \
TARGETS="$(_TARGETS_)" \
TB="$(_TB_)" \
INCDIR=$(INCDIR) \
70,11 → 70,11
WAVES="$(WAVES)"
@echo ""
@echo "----- Running NCELAB ... ----------"
$(MAKE) $(MS) elab \
@$(MAKE) $(MS) elab \
ACCESS="$(ACCESS)" TOP=$(_TOP_)
@echo ""
@echo "----- Running NCSIM ... ----------"
$(MAKE) $(MS) ncsim TOP=$(_TOP_)
@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
@echo ""
 
hal:

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