URL
https://opencores.org/ocsvn/wb_prefetch_spram/wb_prefetch_spram/trunk
Subversion Repositories wb_prefetch_spram
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- This comparison shows the changes necessary to convert path
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- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/bench/verilog/tb_tasks.v
46,12 → 46,17
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
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`include "timescale.v" |
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module tb_tasks; |
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integer errors; |
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// |
// Tests description |
// |
96,7 → 101,8
$display("I. Initializing 1st half of the RAM: "); |
for (addr = 0; addr < `RAM_WORDS/2; addr = addr + 1) begin |
$write("w"); |
data = $random; |
// data = $random; |
data = addr; |
tb_top.wb_master.wr(addr, data, 4'b1111); |
end |
$display(" Done."); |
184,7 → 190,61
end |
endtask |
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// |
// Read and write same addresses in first half (to check for bug reported by Avi) |
// |
task read_write_1sthalf; |
reg [31:0] saddr; |
reg [31:0] daddr; |
reg [31:0] data [63:0]; |
reg [3:0] rndnum; |
reg [1:0] delay; |
reg [2:0] beats; |
integer start_time; |
integer end_time; |
begin |
$display; |
$display("III. Reading and writing same locations in the first half"); |
start_time = $time; |
for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr) begin |
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// |
// Read and write same locations. Beats are spaced with random delays. |
// |
rndnum = $random; |
if (rndnum == 0) |
delay = $random; |
else |
delay = 0; |
while (delay) |
@(posedge tb_top.clk) begin |
delay = delay - 1; |
$write("."); |
end |
$write("r"); |
tb_top.wb_master.rd(saddr, data[1]); |
daddr = saddr; |
$write("w"); |
tb_top.wb_master.wr(daddr, data[1], 4'b1111); |
$write("r"); |
tb_top.wb_master.rd(saddr, data[2]); |
if (data[1] != data[2]) begin |
$write("Read/Write/Read sequence performing accesses "); |
$write("to address %h failed. First read %h != second read %h", saddr, data[1], data[2]); |
errors = errors + 1; |
end |
saddr = saddr + 1; |
end |
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$display(" Done."); |
end_time = $time; |
$display; |
$display(" Clock cycles to complete copy: %d", (end_time - start_time) / (`Thper*2)); |
end |
endtask |
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// |
// Compare 1st half and 2nd half of the RAM and return result of the comparison |
// |
task comp_1stand2ndhalf; |
192,11 → 252,9
reg [31:0] sdata; |
reg [31:0] daddr; |
reg [31:0] ddata; |
integer errors; |
begin |
$display; |
$display("III. Comparing 1st half and 2nd half of the RAM."); |
errors = 0; |
for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr + 1) begin |
daddr = saddr + `RAM_WORDS/2; |
tb_top.wb_master.rd(saddr, sdata); |
227,7 → 285,9
#`Trst; |
describe_test; |
init_1sthalf; |
errors = 0; |
copy_1stto2ndhalf; |
read_write_1sthalf; |
comp_1stand2ndhalf; |
$finish; |
end |