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URL https://opencores.org/ocsvn/wishbone_bfm/wishbone_bfm/trunk

Subversion Repositories wishbone_bfm

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  • This comparison shows the changes necessary to convert path 
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    from Rev 7 to Rev 8
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  •

Rev 7 → Rev 8

/branches/avendor/rtl/io_package.vhd
119,6 → 119,26
);
 
-- ----------------------------------------------------------------------
-- to_nibble
-- ----------------------------------------------------------------------
-- usage to_nibble( slv ); -- convert 4 bit slv to a character
function to_nibble( s:std_logic_vector(3 downto 0)) return character;
 
 
-- ----------------------------------------------------------------------
-- to_hex
-- ----------------------------------------------------------------------
-- usage to_hex( slv ); -- convert a slv to a string
function to_hex( v:std_logic_vector) return string;
 
 
 
 
 
 
 
 
-- ----------------------------------------------------------------------
-- clock_wait
-- ----------------------------------------------------------------------
-- usage clock_wait( number of cycles, bus_record ); -- wait n number of clock cycles
165,7 → 185,7
-- usage rd_32 ( address, data , bus_record )-- read 32 bit data from a 32 bit address
procedure rd_32 (
constant address_data : in std_logic_vector( 31 downto 0);
signal read_data : out std_logic_vector( 31 downto 0);
variable read_data : out std_logic_vector( 31 downto 0);
signal bus_c : inout bus_cycle
);
 
184,8 → 204,48
package body io_pack is
-- -------------------------------------------------------------------------
 
-- ----------------------------------------------------------------------
-- to_nibble
-- ----------------------------------------------------------------------
-- usage to_nibble( slv ); -- convert 4 bit slv to a character
function to_nibble( s:std_logic_vector(3 downto 0)) return character is
begin
case s is
when "0000" => return '0';
when "0001" => return '1';
when "0010" => return '2';
when "0011" => return '3';
when "0100" => return '4';
when "0101" => return '5';
when "0110" => return '6';
when "0111" => return '7';
when "1000" => return '8';
when "1001" => return '9';
when "1010" => return 'A';
when "1011" => return 'B';
when "1100" => return 'C';
when "1101" => return 'D';
when "1110" => return 'E';
when "1111" => return 'F';
when others=> return '?';
end case;
end function to_nibble;
 
 
-- ----------------------------------------------------------------------
-- to_hex
-- ----------------------------------------------------------------------
-- usage to_hex( slv ); -- convert a slv to a string
function to_hex( v:std_logic_vector) return string is
constant c:std_logic_vector(v'length+3 downto 1) := "000" & to_x01(v);
begin
if v'length < 1 then return ""; end if;
return to_hex(c(v'length downto 5)) & to_nibble(c(4 downto 1));
end function to_hex;
 
 
 
-- ----------------------------------------------------------------------
-- clock_wait
-- ----------------------------------------------------------------------
-- usage clock_wait( number of cycles, bus_record ); -- wait n number of clock cycles
292,9 → 352,15
-- rd_32
-- ----------------------------------------------------------------------
-- usage rd_32 ( address, data , bus_record )-- read 32 bit data from a 32 bit address
--
-- Note: need read data to be a variable to be passed back to calling process;
-- If it's a signal, it's one delta out, and in the calling process
-- it will have the wrong value, the one after the clock !
--
 
procedure rd_32 (
constant address_data : in std_logic_vector( 31 downto 0);
signal read_data : out std_logic_vector( 31 downto 0);
variable read_data : out std_logic_vector( 31 downto 0);
signal bus_c : inout bus_cycle
) is
 
320,7 → 386,7
end loop;
 
read_data <= bus_c.dat_i;
read_data := bus_c.dat_i;
bus_c.c_type <= bus_idle;
bus_c.add_o <= ( others => '0');
bus_c.dat_o <= ( others => '0');
/branches/avendor/rtl/wb_master.vhd
69,6 → 69,8
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
 
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
 
105,7 → 107,6
-- --------------------------------------------------------------------
 
signal reset_int : std_logic;
signal slv_32 : std_logic_vector( 31 downto 0);
 
-- --------------------------------------------------------------------
begin
134,6 → 135,14
 
-- --------------------------------------------------------------------
test_loop : process
 
-- need to use variables to get 'data' down from the procedures,
-- if we used a signal, then we get the value after the clock edge,
-- which is not what we want, we need the value at the clock edge.
--
variable slv_32 : std_logic_vector( 31 downto 0);
 
 
begin
 
-- Wait 100 ns for global reset to finish
145,15 → 154,12
wb_init( bus_c); -- initalise wishbone bus
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
 
wr_32( x"8000_0001", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
 
rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
wr_32( x"8000_0004", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
 
wr_32( x"8000_0004", x"AA55_55AA", bus_c); -- write 32 bits address of 32 bit data
 
rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
report to_hex( slv_32);
 
 
clock_wait( 1, bus_c );
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
 

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