OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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    from Rev 70 to Rev 71
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Rev 70 → Rev 71

/neorv32/trunk/setups/radiant/UPduino_v3/.gitignore File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/system_pll/system_pll.ipx File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/system_pll/rtl/system_pll.v File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/README.md File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/neorv32_upduino_v3.pdc File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/neorv32_imem.ice40up_spram.vhd File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/source/impl_1.xcf File deleted
/neorv32/trunk/setups/radiant/UPduino_v3/neorv32_upduino_v3.rdf File deleted
/neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/neorv32_ProcessorTop_Test.vhd File deleted
/neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qpf File deleted
/neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/User_Components.ipx File deleted
/neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qsf File deleted \ No newline at end of file
/neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.sdc File deleted
/neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/figures/neorv32_platform_designer.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/figures/neorv32_platform_designer.png
neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/figures/neorv32_platform_designer.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/.gitignore =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/.gitignore (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/.gitignore (nonexistent) @@ -1,8 +0,0 @@ -/.qsys_edit -/db -/neorv32_test_qsys -/*.sopcinfo -/*.rpt -/output_files -/incremental_db -/*.qws Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/neorv32_test_qsys.qsys =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/neorv32_test_qsys.qsys (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/neorv32_test_qsys.qsys (nonexistent) @@ -1,232 +0,0 @@ - - - - - - - - - - - - - - - - - de0-nano-test-setup.qpf - - - - - - - - - - - - - - $${FILENAME}_access_test_mem - - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_ext_dmem - - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/README.md =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/README.md (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-qsys/README.md (nonexistent) @@ -1,51 +0,0 @@ -# NEORV32 Test Setup using the NEORV32 as a Nios II drop-in replacement - -This setup provides a very simple "demo setup" that uses the NEORV32 Qsys/Platform Designer component -so that the NEORV32 can be used as a drop-in replacement of the Nios II soft CPU from Intel. -The demo is running on the Terasic DE0-Nano FPGA Board. - -The design is based on the de0-nano-test-setup, but the NEORV32 cpu is added as a QSys/Platform Designer -component. As an example the DMEM is "external" and uses an Platform Designer SRAM block. - -![NEORV32 in Platform Designer](figures/neorv32_platform_designer.png) - -For details about the design and use of the NEORV32 as a Qsys/Platform Designer component please -look at the Qsys component files and documentation here [`NEORV32 Qsys Component`](../neorv32_qsys_component) - -It uses the simplified simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). - -* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) -* FPGA: Intel Cyclone-IV `EP4CE22F17C6N` -* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition) - - -### NEORV32 Configuration - -For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used -with a few exceptions: - -* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader -* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) -* Clock: 50MHz from on-board oscillator -* Reset: via on-board button "KEY0" -* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0") -* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header - * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4") - * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6") - -### FPGA Utilization - -``` -Total logic elements 4,064 / 22,320 ( 18 % ) -Total registers 1932 -Total pins 12 / 154 ( 8 % ) -Total virtual pins 0 -Total memory bits 230,400 / 608,256 ( 38 % ) -Embedded Multiplier 9-bit elements 0 / 132 ( 0 % ) -Total PLLs 0 / 4 ( 0 % ) -``` - - -## How To Run - -Open the Quartus project file, compile and upload to FPGA. \ No newline at end of file Index: neorv32/trunk/setups/quartus/de0-nano-test-setup/create_project.tcl =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup/create_project.tcl (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup/create_project.tcl (nonexistent) @@ -1,94 +0,0 @@ -# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file -# and modify the default clock frequency: set to 50MHz -set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd " -exec sh -c $shell_script - -# Copyright (C) 2020 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. - -# Quartus Prime: Generate Tcl File for Project -# File: de0_nano_test.tcl -# Generated on: Sat Apr 10 16:57:48 2021 - -# Load Quartus Prime Tcl Project package -package require ::quartus::project - -set need_to_close_project 0 -set make_assignments 1 - -# Check that the right project is open -if {[is_project_open]} { - if {[string compare $quartus(project) "de0-nano-test-setup"]} { - puts "Project de0-nano-test-setup is not open" - set make_assignments 0 - } -} else { - # Only open if not already open - if {[project_exists de0-nano-test-setup]} { - project_open -revision de0-nano-test-setup de0-nano-test-setup - } else { - project_new -revision de0-nano-test-setup de0-nano-test-setup - } - set need_to_close_project 1 -} - -# Make assignments -if {$make_assignments} { - set_global_assignment -name FAMILY "Cyclone IV E" - set_global_assignment -name DEVICE EP4CE22F17C6 - set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader - set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 - set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021" - set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" - set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files - set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 - set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - - # core VHDL files - set core_src_dir [glob ./../../../rtl/core/*.vhd] - foreach core_src_file $core_src_dir { - set_global_assignment -name VHDL_FILE $core_src_file -library neorv32 - } - set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32 - set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32 - - # top entity: use local modified copy of the original test setup - set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd" - - set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" - set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - set_location_assignment PIN_R8 -to clk_i - set_location_assignment PIN_L3 -to gpio_o[7] - set_location_assignment PIN_B1 -to gpio_o[6] - set_location_assignment PIN_F3 -to gpio_o[5] - set_location_assignment PIN_D1 -to gpio_o[4] - set_location_assignment PIN_A11 -to gpio_o[3] - set_location_assignment PIN_B13 -to gpio_o[2] - set_location_assignment PIN_A13 -to gpio_o[1] - set_location_assignment PIN_A15 -to gpio_o[0] - set_location_assignment PIN_J15 -to rstn_i - set_location_assignment PIN_C3 -to uart0_txd_o - set_location_assignment PIN_A3 -to uart0_rxd_i - - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # Commit assignments - export_assignments -} Index: neorv32/trunk/setups/quartus/de0-nano-test-setup/README.md =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup/README.md (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup/README.md (nonexistent) @@ -1,62 +0,0 @@ -# NEORV32 Test Setup for the Terasic DE0-Nano FPGA Board - -This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic DE0-Nano board. -It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor -top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). - -* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) -* FPGA: Intel Cyclone-IV `EP4CE22F17C6N` -* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition) - - -### NEORV32 Configuration - -:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for -configuration and entity details and `create_project.tcl` for the according FPGA pin mapping. - -* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide) -* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM -* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` -* Tested with version [`1.5.7.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) -* Clock: 50MHz from on-board oscillator -* Reset: via on-board button "KEY0" -* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0") -* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header - * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4") - * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6") - -:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity -is configured for a 100MHz input clock. Since the on-board oscillator of the DE0-nano board generates a 50MHz clock, the test setup has to be modified. -This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file -(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual -top entity. - -### FPGA Utilization - -``` -Total logic elements 4,009 / 22,320 ( 18 % ) -Total registers 1860 -Total pins 12 / 154 ( 8 % ) -Total virtual pins 0 -Total memory bits 230,400 / 608,256 ( 38 % ) -Embedded Multiplier 9-bit elements 0 / 132 ( 0 % ) -Total PLLs 0 / 4 ( 0 % ) -``` - - -## How To Run - -The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project. -If not already available, this script will create a `work` folder in this directory. - -1. start Quartus (in GUI mode) -2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console -3. use the console to naviagte to **this** folder: `cd .../neorv32/boards/de0-nano-test-setup` -4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder -5. if a "select family" prompt appears select the "Cyclone IV E" family and click OK -6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream -7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA -8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: -19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline) -9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) -and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources. Index: neorv32/trunk/setups/quartus/de0-nano-test-setup/.gitignore =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup/.gitignore (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup/.gitignore (nonexistent) @@ -1,7 +0,0 @@ -db -incremental_db -output_files -*.qpf -*.qsf -*.qws -*.vhd Index: neorv32/trunk/setups/quartus/neorv32_qsys_component/README.md =================================================================== --- neorv32/trunk/setups/quartus/neorv32_qsys_component/README.md (revision 70) +++ neorv32/trunk/setups/quartus/neorv32_qsys_component/README.md (nonexistent) @@ -1,73 +0,0 @@ -# NEORV32 Platform Designer Component - -This folder contains a Qsys/Platform Designer wrapper for the NEORV32 together with -an Wishbone to AvalonMM bridge. This makes the NEORV32 a drop-in replacement for the -Altera/Intel Nios II soft CPU. - -This is just a quick template showing a possible solution, and not a feature complete -solution. All parameters in the Generic section could be added to the GUI. - -Only some peripherals (UART0, UART1 and GPIO) are connected, but other peripheral -could easily be connected. - -## Solution overview - -The solution is made up of 3 files. One VHDL file for the component implementation -(neorv32_qsys.vhd), one file for the Qsys component (neorv32_qsys_hw.tcl) and one file -listing files to include (neorv32_qsys.qip) to simplify the Quartus setup (.qsf) file. -The figure below shows how the component is implemented. - -![NEORV32 Qsys Component Solution](figures/overview.png) - -## GUI Settings - -The Qsys component is created so that some parameters can be set in the Platform Design -GUI. More settings could be added as needed. - -![NEORV32 GUI Settings](figures/gui_settings.png) - -## Implementation notes - -The Platform Designer has a bug (feature?) that makes boolean parameters from the Platform -Designer GUI being port mapped to the VHDL component generic as 0/1 instead of true/false. -This is a known bug/feature. - -A workaround for this is made by making the generic (boolean) parameters in the VHDL -as "integer", and then use a "integer2bool" function to make the parameter boolean -again to fit the NEORV32 top. - -## How to use - -To use the Qsys component in your Platform Designer design, you will just need to -make a "User_Components.ipx" file in your Qsys folder, and reference this (rtl/system_integration/neorv32_qsys_component) folder. - -Example "User_Components.ipx" content: -``` - - - -``` - -You will also need to add 3 lines in your Quartus project file (QSF-file) in order to -get the correct source files. - -Example QSF-file info: -``` -...... -set_global_assignment -name QIP_FILE ../neorv32_qsys_component/neorv32_qsys.qip -set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_application_image.vhd -set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_bootloader_image.vhd -...... -``` - -Having seperate links for the bootloader and application images makes it easy to include images -from your own project folders. - -# NEORV32 Platform Designer Component - Example Design - -The branch contains an example design using the Qsys/Platform designer component -and running on the DE0 Nano board. - -The example design can be found here [setups/quartus/de0-nano-test-setup-qsys`](../de0-nano-test-setup-qsys) - -The example design will run the software examples. Index: neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys_hw.tcl =================================================================== --- neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys_hw.tcl (revision 70) +++ neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys_hw.tcl (nonexistent) @@ -1,258 +0,0 @@ - -# -# request TCL package from ACDS 16.1 -# -package require -exact qsys 16.1 - -# -# module neorv32_qsys -# -set_module_property DESCRIPTION "NEORV32 RISC-V CPU" -set_module_property NAME neorv32_qsys -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property GROUP "NEORV32" -set_module_property AUTHOR "Stephan Nolting" -set_module_property DISPLAY_NAME "NEORV32 CPU" -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE false -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false -set_module_property REPORT_HIERARCHY false -set_module_property ELABORATION_CALLBACK elaborate - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL neorv32_qsys -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file neorv32_qsys.vhd VHDL PATH neorv32_qsys.vhd TOP_LEVEL_FILE - -# -# parameters -# -#add_parameter src_id INTEGER 1 "" -#set_parameter_property src_id DEFAULT_VALUE 1 -#set_parameter_property src_id DISPLAY_NAME src_id -#set_parameter_property src_id WIDTH "" -#set_parameter_property src_id TYPE INTEGER -#set_parameter_property src_id UNITS None -#set_parameter_property src_id ALLOWED_RANGES 1:15 -#set_parameter_property src_id DESCRIPTION "Input source ID" -#set_parameter_property src_id HDL_PARAMETER true - -add_parameter GUI_CLOCK_FREQUENCY INTEGER 100000000 -set_parameter_property GUI_CLOCK_FREQUENCY DISPLAY_NAME "CPU Clock Frequency" -set_parameter_property GUI_CLOCK_FREQUENCY DISPLAY_UNITS "Hz" -set_parameter_property GUI_CLOCK_FREQUENCY DESCRIPTION "CPU clock frequency" -set_parameter_property GUI_CLOCK_FREQUENCY ALLOWED_RANGES 1000000:250000000 -set_parameter_property GUI_CLOCK_FREQUENCY GROUP "Core" -set_parameter_property GUI_CLOCK_FREQUENCY HDL_PARAMETER true - -add_parameter GUI_EMABLE_INTERNAL_IMEM BOOLEAN true -set_parameter_property GUI_EMABLE_INTERNAL_IMEM DISPLAY_NAME "Enable Internal IMEM" -set_parameter_property GUI_EMABLE_INTERNAL_IMEM DESCRIPTION "Use interal IMEM" -set_parameter_property GUI_EMABLE_INTERNAL_IMEM GROUP "Core" -set_parameter_property GUI_EMABLE_INTERNAL_IMEM HDL_PARAMETER true - -add_parameter GUI_IMEM_SIZE INTEGER 16 -set_parameter_property GUI_IMEM_SIZE DISPLAY_NAME "Internal IMEM Memory Size" -set_parameter_property GUI_IMEM_SIZE DISPLAY_UNITS "KBytes" -set_parameter_property GUI_IMEM_SIZE DESCRIPTION "Size of IMEM instruction memory" -set_parameter_property GUI_IMEM_SIZE ALLOWED_RANGES {4 8 16 32 64} -set_parameter_property GUI_IMEM_SIZE GROUP "Core" -set_parameter_property GUI_IMEM_SIZE HDL_PARAMETER true - -add_parameter GUI_EMABLE_INTERNAL_DMEM BOOLEAN true -set_parameter_property GUI_EMABLE_INTERNAL_DMEM DISPLAY_NAME "Enable Internal DMEM" -set_parameter_property GUI_EMABLE_INTERNAL_DMEM DESCRIPTION "Use interal DMEM" -set_parameter_property GUI_EMABLE_INTERNAL_DMEM GROUP "Core" -set_parameter_property GUI_EMABLE_INTERNAL_DMEM HDL_PARAMETER true - -add_parameter GUI_DMEM_SIZE INTEGER 8 -set_parameter_property GUI_DMEM_SIZE DISPLAY_NAME "Internal DMEM Memory Size" -set_parameter_property GUI_DMEM_SIZE DISPLAY_UNITS "KBytes" -set_parameter_property GUI_DMEM_SIZE DESCRIPTION "Size of DMEM data memory" -set_parameter_property GUI_DMEM_SIZE ALLOWED_RANGES {2 4 8 16 32 64} -set_parameter_property GUI_DMEM_SIZE GROUP "Core" -set_parameter_property GUI_DMEM_SIZE HDL_PARAMETER true - - -add_parameter GUI_ENABLE_BOOTLOADER BOOLEAN false -set_parameter_property GUI_ENABLE_BOOTLOADER DISPLAY_NAME "Enable Bootloader" -set_parameter_property GUI_ENABLE_BOOTLOADER DESCRIPTION "Add bootloader and start bootloader" -set_parameter_property GUI_ENABLE_BOOTLOADER GROUP "Bootloader" -set_parameter_property GUI_ENABLE_BOOTLOADER HDL_PARAMETER true - - -add_parameter GUI_ENABLE_AVALONMM BOOLEAN true -set_parameter_property GUI_ENABLE_AVALONMM DISPLAY_NAME "Enable AvalonMM Interface" -set_parameter_property GUI_ENABLE_AVALONMM DESCRIPTION "Add AvalonMM Interface for external modules" -set_parameter_property GUI_ENABLE_AVALONMM GROUP "Peripheral" -set_parameter_property GUI_ENABLE_AVALONMM HDL_PARAMETER true - -add_parameter GUI_ENABLE_UART0 BOOLEAN true -set_parameter_property GUI_ENABLE_UART0 DISPLAY_NAME "Enable UART0" -set_parameter_property GUI_ENABLE_UART0 DESCRIPTION "Add UART0 to core" -set_parameter_property GUI_ENABLE_UART0 GROUP "Peripheral" -set_parameter_property GUI_ENABLE_UART0 HDL_PARAMETER true - -add_parameter GUI_ENABLE_UART1 BOOLEAN false -set_parameter_property GUI_ENABLE_UART1 DISPLAY_NAME "Enable UART1" -set_parameter_property GUI_ENABLE_UART1 DESCRIPTION "Add UART1 to core" -set_parameter_property GUI_ENABLE_UART1 GROUP "Peripheral" -set_parameter_property GUI_ENABLE_UART1 HDL_PARAMETER true - -add_parameter GUI_ENABLE_GPIO BOOLEAN false -set_parameter_property GUI_ENABLE_GPIO DISPLAY_NAME "Enable GPIO" -set_parameter_property GUI_ENABLE_GPIO DESCRIPTION "Add GPIO to core" -set_parameter_property GUI_ENABLE_GPIO GROUP "Peripheral" -set_parameter_property GUI_ENABLE_GPIO HDL_PARAMETER true - - - -# -# display items -# - - -# -# connection point clk -# -add_interface clk clock end -set_interface_property clk clockRate 0 -set_interface_property clk ENABLED true -set_interface_property clk EXPORT_OF "" -set_interface_property clk PORT_NAME_MAP "" -set_interface_property clk CMSIS_SVD_VARIABLES "" -set_interface_property clk SVD_ADDRESS_GROUP "" - -add_interface_port clk clk_i clk Input 1 - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clk -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset CMSIS_SVD_VARIABLES "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset rstn_i reset_n Input 1 - -# -# connection point perf_gpio -# -add_interface perf_gpio conduit end -set_interface_property perf_gpio associatedClock none -set_interface_property perf_gpio associatedReset none -set_interface_property perf_gpio ENABLED true -set_interface_property perf_gpio EXPORT_OF "" -set_interface_property perf_gpio PORT_NAME_MAP "" -set_interface_property perf_gpio CMSIS_SVD_VARIABLES "" -set_interface_property perf_gpio SVD_ADDRESS_GROUP "" - -add_interface_port perf_gpio gpio_o gpio_o Output 64 -add_interface_port perf_gpio gpio_i gpio_i Input 64 - -# -# connection point perf_uart0 -# -add_interface perf_uart0 conduit end -set_interface_property perf_uart0 associatedClock none -set_interface_property perf_uart0 associatedReset none -set_interface_property perf_uart0 ENABLED true -set_interface_property perf_uart0 EXPORT_OF "" -set_interface_property perf_uart0 PORT_NAME_MAP "" -set_interface_property perf_uart0 CMSIS_SVD_VARIABLES "" -set_interface_property perf_uart0 SVD_ADDRESS_GROUP "" - -add_interface_port perf_uart0 uart0_txd_o uart0_txd_o Output 1 -add_interface_port perf_uart0 uart0_rxd_i uart0_rxd_i Input 1 - -# -# connection point perf_uart1 -# -add_interface perf_uart1 conduit end -set_interface_property perf_uart1 associatedClock none -set_interface_property perf_uart1 associatedReset none -set_interface_property perf_uart1 ENABLED true -set_interface_property perf_uart1 EXPORT_OF "" -set_interface_property perf_uart1 PORT_NAME_MAP "" -set_interface_property perf_uart1 CMSIS_SVD_VARIABLES "" -set_interface_property perf_uart1 SVD_ADDRESS_GROUP "" - -add_interface_port perf_uart1 uart1_txd_o uart1_txd_o Output 1 -add_interface_port perf_uart1 uart1_rxd_i uart1_rxd_i Input 1 - -# -# connection point master -# -add_interface master avalon start -set_interface_property master addressUnits SYMBOLS -set_interface_property master associatedClock clk -set_interface_property master associatedReset reset -set_interface_property master bitsPerSymbol 8 -set_interface_property master burstOnBurstBoundariesOnly false -set_interface_property master burstcountUnits WORDS -set_interface_property master doStreamReads false -set_interface_property master doStreamWrites false -set_interface_property master holdTime 0 -set_interface_property master linewrapBursts false -set_interface_property master maximumPendingReadTransactions 0 -set_interface_property master maximumPendingWriteTransactions 0 -set_interface_property master readLatency 0 -set_interface_property master readWaitTime 0 -set_interface_property master setupTime 0 -set_interface_property master timingUnits Cycles -set_interface_property master writeWaitTime 0 -set_interface_property master ENABLED true -set_interface_property master EXPORT_OF "" -set_interface_property master PORT_NAME_MAP "" -set_interface_property master CMSIS_SVD_VARIABLES "" -set_interface_property master SVD_ADDRESS_GROUP "" - -add_interface_port master address address Output 32 -add_interface_port master read read Output 1 -add_interface_port master write write Output 1 -add_interface_port master byteenable byteenable Output 4 -add_interface_port master writedata writedata Output 32 -add_interface_port master readdata readdata Input 32 -add_interface_port master waitrequest waitrequest Input 1 - -# Callback to enable/disable interface signals -proc elaborate {} { - - if { [get_parameter_value GUI_ENABLE_GPIO] == "false" } { - set_interface_property perf_gpio ENABLED false - } else { - set_interface_property perf_gpio ENABLED true - } - - if { [get_parameter_value GUI_ENABLE_UART0] == "false" } { - set_interface_property perf_uart0 ENABLED false - } else { - set_interface_property perf_uart0 ENABLED true - } - - if { [get_parameter_value GUI_ENABLE_UART1] == "false" } { - set_interface_property perf_uart1 ENABLED false - } else { - set_interface_property perf_uart1 ENABLED true - } - - if { [get_parameter_value GUI_ENABLE_AVALONMM] == "false" } { - set_interface_property master ENABLED false - } else { - set_interface_property master ENABLED true - } - -} - Index: neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd =================================================================== --- neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd (revision 70) +++ neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd (nonexistent) @@ -1,279 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Processor Top Qsys component with AvalonMM Compatible Master Interface >> # --- # ********************************************************************************************* # --- # (c) "NIOS-2", "Qsys", "Platform Designer" and "AvalonMM" are trademarks of Intel. # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library neorv32; -use neorv32.neorv32_package.all; - -entity neorv32_qsys is - generic ( - GUI_CLOCK_FREQUENCY : integer := 100000000; - GUI_EMABLE_INTERNAL_IMEM : integer := 1; - GUI_IMEM_SIZE : integer := 16; - GUI_EMABLE_INTERNAL_DMEM : integer := 1; - GUI_DMEM_SIZE : integer := 8; - GUI_ENABLE_BOOTLOADER : integer := 0; - GUI_ENABLE_AVALONMM : integer := 1; - GUI_ENABLE_UART0 : integer := 1; - GUI_ENABLE_UART1 : integer := 0; - GUI_ENABLE_GPIO : integer := 0 - ); - port ( - -- Global control -- - clk_i : in std_logic := '0'; -- global clock, rising edge - rstn_i : in std_logic := '0'; -- global reset, low-active, async - -- GPIO -- - gpio_o : out std_logic_vector(63 downto 0); -- parallel output - gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel output - -- UART0 -- - uart0_txd_o : out std_logic; -- UART0 send data - uart0_rxd_i : in std_logic := '0'; -- UART0 receive data - - -- UART1 -- - uart1_txd_o : out std_logic; -- UART0 send data - uart1_rxd_i : in std_logic := '0'; -- UART0 receive data - - -- AvalonMM interface - read : out std_logic; - write : out std_logic; - waitrequest : in std_logic := '0'; - byteenable : out std_logic_vector(3 downto 0); - address : out std_logic_vector(31 downto 0); - writedata : out std_logic_vector(31 downto 0); - readdata : in std_logic_vector(31 downto 0) := (others => '0') - - ); -end entity; - -architecture neorv32_qsys_rtl of neorv32_qsys is - -signal gpio_i_ulogic : std_ulogic_vector(63 downto 0); -signal gpio_o_ulogic : std_ulogic_vector(63 downto 0); - --- Wishbone bus interface (available if MEM_EXT_EN = true) -- -signal wb_tag_o : std_ulogic_vector(02 downto 0); -- request tag -signal wb_adr_o : std_ulogic_vector(31 downto 0); -- address -signal wb_dat_i : std_ulogic_vector(31 downto 0); -- read data -signal wb_dat_o : std_ulogic_vector(31 downto 0); -- write data -signal wb_we_o : std_ulogic; -- read/write -signal wb_sel_o : std_ulogic_vector(03 downto 0); -- byte enable -signal wb_stb_o : std_ulogic; -- strobe -signal wb_cyc_o : std_ulogic; -- valid cycle -signal wb_lock_o : std_ulogic; -- exclusive access request -signal wb_ack_i : std_ulogic; -- transfer acknowledge -signal wb_err_i : std_ulogic; -- transfer error - -signal reset : std_logic; - -function integer2bool(integer_value : integer := 0) return boolean is -begin - if integer_value = 0 then - return false; - else - return true; - end if; -end function; - -begin - - -- The Core Of The Problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_top_inst: neorv32_top - generic map ( - -- General -- - CLOCK_FREQUENCY => GUI_CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz - INT_BOOTLOADER_EN => integer2bool(GUI_ENABLE_BOOTLOADER), -- implement processor-internal bootloader? - HW_THREAD_ID => 0, -- hardware thread id (hartid) - -- On-Chip Debugger (OCD) -- - ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger - -- RISC-V CPU Extensions -- - CPU_EXTENSION_RISCV_A => false, -- implement atomic extension? - CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? - CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? - CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension? - CPU_EXTENSION_RISCV_U => true, -- implement user mode extension? - CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!) - CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? - CPU_EXTENSION_RISCV_Zifencei => false, -- implement instruction stream sync.? - CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension? - -- Extension Options -- - FAST_MUL_EN => false, -- use DSPs for M extension's multiplier - FAST_SHIFT_EN => false, -- use barrel shifter for shift operations - CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64) - CPU_IPB_ENTRIES => 2, -- entries is instruction prefetch buffer, has to be a power of 2 - -- Physical Memory Protection (PMP) -- - PMP_NUM_REGIONS => 0, -- number of regions (0..64) - PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes - -- Hardware Performance Monitors (HPM) -- - HPM_NUM_CNTS => 4, -- number of implemented HPM counters (0..29) - HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64) - -- Internal Instruction memory -- - MEM_INT_IMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_IMEM), -- implement processor-internal instruction memory - MEM_INT_IMEM_SIZE => GUI_IMEM_SIZE*1024, -- size of processor-internal instruction memory in bytes - -- Internal Data memory -- - MEM_INT_DMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_DMEM), -- implement processor-internal data memory - MEM_INT_DMEM_SIZE => GUI_DMEM_SIZE*1024, -- size of processor-internal data memory in bytes - -- Internal Cache memory -- - ICACHE_EN => false, -- implement instruction cache - ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2 - ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 - ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 - -- External memory interface -- - MEM_EXT_EN => integer2bool(GUI_ENABLE_AVALONMM), -- implement external memory bus interface? - MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) - MEM_EXT_PIPE_MODE => false, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode - MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian - MEM_EXT_ASYNC_RX => false, -- use register buffer for RX data when false - -- Stream link interface (SLINK) -- - SLINK_NUM_TX => 0, -- number of TX links (0..8) - SLINK_NUM_RX => 0, -- number of TX links (0..8) - SLINK_TX_FIFO => 1, -- TX fifo depth, has to be a power of two - SLINK_RX_FIFO => 1, -- RX fifo depth, has to be a power of two - -- External Interrupts Controller (XIRQ) -- - XIRQ_NUM_CH => 0, -- number of external IRQ channels (0..32) - XIRQ_TRIGGER_TYPE => (x"FFFFFFFF"), -- trigger type: 0=level, 1=edge - XIRQ_TRIGGER_POLARITY => (x"FFFFFFFF"), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge - -- Processor peripherals -- - IO_GPIO_EN => integer2bool(GUI_ENABLE_GPIO), -- implement general purpose input/output port unit (GPIO)? - IO_MTIME_EN => true, -- implement machine system timer (MTIME)? - IO_UART0_EN => integer2bool(GUI_ENABLE_UART0), -- implement primary universal asynchronous receiver/transmitter (UART0)? - IO_UART1_EN => integer2bool(GUI_ENABLE_UART1), -- implement secondary universal asynchronous receiver/transmitter (UART1)? - IO_SPI_EN => false, -- implement serial peripheral interface (SPI)? - IO_TWI_EN => false, -- implement two-wire interface (TWI)? - IO_PWM_NUM_CH => 0, -- number of PWM channels to implement (0..60); 0 = disabled - IO_WDT_EN => true, -- implement watch dog timer (WDT)? - IO_TRNG_EN => false, -- implement true random number generator (TRNG)? - IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? - IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic - IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits - IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits - IO_NEOLED_EN => false, -- implement NeoPixel-compatible smart LED interface (NEOLED)? - IO_NEOLED_TX_FIFO => 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two - ) - port map ( - -- Global control -- - clk_i => clk_i, -- global clock, rising edge - rstn_i => rstn_i, -- global reset, low-active, async - -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- - jtag_trst_i => '0', -- low-active TAP reset (optional) - jtag_tck_i => '0', -- serial clock - jtag_tdi_i => '0', -- serial data input - jtag_tdo_o => open, -- serial data output - jtag_tms_i => '0', -- mode select - -- Wishbone bus interface (available if MEM_EXT_EN = true) -- - wb_tag_o => wb_tag_o, -- tag - wb_adr_o => wb_adr_o, -- address - wb_dat_i => wb_dat_i, -- read data - wb_dat_o => wb_dat_o, -- write data - wb_we_o => wb_we_o, -- read/write - wb_sel_o => wb_sel_o, -- byte enable - wb_stb_o => wb_stb_o, -- strobe - wb_cyc_o => wb_cyc_o, -- valid cycle - wb_lock_o => wb_lock_o, -- exclusive access request - wb_ack_i => wb_ack_i, -- transfer acknowledge - wb_err_i => wb_err_i, -- transfer error - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o => open, -- indicates an executed FENCE operation - fencei_o => open, -- indicates an executed FENCEI operation - -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- - slink_tx_dat_o => open, -- output data - slink_tx_val_o => open, -- valid output - slink_tx_rdy_i => (others => 'L'), -- ready to send - -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- - slink_rx_dat_i => (others => (others => 'U')), -- input data - slink_rx_val_i => (others => 'L'), -- valid input - slink_rx_rdy_o => open, -- ready to receive - - -- GPIO (available if IO_GPIO_EN = true) -- - gpio_o => gpio_o_ulogic, -- parallel output - gpio_i => gpio_i_ulogic, -- parallel input - -- primary UART0 (available if IO_UART0_EN = true) -- - uart0_txd_o => uart0_txd_o, -- UART0 send data - uart0_rxd_i => uart0_rxd_i, -- UART0 receive data - uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - -- secondary UART1 (available if IO_UART1_EN = true) -- - uart1_txd_o => uart1_txd_o, -- UART1 send data - uart1_rxd_i => uart1_rxd_i, -- UART1 receive data - uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional - uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional - -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o => open, -- SPI serial clock - spi_sdo_o => open, -- controller data out, peripheral data in - spi_sdi_i => '0', -- controller data in, peripheral data out - spi_csn_o => open, -- SPI CS - -- TWI (available if IO_TWI_EN = true) -- - twi_sda_io => open, -- twi serial data line - twi_scl_io => open, -- twi serial clock line - -- PWM (available if IO_PWM_NUM_CH > 0) -- - pwm_o => open, -- pwm channels - -- Custom Functions Subsystem IO -- - cfs_in_i => (others => '0'), -- custom inputs - cfs_out_o => open, -- custom outputs - -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- - neoled_o => open, -- async serial data line - -- System time -- - mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) - mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) - -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- - xirq_i => (others => '0'), -- IRQ channels - -- Interrupts -- - mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false - msw_irq_i => '0', -- machine software interrupt - mext_irq_i => '0' -- machine external interrupt - ); - - -- Convert between std_logic / std_ulogic - gpio_o <= std_logic_vector(gpio_o_ulogic); - gpio_i_ulogic <= std_ulogic_vector(gpio_i); - - reset <= not(rstn_i); - - -- Wishbone to AvalonMM brdige - read <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0'; - write <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0'; - address <= std_logic_vector(wb_adr_o); - writedata <= std_logic_vector(wb_dat_o); - byteenable <= std_logic_vector(wb_sel_o); - - wb_dat_i <= std_ulogic_vector(readdata); - wb_ack_i <= not(waitrequest); - wb_err_i <= '0'; - -end architecture; Index: neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/gui_settings.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/gui_settings.png =================================================================== --- neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/gui_settings.png (revision 70) +++ neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/gui_settings.png (nonexistent)
neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/gui_settings.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/overview.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/overview.png =================================================================== --- neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/overview.png (revision 70) +++ neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/overview.png (nonexistent)
neorv32/trunk/setups/quartus/neorv32_qsys_component/figures/overview.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys.qip =================================================================== --- neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys.qip (revision 70) +++ neorv32/trunk/setups/quartus/neorv32_qsys_component/neorv32_qsys.qip (nonexistent) @@ -1,33 +0,0 @@ -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_package.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_boot_rom.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_busswitch.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_bus_keeper.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cfs.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_alu.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_bus.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_control.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_fpu.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_muldiv.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_decompressor.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_regfile.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_debug_dm.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_debug_dtm.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_gpio.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_icache.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_mtime.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_nco.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_neoled.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_package.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_pwm.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_spi.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_sysinfo.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_top.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_trng.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_twi.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_uart.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_wdt.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_wishbone.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_fifo.vhd"] -library neorv32 -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_shifter.vhd"] -library neorv32 - Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qpf =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qpf (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qpf (nonexistent) @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2019 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition -# Date created = 20:23:30 September 13, 2021 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "18.1" -DATE = "20:23:30 September 13, 2021" - -# Revisions - -PROJECT_REVISION = "de0-nano-test-setup" Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd (nonexistent) @@ -1,163 +0,0 @@ --- megafunction wizard: %RAM: 1-PORT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altsyncram - --- ============================================================ --- File Name: dmem_ram.vhd --- Megafunction Name(s): --- altsyncram --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 18.1.1 Build 646 04/11/2019 SJ Lite Edition --- ************************************************************ - - ---Copyright (C) 2019 Intel Corporation. All rights reserved. ---Your use of Intel Corporation's design tools, logic functions ---and other software and tools, and any partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Intel Program License ---Subscription Agreement, the Intel Quartus Prime License Agreement, ---the Intel FPGA IP License Agreement, or other applicable license ---agreement, including, without limitation, that your use is for ---the sole purpose of programming logic devices manufactured by ---Intel and sold by Intel or its authorized distributors. Please ---refer to the applicable agreement for further details, at ---https://fpgasoftware.intel.com/eula. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY dmem_ram IS - PORT - ( - address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); - byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1'); - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) - ); -END dmem_ram; - - -ARCHITECTURE SYN OF dmem_ram IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); - -BEGIN - q <= sub_wire0(31 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - byte_size => 8, - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone IV E", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2048, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "CLOCK0", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => 11, - width_a => 32, - width_byteena_a => 4 - ) - PORT MAP ( - address_a => address, - byteena_a => byteena, - clock0 => clock, - data_a => data, - wren_a => wren, - q_a => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" --- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" --- Retrieval info: PRIVATE: AclrByte NUMERIC "0" --- Retrieval info: PRIVATE: AclrData NUMERIC "0" --- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" --- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" --- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: Clken NUMERIC "0" --- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" --- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" --- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" --- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" --- Retrieval info: PRIVATE: RegAddr NUMERIC "1" --- Retrieval info: PRIVATE: RegData NUMERIC "1" --- Retrieval info: PRIVATE: RegOutput NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: SingleClock NUMERIC "1" --- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" --- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" --- Retrieval info: PRIVATE: WidthData NUMERIC "32" --- Retrieval info: PRIVATE: rden NUMERIC "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" --- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" --- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" --- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" --- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" --- Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" --- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" --- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" --- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" --- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 --- Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0 --- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 --- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qsf =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qsf (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qsf (nonexistent) @@ -1,108 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2019 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition -# Date created = 20:23:30 September 13, 2021 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# de0-nano-test-setup_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name DEVICE EP4CE22F17C6 -set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_avalonmm -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021" -set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_application_image.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bootloader_image.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_boot_rom.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_busswitch.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bus_keeper.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cfs.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_alu.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_bus.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_control.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_bitmanip.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_fpu.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_muldiv.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_shifter.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_decompressor.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_regfile.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dm.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dtm.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_fifo.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_gpio.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_icache.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_mtime.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_neoled.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_package.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_pwm.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_slink.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_spi.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_sysinfo.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_top.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_trng.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_twi.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_uart.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wdt.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wishbone.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_xirq.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32 -set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32 -set_global_assignment -name VHDL_FILE neorv32_test_setup_avalonmm.vhd -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_location_assignment PIN_R8 -to clk_i -set_location_assignment PIN_L3 -to gpio_o[7] -set_location_assignment PIN_B1 -to gpio_o[6] -set_location_assignment PIN_F3 -to gpio_o[5] -set_location_assignment PIN_D1 -to gpio_o[4] -set_location_assignment PIN_A11 -to gpio_o[3] -set_location_assignment PIN_B13 -to gpio_o[2] -set_location_assignment PIN_A13 -to gpio_o[1] -set_location_assignment PIN_A15 -to gpio_o[0] -set_location_assignment PIN_J15 -to rstn_i -set_location_assignment PIN_C3 -to uart0_txd_o -set_location_assignment PIN_A3 -to uart0_rxd_i -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore (nonexistent) @@ -1,5 +0,0 @@ -db -incremental_db -output_files -greybox_tmp -*.qws Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd (nonexistent) @@ -1,332 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Test Setup using the AvalonMM Interface >> # --- # ********************************************************************************************* # --- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" # --- # are trademarks of Intel # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.std_logic_unsigned.ALL; - -library neorv32; -use neorv32.neorv32_package.all; - -entity neorv32_test_setup_avalonmm is - generic ( - -- adapt these for your setup -- - CLOCK_FREQUENCY : natural := 50000000; -- clock frequency of clk_i in Hz - MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes - MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes - ); - port ( - -- Global control -- - clk_i : in std_ulogic; -- global clock, rising edge - rstn_i : in std_ulogic; -- global reset, low-active, async - -- GPIO -- - gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output - -- UART0 -- - uart0_txd_o : out std_ulogic; -- UART0 send data - uart0_rxd_i : in std_ulogic -- UART0 receive data - ); -end entity; - -architecture neorv32_test_setup_avalonmm_rtl of neorv32_test_setup_avalonmm is - - component neorv32_top_avalonmm is - generic ( - -- General -- - CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz - HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) - INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM - - -- On-Chip Debugger (OCD) -- - ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger - - -- RISC-V CPU Extensions -- - CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? - CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? - CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? - CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? - CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? - CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? - CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) - CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? - CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? - CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? - - -- Extension Options -- - FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier - FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations - CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) - CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2 - - -- Physical Memory Protection (PMP) -- - PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) - PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes - - -- Hardware Performance Monitors (HPM) -- - HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) - HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) - - -- Internal Instruction memory (IMEM) -- - MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory - MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes - - -- Internal Data memory (DMEM) -- - MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory - MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes - - -- Internal Cache memory (iCACHE) -- - ICACHE_EN : boolean := false; -- implement instruction cache - ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 - ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 - ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 - - -- Stream link interface (SLINK) -- - SLINK_NUM_TX : natural := 0; -- number of TX links (0..8) - SLINK_NUM_RX : natural := 0; -- number of TX links (0..8) - SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two - SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two - - -- External Interrupts Controller (XIRQ) -- - XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) - XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge - XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge - - -- Processor peripherals -- - IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? - IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? - IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? - IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)? - IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)? - IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)? - IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled - IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)? - IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? - IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? - IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic - IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits - IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits - IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? - IO_NEOLED_TX_FIFO : natural := 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two - ); - port ( - -- Global control -- - clk_i : in std_ulogic; -- global clock, rising edge - rstn_i : in std_ulogic; -- global reset, low-active, async - - -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- - jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional) - jtag_tck_i : in std_ulogic := 'U'; -- serial clock - jtag_tdi_i : in std_ulogic := 'U'; -- serial data input - jtag_tdo_o : out std_ulogic; -- serial data output - jtag_tms_i : in std_ulogic := 'U'; -- mode select - - -- AvalonMM interface - read_o : out std_logic; - write_o : out std_logic; - waitrequest_i : in std_logic := '0'; - byteenable_o : out std_logic_vector(3 downto 0); - address_o : out std_logic_vector(31 downto 0); - writedata_o : out std_logic_vector(31 downto 0); - readdata_i : in std_logic_vector(31 downto 0) := (others => '0'); - - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o : out std_ulogic; -- indicates an executed FENCE operation - fencei_o : out std_ulogic; -- indicates an executed FENCEI operation - - -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- - slink_tx_dat_o : out sdata_8x32_t; -- output data - slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output - slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send - - -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- - slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data - slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input - slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive - - -- GPIO (available if IO_GPIO_EN = true) -- - gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output - gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input - - -- primary UART0 (available if IO_UART0_EN = true) -- - uart0_txd_o : out std_ulogic; -- UART0 send data - uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data - uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- secondary UART1 (available if IO_UART1_EN = true) -- - uart1_txd_o : out std_ulogic; -- UART1 send data - uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data - uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional - uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional - - -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o : out std_ulogic; -- SPI serial clock - spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in - spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out - spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select - - -- TWI (available if IO_TWI_EN = true) -- - twi_sda_io : inout std_logic := 'U'; -- twi serial data line - twi_scl_io : inout std_logic := 'U'; -- twi serial clock line - - -- PWM (available if IO_PWM_NUM_CH > 0) -- - pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels - - -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- - cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit - cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit - - -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- - neoled_o : out std_ulogic; -- async serial data line - - -- System time -- - mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false) - mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) - - -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- - xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels - - -- CPU interrupts -- - mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false - msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt - mext_irq_i : in std_ulogic := 'L' -- machine external interrupt - ); - end component neorv32_top_avalonmm; - - -- Intel/Altera RAM module created by MegaWizard - COMPONENT dmem_ram IS - PORT - ( - address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); - byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1'); - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) - ); - END COMPONENT dmem_ram; - -signal con_gpio_o : std_ulogic_vector(63 downto 0); - -signal read_o : std_logic; -signal write_o : std_logic; -signal waitrequest_i : std_logic; -signal byteenable_o : std_logic_vector(3 downto 0); -signal address_o : std_logic_vector(31 downto 0); -signal writedata_o : std_logic_vector(31 downto 0); -signal readdata_i : std_logic_vector(31 downto 0); - -signal read_wait_cnt : std_logic_vector(1 downto 0); - - -begin - - -- The Core Of The Problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_top_inst: neorv32_top_avalonmm - generic map ( - -- General -- - CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz - INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM - -- RISC-V CPU Extensions -- - CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? - CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? - CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? - -- Internal Instruction memory -- - MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory - MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes - -- Internal Data memory -- - MEM_INT_DMEM_EN => false, -- implement processor-internal data memory - MEM_INT_DMEM_SIZE => 0, -- size of processor-internal data memory in bytes - -- Processor peripherals -- - IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? - IO_MTIME_EN => true, -- implement machine system timer (MTIME)? - IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)? - ) - port map ( - -- Global control -- - clk_i => clk_i, -- global clock, rising edge - rstn_i => rstn_i, -- global reset, low-active, async - -- GPIO (available if IO_GPIO_EN = true) -- - gpio_o => con_gpio_o, -- parallel output - -- primary UART0 (available if IO_UART0_EN = true) -- - uart0_txd_o => uart0_txd_o, -- UART0 send data - uart0_rxd_i => uart0_rxd_i, -- UART0 receive data - -- AvalonMM Interface - read_o => read_o, - write_o => write_o, - waitrequest_i => waitrequest_i, - byteenable_o => byteenable_o, - address_o => address_o, - writedata_o => writedata_o, - readdata_i => readdata_i - ); - - -- Simple example hooking up RAM module to AvalonMM Interface - -- and using this RAM as DMEM - my_dmem_ram : dmem_ram - port map( - address => address_o(12 downto 2), - byteena => byteenable_o, - clock => clk_i, - data => writedata_o, - wren => write_o, - q => readdata_i); - - - -- Very simple AvalonMM control signals - -- Write has 0 wait-states - -- Read has 2 wait-states - waitrequest_i <= '1' when (read_o = '1' and read_wait_cnt /= "10") else '0'; - process(clk_i, rstn_i) - begin - if rstn_i = '0' then - read_wait_cnt <= "00"; - elsif rising_edge(clk_i) then - if read_o = '0' then - read_wait_cnt <= "00"; - else - read_wait_cnt <= read_wait_cnt + '1'; - end if; - end if; - end process; - - -- GPIO output -- - gpio_o <= con_gpio_o(7 downto 0); - - -end architecture; Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.qip =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.qip (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.qip (nonexistent) @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "18.1" -set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dmem_ram.vhd"] Index: neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/README.md =================================================================== --- neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/README.md (revision 70) +++ neorv32/trunk/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/README.md (nonexistent) @@ -1,60 +0,0 @@ -# NEORV32 Test Setup using the NEORV32 with AvalonMM Master Interface wrapper - -This setup provides a very simple "demo setup" that uses the NEORV32 with a AvalonMM -Interface wrapper. This makes if possible to connect you own modules using a simple -version of the AvalonMM Master interface. - -Note that the AvalonMM Master is a very simple version providing only basic features: - -* Single read and write access -* Flow control (variable wait-states) -* 8/16/32 bit data access -* Aligned and unaligned access supported - -The AvalonMM Master does **not** support: -* Burst access -* Pipeline transfer -* Pending reads - -The design is based on the de0-nano-test-setup, but added a AvalonMM Master wrapper. -The wrapper file can be found here [`AvalonMM wrapper`](../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd). - -As a test an "external" DMEM is conneced to the NEORV32 over the AvalonMM Master Interface. - -It uses the simplified and simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). - -* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) -* FPGA: Intel Cyclone-IV `EP4CE22F17C6N` -* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition) - - -### NEORV32 Configuration - -For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used -with a few exceptions: - -* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader -* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) -* Clock: 50MHz from on-board oscillator -* Reset: via on-board button "KEY0" -* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0") -* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header - * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4") - * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6") - -### FPGA Utilization - -``` -Total logic elements 3,439 / 22,320 ( 15 % ) -Total registers 1674 -Total pins 12 / 154 ( 8 % ) -Total virtual pins 0 -Total memory bits 197,632 / 608,256 ( 32 % ) -Embedded Multiplier 9-bit elements 0 / 132 ( 0 % ) -Total PLLs 0 / 4 ( 0 % ) -``` - - -## How To Run - -Open the Quartus project file, compile and upload to FPGA. \ No newline at end of file Index: neorv32/trunk/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/create_project.tcl =================================================================== --- neorv32/trunk/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/create_project.tcl (revision 70) +++ neorv32/trunk/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/create_project.tcl (nonexistent) @@ -1,108 +0,0 @@ -# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file -# and modify the default clock frequency: set to 50MHz -set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd " -exec sh -c $shell_script - -# Copyright (C) 2020 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. - -# Quartus Prime: Generate Tcl File for Project -# File: terasic-cyclone-V-gx=starter-kit_test.tcl -# Generated on: Sat Apr 10 16:57:48 2021 - -# Load Quartus Prime Tcl Project package -package require ::quartus::project - -set need_to_close_project 0 -set make_assignments 1 - -# Check that the right project is open -if {[is_project_open]} { - if {[string compare $quartus(project) "terasic-cyclone-V-gx-starter-kit-test-setup"]} { - puts "Project terasic-cyclone-V-gx-starter-kit-test-setup is not open" - set make_assignments 0 - } -} else { - # Only open if not already open - if {[project_exists de0-nano-test-setup]} { - project_open -revision terasic-cyclone-V-gx-starter-kit-setup terasic-cyclone-V-gx-starter-kit-test-setup - } else { - project_new -revision terasic-cyclone-V-gx-starter-kit-test-setup terasic-cyclone-V-gx-starter-kit-test-setup - } - set need_to_close_project 1 -} - -# Make assignments -if {$make_assignments} { - set_global_assignment -name FAMILY "Cyclone V" - set_global_assignment -name DEVICE 5CGXFC5C6F27C7 - set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader - set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 - set_global_assignment -name PROJECT_CREATION_TIME_DATE "TUE JUN 4 20:41:15 2013" - set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" - set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files - set_global_assignment -name BOARD "Cyclone V GX Starter Kit" - set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 - set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - - # core VHDL files - set core_src_dir [glob ./../../../rtl/core/*.vhd] - foreach core_src_file $core_src_dir { - set_global_assignment -name VHDL_FILE $core_src_file -library neorv32 - } - - # top entity: use local modified copy of the original test setup - set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd" - - set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" - set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i - set_instance_assignment -name IO_STANDARD "1.2 V" -to rstn_i - set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[0] - set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[1] - set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[2] - set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[3] - set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[4] - set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[5] - set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[6] - set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[7] - set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_rxd_i - set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_txd_o - - set_location_assignment PIN_R20 -to clk_i - set_location_assignment PIN_P11 -to rstn_i - set_location_assignment PIN_L7 -to gpio_o[0] - set_location_assignment PIN_K6 -to gpio_o[1] - set_location_assignment PIN_D8 -to gpio_o[2] - set_location_assignment PIN_E9 -to gpio_o[3] - set_location_assignment PIN_A5 -to gpio_o[4] - set_location_assignment PIN_B6 -to gpio_o[5] - set_location_assignment PIN_H8 -to gpio_o[6] - set_location_assignment PIN_H9 -to gpio_o[7] - set_location_assignment PIN_M9 -to uart0_rxd_i - set_location_assignment PIN_L9 -to uart0_txd_o - - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # Commit assignments - export_assignments -} Index: neorv32/trunk/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/README.md =================================================================== --- neorv32/trunk/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/README.md (revision 70) +++ neorv32/trunk/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/README.md (nonexistent) @@ -1,65 +0,0 @@ -# NEORV32 Test Setup for the Terasic Cyclone-V GX Starter Kit FPGA Board - -This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic Cyclone-V GX Starter Kit board. -It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor -top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). - -* FPGA Board: :books: [Terasic Cyclone-V GX Starter Kit FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830) -* FPGA: Intel Cyclone-V GX `5CGXFC5C6F27C7N` -* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition) - - -### NEORV32 Configuration - -:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for -configuration and entity details and `create_project.tcl` for the according FPGA pin mapping. - -* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide) -* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM -* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` -* Tested with version [`1.5.9.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) -* Clock: 50MHz from on-board oscillator -* Reset: via on-board button "KEY0" -* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0") -* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board provided USB to UART converter - -:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity -is configured for a 100MHz input clock. Since the on-board clock generator of the Cyclone-V GX Starter Kit board needs I2C to be programmed, the fixed 50MHz clock on bank 5B, pin R20 is used for this test setup, and the test setup has to be modified accordingly. -This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file -(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual -top entity. - -### FPGA Utilization - -``` -Logic utilization (in ALMs) 1,442 / 29,080 ( 5 % ) -Total registers 1771 -Total pins 12 / 364 ( 3 % ) -Total virtual pins 0 -Total block memory bits 231,424 / 4,567,040 ( 5 % ) -Total DSP Blocks 0 / 150 ( 0 % ) -Total HSSI RX PCSs 0 / 6 ( 0 % ) -Total HSSI PMA RX Deserializers 0 / 6 ( 0 % ) -Total HSSI TX PCSs 0 / 6 ( 0 % ) -Total HSSI PMA TX Serializers 0 / 6 ( 0 % ) -Total PLLs 0 / 12 ( 0 % ) -Total DLLs 0 / 4 ( 0 % ) -``` - - -## How To Run - -The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project. -If not already available, this script will create a `work` folder in this directory. - -1. start Quartus (in GUI mode) -2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console -3. use the console to navigate to **this** folder: `cd .../setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup` -4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder. Do NOT run the Quartus-supplied tcl setup script, as that will change all assignment names. -5. if a "select family" prompt appears, go to the "Board" tab, select the "Cyclone V GX Starter Kit" board and click OK -6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream -7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA -8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: -19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline) -9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) -and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources. Index: neorv32/trunk/setups/vivado/README.md =================================================================== --- neorv32/trunk/setups/vivado/README.md (revision 70) +++ neorv32/trunk/setups/vivado/README.md (nonexistent) @@ -1,32 +0,0 @@ -# NEORV32 Xilinx Vivado Example Setups - -## How To Run - -The `create_project.tcl` TCL script in the board subdirectories can be used for creating a complete Vivado project and for running the implementation. -If not already available, this script will create a `work` folder in those subdirectories. - -Note that you may need to install support for your particular development board through "XHub Stores" menu item within Vivado prior to sourcing the `create_project.tcl` script. - -### Batch mode - -Execute `vivado -mode batch -nojournal -nolog -source create_project.tcl` from the board subdir. -The project will be created and implementation will be run until generation of `work/neorv32_test_setup.runs/impl_1/neorv32_test_setup.bit`. - -### GUI - -1. start Vivado (in GUI mode) -2. click on "TCL Console" at the bottom -3. use the console to naviagte to the boards folder. For example: `cd .../neorv32/setups/vivado/arty-a7-test-setup` -4. execute `source create_project.tcl` - this will create the actual Vivado project in `work` -5. when the Vivado project has openend, Implementation will run and a bitstream will be generated. -6. maybe a prompt will notify about it. - -### Programming the Bitstream - -1. open the "Hardware Manager" (maybe a prompt will ask for that) -2. click on "Open target/Auto Connect" -3. click on "Program device" and select `work/neorv32_test_setup.runs/impl_1/neorv32_test_setup.bit`; click "Program" -4. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: -19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline) -5. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) -and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources. Index: neorv32/trunk/setups/vivado/arty-a7-test-setup/.gitignore =================================================================== --- neorv32/trunk/setups/vivado/arty-a7-test-setup/.gitignore (revision 70) +++ neorv32/trunk/setups/vivado/arty-a7-test-setup/.gitignore (nonexistent) @@ -1,3 +0,0 @@ -/vivado* -/.Xil -/work/* Index: neorv32/trunk/setups/vivado/arty-a7-test-setup/create_project.tcl =================================================================== --- neorv32/trunk/setups/vivado/arty-a7-test-setup/create_project.tcl (revision 70) +++ neorv32/trunk/setups/vivado/arty-a7-test-setup/create_project.tcl (nonexistent) @@ -1,57 +0,0 @@ -set board "arty-a7-35" - -# Create and clear output directory -set outputdir work -file mkdir $outputdir - -set files [glob -nocomplain "$outputdir/*"] -if {[llength $files] != 0} { - puts "deleting contents of $outputdir" - file delete -force {*}[glob -directory $outputdir *]; # clear folder contents -} else { - puts "$outputdir is empty" -} - -switch $board { - "arty-a7-35" { - set a7part "xc7a35ticsg324-1L" - set a7prj ${board}-test-setup - } -} - -# Create project -create_project -part $a7part $a7prj $outputdir - -set_property board_part digilentinc.com:${board}:part0:1.0 [current_project] -set_property target_language VHDL [current_project] - -# Define filesets - -## Core: NEORV32 -add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd -set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]] -set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]] - -## Design: processor subsystem template, and (optionally) BoardTop and/or other additional sources -set fileset_design ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd - -## Constraints -set fileset_constraints [glob ./*.xdc] - -## Simulation-only sources -set fileset_sim [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd] - -# Add source files - -## Design -add_files $fileset_design - -## Constraints -add_files -fileset constrs_1 $fileset_constraints - -## Simulation-only -add_files -fileset sim_1 $fileset_sim - -# Run synthesis, implementation and bitstream generation -launch_runs impl_1 -to_step write_bitstream -jobs 4 -wait_on_run impl_1 Index: neorv32/trunk/setups/vivado/arty-a7-test-setup/README.md =================================================================== --- neorv32/trunk/setups/vivado/arty-a7-test-setup/README.md (revision 70) +++ neorv32/trunk/setups/vivado/arty-a7-test-setup/README.md (nonexistent) @@ -1,29 +0,0 @@ -# NEORV32 Test Setup for the Digilent Arty A7-35 FPGA Board - -This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Arty A7-35 board. -It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor -top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs). - -* FPGA Board: :books: [Digilent Arty A7-35 FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual) -* FPGA: Xilinx Artix-7 `XC7A35TICSG324-1L` -* Toolchain: Xilinx Vivado (tested with Vivado 2019.2) - - -## NEORV32 Configuration - -:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for -configuration and entity details and [`arty_a7_35_test_setup.xdc`](https://github.com/stnolting/neorv32/blob/master/boards/arty-a7-35-test-setup/arty_a7_35_test_setup.xdc) -for the according FPGA pin mapping. - -* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors) -* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM -* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` -* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) -* Clock: 100MHz from on-board oscillator -* Reset: Via dedicated on-board "RESET" button -* GPIO output port `gpio_o` - * bits 0..3 are connected to the green on-board LEDs (LD4 - LD7); LD4 is the bootloader status LED - * bits 4..7 are (not actually used) connected to PMOD `JA` connector pins 1-4 -* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip - - Index: neorv32/trunk/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc =================================================================== --- neorv32/trunk/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc (revision 70) +++ neorv32/trunk/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc (nonexistent) @@ -1,26 +0,0 @@ -## This file is a general .xdc for the Arty A7-35 Rev. D - -## For default neorv32_test_setup.vhd top entity - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk_i }]; - -## LEDs -set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; #IO_L24N_T3_35 Sch=led[4] -set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; #IO_25_35 Sch=led[5] -set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] -set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] - -## Pmod Header JA (unused GPIO outputs) -set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[4] }]; #IO_0_15 Sch=ja[1] -set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; #IO_L4P_T0_15 Sch=ja[2] -set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; #IO_L4N_T0_15 Sch=ja[3] -set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; #IO_L6P_T0_15 Sch=ja[4] - -## USB-UART Interface -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd_o }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out -set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd_i }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in - -## Misc. -set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { rstn_i }]; #IO_L16P_T2_35 Sch=ck_rst Index: neorv32/trunk/setups/vivado/nexys-a7-test-setup/nexys_a7_test_setup.xdc =================================================================== --- neorv32/trunk/setups/vivado/nexys-a7-test-setup/nexys_a7_test_setup.xdc (revision 70) +++ neorv32/trunk/setups/vivado/nexys-a7-test-setup/nexys_a7_test_setup.xdc (nonexistent) @@ -1,23 +0,0 @@ -## This file is a general .xdc for the Nexys A7 and Nexys 4 DDR -## For default neorv32_test_setup.vhd top entity - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk_i }]; - -## LEDs -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] - -## USB-UART Interface -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd_o }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd_i }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in - -## Misc. -set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rstn_i }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_rst Index: neorv32/trunk/setups/vivado/nexys-a7-test-setup/create_project.tcl =================================================================== --- neorv32/trunk/setups/vivado/nexys-a7-test-setup/create_project.tcl (revision 70) +++ neorv32/trunk/setups/vivado/nexys-a7-test-setup/create_project.tcl (nonexistent) @@ -1,45 +0,0 @@ -set board "A7-50" - -# create and clear output directory -set outputdir work -file mkdir $outputdir - -set files [glob -nocomplain "$outputdir/*"] -if {[llength $files] != 0} { - puts "deleting contents of $outputdir" - file delete -force {*}[glob -directory $outputdir *]; # clear folder contents -} else { - puts "$outputdir is empty" -} - -switch $board { - "A7-50" { - set a7part "xc7a50tcsg324-1" - set a7prj "nexys-a7-50-test-setup" - } - "A7-100" { - set a7part "xc7a100tcsg324-1" - set a7prj "nexys-a7-100-test-setup" - } -} - -# create project -create_project -part $a7part $a7prj $outputdir - -# add source files: core sources -add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd -set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]] -set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]] - -# add source file: top entity -add_files [glob ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd] - -# add source files: simulation-only -add_files -fileset sim_1 [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd] - -# add source files: constraints -add_files -fileset constrs_1 [glob ./*.xdc] - -# run synthesis, implementation and bitstream generation -launch_runs impl_1 -to_step write_bitstream -jobs 4 -wait_on_run impl_1 Index: neorv32/trunk/setups/vivado/nexys-a7-test-setup/README.md =================================================================== --- neorv32/trunk/setups/vivado/nexys-a7-test-setup/README.md (revision 70) +++ neorv32/trunk/setups/vivado/nexys-a7-test-setup/README.md (nonexistent) @@ -1,29 +0,0 @@ -# NEORV32 Test Setup for the Digilent Nexys A7 and Nexys 4 DDR FPGA Boards - -This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Nexys A7 and Nexys 4 DDR boards. -It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor -top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs). - -* FPGA Boards: - * :books: [Digilent Nexys A7 FPGA Boards](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual) - * :books: [Digilent Nexys 4 DDR FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/reference-manual) -* FPGAs: - * Xilinx Artix-7 `XC7A50TCSG324-1` - * Xilinx Artix-7 `XC7A100TCSG324-1` -* Toolchain: Xilinx Vivado (tested with Vivado 2020.2) - - -## NEORV32 Configuration - -:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for -configuration and entity details and [`nexys_a7_test_setup.xdc`](https://github.com/AWenzel83/neorv32/blob/nexys_a7_example/boards/nexys-a7-test-setup/nexys_a7_test_setup.xdc) -for the according FPGA pin mapping. - -* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors) -* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM -* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` -* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) -* Clock: 100MHz from on-board oscillator -* Reset: Via dedicated on-board "RESET" button -* GPIO output port `gpio_o` bits 0..7 are connected to the green on-board LEDs (LD0 - LD7); LD0 is the bootloader status LED -* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip Index: neorv32/trunk/setups/vivado/nexys-a7-test-setup/.gitignore =================================================================== --- neorv32/trunk/setups/vivado/nexys-a7-test-setup/.gitignore (revision 70) +++ neorv32/trunk/setups/vivado/nexys-a7-test-setup/.gitignore (nonexistent) @@ -1,3 +0,0 @@ -/vivado* -/.Xil -/work/* Index: neorv32/trunk/setups/osflow/PnR_Bit.mk =================================================================== --- neorv32/trunk/setups/osflow/PnR_Bit.mk (revision 70) +++ neorv32/trunk/setups/osflow/PnR_Bit.mk (nonexistent) @@ -1,14 +0,0 @@ -${IMPL}.${PNR2BIT_EXT}: $(IMPL).json $(CONSTRAINTS) - $(NEXTPNR) \ - $(PNRFLAGS) \ - --$(CONSTRAINTS_FORMAT) $(CONSTRAINTS) \ - --json $(IMPL).json \ - --${NEXTPNR_OUT} $@ 2>&1 | tee nextpnr-report.txt - -${IMPL}.bit: ${IMPL}.${PNR2BIT_EXT} - $(PACKTOOL) $< $@ - -ifeq ($(DEVICE_SERIES),ecp5) -${IMPL}.svf: ${IMPL}.${PNR2BIT_EXT} - $(PACKTOOL) $(PACKARGS) --svf $@ $< -endif Index: neorv32/trunk/setups/osflow/filesets.mk =================================================================== --- neorv32/trunk/setups/osflow/filesets.mk (revision 70) +++ neorv32/trunk/setups/osflow/filesets.mk (nonexistent) @@ -1,66 +0,0 @@ -RTL_CORE_SRC := ../../rtl/core - -NEORV32_PKG := $(RTL_CORE_SRC)/neorv32_package.vhd - -NEORV32_APP_SRC := \ - $(RTL_CORE_SRC)/neorv32_application_image.vhd \ - -NEORV32_MEM_ENTITIES := \ - $(RTL_CORE_SRC)/neorv32_dmem.entity.vhd \ - $(RTL_CORE_SRC)/neorv32_imem.entity.vhd - -NEORV32_CORE_SRC := \ - $(RTL_CORE_SRC)/neorv32_bootloader_image.vhd \ - $(RTL_CORE_SRC)/neorv32_boot_rom.vhd \ - $(RTL_CORE_SRC)/neorv32_bus_keeper.vhd \ - $(RTL_CORE_SRC)/neorv32_busswitch.vhd \ - $(RTL_CORE_SRC)/neorv32_cfs.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_alu.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_bus.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_control.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_cp_bitmanip.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_cp_fpu.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_cp_muldiv.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_cp_shifter.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_decompressor.vhd \ - $(RTL_CORE_SRC)/neorv32_cpu_regfile.vhd \ - $(RTL_CORE_SRC)/neorv32_debug_dm.vhd \ - $(RTL_CORE_SRC)/neorv32_debug_dtm.vhd \ - $(RTL_CORE_SRC)/neorv32_fifo.vhd \ - $(RTL_CORE_SRC)/neorv32_gpio.vhd \ - $(RTL_CORE_SRC)/neorv32_gptmr.vhd \ - $(RTL_CORE_SRC)/neorv32_icache.vhd \ - $(RTL_CORE_SRC)/neorv32_mtime.vhd \ - $(RTL_CORE_SRC)/neorv32_neoled.vhd \ - $(RTL_CORE_SRC)/neorv32_pwm.vhd \ - $(RTL_CORE_SRC)/neorv32_slink.vhd \ - $(RTL_CORE_SRC)/neorv32_spi.vhd \ - $(RTL_CORE_SRC)/neorv32_sysinfo.vhd \ - $(RTL_CORE_SRC)/neorv32_top.vhd \ - $(RTL_CORE_SRC)/neorv32_trng.vhd \ - $(RTL_CORE_SRC)/neorv32_twi.vhd \ - $(RTL_CORE_SRC)/neorv32_uart.vhd \ - $(RTL_CORE_SRC)/neorv32_wdt.vhd \ - $(RTL_CORE_SRC)/neorv32_wishbone.vhd \ - $(RTL_CORE_SRC)/neorv32_xirq.vhd - -# Before including this partial makefile, NEORV32_MEM_SRC needs to be set -# (containing two VHDL sources: one for IMEM and one for DMEM) - -NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} ${NEORV32_MEM_SRC} ${NEORV32_MEM_SRC_EXTRA} ${NEORV32_CORE_SRC} ${NEORV32_CORE_SRC_EXTRA} -NEORV32_VERILOG_ALL := ${NEORV32_VERILOG_SRC} ${NEORV32_VERILOG_SRC_EXTRA} - -ICE40_SRC := \ - devices/ice40/sb_ice40_components.vhd - -ECP5_SRC := \ - devices/ecp5/ecp5_components.vhd - -ifeq ($(DEVICE_SERIES),ecp5) -DEVICE_SRC := ${ECP5_SRC} -else -DEVICE_SRC := ${ICE40_SRC} -endif - -# Optionally NEORV32_VERILOG_SRC can be set to a list of Verilog sources Index: neorv32/trunk/setups/osflow/.gitignore =================================================================== --- neorv32/trunk/setups/osflow/.gitignore (revision 70) +++ neorv32/trunk/setups/osflow/.gitignore (nonexistent) @@ -1,8 +0,0 @@ -*.asc -*.bit -*.cfg -*.dfu -*.history -*.json -*.svf -*-report.txt Index: neorv32/trunk/setups/osflow/tools.mk =================================================================== --- neorv32/trunk/setups/osflow/tools.mk (revision 70) +++ neorv32/trunk/setups/osflow/tools.mk (nonexistent) @@ -1,28 +0,0 @@ -GHDL_FLAGS += --std=08 -GHDL ?= ghdl -GHDLSYNTH ?= ghdl -YOSYS ?= yosys -ICEPACK ?= icepack -ECPPACK ?= ecppack -OPENOCD ?= openocd -COPY ?= cp -a - -DEVICE_SERIES ?= ice40 -DEVICE_LIB ?= $(DEVICE_SERIES) -YOSYSSYNTH ?= $(DEVICE_SERIES) -NEXTPNR ?= nextpnr-$(DEVICE_SERIES) - -ifeq ($(DEVICE_SERIES),ice40) -YOSYSPIPE ?= -dsp -CONSTRAINTS_FORMAT ?= pcf -NEXTPNR_OUT ?= asc -PNR2BIT_EXT ?= asc -PACKTOOL ?= $(ICEPACK) -PACKARGS ?= -else -CONSTRAINTS_FORMAT ?= lpf -NEXTPNR_OUT ?= textcfg -PNR2BIT_EXT ?= cfg -PACKTOOL ?= $(ECPPACK) -PACKARGS ?= --compress -endif Index: neorv32/trunk/setups/osflow/constraints/Fomu-hacker.pcf =================================================================== --- neorv32/trunk/setups/osflow/constraints/Fomu-hacker.pcf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/Fomu-hacker.pcf (nonexistent) @@ -1,16 +0,0 @@ -# Configuration for the Fomu 'hacker' board -set_io clki F5 # Clock input from 48MHz Oscillator -set_io rgb[0] A5 # Blue LED -set_io rgb[1] B5 # Green LED -set_io rgb[2] C5 # Red LED -set_io user[0] F4 # User touch pad 1 -set_io user[1] E5 # User touch pad 2 -set_io user[2] E4 # User touch pad 3 -set_io user[3] F2 # User touch pad 4 -set_io spi_mosi F1 # SPI Master Out, Slave In Pin -set_io spi_miso E1 # SPI Master In, Slave Out Pin -set_io spi_clk D1 # SPI Master Clock Output Pin -set_io spi_cs C1 # SPI Chip Select -set_io usb_dn A2 # USB D- pad -set_io usb_dp A4 # USB D+ pad -set_io usb_dp_pu D5 # USB D+ pull up (indicates device connected) Index: neorv32/trunk/setups/osflow/constraints/iCESugar.pcf =================================================================== --- neorv32/trunk/setups/osflow/constraints/iCESugar.pcf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/iCESugar.pcf (nonexistent) @@ -1,69 +0,0 @@ -#| iCESugar-v1.5 - - -#> Clock (12 MHz) -set_io --warn-no-port iCESugarv15_CLK 35 - - -#> Tri-colour LED -set_io --warn-no-port iCESugarv15_LED_G 41 -set_io --warn-no-port iCESugarv15_LED_R 40 -set_io --warn-no-port iCESugarv15_LED_B 39 - - -#> UART -set_io --warn-no-port iCESugarv15_RX 4 -set_io --warn-no-port iCESugarv15_TX 6 - - -#> USB -set_io --warn-no-port iCESugarv15_USB_DN 9 -set_io --warn-no-port iCESugarv15_USB_DP 10 -set_io --warn-no-port iCESugarv15_USB_DP_PU 11 - - -#> PMOD 1 -set_io --warn-no-port iCESugarv15_PMOD1A_0 10 -set_io --warn-no-port iCESugarv15_PMOD1A_1 6 -set_io --warn-no-port iCESugarv15_PMOD1A_2 3 -set_io --warn-no-port iCESugarv15_PMOD1A_3 48 -set_io --warn-no-port iCESugarv15_PMOD1B_0 47 -set_io --warn-no-port iCESugarv15_PMOD1B_1 2 -set_io --warn-no-port iCESugarv15_PMOD1B_2 4 -set_io --warn-no-port iCESugarv15_PMOD1B_3 9 - - -#> PMOD 2 -set_io --warn-no-port iCESugarv15_PMOD2A_0 46 -set_io --warn-no-port iCESugarv15_PMOD2A_1 44 -set_io --warn-no-port iCESugarv15_PMOD2A_2 42 -set_io --warn-no-port iCESugarv15_PMOD2A_3 37 -set_io --warn-no-port iCESugarv15_PMOD2B_0 36 -set_io --warn-no-port iCESugarv15_PMOD2B_1 38 -set_io --warn-no-port iCESugarv15_PMOD2B_2 43 -set_io --warn-no-port iCESugarv15_PMOD2B_3 45 - - -#> PMOD 3 -set_io --warn-no-port iCESugarv15_PMOD3A_0 34 -set_io --warn-no-port iCESugarv15_PMOD3A_1 31 -set_io --warn-no-port iCESugarv15_PMOD3A_2 27 -set_io --warn-no-port iCESugarv15_PMOD3A_3 25 -set_io --warn-no-port iCESugarv15_PMOD3B_0 23 -set_io --warn-no-port iCESugarv15_PMOD3B_1 26 -set_io --warn-no-port iCESugarv15_PMOD3B_2 28 -set_io --warn-no-port iCESugarv15_PMOD3B_3 32 - - -#> PMOD 4 | Switches -set_io --warn-no-port iCESugarv15_PMOD4_0 21 -set_io --warn-no-port iCESugarv15_PMOD4_1 20 -set_io --warn-no-port iCESugarv15_PMOD4_2 19 -set_io --warn-no-port iCESugarv15_PMOD4_3 18 - - -#> SPI -set_io --warn-no-port iCESugarv15_SPI_SS 16 -set_io --warn-no-port iCESugarv15_SPI_SCK 15 -set_io --warn-no-port iCESugarv15_SPI_MOSI 17 -set_io --warn-no-port iCESugarv15_SPI_MISO 14 Index: neorv32/trunk/setups/osflow/constraints/Fomu-evt2.pcf =================================================================== --- neorv32/trunk/setups/osflow/constraints/Fomu-evt2.pcf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/Fomu-evt2.pcf (nonexistent) @@ -1,34 +0,0 @@ -# Configuration for the Fomu 'evt2' board -set_io clki 44 -set_io clki_alt 20 -set_io rgb[0] 39 -set_io rgb[1] 40 -set_io rgb[2] 41 -set_io pmod[0] 25 -set_io pmod[1] 26 -set_io pmod[2] 27 -set_io pmod[3] 28 -set_io user[0] 48 -set_io user[1] 47 -set_io user[2] 46 -set_io user[3] 45 -set_io user[4] 42 -set_io user[5] 38 -set_io spi_mosi 14 -set_io spi_miso 17 -set_io spi_clk 15 -set_io spi_cs 16 -set_io spi_io2 18 -set_io spi_io3 19 -set_io uart_tx 21 -set_io uart_rx 13 -set_io usb_dn 37 -set_io usb_dp 34 -set_io usb_dp_pu 35 -set_io usb_dn_pu 36 -set_io dbg[0] 20 -set_io dbg[1] 12 -set_io dbg[2] 11 -set_io dbg[3] 23 -set_io dbg[4] 10 -set_io dbg[5] 9 Index: neorv32/trunk/setups/osflow/constraints/Fomu-evt3.pcf =================================================================== --- neorv32/trunk/setups/osflow/constraints/Fomu-evt3.pcf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/Fomu-evt3.pcf (nonexistent) @@ -1,34 +0,0 @@ -# Configuration for the Fomu 'evt3' board -set_io rgb[0] 39 -set_io rgb[1] 40 -set_io rgb[2] 41 -set_io pmod[0] 28 -set_io pmod[1] 27 -set_io pmod[2] 26 -set_io pmod[3] 23 -set_io clki_alt 20 -set_io clki 44 -set_io user[0] 48 -set_io user[1] 47 -set_io user[2] 46 -set_io user[3] 45 -set_io user[4] 42 -set_io user[5] 38 -set_io spi_mosi 14 -set_io spi_miso 17 -set_io spi_clk 15 -set_io spi_io2 18 -set_io spi_io3 19 -set_io spi_cs 16 -set_io uart_tx 21 -set_io uart_rx 13 -set_io usb_dn 37 -set_io usb_dp 34 -set_io usb_dp_pu 35 -set_io usb_dn_pu 36 -set_io dbg[0] 20 -set_io dbg[1] 12 -set_io dbg[2] 11 -set_io dbg[3] 25 -set_io dbg[4] 10 -set_io dbg[5] 9 Index: neorv32/trunk/setups/osflow/constraints/ULX3S.lpf =================================================================== --- neorv32/trunk/setups/osflow/constraints/ULX3S.lpf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/ULX3S.lpf (nonexistent) @@ -1,598 +0,0 @@ -BLOCK RESETPATHS; -BLOCK ASYNCPATHS; -## ULX3S v2.x.x and v3.0.x - -# The clock "usb" and "gpdi" sheet -LOCATE COMP "ULX3S_CLK" SITE "G2"; -IOBUF PORT "ULX3S_CLK" PULLMODE=NONE IO_TYPE=LVCMOS33; -FREQUENCY PORT "ULX3S_CLK" 25 MHZ; - -# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash -# write to FLASH possible any time from JTAG: -SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE; -# write to FLASH possible from user bitstream: -# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; - -## USBSERIAL FTDI-FPGA serial port "usb" sheet -LOCATE COMP "ULX3S_TX" SITE "L4"; # FPGA transmits to ftdi -LOCATE COMP "ULX3S_RX" SITE "M1"; # FPGA receives from ftdi -LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives -LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives -LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives -IOBUF PORT "ULX3S_TX" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ULX3S_RX" PULLMODE=UP IO_TYPE=LVCMOS33; -IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; -IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; -IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; - -## LED indicators "blinkey" and "gpio" sheet -LOCATE COMP "ULX3S_LED7" SITE "H3"; -LOCATE COMP "ULX3S_LED6" SITE "E1"; -LOCATE COMP "ULX3S_LED5" SITE "E2"; -LOCATE COMP "ULX3S_LED4" SITE "D1"; -LOCATE COMP "ULX3S_LED3" SITE "D2"; -LOCATE COMP "ULX3S_LED2" SITE "C1"; -LOCATE COMP "ULX3S_LED1" SITE "C2"; -LOCATE COMP "ULX3S_LED0" SITE "B2"; -IOBUF PORT "ULX3S_LED0" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ULX3S_LED1" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ULX3S_LED2" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ULX3S_LED3" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ULX3S_LED4" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ULX3S_LED5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ULX3S_LED6" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "ULX3S_LED7" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; - -## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet -LOCATE COMP "ULX3S_RST_N" SITE "D6"; # BTN_PWRn (inverted logic) -LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 -LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 -LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 -LOCATE COMP "btn[4]" SITE "V1"; # DOWN -LOCATE COMP "btn[5]" SITE "U1"; # LEFT -LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 -IOBUF PORT "ULX3S_RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; - -## DIP switch "blinkey", "gpio" sheet -LOCATE COMP "sw[0]" SITE "E8"; # SW1 -LOCATE COMP "sw[1]" SITE "D8"; # SW2 -LOCATE COMP "sw[2]" SITE "D7"; # SW3 -LOCATE COMP "sw[3]" SITE "E7"; # SW4 -IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; - -## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet -LOCATE COMP "oled_clk" SITE "P4"; -LOCATE COMP "oled_mosi" SITE "P3"; -LOCATE COMP "oled_dc" SITE "P1"; -LOCATE COMP "oled_resn" SITE "P2"; -LOCATE COMP "oled_csn" SITE "N2"; -IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## SPI Flash chip "flash" sheet -LOCATE COMP "flash_csn" SITE "R2"; -LOCATE COMP "flash_clk" SITE "U3"; -LOCATE COMP "flash_mosi" SITE "W2"; -LOCATE COMP "flash_miso" SITE "V2"; -LOCATE COMP "flash_holdn" SITE "W1"; -LOCATE COMP "flash_wpn" SITE "Y2"; -#LOCATE COMP "flash_csspin" SITE "AJ3"; -#LOCATE COMP "flash_initn" SITE "AG4"; -#LOCATE COMP "flash_done" SITE "AJ4"; -#LOCATE COMP "flash_programn" SITE "AH4"; -#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; -#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; -#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; -IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; - -## SD card "sdcard", "usb" sheet -# wifi_gpio2,4,12,13,14,15 are shared with SD card. -# If any of wifi_gpio2,4,12,13 is used in toplevel, don't use sd_d[]. -# If SD is used in 1-bit SPI mode, wifi_gpio4,12 = sd_d[1,2] are free, -LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 -LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 -LOCATE COMP "sd_d[0]" SITE "J3"; # sd_d0_do (MISO) WiFi GPIO2 -LOCATE COMP "sd_d[1]" SITE "H1"; # sd_d1_irq WiFi GPIO4 -LOCATE COMP "sd_d[2]" SITE "K1"; # sd_d2 WiFi_GPIO12 -LOCATE COMP "sd_d[3]" SITE "K2"; # sd_d3_csn WiFi_GPIO13 -LOCATE COMP "sd_wp" SITE "P5"; # not connected -LOCATE COMP "sd_cdn" SITE "N5"; # not connected -IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping without 3.3V efuse -IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## ADC SPI (MAX11123) "analog", "ram" sheet -# input lines shared with GP,GN14-17 -LOCATE COMP "adc_csn" SITE "R17"; -LOCATE COMP "adc_mosi" SITE "R16"; -LOCATE COMP "adc_miso" SITE "U16"; -LOCATE COMP "adc_sclk" SITE "P17"; -IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## Audio 4-bit DAC "analog", "gpio" sheet -# output impedance: 75 ohm -# Stereo 16 ohm earphones, analog audio, -# SPDIF digital audio and composite video. -LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) -LOCATE COMP "audio_l[2]" SITE "C3"; -LOCATE COMP "audio_l[1]" SITE "D3"; -LOCATE COMP "audio_l[0]" SITE "E4"; -LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) -LOCATE COMP "audio_r[2]" SITE "D5"; -LOCATE COMP "audio_r[1]" SITE "B5"; -LOCATE COMP "audio_r[0]" SITE "A3"; -LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) -LOCATE COMP "audio_v[2]" SITE "F5"; -LOCATE COMP "audio_v[1]" SITE "F2"; -LOCATE COMP "audio_v[0]" SITE "H5"; -IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; - -## WiFi ESP-32 "wifi", "usb", "flash" sheet -# wifi_gpio2,4,12,13,14,15 are shared with SD card. -# If any of wifi_gpio2,4,12,13 is used in toplevel, don't use sd_d[]. -# If SD is used in 1-bit SPI mode, wifi_gpio4,12 = sd_d[1,2] are free, -# other pins are shared with GP/GN, and JTAG -LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi -LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi -LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi -LOCATE COMP "wifi_gpio0" SITE "L2"; -LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED -LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX -LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX -# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active -# wifi lines shared with SD card -LOCATE COMP "wifi_gpio2" SITE "J3"; # sd_d0_do (MISO) WiFi GPIO2 -LOCATE COMP "wifi_gpio4" SITE "H1"; # sd_d1_irq WiFi GPIO4 -LOCATE COMP "wifi_gpio12" SITE "K1"; # sd_d2 WiFi_GPIO12 -LOCATE COMP "wifi_gpio13" SITE "K2"; # sd_d3_csn WiFi_GPIO13 -LOCATE COMP "wifi_gpio14" SITE "H2"; # sd_clk WiFi_GPIO14 -LOCATE COMP "wifi_gpio15" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 -# wifi lines shared with JTAG -# LOCATE COMP "wifi_gpio21" SITE "U5"; # JTAG TMS -# LOCATE COMP "wifi_gpio18" SITE "T5"; # JTAG TCK -# LOCATE COMP "wifi_gpio23" SITE "R5"; # JTAG TDI -# LOCATE COMP "wifi_gpio19" SITE "V4"; # JTAG TDO -IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_gpio5" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming -IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## PCB antenna 433 MHz (may be also used for FM) "usb" sheet -LOCATE COMP "ant_433mhz" SITE "G1"; -IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; - -## Second USB port "US2" going directly into FPGA "usb", "ram" sheet -LOCATE COMP "ULX3S_USB_D_P" SITE "E16"; # single ended or differential input only -LOCATE COMP "ULX3S_USB_D_N" SITE "F16"; -IOBUF PORT "ULX3S_USB_D_P" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16; -IOBUF PORT "ULX3S_USB_D_N" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16; -LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional -LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; -IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "ULX3S_USB_DP_PU" SITE "B12"; # pull up/down control -LOCATE COMP "ULX3S_USB_DN_PU" SITE "C12"; -IOBUF PORT "ULX3S_USB_DP_PU" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; -IOBUF PORT "ULX3S_USB_DN_PU" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; - -## JTAG ESP-32 "usb" sheet -# connected to FT231X and ESP-32 -# commented out because those are dedicated pins, not directly useable as GPIO -# but could be used by some vendor-specific JTAG bridging (boundary scan) module -#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives -#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits -#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives -#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives -#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## SDRAM "ram" sheet -LOCATE COMP "sdram_clk" SITE "F19"; -LOCATE COMP "sdram_cke" SITE "F20"; -LOCATE COMP "sdram_csn" SITE "P20"; -LOCATE COMP "sdram_wen" SITE "T20"; -LOCATE COMP "sdram_rasn" SITE "R20"; -LOCATE COMP "sdram_casn" SITE "T19"; -LOCATE COMP "sdram_a[0]" SITE "M20"; -LOCATE COMP "sdram_a[1]" SITE "M19"; -LOCATE COMP "sdram_a[2]" SITE "L20"; -LOCATE COMP "sdram_a[3]" SITE "L19"; -LOCATE COMP "sdram_a[4]" SITE "K20"; -LOCATE COMP "sdram_a[5]" SITE "K19"; -LOCATE COMP "sdram_a[6]" SITE "K18"; -LOCATE COMP "sdram_a[7]" SITE "J20"; -LOCATE COMP "sdram_a[8]" SITE "J19"; -LOCATE COMP "sdram_a[9]" SITE "H20"; -LOCATE COMP "sdram_a[10]" SITE "N19"; -LOCATE COMP "sdram_a[11]" SITE "G20"; -LOCATE COMP "sdram_a[12]" SITE "G19"; -LOCATE COMP "sdram_ba[0]" SITE "P19"; -LOCATE COMP "sdram_ba[1]" SITE "N20"; -LOCATE COMP "sdram_dqm[0]" SITE "U19"; -LOCATE COMP "sdram_dqm[1]" SITE "E20"; -LOCATE COMP "sdram_d[0]" SITE "J16"; -LOCATE COMP "sdram_d[1]" SITE "L18"; -LOCATE COMP "sdram_d[2]" SITE "M18"; -LOCATE COMP "sdram_d[3]" SITE "N18"; -LOCATE COMP "sdram_d[4]" SITE "P18"; -LOCATE COMP "sdram_d[5]" SITE "T18"; -LOCATE COMP "sdram_d[6]" SITE "T17"; -LOCATE COMP "sdram_d[7]" SITE "U20"; -LOCATE COMP "sdram_d[8]" SITE "E19"; -LOCATE COMP "sdram_d[9]" SITE "D20"; -LOCATE COMP "sdram_d[10]" SITE "D19"; -LOCATE COMP "sdram_d[11]" SITE "C20"; -LOCATE COMP "sdram_d[12]" SITE "E18"; -LOCATE COMP "sdram_d[13]" SITE "F18"; -LOCATE COMP "sdram_d[14]" SITE "J18"; -LOCATE COMP "sdram_d[15]" SITE "J17"; -IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; - -# GPDI differential interface (Video) "gpdi" sheet -LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + -LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - -LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + -LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - -LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + -LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - -LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + -LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - -LOCATE COMP "gpdi_util" SITE "A19"; # add 10k parallel to C -LOCATE COMP "gpdi_hpd" SITE "B20"; # add 549ohm parallel to C -LOCATE COMP "gpdi_cec" SITE "A18"; -LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC -LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 -IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; -IOBUF PORT "gpdi_util" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_hpd" IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet -# Pins enumerated gp[0-27], gn[0-27]. -# With differential mode enabled on Lattice, -# gp[] (+) are used, gn[] (-) are ignored from design -# as they handle inverted signal by default. -# To enable differential, rename LVCMOS33->LVCMOS33D -# FEMALE ANGLED (90 deg PMOD) on TOP or -# MALE VERTICAL ( 0 deg pins) on BOTTOM and flat cable -LOCATE COMP "gp[0]" SITE "B11"; # PCLK -LOCATE COMP "gn[0]" SITE "C11"; # PCLK -LOCATE COMP "gp[1]" SITE "A10"; # PCLK -LOCATE COMP "gn[1]" SITE "A11"; # PCLK -LOCATE COMP "gp[2]" SITE "A9"; # GR_PCLK -LOCATE COMP "gn[2]" SITE "B10"; # GR_PCLK -LOCATE COMP "gp[3]" SITE "B9"; -LOCATE COMP "gn[3]" SITE "C10"; -LOCATE COMP "gp[4]" SITE "A7"; -LOCATE COMP "gn[4]" SITE "A8"; -LOCATE COMP "gp[5]" SITE "C8"; -LOCATE COMP "gn[5]" SITE "B8"; -LOCATE COMP "gp[6]" SITE "C6"; -LOCATE COMP "gn[6]" SITE "C7"; -IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp[7]" SITE "A6"; -LOCATE COMP "gn[7]" SITE "B6"; -LOCATE COMP "gp[8]" SITE "A4"; # DIFF -LOCATE COMP "gn[8]" SITE "A5"; # DIFF -LOCATE COMP "gp[9]" SITE "A2"; # DIFF -LOCATE COMP "gn[9]" SITE "B1"; # DIFF -LOCATE COMP "gp[10]" SITE "C4"; # DIFF -LOCATE COMP "gn[10]" SITE "B4"; # DIFF -LOCATE COMP "gp[11]" SITE "F4"; # DIFF wifi_gpio26 -LOCATE COMP "gn[11]" SITE "E3"; # DIFF wifi_gpio25 -LOCATE COMP "gp[12]" SITE "G3"; # DIFF wifi_gpio33 PCLK -LOCATE COMP "gn[12]" SITE "F3"; # DIFF wifi_gpio32 PCLK -LOCATE COMP "gp[13]" SITE "H4"; # DIFF wifi_gpio35 -LOCATE COMP "gn[13]" SITE "G5"; # DIFF wifi_gpio34 -IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[12]" PULLMODE=NONE IO_TYPE=LVCMOS33; -FREQUENCY PORT "gn[12]" 50 MHZ; -IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp[14]" SITE "U18"; # DIFF ADC AIN1 -LOCATE COMP "gn[14]" SITE "U17"; # DIFF ADC AIN0 -LOCATE COMP "gp[15]" SITE "N17"; # DIFF ADC AIN3 -LOCATE COMP "gn[15]" SITE "P16"; # DIFF ADC AIN2 -LOCATE COMP "gp[16]" SITE "N16"; # DIFF ADC AIN5 -LOCATE COMP "gn[16]" SITE "M17"; # DIFF ADC AIN4 -LOCATE COMP "gp[17]" SITE "L16"; # DIFF ADC AIN7 GR_PCLK -LOCATE COMP "gn[17]" SITE "L17"; # DIFF ADC AIN6 -LOCATE COMP "gp[18]" SITE "H18"; # DIFF -LOCATE COMP "gn[18]" SITE "H17"; # DIFF -LOCATE COMP "gp[19]" SITE "F17"; # DIFF -LOCATE COMP "gn[19]" SITE "G18"; # DIFF -LOCATE COMP "gp[20]" SITE "D18"; # DIFF -LOCATE COMP "gn[20]" SITE "E17"; # DIFF -IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp[21]" SITE "C18"; # DIFF -LOCATE COMP "gn[21]" SITE "D17"; # DIFF -LOCATE COMP "gp[22]" SITE "B15"; -LOCATE COMP "gn[22]" SITE "C15"; -LOCATE COMP "gp[23]" SITE "B17"; -LOCATE COMP "gn[23]" SITE "C17"; -LOCATE COMP "gp[24]" SITE "C16"; -LOCATE COMP "gn[24]" SITE "D16"; -LOCATE COMP "gp[25]" SITE "D14"; -LOCATE COMP "gn[25]" SITE "E14"; -LOCATE COMP "gp[26]" SITE "B13"; -LOCATE COMP "gn[26]" SITE "C13"; -LOCATE COMP "gp[27]" SITE "D13"; -LOCATE COMP "gn[27]" SITE "E13"; -IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## GPIO repeated as individual signals (non-vector) -# Allows mixed input, output, bidirectional, clock, differential -# If any of individual gp is used, then don't use gp[] vector. -# Same for gn and gn[]. -# FEMALE ANGLED (90 deg PMOD) on TOP or -# MALE VERTICAL ( 0 deg pins) on BOTTOM and flat cable -LOCATE COMP "gp0" SITE "B11"; # PCLK -LOCATE COMP "gn0" SITE "C11"; # PCLK -LOCATE COMP "gp1" SITE "A10"; # PCLK -LOCATE COMP "gn1" SITE "A11"; # PCLK -LOCATE COMP "gp2" SITE "A9"; # GR_PCLK -LOCATE COMP "gn2" SITE "B10"; # GR_PCLK -LOCATE COMP "gp3" SITE "B9"; -LOCATE COMP "gn3" SITE "C10"; -LOCATE COMP "gp4" SITE "A7"; -LOCATE COMP "gn4" SITE "A8"; -LOCATE COMP "gp5" SITE "C8"; -LOCATE COMP "gn5" SITE "B8"; -LOCATE COMP "gp6" SITE "C6"; -LOCATE COMP "gn6" SITE "C7"; -IOBUF PORT "gp0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp7" SITE "A6"; -LOCATE COMP "gn7" SITE "B6"; -LOCATE COMP "gp8" SITE "A4"; # DIFF -LOCATE COMP "gn8" SITE "A5"; # DIFF -LOCATE COMP "gp9" SITE "A2"; # DIFF -LOCATE COMP "gn9" SITE "B1"; # DIFF -LOCATE COMP "gp10" SITE "C4"; # DIFF -LOCATE COMP "gn10" SITE "B4"; # DIFF -LOCATE COMP "gp11" SITE "F4"; # DIFF wifi_gpio26 -LOCATE COMP "gn11" SITE "E3"; # DIFF wifi_gpio25 -LOCATE COMP "gp12" SITE "G3"; # DIFF wifi_gpio33 PCLK -LOCATE COMP "gn12" SITE "F3"; # DIFF wifi_gpio32 PCLK -LOCATE COMP "gp13" SITE "H4"; # DIFF wifi_gpio35 -LOCATE COMP "gn13" SITE "G5"; # DIFF wifi_gpio34 -# wifi sharing PCB v2.0.6-v3.0.8 -# prior to v2.0.6 see schematics -IOBUF PORT "gp7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -FREQUENCY PORT "gn12" 50 MHZ; -IOBUF PORT "gp13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp14" SITE "U18"; # DIFF ADC AIN1 -LOCATE COMP "gn14" SITE "U17"; # DIFF ADC AIN0 -LOCATE COMP "gp15" SITE "N17"; # DIFF ADC AIN3 -LOCATE COMP "gn15" SITE "P16"; # DIFF ADC AIN2 -LOCATE COMP "gp16" SITE "N16"; # DIFF ADC AIN5 -LOCATE COMP "gn16" SITE "M17"; # DIFF ADC AIN4 -LOCATE COMP "gp17" SITE "L16"; # DIFF ADC AIN7 GR_PCLK -LOCATE COMP "gn17" SITE "L17"; # DIFF ADC AIN6 -LOCATE COMP "gp18" SITE "H18"; # DIFF -LOCATE COMP "gn18" SITE "H17"; # DIFF -LOCATE COMP "gp19" SITE "F17"; # DIFF -LOCATE COMP "gn19" SITE "G18"; # DIFF -LOCATE COMP "gp20" SITE "D18"; # DIFF -LOCATE COMP "gn20" SITE "E17"; # DIFF -IOBUF PORT "gp14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "gp21" SITE "C18"; # DIFF -LOCATE COMP "gn21" SITE "D17"; # DIFF -LOCATE COMP "gp22" SITE "B15"; -LOCATE COMP "gn22" SITE "C15"; -LOCATE COMP "gp23" SITE "B17"; -LOCATE COMP "gn23" SITE "C17"; -LOCATE COMP "gp24" SITE "C16"; -LOCATE COMP "gn24" SITE "D16"; -LOCATE COMP "gp25" SITE "D14"; -LOCATE COMP "gn25" SITE "E14"; -LOCATE COMP "gp26" SITE "B13"; -LOCATE COMP "gn26" SITE "C13"; -LOCATE COMP "gp27" SITE "D13"; -LOCATE COMP "gn27" SITE "E13"; -IOBUF PORT "gp21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gp27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "gn27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## PROGRAMN (reload bitstream from FLASH, exit from bootloader) -# PCB v2.0.5 and higher -LOCATE COMP "user_programn" SITE "M4"; -IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) -# on PCB v1.7 shutdown is not connected to FPGA -LOCATE COMP "shutdown" SITE "G16"; # FPGA receives -IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; Index: neorv32/trunk/setups/osflow/constraints/AlhambraII.pcf =================================================================== --- neorv32/trunk/setups/osflow/constraints/AlhambraII.pcf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/AlhambraII.pcf (nonexistent) @@ -1,24 +0,0 @@ -# ----------------------------------------------------------------------------- -#- Alhambra II constraint file (.pcf) -#- By Carlos Dominguez -#- May - 2021 -#- GPL license -#- Repo: https://github.com/zipotron/neorv32 -# ----------------------------------------------------------------------------- - -# UART port (on-board FTDI) -set_io AlhambraII_TX 61 # output (ser-tx) -set_io AlhambraII_RX 62 # input (ser-rx) - -#> External clock (12 MHz) -set_io AlhambraII_CLK 49 - -#> On-Board LEDs -set_io AlhambraII_LED0 45 -set_io AlhambraII_LED1 44 -set_io AlhambraII_LED2 43 -set_io AlhambraII_LED3 42 -set_io AlhambraII_LED4 41 -set_io AlhambraII_LED5 39 -set_io AlhambraII_LED6 38 -set_io AlhambraII_LED7 37 Index: neorv32/trunk/setups/osflow/constraints/UPduino_v3.pcf =================================================================== --- neorv32/trunk/setups/osflow/constraints/UPduino_v3.pcf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/UPduino_v3.pcf (nonexistent) @@ -1,36 +0,0 @@ -## UART (uart0) -set_io uart_txd_o 38 -set_io uart_rxd_i 28 - -## SPI - on-board flash -set_io flash_sdo_o 14 -set_io flash_sck_o 15 -set_io flash_csn_o 16 -set_io flash_sdi_i 17 - -## SPI - user port -set_io spi_sdo_o 34 -set_io spi_sck_o 43 -set_io spi_csn_o 36 -set_io spi_sdi_i 42 - -## TWI -set_io twi_sda_io 31 -set_io twi_scl_io 37 - -## GPIO - input -set_io gpio_i[0] 44 -set_io gpio_i[1] 4 -set_io gpio_i[2] 3 -set_io gpio_i[3] 48 - -## GPIO - output -set_io gpio_o[0] 45 -set_io gpio_o[1] 47 -set_io gpio_o[2] 46 -set_io gpio_o[3] 2 - -## RGB power LED -set_io pwm_o[0] 39 -set_io pwm_o[1] 40 -set_io pwm_o[2] 41 Index: neorv32/trunk/setups/osflow/constraints/iCEBreaker.pcf =================================================================== --- neorv32/trunk/setups/osflow/constraints/iCEBreaker.pcf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/iCEBreaker.pcf (nonexistent) @@ -1,39 +0,0 @@ -## UART (uart0) -set_io uart_txd_o 9 -set_io uart_rxd_i 6 - -## SPI - on-board flash -set_io flash_sdo_o 14 -set_io flash_sck_o 15 -set_io flash_csn_o 16 -set_io flash_sdi_i 17 - -## SPI - user port -set_io spi_sdo_o 43 -set_io spi_sck_o 38 -set_io spi_csn_o 34 -set_io spi_sdi_i 31 - -## TWI -set_io twi_sda_io 2 -set_io twi_scl_io 4 - -## GPIO - input -set_io gpio_i[0] 18 -set_io gpio_i[1] 19 -set_io gpio_i[2] 20 -set_io gpio_i[3] 28 - -## GPIO - output -set_io gpio_o[0] 25 -set_io gpio_o[1] 26 -set_io gpio_o[2] 27 -set_io gpio_o[3] 23 - -## RGB power LED -set_io pwm_o[0] 39 -set_io pwm_o[1] 40 -set_io pwm_o[2] 41 - -#User Reset Btn -set_io user_reset_btn 10 Index: neorv32/trunk/setups/osflow/constraints/OrangeCrab.lpf =================================================================== --- neorv32/trunk/setups/osflow/constraints/OrangeCrab.lpf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/OrangeCrab.lpf (nonexistent) @@ -1,278 +0,0 @@ -#| OrangeCrab-r02-25F - - -LOCATE COMP "OrangeCrab_CLK" SITE "A9"; -IOBUF PORT "OrangeCrab_CLK" IO_TYPE=LVCMOS33; -FREQUENCY PORT "OrangeCrab_CLK" 48.0 MHz; - -LOCATE COMP "OrangeCrab_RST_N" SITE "V17"; -IOBUF PORT "OrangeCrab_RST_N" IO_TYPE=LVCMOS33; - -LOCATE COMP "OrangeCrab_LED_RGB_R" SITE "K4"; -IOBUF PORT "OrangeCrab_LED_RGB_R" IO_TYPE=LVCMOS33; -LOCATE COMP "OrangeCrab_LED_RGB_G" SITE "M3"; -IOBUF PORT "OrangeCrab_LED_RGB_G" IO_TYPE=LVCMOS33; -LOCATE COMP "OrangeCrab_LED_RGB_B" SITE "J3"; -IOBUF PORT "OrangeCrab_LED_RGB_B" IO_TYPE=LVCMOS33; - -LOCATE COMP "OrangeCrab_USR_BTN" SITE "J17"; -IOBUF PORT "OrangeCrab_USR_BTN" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_USB_D_P" SITE "N1"; -IOBUF PORT "OrangeCrab_USB_D_P" IO_TYPE=LVCMOS33; -LOCATE COMP "OrangeCrab_USB_D_N" SITE "M2"; -IOBUF PORT "OrangeCrab_USB_D_N" IO_TYPE=LVCMOS33; -LOCATE COMP "OrangeCrab_USB_DP_PU" SITE "N2"; -IOBUF PORT "OrangeCrab_USB_DP_PU" IO_TYPE=LVCMOS33; - -LOCATE COMP "OrangeCrab_GPIO_0" SITE "N17"; -IOBUF PORT "OrangeCrab_GPIO_0" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_0" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_1" SITE "M18"; -IOBUF PORT "OrangeCrab_GPIO_1" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_1" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_5" SITE "B10"; -IOBUF PORT "OrangeCrab_GPIO_5" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_5" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_6" SITE "B9"; -IOBUF PORT "OrangeCrab_GPIO_6" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_6" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_9" SITE "C8"; -IOBUF PORT "OrangeCrab_GPIO_9" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_9" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_10" SITE "B8"; -IOBUF PORT "OrangeCrab_GPIO_10" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_10" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_11" SITE "A8"; -IOBUF PORT "OrangeCrab_GPIO_11" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_11" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_12" SITE "H2"; -IOBUF PORT "OrangeCrab_GPIO_12" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_12" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_13" SITE "J2"; -IOBUF PORT "OrangeCrab_GPIO_13" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_13" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_A0" SITE "L4"; -IOBUF PORT "OrangeCrab_GPIO_A0" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_A0" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_A1" SITE "N3"; -IOBUF PORT "OrangeCrab_GPIO_A1" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_A1" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_A2" SITE "N4"; -IOBUF PORT "OrangeCrab_GPIO_A2" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_A2" PULLMODE=DOWN; -LOCATE COMP "OrangeCrab_GPIO_A3" SITE "H4"; -IOBUF PORT "OrangeCrab_GPIO_A3" IO_TYPE=LVCMOS33; -IOBUF PORT "OrangeCrab_GPIO_A3" PULLMODE=DOWN; - -LOCATE COMP "OrangeCrab_DDRAM_A[0]" SITE "C4"; -IOBUF PORT "OrangeCrab_DDRAM_A[0]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[0]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[1]" SITE "D2"; -IOBUF PORT "OrangeCrab_DDRAM_A[1]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[1]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[2]" SITE "D3"; -IOBUF PORT "OrangeCrab_DDRAM_A[2]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[2]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[3]" SITE "A3"; -IOBUF PORT "OrangeCrab_DDRAM_A[3]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[3]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[4]" SITE "A4"; -IOBUF PORT "OrangeCrab_DDRAM_A[4]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[4]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[5]" SITE "D4"; -IOBUF PORT "OrangeCrab_DDRAM_A[5]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[5]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[6]" SITE "C3"; -IOBUF PORT "OrangeCrab_DDRAM_A[6]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[6]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[7]" SITE "B2"; -IOBUF PORT "OrangeCrab_DDRAM_A[7]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[7]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[8]" SITE "B1"; -IOBUF PORT "OrangeCrab_DDRAM_A[8]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[8]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[9]" SITE "D1"; -IOBUF PORT "OrangeCrab_DDRAM_A[9]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[9]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[10]" SITE "A7"; -IOBUF PORT "OrangeCrab_DDRAM_A[10]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[10]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[11]" SITE "C2"; -IOBUF PORT "OrangeCrab_DDRAM_A[11]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[11]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[12]" SITE "B6"; -IOBUF PORT "OrangeCrab_DDRAM_A[12]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[12]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[13]" SITE "C1"; -IOBUF PORT "OrangeCrab_DDRAM_A[13]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[13]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[14]" SITE "A2"; -IOBUF PORT "OrangeCrab_DDRAM_A[14]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[14]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_A[15]" SITE "C7"; -IOBUF PORT "OrangeCrab_DDRAM_A[15]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_A[15]" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_BA[0]" SITE "D6"; -IOBUF PORT "OrangeCrab_DDRAM_BA[0]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_BA[0]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_BA[1]" SITE "B7"; -IOBUF PORT "OrangeCrab_DDRAM_BA[1]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_BA[1]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_BA[2]" SITE "A6"; -IOBUF PORT "OrangeCrab_DDRAM_BA[2]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_BA[2]" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_RAS_N" SITE "C12"; -IOBUF PORT "OrangeCrab_DDRAM_RAS_N" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_RAS_N" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_CAS_N" SITE "D13"; -IOBUF PORT "OrangeCrab_DDRAM_CAS_N" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_CAS_N" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_WE_N" SITE "B12"; -IOBUF PORT "OrangeCrab_DDRAM_WE_N" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_WE_N" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_CS_N" SITE "A12"; -IOBUF PORT "OrangeCrab_DDRAM_CS_N" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_CS_N" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_DM[0]" SITE "D16"; -IOBUF PORT "OrangeCrab_DDRAM_DM[0]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DM[0]" IO_TYPE=SSTL135_I; -LOCATE COMP "OrangeCrab_DDRAM_DM[1]" SITE "G16"; -IOBUF PORT "OrangeCrab_DDRAM_DM[1]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DM[1]" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_DQ[0]" SITE "C17"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[1]" SITE "D15"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[2]" SITE "B17"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[3]" SITE "C16"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[4]" SITE "A15"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[5]" SITE "B13"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[6]" SITE "A17"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[7]" SITE "A13"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[8]" SITE "F17"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[9]" SITE "F16"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[10]" SITE "G15"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[11]" SITE "F15"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[12]" SITE "J16"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[13]" SITE "C18"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[14]" SITE "H16"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" TERMINATION=OFF; -LOCATE COMP "OrangeCrab_DDRAM_DQ[15]" SITE "F18"; -IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" IO_TYPE=SSTL135_I; -IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" TERMINATION=OFF; - -LOCATE COMP "OrangeCrab_DDRAM_DQS_P[0]" SITE "B15"; -IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" IO_TYPE=SSTL135D_I; -IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" TERMINATION=OFF; -IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" DIFFRESISTOR=100; -LOCATE COMP "OrangeCrab_DDRAM_DQS_P[1]" SITE "G18"; -IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" IO_TYPE=SSTL135D_I; -IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" TERMINATION=OFF; -IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" DIFFRESISTOR=100; - -LOCATE COMP "OrangeCrab_DDRAM_CLK_P" SITE "J18"; -IOBUF PORT "OrangeCrab_DDRAM_CLK_P" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_CLK_P" IO_TYPE=SSTL135D_I; - -LOCATE COMP "OrangeCrab_DDRAM_CKE" SITE "D18"; -IOBUF PORT "OrangeCrab_DDRAM_CKE" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_CKE" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_ODT" SITE "C13"; -IOBUF PORT "OrangeCrab_DDRAM_ODT" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_ODT" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_RESET_N" SITE "L18"; -IOBUF PORT "OrangeCrab_DDRAM_RESET_N" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_RESET_N" IO_TYPE=SSTL135_I; - -LOCATE COMP "OrangeCrab_DDRAM_VCCIO[0]" SITE "K16"; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[0]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[0]" IO_TYPE=SSTL135_II; -LOCATE COMP "OrangeCrab_DDRAM_VCCIO[1]" SITE "D17"; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[1]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[1]" IO_TYPE=SSTL135_II; -LOCATE COMP "OrangeCrab_DDRAM_VCCIO[2]" SITE "K15"; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[2]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[2]" IO_TYPE=SSTL135_II; -LOCATE COMP "OrangeCrab_DDRAM_VCCIO[3]" SITE "K17"; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[3]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[3]" IO_TYPE=SSTL135_II; -LOCATE COMP "OrangeCrab_DDRAM_VCCIO[4]" SITE "B18"; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[4]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[4]" IO_TYPE=SSTL135_II; -LOCATE COMP "OrangeCrab_DDRAM_VCCIO[5]" SITE "C6"; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[5]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_VCCIO[5]" IO_TYPE=SSTL135_II; - -LOCATE COMP "OrangeCrab_DDRAM_GND[0]" SITE "L15"; -IOBUF PORT "OrangeCrab_DDRAM_GND[0]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_GND[0]" IO_TYPE=SSTL135_II; -LOCATE COMP "OrangeCrab_DDRAM_GND[1]" SITE "L16"; -IOBUF PORT "OrangeCrab_DDRAM_GND[1]" SLEWRATE=FAST; -IOBUF PORT "OrangeCrab_DDRAM_GND[1]" IO_TYPE=SSTL135_II; - -LOCATE COMP "OrangeCrab_SPIFLASH_CS_N" SITE "U17"; -IOBUF PORT "OrangeCrab_SPIFLASH_CS_N" IO_TYPE=LVCMOS33; - -LOCATE COMP "OrangeCrab_SPIFLASH_DQ[0]" SITE "U18"; -IOBUF PORT "OrangeCrab_SPIFLASH_DQ[0]" IO_TYPE=LVCMOS33; -LOCATE COMP "OrangeCrab_SPIFLASH_DQ[1]" SITE "T18"; -IOBUF PORT "OrangeCrab_SPIFLASH_DQ[1]" IO_TYPE=LVCMOS33; -LOCATE COMP "OrangeCrab_SPIFLASH_DQ[2]" SITE "R18"; -IOBUF PORT "OrangeCrab_SPIFLASH_DQ[2]" IO_TYPE=LVCMOS33; -LOCATE COMP "OrangeCrab_SPIFLASH_DQ[3]" SITE "N18"; -IOBUF PORT "OrangeCrab_SPIFLASH_DQ[3]" IO_TYPE=LVCMOS33; Index: neorv32/trunk/setups/osflow/constraints/Fomu-pvt.pcf =================================================================== --- neorv32/trunk/setups/osflow/constraints/Fomu-pvt.pcf (revision 70) +++ neorv32/trunk/setups/osflow/constraints/Fomu-pvt.pcf (nonexistent) @@ -1,18 +0,0 @@ -# Configuration for the Fomu 'pvt' board -set_io clki F4 # Clock input from 48MHz Oscillator -set_io rgb[0] A5 # Blue LED -set_io rgb[1] B5 # Green LED -set_io rgb[2] C5 # Red LED -set_io user[0] E4 # User touch pad 1 -set_io user[1] D5 # User touch pad 2 -set_io user[2] E5 # User touch pad 3 -set_io user[3] F5 # User touch pad 4 -set_io spi_mosi F1 # SPI Master Out, Slave In Pin -set_io spi_miso E1 # SPI Master In, Slave Out Pin -set_io spi_clk D1 # SPI Master Clock Output Pin -set_io spi_cs C1 # SPI Chip Select -set_io spi_io2 F2 -set_io spi_io3 B1 -set_io usb_dn A2 # USB D- pad -set_io usb_dp A1 # USB D+ pad -set_io usb_dp_pu A4 # USB D+ pull up (indicates device connected) Index: neorv32/trunk/setups/osflow/boards/ULX3S.mk =================================================================== --- neorv32/trunk/setups/osflow/boards/ULX3S.mk (revision 70) +++ neorv32/trunk/setups/osflow/boards/ULX3S.mk (nonexistent) @@ -1,4 +0,0 @@ -.PHONY: all - -all: bit - echo "! Built $(IMPL) for $(BOARD)" Index: neorv32/trunk/setups/osflow/boards/iCESugar.mk =================================================================== --- neorv32/trunk/setups/osflow/boards/iCESugar.mk (revision 70) +++ neorv32/trunk/setups/osflow/boards/iCESugar.mk (nonexistent) @@ -1,4 +0,0 @@ -.PHONY: all - -all: bit - echo "! Built $(IMPL) for $(BOARD)" Index: neorv32/trunk/setups/osflow/boards/OrangeCrab.mk =================================================================== --- neorv32/trunk/setups/osflow/boards/OrangeCrab.mk (revision 70) +++ neorv32/trunk/setups/osflow/boards/OrangeCrab.mk (nonexistent) @@ -1,4 +0,0 @@ -.PHONY: all - -all: bit - echo "! Built $(IMPL) for $(BOARD)" Index: neorv32/trunk/setups/osflow/boards/UPduino.mk =================================================================== --- neorv32/trunk/setups/osflow/boards/UPduino.mk (revision 70) +++ neorv32/trunk/setups/osflow/boards/UPduino.mk (nonexistent) @@ -1,4 +0,0 @@ -.PHONY: all - -all: bit - echo "! Built $(IMPL) for $(BOARD)" Index: neorv32/trunk/setups/osflow/boards/Fomu.mk =================================================================== --- neorv32/trunk/setups/osflow/boards/Fomu.mk (revision 70) +++ neorv32/trunk/setups/osflow/boards/Fomu.mk (nonexistent) @@ -1,16 +0,0 @@ -.PHONY: all - -# Default target: run all required targets to build the DFU image. -all: $(IMPL).dfu - echo "! Built $(IMPL) for $(BOARD) $(FOMU_REV)" - -# Use dfu-suffix to generate the DFU image from the FPGA bitstream. -${IMPL}.dfu: $(IMPL).bit - $(COPY) $< $@ - dfu-suffix -v 1209 -p 70b1 -a $@ - -# Use df-util to load the DFU image onto the Fomu. -load: $(IMPL).dfu - dfu-util -D $< - -.PHONY: load Index: neorv32/trunk/setups/osflow/boards/index.mk =================================================================== --- neorv32/trunk/setups/osflow/boards/index.mk (revision 70) +++ neorv32/trunk/setups/osflow/boards/index.mk (nonexistent) @@ -1,107 +0,0 @@ -PCF_PATH ?= constraints - - -ifeq ($(BOARD),Fomu) - -$(info Setting constraints and implementation args for BOARD Fomu) - -# Different Fomu hardware revisions are wired differently and thus -# require different configurations for yosys and nextpnr. -# Configuration is performed by setting the environment variable FOMU_REV accordingly. - -FOMU_REV ?= pvt - -ifeq ($(FOMU_REV),evt1) -YOSYSFLAGS ?= -D EVT=1 -D EVT1=1 -D HAVE_PMOD=1 -PNRFLAGS ?= --up5k --package sg48 -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-evt2.pcf -else ifeq ($(FOMU_REV),evt2) -YOSYSFLAGS ?= -D EVT=1 -D EVT2=1 -D HAVE_PMOD=1 -PNRFLAGS ?= --up5k --package sg48 -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf -else ifeq ($(FOMU_REV),evt3) -YOSYSFLAGS ?= -D EVT=1 -D EVT3=1 -D HAVE_PMOD=1 -PNRFLAGS ?= --up5k --package sg48 -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf -else ifeq ($(FOMU_REV),hacker) -YOSYSFLAGS ?= -D HACKER=1 -PNRFLAGS ?= --up5k --package uwg30 -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf -else ifeq ($(FOMU_REV),pvt) -YOSYSFLAGS ?= -D PVT=1 -PNRFLAGS ?= --up5k --package uwg30 -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf -else -$(error Unrecognized FOMU_REV value. must be "evt1", "evt2", "evt3", "pvt", or "hacker") -endif - -IMPL := neorv32_Fomu_$(FOMU_REV)_$(ID) - -endif - - -ifeq ($(BOARD),iCESugar) -$(info Setting constraints and implementation args for BOARD iCESugar) - -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf -PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail -IMPL ?= neorv32_$(BOARD)_$(ID) - -endif - - -ifeq ($(BOARD),UPduino) -$(info Setting constraints and implementation args for BOARD UPduino) - -UPduino_REV ?= v3 - -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)_v3.pcf -PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail -IMPL ?= neorv32_$(BOARD)_$(UPduino_REV)_$(ID) - -endif - -ifeq ($(BOARD),iCEBreaker) -$(info Setting constraints and implementation args for BOARD iCEBreaker) - -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf -PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail -IMPL ?= neorv32_$(BOARD)_$(ID) - -endif - - - -ifeq ($(BOARD),OrangeCrab) -$(info Setting constraints and implementation args for BOARD OrangeCrab) - -DEVICE_SERIES = ecp5 - -OrangeCrab_REV ?= r02-25F - -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).lpf -PNRFLAGS ?= --25k --package CSFBGA285 --ignore-loops --timing-allow-fail -IMPL ?= neorv32_$(BOARD)_$(OrangeCrab_REV)_$(ID) - -endif - -ifeq ($(BOARD),AlhambraII) -$(info Setting constraints and implementation args for BOARD AlhambraII) - -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf -PNRFLAGS ?= --hx8k --package tq144:4k --ignore-loops --timing-allow-fail -IMPL ?= neorv32_$(BOARD)_$(ID) - -endif - - -ifeq ($(BOARD),ULX3S) -$(info Setting constraints and implementation args for BOARD ULX3S) - -DEVICE_SERIES = ecp5 - -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).lpf -PNRFLAGS ?= --85k --freq 25 --package CABGA381 --ignore-loops --timing-allow-fail -IMPL ?= neorv32_$(BOARD)_$(ID) - -endif Index: neorv32/trunk/setups/osflow/boards/AlhambraII.mk =================================================================== --- neorv32/trunk/setups/osflow/boards/AlhambraII.mk (revision 70) +++ neorv32/trunk/setups/osflow/boards/AlhambraII.mk (nonexistent) @@ -1,4 +0,0 @@ -.PHONY: all - -all: bit - echo "! Built $(IMPL) for $(BOARD)" Index: neorv32/trunk/setups/osflow/boards/iCEBreaker.mk =================================================================== --- neorv32/trunk/setups/osflow/boards/iCEBreaker.mk (revision 70) +++ neorv32/trunk/setups/osflow/boards/iCEBreaker.mk (nonexistent) @@ -1,4 +0,0 @@ -.PHONY: all - -all: bit - echo "! Built $(IMPL) for $(BOARD)" Index: neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd (nonexistent) @@ -1,185 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup for the Fomu (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_Fomu_BoardTop_UP5KDemo is - port ( - -- 48MHz Clock input - clki : in std_logic; - -- LED outputs - rgb : out std_logic_vector(2 downto 0); - -- USB Pins (which should be statically driven if not being used) - usb_dp : out std_logic; - usb_dn : out std_logic; - usb_dp_pu : out std_logic - ); -end entity; - -architecture neorv32_Fomu_BoardTop_UP5KDemo_rtl of neorv32_Fomu_BoardTop_UP5KDemo is - - -- configuration -- - constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz - - -- On-chip oscillator -- - signal hf_osc_clk : std_logic; - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_pwm : std_ulogic_vector(2 downto 0); - signal con_gpio_o : std_ulogic_vector(3 downto 0); - -begin - - -- Assign USB pins to "0" so as to disconnect Fomu from - -- the host system. Otherwise it would try to talk to - -- us over USB, which wouldn't work since we have no stack. - usb_dp <= '0'; - usb_dn <= '0'; - usb_dp_pu <= '0'; - - -- On-Chip HF Oscillator ------------------------------------------------------------------ - -- ------------------------------------------------------------------------------------------- - HSOSC_inst : SB_HFOSC - generic map ( - CLKHF_DIV => "0b10" -- 12 MHz - ) - port map ( - CLKHFPU => '1', - CLKHFEN => '1', - CLKHF => hf_osc_clk - ); - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 12 -o 18: - -- F_PLLIN: 12.000 MHz (given) - -- F_PLLOUT: 18.000 MHz (requested) - -- F_PLLOUT: 18.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 12.000 MHz - -- F_VCO: 576.000 MHz - -- DIVR: 0 (4'b0000) - -- DIVF: 47 (7'b0101111) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_CORE - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"0", - DIVF => 7x"2F", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - REFERENCECLK => hf_osc_clk, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => '1', - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - -- primary UART -- - uart_txd_o => open, - uart_rxd_i => '0', - uart_rts_o => open, - uart_cts_i => '0', - -- SPI to on-board flash -- - flash_sck_o => open, - flash_sdo_o => open, - flash_sdi_i => '0', - flash_csn_o => open, - -- SPI to IO pins -- - spi_sck_o => open, - spi_sdo_o => open, - spi_sdi_i => '0', - spi_csn_o => open, - -- TWI -- - twi_sda_io => open, - twi_scl_io => open, - -- GPIO -- - gpio_i => (others=>'0'), - gpio_o => con_gpio_o, - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000011", - RGB1_CURRENT => "0b000011", - RGB2_CURRENT => "0b000011" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 - RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink - RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 - RGB2 => rgb(2), -- O - blue - RGB1 => rgb(1), -- O - red - RGB0 => rgb(0) -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd (nonexistent) @@ -1,174 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup including the bootloader, for the Fomu (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_Fomu_BoardTop_MinimalBoot is - port ( - -- 48MHz Clock input - clki : in std_logic; - -- LED outputs - rgb : out std_logic_vector(2 downto 0); - -- USB Pins (which should be statically driven if not being used) - usb_dp : out std_logic; - usb_dn : out std_logic; - usb_dp_pu : out std_logic - ); -end entity; - -architecture neorv32_Fomu_BoardTop_MinimalBoot_rtl of neorv32_Fomu_BoardTop_MinimalBoot is - - -- configuration -- - constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz - - -- On-chip oscillator -- - signal hf_osc_clk : std_logic; - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_gpio_o : std_ulogic_vector(3 downto 0); - signal con_pwm : std_logic_vector(2 downto 0); - -begin - - -- Assign USB pins to "0" so as to disconnect Fomu from - -- the host system. Otherwise it would try to talk to - -- us over USB, which wouldn't work since we have no stack. - usb_dp <= '0'; - usb_dn <= '0'; - usb_dp_pu <= '0'; - - -- On-Chip HF Oscillator ------------------------------------------------------------------ - -- ------------------------------------------------------------------------------------------- - HSOSC_inst : SB_HFOSC - generic map ( - CLKHF_DIV => "0b10" -- 12 MHz - ) - port map ( - CLKHFPU => '1', - CLKHFEN => '1', - CLKHF => hf_osc_clk - ); - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 12 -o 18: - -- F_PLLIN: 12.000 MHz (given) - -- F_PLLOUT: 18.000 MHz (requested) - -- F_PLLOUT: 18.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 12.000 MHz - -- F_VCO: 576.000 MHz - -- DIVR: 0 (4'b0000) - -- DIVF: 47 (7'b0101111) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_CORE - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"0", - DIVF => 7x"2F", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - REFERENCECLK => hf_osc_clk, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => '1', - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- GPIO -- - gpio_o => con_gpio_o, - - -- primary UART -- - uart_txd_o => open, -- UART0 send data - uart_rxd_i => '0', -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000011", - RGB1_CURRENT => "0b000011", - RGB2_CURRENT => "0b000011" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 - RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink - RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 - RGB2 => rgb(2), -- O - blue - RGB1 => rgb(1), -- O - red - RGB0 => rgb(0) -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd (nonexistent) @@ -1,139 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup including the bootloader, for the Fomu (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_Fomu_BoardTop_MixedLanguage is - port ( - -- 48MHz Clock input - clki : in std_logic; - -- LED outputs - rgb : out std_logic_vector(2 downto 0); - -- USB Pins (which should be statically driven if not being used) - usb_dp : out std_logic; - usb_dn : out std_logic; - usb_dp_pu : out std_logic - ); -end entity; - -architecture neorv32_Fomu_BoardTop_MixedLanguage_rtl of neorv32_Fomu_BoardTop_MixedLanguage is - - -- configuration -- - constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz - - component neorv32_Fomu_MixedLanguage_ClkGen - port ( - clk_o : out std_logic; - rstn_o : out std_logic - ); - end component; - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_gpio_o : std_ulogic_vector(3 downto 0); - signal con_pwm : std_logic_vector(2 downto 0); - -begin - - -- Assign USB pins to "0" so as to disconnect Fomu from - -- the host system. Otherwise it would try to talk to - -- us over USB, which wouldn't work since we have no stack. - usb_dp <= '0'; - usb_dn <= '0'; - usb_dp_pu <= '0'; - - -- On-Chip HF Oscillator and System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - Clk_inst : neorv32_Fomu_MixedLanguage_ClkGen - port map ( - clk_o => pll_clk, - rstn_o => pll_rstn - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- GPIO -- - gpio_o => con_gpio_o, - - -- primary UART -- - uart_txd_o => open, -- UART0 send data - uart_rxd_i => '0', -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000011", - RGB1_CURRENT => "0b000011", - RGB2_CURRENT => "0b000011" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 - RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink - RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 - RGB2 => rgb(2), -- O - blue - RGB1 => rgb(1), -- O - red - RGB0 => rgb(0) -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd (nonexistent) @@ -1,128 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup including the bootloader, for the AlhambraII (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_AlhambraII_BoardTop_MinimalBoot is - port ( - -- external clock (12 MHz) - AlhambraII_CLK : in std_logic; - -- LED outputs - AlhambraII_LED0 : out std_logic; - AlhambraII_LED1 : out std_logic; - AlhambraII_LED2 : out std_logic; - AlhambraII_LED3 : out std_logic; - AlhambraII_LED4 : out std_logic; - AlhambraII_LED5 : out std_logic; - AlhambraII_LED6 : out std_logic; - AlhambraII_LED7 : out std_logic; - -- UART0 - AlhambraII_RX : in std_logic; - AlhambraII_TX : out std_logic - ); -end entity; - -architecture neorv32_AlhambraII_BoardTop_MinimalBoot_rtl of neorv32_AlhambraII_BoardTop_MinimalBoot is - - -- configuration -- - constant f_clock_c : natural := 12000000; -- clock frequency in Hz - - -- reset generator -- - signal rst_cnt : std_logic_vector(8 downto 0) := (others => '0'); -- initialized by bitstream - signal sys_rstn : std_logic; - - -- internal IO connection -- - signal con_gpio_o : std_ulogic_vector(3 downto 0); - signal con_pwm : std_logic_vector(2 downto 0); - -begin - - -- Reset Generator ------------------------------------------------------------------------ - -- ------------------------------------------------------------------------------------------- - reset_generator: process(AlhambraII_CLK) - begin - if rising_edge(AlhambraII_CLK) then - if (rst_cnt(rst_cnt'left) = '0') then - rst_cnt <= std_logic_vector(unsigned(rst_cnt) + 1); - end if; - end if; - end process reset_generator; - - sys_rstn <= rst_cnt(rst_cnt'left); - - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz - MEM_INT_IMEM_SIZE => 4*1024, -- size of processor-internal instruction memory in bytes - MEM_INT_DMEM_SIZE => 2*1024 -- size of processor-internal data memory in bytes - ) - port map ( - -- Global control -- - clk_i => std_ulogic(AlhambraII_CLK), - rstn_i => std_ulogic(sys_rstn), - - -- GPIO -- - gpio_o => con_gpio_o, - - -- primary UART -- - uart_txd_o => AlhambraII_TX, -- UART0 send data - uart_rxd_i => AlhambraII_RX, -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - AlhambraII_LED0 <= con_gpio_o(0); - AlhambraII_LED1 <= con_gpio_o(1); - AlhambraII_LED2 <= con_gpio_o(2); - AlhambraII_LED3 <= con_gpio_o(3); - AlhambraII_LED4 <= '0'; -- unused - AlhambraII_LED5 <= con_pwm(0); - AlhambraII_LED6 <= con_pwm(1); - AlhambraII_LED7 <= con_pwm(2); - - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_UP5KDemo.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_UP5KDemo.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_UP5KDemo.vhd (nonexistent) @@ -1,205 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_iCEBreaker_BoardTop_UP5KDemo is - port ( - user_reset_btn : in std_ulogic; - -- UART (uart0) -- - uart_txd_o : out std_ulogic; - uart_rxd_i : in std_ulogic; - -- SPI to on-board flash -- - flash_sck_o : out std_ulogic; - flash_sdo_o : out std_ulogic; - flash_sdi_i : in std_ulogic; - flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0) - -- SPI to IO pins -- - spi_sck_o : out std_ulogic; - spi_sdo_o : out std_ulogic; - spi_sdi_i : in std_ulogic; - spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1) - -- TWI -- - twi_sda_io : inout std_logic; - twi_scl_io : inout std_logic; - -- GPIO -- - gpio_i : in std_ulogic_vector(3 downto 0); - gpio_o : out std_ulogic_vector(3 downto 0); - -- PWM (to on-board RGB power LED) -- - pwm_o : out std_ulogic_vector(2 downto 0) - ); -end entity; - -architecture neorv32_iCEBreaker_BoardTop_UP5KDemo_rtl of neorv32_iCEBreaker_BoardTop_UP5KDemo is - - -- configuration -- - constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz - - -- On-chip oscillator -- - signal hf_osc_clk : std_logic; - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_pwm : std_ulogic_vector(2 downto 0); - signal con_spi_sdi : std_ulogic; - signal con_spi_csn : std_ulogic; - -begin - - -- On-Chip HF Oscillator ------------------------------------------------------------------ - -- ------------------------------------------------------------------------------------------- - HSOSC_inst : SB_HFOSC - generic map ( - CLKHF_DIV => "0b10" -- 12 MHz - ) - port map ( - CLKHFPU => '1', - CLKHFEN => '1', - CLKHF => hf_osc_clk - ); - - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 12 -o 18: - -- F_PLLIN: 12.000 MHz (given) - -- F_PLLOUT: 18.000 MHz (requested) - -- F_PLLOUT: 18.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 12.000 MHz - -- F_VCO: 576.000 MHz - -- DIVR: 0 (4'b0000) - -- DIVF: 47 (7'b0101111) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_CORE - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"0", - DIVF => 7x"2F", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - REFERENCECLK => hf_osc_clk, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => user_reset_btn, - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- primary UART -- - uart_txd_o => uart_txd_o, - uart_rxd_i => uart_rxd_i, - uart_rts_o => open, - uart_cts_i => '0', - - -- SPI to on-board flash -- - flash_sck_o => flash_sck_o, - flash_sdo_o => flash_sdo_o, - flash_sdi_i => flash_sdi_i, - flash_csn_o => flash_csn_o, - - -- SPI to IO pins -- - spi_sck_o => spi_sck_o, - spi_sdo_o => spi_sdo_o, - spi_sdi_i => con_spi_sdi, - spi_csn_o => con_spi_csn, - - -- TWI -- - twi_sda_io => twi_sda_io, - twi_scl_io => twi_scl_io, - - -- GPIO -- - gpio_i => gpio_i, - gpio_o => gpio_o, - - -- PWM (to on-board RGB power LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - -- SPI sdi read-back -- - spi_csn_o <= con_spi_csn; - con_spi_sdi <= flash_sdi_i when (con_spi_csn = '0') else spi_sdi_i; - - -- RGB -- - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000001", - RGB1_CURRENT => "0b000001", - RGB2_CURRENT => "0b000001" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB0PWM => con_pwm(1), -- I - green - pwm channel 1 - RGB1PWM => con_pwm(2), -- I - bluee - pwm channel 2 - RGB2PWM => con_pwm(0), -- I - red - pwm channel 0 - RGB2 => pwm_o(2), -- O - red - RGB1 => pwm_o(1), -- O - blue - RGB0 => pwm_o(0) -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd (nonexistent) @@ -1,163 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_iCEBreaker_BoardTop_MinimalBoot is - port ( - -- UART (uart0) -- - uart_txd_o : out std_ulogic; - uart_rxd_i : in std_ulogic; - -- GPIO -- - gpio_o : out std_ulogic_vector(3 downto 0); - -- PWM (to on-board RGB power LED) -- - pwm_o : out std_logic_vector(2 downto 0) - ); -end entity; - -architecture neorv32_iCEBreaker_BoardTop_MinimalBoot_rtl of neorv32_iCEBreaker_BoardTop_MinimalBoot is - - -- configuration -- - constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz - - -- On-chip oscillator -- - signal hf_osc_clk : std_logic; - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_pwm : std_logic_vector(2 downto 0); - -begin - - -- On-Chip HF Oscillator ------------------------------------------------------------------ - -- ------------------------------------------------------------------------------------------- - HSOSC_inst : SB_HFOSC - generic map ( - CLKHF_DIV => "0b10" -- 12 MHz - ) - port map ( - CLKHFPU => '1', - CLKHFEN => '1', - CLKHF => hf_osc_clk - ); - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 12 -o 18: - -- F_PLLIN: 12.000 MHz (given) - -- F_PLLOUT: 18.000 MHz (requested) - -- F_PLLOUT: 18.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 12.000 MHz - -- F_VCO: 576.000 MHz - -- DIVR: 0 (4'b0000) - -- DIVF: 47 (7'b0101111) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_CORE - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"0", - DIVF => 7x"2F", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - REFERENCECLK => hf_osc_clk, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => '1', - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- GPIO -- - gpio_o => gpio_o, - - -- primary UART -- - uart_txd_o => uart_txd_o, -- UART0 send data - uart_rxd_i => uart_rxd_i, -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000011", - RGB1_CURRENT => "0b000011", - RGB2_CURRENT => "0b000011" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB0PWM => con_pwm(1), -- I - green - pwm channel 1 - RGB1PWM => con_pwm(2), -- I - blue - pwm channel 2 - RGB2PWM => con_pwm(0), -- I - red - pwm channel 0 - RGB2 => pwm_o(2), -- O - red - RGB1 => pwm_o(1), -- O - blue - RGB0 => pwm_o(0) -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd (nonexistent) @@ -1,110 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup including the bootloader, for the ULX3S (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library ECP5; -use ECP5.components.all; -- for device primitives and macros - -entity neorv32_ULX3S_BoardTop_MinimalBoot is - port ( - -- Clock and Reset inputs - ULX3S_CLK : in std_logic; - ULX3S_RST_N : in std_logic; - -- LED outputs - ULX3S_LED0 : out std_logic; - ULX3S_LED1 : out std_logic; - ULX3S_LED2 : out std_logic; - ULX3S_LED3 : out std_logic; - ULX3S_LED4 : out std_logic; - ULX3S_LED5 : out std_logic; - ULX3S_LED6 : out std_logic; - ULX3S_LED7 : out std_logic; - -- UART0 - ULX3S_RX : in std_logic; - ULX3S_TX : out std_logic - ); -end entity; - -architecture neorv32_ULX3S_BoardTop_MinimalBoot_rtl of neorv32_ULX3S_BoardTop_MinimalBoot is - - -- configuration -- - constant f_clock_c : natural := 25000000; -- clock frequency in Hz - - -- internal IO connection -- - signal con_pwm : std_logic_vector(2 downto 0); - signal con_gpio_o : std_ulogic_vector(3 downto 0); - -begin - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz - MEM_INT_IMEM_SIZE => 16*1024, - MEM_INT_DMEM_SIZE => 8*1024 - ) - port map ( - -- Global control -- - clk_i => std_ulogic(ULX3S_CLK), - rstn_i => std_ulogic(ULX3S_RST_N), - - -- GPIO -- - gpio_o => con_gpio_o, - - -- primary UART -- - uart_txd_o => ULX3S_TX, -- UART0 send data - uart_rxd_i => ULX3S_RX, -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - ULX3S_LED0 <= con_gpio_o(0); - ULX3S_LED1 <= con_gpio_o(1); - ULX3S_LED2 <= con_gpio_o(2); - ULX3S_LED3 <= con_gpio_o(3); - ULX3S_LED4 <= '0'; -- unused - ULX3S_LED5 <= con_pwm(0); - ULX3S_LED6 <= con_pwm(1); - ULX3S_LED7 <= con_pwm(2); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd (nonexistent) @@ -1,172 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup with an external clock, for the iCESugar (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_iCESugar_BoardTop_Minimal is - port ( - -- 48MHz Clock input - iCESugarv15_CLK : in std_logic; - -- UART0 - iCESugarv15_RX : in std_logic; - iCESugarv15_TX : out std_logic; - -- LED outputs - iCESugarv15_LED_R : out std_logic; - iCESugarv15_LED_G : out std_logic; - iCESugarv15_LED_B : out std_logic; - -- USB Pins (which should be statically driven if not being used) - iCESugarv15_USB_DP : out std_logic; - iCESugarv15_USB_DN : out std_logic; - iCESugarv15_USB_DP_PU : out std_logic - ); -end entity; - -architecture neorv32_iCESugar_BoardTop_Minimal_rtl of neorv32_iCESugar_BoardTop_Minimal is - - -- configuration -- - constant f_clock_c : natural := 22000000; -- PLL output clock frequency in Hz - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_gpio_o : std_ulogic_vector(3 downto 0); - signal con_pwm : std_logic_vector(2 downto 0); - -begin - - -- Assign USB pins to "0" so as to disconnect iCESugar from - -- the host system. Otherwise it would try to talk to - -- us over USB, which wouldn't work since we have no stack. - iCESugarv15_USB_DP <= '0'; - iCESugarv15_USB_DN <= '0'; - iCESugarv15_USB_DP_PU <= '0'; - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 12 -o 22: - -- F_PLLIN: 12.000 MHz (given) - -- F_PLLOUT: 22.000 MHz (requested) - -- F_PLLOUT: 22.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 12.000 MHz - -- F_VCO: 708.000 MHz - -- DIVR: 0 (4'b0000) - -- DIVF: 58 (7'b0111010) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_PAD - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"0", - DIVF => 7x"3A", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - PACKAGEPIN => iCESugarv15_CLK, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => '1', - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz - CPU_EXTENSION_RISCV_A => false, - CPU_EXTENSION_RISCV_C => false, - CPU_EXTENSION_RISCV_E => false, - CPU_EXTENSION_RISCV_M => false, - CPU_EXTENSION_RISCV_U => false, - CPU_EXTENSION_RISCV_Zfinx => false, - CPU_EXTENSION_RISCV_Zicsr => true, - CPU_EXTENSION_RISCV_Zifencei => false - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- GPIO -- - gpio_o => con_gpio_o, - - -- primary UART -- - uart_txd_o => iCESugarv15_TX, -- UART0 send data - uart_rxd_i => iCESugarv15_RX, -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000011", - RGB1_CURRENT => "0b000011", - RGB2_CURRENT => "0b000011" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 - RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink - RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 - RGB2 => iCESugarv15_LED_B, -- O - blue - RGB1 => iCESugarv15_LED_R, -- O - red - RGB0 => iCESugarv15_LED_G -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd (nonexistent) @@ -1,177 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup including the bootloader, for the iCESugar (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_iCESugar_BoardTop_MinimalBoot is - port ( - -- LED outputs - iCESugarv15_LED_R : out std_logic; - iCESugarv15_LED_G : out std_logic; - iCESugarv15_LED_B : out std_logic; - -- UART0 - iCESugarv15_RX : in std_logic; - iCESugarv15_TX : out std_logic; - -- USB Pins (which should be statically driven if not being used) - iCESugarv15_USB_DP : out std_logic; - iCESugarv15_USB_DN : out std_logic; - iCESugarv15_USB_DP_PU : out std_logic - ); -end entity; - -architecture neorv32_iCESugar_BoardTop_MinimalBoot_rtl of neorv32_iCESugar_BoardTop_MinimalBoot is - - -- configuration -- - constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz - - -- On-chip oscillator -- - signal hf_osc_clk : std_logic; - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_gpio_o : std_ulogic_vector(3 downto 0); - signal con_pwm : std_logic_vector(2 downto 0); - -begin - - -- Assign USB pins to "0" so as to disconnect iCESugar from - -- the host system. Otherwise it would try to talk to - -- us over USB, which wouldn't work since we have no stack. - iCESugarv15_USB_DP <= '0'; - iCESugarv15_USB_DN <= '0'; - iCESugarv15_USB_DP_PU <= '0'; - - -- On-Chip HF Oscillator ------------------------------------------------------------------ - -- ------------------------------------------------------------------------------------------- - HSOSC_inst : SB_HFOSC - generic map ( - CLKHF_DIV => "0b10" -- 12 MHz - ) - port map ( - CLKHFPU => '1', - CLKHFEN => '1', - CLKHF => hf_osc_clk - ); - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 12 -o 18: - -- F_PLLIN: 12.000 MHz (given) - -- F_PLLOUT: 18.000 MHz (requested) - -- F_PLLOUT: 18.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 12.000 MHz - -- F_VCO: 576.000 MHz - -- DIVR: 0 (4'b0000) - -- DIVF: 47 (7'b0101111) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_CORE - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"0", - DIVF => 7x"2F", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - REFERENCECLK => hf_osc_clk, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => '1', - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- GPIO -- - gpio_o => con_gpio_o, - - -- primary UART -- - uart_txd_o => iCESugarv15_TX, -- UART0 send data - uart_rxd_i => iCESugarv15_RX, -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000011", - RGB1_CURRENT => "0b000011", - RGB2_CURRENT => "0b000011" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 - RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink - RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 - RGB2 => iCESugarv15_LED_B, -- O - blue - RGB1 => iCESugarv15_LED_R, -- O - red - RGB0 => iCESugarv15_LED_G -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd (nonexistent) @@ -1,149 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example minimal setup for the Fomu (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_Fomu_BoardTop_Minimal is - port ( - -- 48MHz Clock input - clki : in std_logic; - -- LED outputs - rgb : out std_logic_vector(2 downto 0); - -- USB Pins (which should be statically driven if not being used) - usb_dp : out std_logic; - usb_dn : out std_logic; - usb_dp_pu : out std_logic - ); -end entity; - -architecture neorv32_Fomu_BoardTop_Minimal_rtl of neorv32_Fomu_BoardTop_Minimal is - - -- configuration -- - constant f_clock_c : natural := 22000000; -- PLL output clock frequency in Hz - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_pwm : std_logic_vector(2 downto 0); - -begin - - -- Assign USB pins to "0" so as to disconnect Fomu from - -- the host system. Otherwise it would try to talk to - -- us over USB, which wouldn't work since we have no stack. - usb_dp <= '0'; - usb_dn <= '0'; - usb_dp_pu <= '0'; - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 48 -o 21: - -- F_PLLIN: 48.000 MHz (given) - -- F_PLLOUT: 22.000 MHz (requested) - -- F_PLLOUT: 22.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 16.000 MHz - -- F_VCO: 704.000 MHz - -- DIVR: 2 (4'b0010) - -- DIVF: 43 (7'b0101011) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_CORE - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"2", - DIVF => 7x"2B", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - REFERENCECLK => clki, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => '1', - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_Minimal - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000011", - RGB1_CURRENT => "0b000011", - RGB2_CURRENT => "0b000011" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 - RGB1PWM => con_pwm(1), -- I - red - pwm channel 1 || BOOT blink - RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 - RGB2 => rgb(2), -- O - blue - RGB1 => rgb(1), -- O - red - RGB0 => rgb(0) -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd (nonexistent) @@ -1,204 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_UPduino_BoardTop_UP5KDemo is - port ( - -- UART (uart0) -- - uart_txd_o : out std_ulogic; - uart_rxd_i : in std_ulogic; - -- SPI to on-board flash -- - flash_sck_o : out std_ulogic; - flash_sdo_o : out std_ulogic; - flash_sdi_i : in std_ulogic; - flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0) - -- SPI to IO pins -- - spi_sck_o : out std_ulogic; - spi_sdo_o : out std_ulogic; - spi_sdi_i : in std_ulogic; - spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1) - -- TWI -- - twi_sda_io : inout std_logic; - twi_scl_io : inout std_logic; - -- GPIO -- - gpio_i : in std_ulogic_vector(3 downto 0); - gpio_o : out std_ulogic_vector(3 downto 0); - -- PWM (to on-board RGB power LED) -- - pwm_o : out std_ulogic_vector(2 downto 0) - ); -end entity; - -architecture neorv32_UPduino_BoardTop_UP5KDemo_rtl of neorv32_UPduino_BoardTop_UP5KDemo is - - -- configuration -- - constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz - - -- On-chip oscillator -- - signal hf_osc_clk : std_logic; - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_pwm : std_ulogic_vector(2 downto 0); - signal con_spi_sdi : std_ulogic; - signal con_spi_csn : std_ulogic; - -begin - - -- On-Chip HF Oscillator ------------------------------------------------------------------ - -- ------------------------------------------------------------------------------------------- - HSOSC_inst : SB_HFOSC - generic map ( - CLKHF_DIV => "0b10" -- 12 MHz - ) - port map ( - CLKHFPU => '1', - CLKHFEN => '1', - CLKHF => hf_osc_clk - ); - - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 12 -o 18: - -- F_PLLIN: 12.000 MHz (given) - -- F_PLLOUT: 18.000 MHz (requested) - -- F_PLLOUT: 18.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 12.000 MHz - -- F_VCO: 576.000 MHz - -- DIVR: 0 (4'b0000) - -- DIVF: 47 (7'b0101111) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_CORE - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"0", - DIVF => 7x"2F", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - REFERENCECLK => hf_osc_clk, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => '1', - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- primary UART -- - uart_txd_o => uart_txd_o, - uart_rxd_i => uart_rxd_i, - uart_rts_o => open, - uart_cts_i => '0', - - -- SPI to on-board flash -- - flash_sck_o => flash_sck_o, - flash_sdo_o => flash_sdo_o, - flash_sdi_i => flash_sdi_i, - flash_csn_o => flash_csn_o, - - -- SPI to IO pins -- - spi_sck_o => spi_sck_o, - spi_sdo_o => spi_sdo_o, - spi_sdi_i => con_spi_sdi, - spi_csn_o => con_spi_csn, - - -- TWI -- - twi_sda_io => twi_sda_io, - twi_scl_io => twi_scl_io, - - -- GPIO -- - gpio_i => gpio_i, - gpio_o => gpio_o, - - -- PWM (to on-board RGB power LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - -- SPI sdi read-back -- - spi_csn_o <= con_spi_csn; - con_spi_sdi <= flash_sdi_i when (con_spi_csn = '0') else spi_sdi_i; - - -- RGB -- - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000001", - RGB1_CURRENT => "0b000001", - RGB2_CURRENT => "0b000001" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB0PWM => con_pwm(1), -- I - green - pwm channel 1 - RGB1PWM => con_pwm(2), -- I - bluee - pwm channel 2 - RGB2PWM => con_pwm(0), -- I - red - pwm channel 0 - RGB2 => pwm_o(2), -- O - red - RGB1 => pwm_o(1), -- O - blue - RGB0 => pwm_o(0) -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd (nonexistent) @@ -1,130 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup including the bootloader, for the OrangeCrab (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library ECP5; -use ECP5.components.all; -- for device primitives and macros - -entity neorv32_OrangeCrab_BoardTop_MinimalBoot is - port ( - -- Clock and Reset inputs - OrangeCrab_CLK : in std_logic; - OrangeCrab_RST_N : in std_logic; - -- LED outputs - OrangeCrab_LED_RGB_R : out std_logic; - OrangeCrab_LED_RGB_G : out std_logic; - OrangeCrab_LED_RGB_B : out std_logic; - -- UART0 - OrangeCrab_GPIO_0 : in std_logic; - OrangeCrab_GPIO_1 : out std_logic; - OrangeCrab_GPIO_9 : out std_logic; - -- USB Pins (which should be statically driven if not being used) - OrangeCrab_USB_D_P : out std_logic; - OrangeCrab_USB_D_N : out std_logic; - OrangeCrab_USB_DP_PU : out std_logic - ); -end entity; - -architecture neorv32_OrangeCrab_BoardTop_MinimalBoot_rtl of neorv32_OrangeCrab_BoardTop_MinimalBoot is - - -- configuration -- - constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz - - -- Globals - signal pll_clk: std_logic; - - -- internal IO connection -- - signal con_pwm : std_logic_vector(2 downto 0); - signal con_gpio_o : std_ulogic_vector(3 downto 0); - -begin - - -- Assign USB pins to "0" so as to disconnect OrangeCrab from - -- the host system. Otherwise it would try to talk to - -- us over USB, which wouldn't work since we have no stack. - OrangeCrab_USB_D_P <= '0'; - OrangeCrab_USB_D_N <= '0'; - OrangeCrab_USB_DP_PU <= '0'; - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - PLL_inst: EHXPLLL - generic map ( - CLKI_DIV => 2, -- from `ecppll -i 48 -o 24` - CLKFB_DIV => 1, - CLKOP_DIV => 25 - ) - port map ( - CLKI => OrangeCrab_CLK, - CLKFB => pll_clk, - ENCLKOP => '1', - CLKOP => pll_clk, - LOCK => OrangeCrab_GPIO_9 - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz - MEM_INT_IMEM_SIZE => 16*1024, - MEM_INT_DMEM_SIZE => 8*1024 - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(OrangeCrab_RST_N), - - -- GPIO -- - gpio_o => con_gpio_o, - - -- primary UART -- - uart_txd_o => OrangeCrab_GPIO_1, -- UART0 send data - uart_rxd_i => OrangeCrab_GPIO_0, -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - OrangeCrab_LED_RGB_R <= con_pwm(0) or not con_gpio_o(0); - OrangeCrab_LED_RGB_G <= con_pwm(1); - OrangeCrab_LED_RGB_B <= con_pwm(2); - -end architecture; Index: neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v (nonexistent) @@ -1,47 +0,0 @@ -module neorv32_Fomu_MixedLanguage_ClkGen ( - output wire clk_o, - output wire rstn_o -); - - wire hf_osc_clk; - - SB_HFOSC #( - .CLKHF_DIV("0b10") // 12 MHz - ) HSOSC_inst ( - .CLKHFPU(1'b1), - .CLKHFEN(1'b1), - .CLKHF(hf_osc_clk) - ); - - // Settings generated by icepll -i 12 -o 18: - // F_PLLIN: 12.000 MHz (given) - // F_PLLOUT: 18.000 MHz (requested) - // F_PLLOUT: 18.000 MHz (achieved) - // FEEDBACK: SIMPLE - // F_PFD: 12.000 MHz - // F_VCO: 576.000 MHz - // DIVR: 0 (4'b0000) - // DIVF: 47 (7'b0101111) - // DIVQ: 5 (3'b101) - // FILTER_RANGE: 1 (3'b001) - - SB_PLL40_CORE #( - .FEEDBACK_PATH("SIMPLE"), - .DIVR(4'd0), - .DIVF(7'd47), - .DIVQ(3'd5), - .FILTER_RANGE(3'd1) - ) Pll_inst ( - .REFERENCECLK(hf_osc_clk), - .PLLOUTGLOBAL(clk_o), - .EXTFEEDBACK(1'b0), - .LOCK(rstn_o), - .BYPASS(1'b0), - .RESETB(1'b1), - .LATCHINPUTVALUE(1'b0), - .SDI(1'b0), - .SCLK(1'b0) - ); - -endmodule - Index: neorv32/trunk/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd =================================================================== --- neorv32/trunk/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd (revision 70) +++ neorv32/trunk/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd (nonexistent) @@ -1,163 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library iCE40; -use iCE40.components.all; -- for device primitives and macros - -entity neorv32_UPduino_BoardTop_MinimalBoot is - port ( - -- UART (uart0) -- - uart_txd_o : out std_ulogic; - uart_rxd_i : in std_ulogic; - -- GPIO -- - gpio_o : out std_ulogic_vector(3 downto 0); - -- PWM (to on-board RGB power LED) -- - pwm_o : out std_logic_vector(2 downto 0) - ); -end entity; - -architecture neorv32_UPduino_BoardTop_MinimalBoot_rtl of neorv32_UPduino_BoardTop_MinimalBoot is - - -- configuration -- - constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz - - -- On-chip oscillator -- - signal hf_osc_clk : std_logic; - - -- Globals - signal pll_rstn : std_logic; - signal pll_clk : std_logic; - - -- internal IO connection -- - signal con_pwm : std_logic_vector(2 downto 0); - -begin - - -- On-Chip HF Oscillator ------------------------------------------------------------------ - -- ------------------------------------------------------------------------------------------- - HSOSC_inst : SB_HFOSC - generic map ( - CLKHF_DIV => "0b10" -- 12 MHz - ) - port map ( - CLKHFPU => '1', - CLKHFEN => '1', - CLKHF => hf_osc_clk - ); - - -- System PLL ----------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - -- Settings generated by icepll -i 12 -o 18: - -- F_PLLIN: 12.000 MHz (given) - -- F_PLLOUT: 18.000 MHz (requested) - -- F_PLLOUT: 18.000 MHz (achieved) - -- FEEDBACK: SIMPLE - -- F_PFD: 12.000 MHz - -- F_VCO: 576.000 MHz - -- DIVR: 0 (4'b0000) - -- DIVF: 47 (7'b0101111) - -- DIVQ: 5 (3'b101) - -- FILTER_RANGE: 1 (3'b001) - Pll_inst : SB_PLL40_CORE - generic map ( - FEEDBACK_PATH => "SIMPLE", - DIVR => x"0", - DIVF => 7x"2F", - DIVQ => 3x"5", - FILTER_RANGE => 3x"1" - ) - port map ( - REFERENCECLK => hf_osc_clk, - PLLOUTCORE => open, - PLLOUTGLOBAL => pll_clk, - EXTFEEDBACK => '0', - DYNAMICDELAY => x"00", - LOCK => pll_rstn, - BYPASS => '0', - RESETB => '1', - LATCHINPUTVALUE => '0', - SDO => open, - SDI => '0', - SCLK => '0' - ); - - -- The core of the problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot - generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz - ) - port map ( - -- Global control -- - clk_i => std_ulogic(pll_clk), - rstn_i => std_ulogic(pll_rstn), - - -- GPIO -- - gpio_o => gpio_o, - - -- primary UART -- - uart_txd_o => uart_txd_o, -- UART0 send data - uart_rxd_i => uart_rxd_i, -- UART0 receive data - uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional - - -- PWM (to on-board RGB LED) -- - pwm_o => con_pwm - ); - - -- IO Connection -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - RGB_inst: SB_RGBA_DRV - generic map ( - CURRENT_MODE => "0b1", - RGB0_CURRENT => "0b000011", - RGB1_CURRENT => "0b000011", - RGB2_CURRENT => "0b000011" - ) - port map ( - CURREN => '1', -- I - RGBLEDEN => '1', -- I - RGB0PWM => con_pwm(1), -- I - green - pwm channel 1 - RGB1PWM => con_pwm(2), -- I - blue - pwm channel 2 - RGB2PWM => con_pwm(0), -- I - red - pwm channel 0 - RGB2 => pwm_o(2), -- O - red - RGB1 => pwm_o(1), -- O - blue - RGB0 => pwm_o(0) -- O - green - ); - -end architecture; Index: neorv32/trunk/setups/osflow/README.md =================================================================== --- neorv32/trunk/setups/osflow/README.md (revision 70) +++ neorv32/trunk/setups/osflow/README.md (nonexistent) @@ -1,145 +0,0 @@ -# Exemplary FPAG Board Setups - Using Open Source Toolchains - -* [Folder Structure](#Folder-Structure) -* [Prerequisites](#Prerequisites) -* [How To Run](#How-To-Run) -* [Porting to a new FPGA or Board](#Porting-to-a-new-FPGA-or-Board) - -This folder provides the infrastructure for generating bitstream for various FPGAs using -open-source toolchains. Synthesis is based on [ghdl-yosys](https://github.com/ghdl/ghdl-yosys-plugin). - -:information_source: Note that the provided setups just implement very basic SoC configurations. -These setups are intended as minimal example (how to synthesize the processor) for a given FPGA + board -that can be used as starting point to build more complex user-defined SoCs. - -## Folder Structure - -* `.`: Main makefile (main entry point) and partial-makefiles for synthesis, place & route and bitstream generation -* `boards`: board-specific _partial makefiles_ (used by main makefile "`Makefile`") for generating bitstreams -* `board_top`: board-specific top entities (board wrappers; may include FPGA-specific modules) -* `constraints`: physical constraints (mainly pin mappings) -* `devices`: FPGA-specific primitives and optimized processor modules (like memories) - - -## Prerequisites - -:construction: TODO :construction: - -* local installation of the tools -* using containers - - -## How To Run - -:construction: TODO :construction: - -The `Makefile` in this folder is the main entry point. To run the whole process of synthesis, place & route and bitstream -generation run: - -**Prototype:** -``` -make BOARD= -``` - -**Example:** -``` -make BOARD=Fomu Minimal -``` - -`` specifies the actual FPGA board and implicitly sets the FPGA type. The currently supported FPGA board -targets are listed in the `boards/` folder where each partial-makefile corresponds to a supported platform. - -`` is used to define the actual SoC top. Available SoCs are located in -[`rtl/processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates). - - -## Porting to a new FPGA or Board - -This sections illustrates how to add a new basic setup for a specific FPGA and board. This tutorial used the iCEBreaker -"MinimalBoot" setup as reference. - -#### 1. Setup a board- and FPGA-specific top entity - -1. Write a new top design unit that instantiates one of the provided processor templates from -[`rtl/processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates). -This new top unit can be a Verilog or VHDL file. -2. _Optional:_ You can also include FPGA-specific primitives like PLLs or block RAMs (but keep it simple). These components -need to be added to a FPGA-specific library in [`setups/osflow/devices`](https://github.com/stnolting/neorv32/tree/master/setups/osflow/devices). -3. Try to keep the external IO at a minimum even if the targeted FPGA boards provides cool features. Besides of clock and reset -you need to add at least one kind of IO interface like a UART, GPIO or PWM. -4. Give your new top entity file a specific name that includes the board's name and the instantiated processor template. -The name scheme is `neorv32_[board-name]_BoardTop_[template-name].[v/vhd]`. -5. Put this file in `setups/osflow/board_tops`. -6. Take a look at the iCEBreaker MinimalBoot top entity as a reference: -[`setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd) - -#### 2. Pin mapping - -1. Add a new constraints file to define the mapping between the your top unit's IO and the FPGA's physical pins. -You can add _all_ of the FPGA's physical pins even though just a subset is used by the new setup. -2. Name the new constraints file according to the board `[board-name].pcf`. -3. Put this file in `setups/osflow/constraints`. -4. Take a look at the iCEBreaker pin mapping as a reference: -[`setups/osflow/constraints/iCEBreaker.pcf`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/constraints/iCEBreaker.pcf) - -#### 3. Adding a board-specific makefile - -1. Add a board-specific makefile to the `setups/osflow/boards` folder. Name the new constraints file according to the board `[board-name].mk`. -2. The makefile contains (at least) one target to build the final bitstream: -```makefile -.PHONY: all - -all: bit - echo "! Built $(IMPL) for $(BOARD)" -``` -3. Take a look at the iCEBreaker pin mapping as a reference: -[` setups/osflow/boards/iCEBreaker.mk`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/boards/iCEBreaker.mk) - -#### 4. Adding a new target to `index.mk` - -1. Add a new conditional section to the boards management makefile `setups/osflow/boards/index.mk`. -2. This board-specific section sets variables that are required to run synthesis, mapping, place & route and bitstream generation: - * `CONSTRAINTS` defines the physical pin mapping file - * `PNRFLAGS` defines the FPGA-specific flags for mapping and place & route - * `IMPL` defines the setup's implementation name -```makefile -ifeq ($(BOARD),iCEBreaker) -$(info Setting constraints and implementation args for BOARD iCEBreaker) - -CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf -PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail -IMPL ?= neorv32_$(BOARD)_$(ID) - -endif -``` - -#### 5. Adding a new target to the main makefile - -1. As final step add the new setup to the main osflow makefile `setups/osflow/Makefile`. -2. Use the board's name to create a new makefile target. - * The new target should set the final bitstream's name using the `BITSTREAM` variable. - * Alternative _memory_ HDL sources like FPGA-optimized module can be set using the `NEORV32_MEM_SRC` variable. -```makefile -iCEBreaker: - $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) - $(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd) - $(MAKE) \ - BITSTREAM="$(BITSTREAM)" \ - NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ - run -``` - -#### 6. _Optional:_ Add the new setup to the automatic "Implementation" github workflow - -If you like you can add the new setup to the automatic build environment of the project. The project's "Implementation" -workflow will generate bitstreams for all configured osflow setups on every repository push. This is used to check for -regressions and also to provide up-to-date bitstreams that can be used right away. - -1. Add the new setup to the job matrix file `.github/generate-job-matrix.py`. -```python -{ - 'board': 'iCEBreaker', - 'design': 'MinimalBoot', - 'bitstream': 'neorv32_iCEBreaker_MinimalBoot.bit' -}, -``` Index: neorv32/trunk/setups/osflow/Makefile =================================================================== --- neorv32/trunk/setups/osflow/Makefile (revision 70) +++ neorv32/trunk/setups/osflow/Makefile (nonexistent) @@ -1,134 +0,0 @@ -TEMPLATES := ../../rtl/processor_templates -MV := mv - -.DEFAULT_GOAL := help - -TASK := clean $(BITSTREAM) - -FOMU_REV ?= pvt -OrangeCrab_REV ?= r02-25F -UPduino_REV ?= v3 - -#ifndef BOARD -#$(error BOARD needs to be set to 'Fomu', 'iCESugar', 'UPDuino', 'iCEBreaker' or 'OrangeCrab' !) -#endif - -run: - $(eval TASK ?= clean $(BITSTREAM)) - $(MAKE) -f common.mk \ - BOARD_SRC=./board_tops/neorv32_$(BOARD)_BoardTop_$(DESIGN).vhd \ - TOP=neorv32_$(BOARD)_BoardTop_$(DESIGN) \ - ID=$(DESIGN) \ - $(TASK) - IMPL="$${BITSTREAM%%.*}"; for item in ".bit" ".svf"; do \ - if [ -f "./$$IMPL$$item" ]; then \ - $(MV) "./$$IMPL$$item" ./; \ - fi \ - done - -# Boards - -Fomu: - $(eval BITSTREAM ?= neorv32_$(BOARD)_$(FOMU_REV)_$(DESIGN).bit) -ifeq ($(DESIGN),Minimal) - $(eval IMEM_SRC := ../../rtl/core/mem/neorv32_imem.default.vhd) -else - $(eval IMEM_SRC := devices/ice40/neorv32_imem.ice40up_spram.vhd) -endif - $(eval NEORV32_MEM_SRC ?= ${IMEM_SRC} devices/ice40/neorv32_dmem.ice40up_spram.vhd) - $(MAKE) \ - BITSTREAM="$(BITSTREAM)" \ - NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ - run - -iCESugar: - $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) - $(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd) - $(MAKE) \ - BITSTREAM="$(BITSTREAM)" \ - NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ - run - -UPduino: - $(eval BITSTREAM ?= neorv32_$(BOARD)_$(UPduino_REV)_$(DESIGN).bit) - $(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd) - $(MAKE) \ - BITSTREAM="$(BITSTREAM)" \ - NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ - run - -OrangeCrab: - $(eval BITSTREAM ?= neorv32_$(BOARD)_$(OrangeCrab_REV)_$(DESIGN).bit) - $(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd) - $(MAKE) \ - BITSTREAM="$(BITSTREAM)" \ - NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ - run - -AlhambraII: - $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) - $(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd) - $(MAKE) \ - BITSTREAM="$(BITSTREAM)" \ - NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ - run - -ULX3S: - $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) - $(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd) - $(MAKE) \ - BITSTREAM="$(BITSTREAM)" \ - NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ - run - -iCEBreaker: - $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) - $(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd) - $(MAKE) \ - BITSTREAM="$(BITSTREAM)" \ - NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ - run - -# Designs - -Minimal: - $(eval DESIGN ?= $@) - $(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_Minimal*.vhd) - $(MAKE) \ - DESIGN="$(DESIGN)" \ - DESIGN_SRC="$(DESIGN_SRC)" \ - $(BOARD) - -MinimalBoot: - $(eval DESIGN ?= $@) - $(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_MinimalBoot.vhd) - $(MAKE) \ - DESIGN="$(DESIGN)" \ - DESIGN_SRC="$(DESIGN_SRC)" \ - $(BOARD) - -UP5KDemo: - $(eval DESIGN ?= $@) - $(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_UP5KDemo.vhd) - $(MAKE) \ - DESIGN="$(DESIGN)" \ - DESIGN_SRC="$(DESIGN_SRC)" \ - $(BOARD) - -MixedLanguage: - $(eval DESIGN ?= $@) - $(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_Minimal*.vhd) - $(eval NEORV32_VERILOG_SRC ?= devices/ice40/sb_ice40_components.v board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v) - $(MAKE) \ - DESIGN="$(DESIGN)" \ - DESIGN_SRC="$(DESIGN_SRC)" \ - NEORV32_VERILOG_SRC="$(NEORV32_VERILOG_SRC)" \ - $(BOARD) - -# Help - -help: - @echo "Open-Source Synthesis, P&R, Routing and Bitstream Generation" - @echo "Usage: make BOARD= " - @echo "Example: make BOARD=Fomu Minimal" - Index: neorv32/trunk/setups/osflow/common.mk =================================================================== --- neorv32/trunk/setups/osflow/common.mk (revision 70) +++ neorv32/trunk/setups/osflow/common.mk (nonexistent) @@ -1,39 +0,0 @@ -ID ?= impl_1 - -include boards/index.mk - -ifndef TOP -$(error TOP needs to be specified!) -endif - -include filesets.mk - -ifndef DESIGN_SRC -ifndef BOARD_SRC -$(error Neither DESIGN_SRC nor BOARD_SRC were set!) -endif -endif - -include tools.mk - -ifdef GHDL_PLUGIN_MODULE -YOSYSFLAGS += -m $(GHDL_PLUGIN_MODULE) -endif - -include synthesis.mk -include PnR_Bit.mk - -.PHONY: syn impl bit svf clean - -syn: ${IMPL}.json -impl: ${IMPL}.${PNR2BIT_EXT} -bit: ${IMPL}.bit - -ifeq ($(DEVICE_SERIES),ecp5) -svf: ${IMPL}.svf -endif - -clean: - rm -rf *.{${PNR2BIT_EXT},bit,cf,dfu,history,json,o,svf} *-report.txt - -include boards/$(BOARD).mk Index: neorv32/trunk/setups/osflow/synthesis.mk =================================================================== --- neorv32/trunk/setups/osflow/synthesis.mk (revision 70) +++ neorv32/trunk/setups/osflow/synthesis.mk (nonexistent) @@ -1,22 +0,0 @@ -${DEVICE_LIB}-obj08.cf: ${DEVICE_SRC} - ghdl -a $(GHDL_FLAGS) --work=${DEVICE_LIB} ${DEVICE_SRC} - -neorv32-obj08.cf: ${DEVICE_LIB}-obj08.cf ${NEORV32_SRC} - ghdl -a $(GHDL_FLAGS) --work=neorv32 ${NEORV32_SRC} - -work-obj08.cf: neorv32-obj08.cf ${DESIGN_SRC} ${BOARD_SRC} - ghdl -a $(GHDL_FLAGS) --work=work ${DESIGN_SRC} ${BOARD_SRC} - -ifeq ($(strip $(NEORV32_VERILOG_ALL)),) -READ_VERILOG = -else -READ_VERILOG = read_verilog ${NEORV32_VERILOG_ALL}; -endif - -${IMPL}.json: work-obj08.cf $(NEORV32_VERILOG_ALL) - $(YOSYS) $(YOSYSFLAGS) \ - -p \ - "$(GHDLSYNTH) $(GHDL_FLAGS) --no-formal $(TOP); \ - $(READ_VERILOG) synth_${YOSYSSYNTH} \ - -top $(TOP) $(YOSYSPIPE) \ - -json $@" 2>&1 | tee yosys-report.txt Index: neorv32/trunk/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd =================================================================== --- neorv32/trunk/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd (revision 70) +++ neorv32/trunk/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd (nonexistent) @@ -1,145 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Processor-Internal DMEM for Lattice iCE40 UltraPlus >> # --- # ********************************************************************************************* # --- # Memory has a physical size of 64kb (2 x SPRAMs). # --- # Logical size DMEM_SIZE must be less or equal. # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library neorv32; -use neorv32.neorv32_package.all; - -library iCE40; -use iCE40.components.all; - -architecture neorv32_dmem_rtl of neorv32_dmem is - - -- advanced configuration -------------------------------------------------------------------------------- - constant spram_sleep_mode_en_c : boolean := false; -- put DMEM into sleep mode when idle (for low power) - -- ------------------------------------------------------------------------------------------------------- - - -- IO space: module base address -- - constant hi_abb_c : natural := 31; -- high address boundary bit - constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit - - -- local signals -- - signal acc_en : std_ulogic; - signal mem_cs : std_ulogic; - signal rdata : std_ulogic_vector(31 downto 0); - signal rden : std_ulogic; - - -- SPRAM signals -- - signal spram_clk : std_logic; - signal spram_addr : std_logic_vector(13 downto 0); - signal spram_di_lo : std_logic_vector(15 downto 0); - signal spram_di_hi : std_logic_vector(15 downto 0); - signal spram_do_lo : std_logic_vector(15 downto 0); - signal spram_do_hi : std_logic_vector(15 downto 0); - signal spram_be_lo : std_logic_vector(03 downto 0); - signal spram_be_hi : std_logic_vector(03 downto 0); - signal spram_we : std_logic; - signal spram_pwr_n : std_logic; - signal spram_cs : std_logic; - -begin - - -- Sanity Checks -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based DMEM." severity note; - assert not (DMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: DMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error; - - - -- Access Control ------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; - mem_cs <= acc_en and (rden_i or wren_i); - - - -- Memory Access -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - imem_spram_lo_inst : SB_SPRAM256KA - port map ( - ADDRESS => spram_addr, -- I - DATAIN => spram_di_lo, -- I - MASKWREN => spram_be_lo, -- I - WREN => spram_we, -- I - CHIPSELECT => spram_cs, -- I - CLOCK => spram_clk, -- I - STANDBY => '0', -- I - SLEEP => spram_pwr_n, -- I - POWEROFF => '1', -- I - DATAOUT => spram_do_lo -- O - ); - - imem_spram_hi_inst : SB_SPRAM256KA - port map ( - ADDRESS => spram_addr, -- I - DATAIN => spram_di_hi, -- I - MASKWREN => spram_be_hi, -- I - WREN => spram_we, -- I - CHIPSELECT => spram_cs, -- I - CLOCK => spram_clk, -- I - STANDBY => '0', -- I - SLEEP => spram_pwr_n, -- I - POWEROFF => '1', -- I - DATAOUT => spram_do_hi -- O - ); - - -- access logic and signal type conversion -- - spram_clk <= std_logic(clk_i); - spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2)); - spram_di_lo <= std_logic_vector(data_i(15 downto 00)); - spram_di_hi <= std_logic_vector(data_i(31 downto 16)); - spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable - spram_cs <= std_logic(mem_cs); - spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable - spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable - spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected - rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo); - - buffer_ff: process(clk_i) - begin - if rising_edge(clk_i) then - ack_o <= mem_cs; - rden <= acc_en and rden_i; - end if; - end process buffer_ff; - - -- output gate -- - data_o <= rdata when (rden = '1') else (others => '0'); - - -end neorv32_dmem_rtl; Index: neorv32/trunk/setups/osflow/devices/ice40/sb_ice40_components.vhd =================================================================== --- neorv32/trunk/setups/osflow/devices/ice40/sb_ice40_components.vhd (revision 70) +++ neorv32/trunk/setups/osflow/devices/ice40/sb_ice40_components.vhd (nonexistent) @@ -1,126 +0,0 @@ -library ieee ; -use ieee.std_logic_1164.all; - -package components is - - -- Yosys / IceCube wrapper components - - component SB_GB - port( - GLOBAL_BUFFER_OUTPUT : out std_logic; - USER_SIGNAL_TO_GLOBAL_BUFFER : in std_logic - ); - end component; - - component SB_HFOSC - generic ( - CLKHF_DIV : string - ); - port ( - CLKHFPU : in std_logic; - CLKHFEN : in std_logic; - CLKHF : out std_logic - ); - end component; - - component SB_PLL40_CORE is - generic ( - FEEDBACK_PATH : string := "SIMPLE"; - DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED"; - DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED"; - SHIFTREG_DIV_MODE : std_logic := '0'; - FDA_FEEDBACK : std_logic_vector(3 downto 0) := x"0"; - FDA_RELATIVE : std_logic_vector(3 downto 0) := x"0"; - PLLOUT_SELECT : string := "GENCLK"; - DIVR : std_logic_vector(3 downto 0) := x"0"; - DIVF : std_logic_vector(6 downto 0) := "0000000"; - DIVQ : std_logic_vector(2 downto 0) := "000"; - FILTER_RANGE : std_logic_vector(2 downto 0) := "000"; - ENABLE_ICEGATE : bit := '0'; - TEST_MODE : bit := '0'; - EXTERNAL_DIVIDE_FACTOR : integer := 1 - ); - port ( - REFERENCECLK : in std_logic; - PLLOUTCORE : out std_logic; - PLLOUTGLOBAL : out std_logic; - EXTFEEDBACK : in std_logic; - DYNAMICDELAY : in std_logic_vector(7 downto 0); - LOCK : out std_logic; - BYPASS : in std_logic; - RESETB : in std_logic; - LATCHINPUTVALUE : in std_logic; - SDO : out std_logic; - SDI : in std_logic; - SCLK : in std_logic - ); - end component; - - component SB_PLL40_PAD - generic ( - FEEDBACK_PATH : string := "SIMPLE"; - DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED"; - DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED"; - SHIFTREG_DIV_MODE : bit_vector(1 downto 0) := "00"; - FDA_FEEDBACK : bit_vector(3 downto 0) := "0000"; - FDA_RELATIVE : bit_vector(3 downto 0) := "0000"; - PLLOUT_SELECT : string := "GENCLK"; - DIVR : bit_vector(3 downto 0) := x"0"; - DIVF : bit_vector(6 downto 0) := "0000000"; - DIVQ : bit_vector(2 downto 0) := "000"; - FILTER_RANGE : bit_vector(2 downto 0) := "000"; - ENABLE_ICEGATE : bit := '0'; - TEST_MODE : bit := '0'; - EXTERNAL_DIVIDE_FACTOR : integer := 1 - ); - port ( - PACKAGEPIN : in std_logic; - PLLOUTCORE : out std_logic; - PLLOUTGLOBAL : out std_logic; - EXTFEEDBACK : in std_logic; - DYNAMICDELAY : in std_logic_vector(7 downto 0); - LOCK : out std_logic; - BYPASS : in std_logic; - RESETB : in std_logic; - LATCHINPUTVALUE : in std_logic; - SDO : out std_logic; - SDI : in std_logic; - SCLK : in std_logic - ); - end component; - - component SB_RGBA_DRV - generic ( - CURRENT_MODE : string := "0b0"; - RGB0_CURRENT : string := "0b000000"; - RGB1_CURRENT : string := "0b000000"; - RGB2_CURRENT : string := "0b000000" - ); - port ( - RGB0PWM : in std_logic; - RGB1PWM : in std_logic; - RGB2PWM : in std_logic; - CURREN : in std_logic; - RGBLEDEN : in std_logic; - RGB0 : out std_logic; - RGB1 : out std_logic; - RGB2 : out std_logic - ); - end component; - - component SB_SPRAM256KA - port ( - ADDRESS : in std_logic_vector(13 downto 0); - DATAIN : in std_logic_vector(15 downto 0); - MASKWREN : in std_logic_vector(3 downto 0); - WREN : in std_logic; - CHIPSELECT : in std_logic; - CLOCK : in std_logic; - STANDBY : in std_logic; - SLEEP : in std_logic; - POWEROFF : in std_logic; - DATAOUT : out std_logic_vector(15 downto 0) - ); - end component; - -end package; Index: neorv32/trunk/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd =================================================================== --- neorv32/trunk/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd (revision 70) +++ neorv32/trunk/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd (nonexistent) @@ -1,146 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Processor-Internal IMEM for Lattice iCE40 UltraPlus >> # --- # ********************************************************************************************* # --- # Memory has a physical size of 64kb (2 x SPRAMs). # --- # Logical size IMEM_SIZE must be less or equal. # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library neorv32; -use neorv32.neorv32_package.all; - -library iCE40; -use iCE40.components.all; - -architecture neorv32_imem_rtl of neorv32_imem is - - -- advanced configuration -------------------------------------------------------------------------------- - constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power) - -- ------------------------------------------------------------------------------------------------------- - - -- IO space: module base address -- - constant hi_abb_c : natural := 31; -- high address boundary bit - constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit - - -- local signals -- - signal acc_en : std_ulogic; - signal mem_cs : std_ulogic; - signal rdata : std_ulogic_vector(31 downto 0); - signal rden : std_ulogic; - - -- SPRAM signals -- - signal spram_clk : std_logic; - signal spram_addr : std_logic_vector(13 downto 0); - signal spram_di_lo : std_logic_vector(15 downto 0); - signal spram_di_hi : std_logic_vector(15 downto 0); - signal spram_do_lo : std_logic_vector(15 downto 0); - signal spram_do_hi : std_logic_vector(15 downto 0); - signal spram_be_lo : std_logic_vector(03 downto 0); - signal spram_be_hi : std_logic_vector(03 downto 0); - signal spram_we : std_logic; - signal spram_pwr_n : std_logic; - signal spram_cs : std_logic; - -begin - - -- Sanity Checks -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based IMEM." severity note; - assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure; - assert not (IMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: IMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error; - - - -- Access Control ------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; - mem_cs <= acc_en and (rden_i or wren_i); - - - -- Memory Access -------------------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - imem_spram_lo_inst : SB_SPRAM256KA - port map ( - ADDRESS => spram_addr, -- I - DATAIN => spram_di_lo, -- I - MASKWREN => spram_be_lo, -- I - WREN => spram_we, -- I - CHIPSELECT => spram_cs, -- I - CLOCK => spram_clk, -- I - STANDBY => '0', -- I - SLEEP => spram_pwr_n, -- I - POWEROFF => '1', -- I - DATAOUT => spram_do_lo -- O - ); - - imem_spram_hi_inst : SB_SPRAM256KA - port map ( - ADDRESS => spram_addr, -- I - DATAIN => spram_di_hi, -- I - MASKWREN => spram_be_hi, -- I - WREN => spram_we, -- I - CHIPSELECT => spram_cs, -- I - CLOCK => spram_clk, -- I - STANDBY => '0', -- I - SLEEP => spram_pwr_n, -- I - POWEROFF => '1', -- I - DATAOUT => spram_do_hi -- O - ); - - -- access logic and signal type conversion -- - spram_clk <= std_logic(clk_i); - spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2)); - spram_di_lo <= std_logic_vector(data_i(15 downto 00)); - spram_di_hi <= std_logic_vector(data_i(31 downto 16)); - spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable - spram_cs <= std_logic(mem_cs); - spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable - spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable - spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected - rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo); - - buffer_ff: process(clk_i) - begin - if rising_edge(clk_i) then - ack_o <= mem_cs; - rden <= acc_en and rden_i; - end if; - end process buffer_ff; - - -- output gate -- - data_o <= rdata when (rden = '1') else (others => '0'); - - -end neorv32_imem_rtl; Index: neorv32/trunk/setups/osflow/devices/ice40/sb_ice40_components.v =================================================================== --- neorv32/trunk/setups/osflow/devices/ice40/sb_ice40_components.v (revision 70) +++ neorv32/trunk/setups/osflow/devices/ice40/sb_ice40_components.v (nonexistent) @@ -1,39 +0,0 @@ -(* blackbox *) -module SB_HFOSC ( - input CLKHFEN, - input CLKHFPU, - output CLKHF -); - parameter CLKHF_DIV = 2'b00; -endmodule - -(* blackbox *) -module SB_PLL40_CORE ( - input REFERENCECLK, - output PLLOUTCORE, - output PLLOUTGLOBAL, - input EXTFEEDBACK, - input [7:0] DYNAMICDELAY, - output LOCK, - input BYPASS, - input RESETB, - input LATCHINPUTVALUE, - output SDO, - input SDI, - input SCLK -); - parameter FEEDBACK_PATH = "SIMPLE"; - parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; - parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; - parameter SHIFTREG_DIV_MODE = 1'b0; - parameter FDA_FEEDBACK = 4'b0000; - parameter FDA_RELATIVE = 4'b0000; - parameter PLLOUT_SELECT = "GENCLK"; - parameter DIVR = 4'b0000; - parameter DIVF = 7'b0000000; - parameter DIVQ = 3'b000; - parameter FILTER_RANGE = 3'b000; - parameter ENABLE_ICEGATE = 1'b0; - parameter TEST_MODE = 1'b0; - parameter EXTERNAL_DIVIDE_FACTOR = 1; -endmodule Index: neorv32/trunk/setups/osflow/devices/ecp5/ecp5_components.vhd =================================================================== --- neorv32/trunk/setups/osflow/devices/ecp5/ecp5_components.vhd (revision 70) +++ neorv32/trunk/setups/osflow/devices/ecp5/ecp5_components.vhd (nonexistent) @@ -1,75 +0,0 @@ -library ieee ; -use ieee.std_logic_1164.all; - -package components is - - -- Yosys wrapper components - - component EHXPLLL - generic - ( - CLKI_DIV : integer := 1; - CLKFB_DIV : integer := 1; - CLKOP_DIV : integer := 8; - CLKOS_DIV : integer := 8; - CLKOS2_DIV : integer := 8; - CLKOS3_DIV : integer := 8; - CLKOP_ENABLE : string := "ENABLED"; - CLKOS_ENABLE : string := "DISABLED"; - CLKOS2_ENABLE : string := "DISABLED"; - CLKOS3_ENABLE : string := "DISABLED"; - CLKOP_CPHASE : integer := 0; - CLKOS_CPHASE : integer := 0; - CLKOS2_CPHASE : integer := 0; - CLKOS3_CPHASE : integer := 0; - CLKOP_FPHASE : integer := 0; - CLKOS_FPHASE : integer := 0; - CLKOS2_FPHASE : integer := 0; - CLKOS3_FPHASE : integer := 0; - FEEDBK_PATH : string := "CLKOP"; - CLKOP_TRIM_POL : string := "RISING"; - CLKOP_TRIM_DELAY : integer := 0; - CLKOS_TRIM_POL : string := "RISING"; - CLKOS_TRIM_DELAY : integer := 0; - OUTDIVIDER_MUXA : string := "DIVA"; - OUTDIVIDER_MUXB : string := "DIVB"; - OUTDIVIDER_MUXC : string := "DIVC"; - OUTDIVIDER_MUXD : string := "DIVD"; - PLL_LOCK_MODE : integer := 0; - PLL_LOCK_DELAY : integer := 200; - STDBY_ENABLE : string := "DISABLED"; - REFIN_RESET : string := "DISABLED"; - SYNC_ENABLE : string := "DISABLED"; - INT_LOCK_STICKY : string := "ENABLED"; - DPHASE_SOURCE : string := "DISABLED"; - PLLRST_ENA : string := "DISABLED"; - INTFB_WAKE : string := "DISABLED" - ); - port - ( - CLKI : IN std_logic := 'X'; - CLKFB : IN std_logic := 'X'; - RST : IN std_logic := 'X'; - STDBY : IN std_logic := 'X'; - PLLWAKESYNC : IN std_logic := 'X'; - PHASESEL1 : IN std_logic := 'X'; - PHASESEL0 : IN std_logic := 'X'; - PHASEDIR : IN std_logic := 'X'; - PHASESTEP : IN std_logic := 'X'; - PHASELOADREG : IN std_logic := 'X'; - ENCLKOP : IN std_logic := 'X'; - ENCLKOS : IN std_logic := 'X'; - ENCLKOS2 : IN std_logic := 'X'; - ENCLKOS3 : IN std_logic := 'X'; - CLKOP : OUT std_logic := 'X'; - CLKOS : OUT std_logic := 'X'; - CLKOS2 : OUT std_logic := 'X'; - CLKOS3 : OUT std_logic := 'X'; - LOCK : OUT std_logic := 'X'; - INTLOCK : OUT std_logic := 'X'; - REFCLK : OUT std_logic := 'X'; - CLKINTFB : OUT std_logic := 'X' - ); - end component; - -end package; Index: neorv32/trunk/setups/README.md =================================================================== --- neorv32/trunk/setups/README.md (revision 70) +++ neorv32/trunk/setups/README.md (nonexistent) @@ -1,65 +0,0 @@ -# Exemplary FPGA Board Setups - -* [Setups using Commercial Toolchains](#Setups-using-Commercial-Toolchains) -* [Setups using Open-Source Toolchains](#Setups-using-Open-Source-Toolchains) -* [Adding Your Project Setup](#Adding-Your-Project-Setup) -* [Setup-Specific NEORV32 Software Framework Modification](#Setup-Specific-NEORV32-Software-Framework-Modification) - -This folder provides exemplary NEORV32 SoC setups and projects for different FPGA platforms/boards. -You can directly use one of the provided setups or use them as starting point to build your own setup. -Project maintainers may make pull requests against this repository to [add or link their setups](#Adding-Your-Project-Setup). - - -## Setups using Commercial Toolchains - -| Setup | Toolchain | Board :books: | FPGA | Author(s) | -|:------|:----------|:--------------|:------|:----------| -| :file_folder: [`de0-nano-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/quartus/de0-nano-test-setup) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [stnolting](https://github.com/stnolting) | -| :file_folder: [`de0-nano-test-setup-qsys`](quartus/de0-nano-test-setup-qsys) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [torerams](https://github.com/torerams) | -| :file_folder: [`de0-nano-test-setup-avalonmm`](quartus/de0-nano-test-setup-avalonmm-wrapper) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [torerams](https://github.com/torerams) | -| :file_folder: [`terasic-cyclone-V-gx-starter-kit-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup) | Intel Quartus Prime | [Terasic Cyclone-V GX Starter Kit](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830) | Intel Cyclone V `5CGXFC5C6F27C7N` | zs6mue | -| :file_folder: [`UPduino_v3`](https://github.com/stnolting/neorv32/tree/master/setups/radiant/UPduino_v3) | Lattice Radiant | [tinyVision.ai Inc. UPduino `v3.0`](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [stnolting](https://github.com/stnolting) | -| :file_folder: [`arty-a7-35-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/arty-a7-test-setup) | Xilinx Vivado | [Digilent Arty A7-35](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) | Xilinx Artix-7 `XC7A35TICSG324-1L` | [stnolting](https://github.com/stnolting) | -| :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/nexys-a7-test-setup) | Xilinx Vivado | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start) | Xilinx Artix-7 `XC7A50TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) | -| :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/nexys-a7-test-setup) | Xilinx Vivado | [Digilent Nexys 4 DDR](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start) | Xilinx Artix-7 `XC7A100TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) | -| :earth_africa: [custom CRC32 processor module for the nexys-a7 boards (**tutorial**)](https://github.com/motius/neorv32/tree/add-custom-crc32-module) | Xilinx Vivado | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start) | Xilinx Artix-7 `XC7A50TCSG324-1` | [motius](https://github.com/motius) ([ikstvn](https://github.com/ikstvn), [turbinenreiter](https://github.com/turbinenreiter)) | -| :earth_africa: [neorv32-examples](https://github.com/emb4fun/neorv32-examples) | Intel Quartus Prime | Different Terasic boards | Different Intel FPGAs | [emb4fun](https://github.com/emb4fun) | - - -## Setups using Open-Source Toolchains - -| Setup | Toolchain | Board :books: | FPGA | Author(s) | -|:------|:----------|:--------------|:------|:----------| -| :file_folder: [`UPduino v3`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [UPduino v3.0](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [tmeissner](https://github.com/tmeissner) | -| :file_folder: [`FOMU`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [FOMU](https://tomu.im/fomu.html) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [umarcor](https://github.com/umarcor) | -| :file_folder: [`iCESugar`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [iCESugar](https://github.com/wuxx/icesugar/blob/master/README_en.md) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [umarcor](https://github.com/umarcor) | -| :file_folder: [`AlhambraII`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [AlhambraII](https://alhambrabits.com/alhambra/) | Lattice iCE40HX4K | [zipotron](https://github.com/zipotron) | -| :file_folder: [`Orange Crab`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [Orange Crab](https://github.com/gregdavill/OrangeCrab) | Lattice ECP5-25F | [umarcor](https://github.com/umarcor), [jeremyherbert](https://github.com/jeremyherbert) | -| :file_folder: [`ULX3S`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/) | Lattice ECP5 `LFE5U-85F-6BG381C` | [zipotron](https://github.com/zipotron) | -| :earth_africa: [`ULX3S-SDRAM`](https://github.com/zipotron/neorv32-complex-setups) | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/) | Lattice ECP5 `LFE5U-85F-6BG381C` | [zipotron](https://github.com/zipotron) | - -:information_source: All setups using open-source toolchains are located in the -[`osflow`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) folder. -See the README there for more information how to run a specific setup / configuration. - - -## Adding Your Project Setup - -Please respect the following guidelines if you'd like to add (or link) your setup to the list. - -* check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md) -* add a link if the board you are using provides online documentation (and/or can be purchased somewhere) -* use the :file_folder: emoji (`:file_folder:`) if the setup is located *in this* folder; use the :earth_africa: -emoji (`:earth_africa:`) if it is a link to your local project -* please add a `README` to give some brief information about the setup and a `.gitignore` to keep things clean; -take a look at [`UPduino_v3`](https://github.com/stnolting/neorv32/tree/master/setups/radiant/UPduino_v3) to get some ideas what a project setup might look like - - -## Setup-Specific NEORV32 Software Framework Modification - -In order to use the features provided by the setups, minor *optional* changes can be made to the default NEORV32 setup. - -* To change the default data memory size take a look at the :books: User Guide section -[_General Software Framework Setup_](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) -* To modify the SPI flash base address for storing/booting software application see :books: User Guide section -[_Customizing the Internal Bootloader_](https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader) Index: neorv32/trunk/docs/datasheet/cpu.adoc =================================================================== --- neorv32/trunk/docs/datasheet/cpu.adoc (revision 70) +++ neorv32/trunk/docs/datasheet/cpu.adoc (revision 71) @@ -269,13 +269,7 @@ The `A` CPU extension only implements the `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further atomic memory operations. -.Bit-Manipulation ISA Extension -[IMPORTANT] -The NEORV32 `B` extension only implements the _basic bit-manipulation instructions_ (`Zbb`) subset -and the _address generation instructions_ (`Zba`) subset yet. - - <<< // #################################################################################################################### :sectnums: @@ -422,24 +416,28 @@ The `B` ISA extension adds instructions for bit-manipulation operations. This extension is enabled if the `CPU_EXTENSION_RISCV_B` configuration generic is _true_. The official RISC-V specifications can be found here: https://github.com/riscv/riscv-bitmanip +A copy of the spec is also available in `docs/references`. -[IMPORTANT] -The NEORV32 `B` extension only implements the _basic bit-manipulation instructions_ (`Zbb`) subset -and the _address generation instructions_ (`Zba`) subset yet. +The NEORV32 `B` ISA extension includes the following sub-extensions (according to the RISC-V +bit-manipulation spec. v.093) and their corresponding instructions: -The `Zbb` sub-extension adds the following instructions: +* **`Zba` - Address-generation instructions** +** `sh1add` `sh2add` `sh3add` +* **`Zbb` - Basic bit-manipulation instructions** +** `andn` `orn` `xnor` +** `clz` `ctz` `cpop` +** `max` `maxu` `min` `minu` +** `sext.b` `sext.h` `zext.h` +** `rol` `ror` `rori` +** `orc.b` `rev8` +* **`Zbc` - Carry-less multiplication instructions** +** `clmul` `clmulh` `clmulr` +* **`Zbs` - Single-bit instructions** +** `bclr` `bclri` +** `bext` `bexti` +** `bext` `binvi` +** `bset` `bseti` -* `andn` `orn` `xnor` -* `clz` `ctz` `cpop` -* `max` `maxu` `min` `minu` -* `sext.b` `sext.h` `zext.h` -* `rol` `ror` `rori` -* `orc.b` `rev8` - -The `Zba` sub-extension adds the following instructions: - -* `sh1add` `sh2add` `sh3add` - [TIP] By default, the bit-manipulation unit uses an _iterative_ approach to compute shift-related operations like `clz` and `rol`. To increase performance (at the cost of additional hardware resources) the @@ -447,10 +445,10 @@ shift-related `B` instructions. [WARNING] -The `B` extension is frozen but not officially ratified yet. There is no -software support for this extension in the upstream GCC RISC-V port yet. However, an +The `B` extension is frozen and officially ratified. However, there is no +software support for this extension in the upstream GCC RISC-V port yet. An intrinsic library is provided to utilize the provided `B` extension features from C-language -code (see `sw/example/bitmanip_test`). +code (see `sw/example/bitmanip_test`) to circumvent this. ==== **`C`** - Compressed Instructions @@ -795,8 +793,9 @@ | Bit-manipulation - shifts | `B(Zbb)` | `clz` `ctz` | 3 + 0..32 | Bit-manipulation - shifts | `B(Zbb)` | `cpop` | 3 + 32 | Bit-manipulation - shifts | `B(Zbb)` | `rol` `ror` `rori` | 3 + SA -| Bit-manipulation - single-bit | `B(Zbs)` | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 3 +| Bit-manipulation - single-bit | `B(Zbs)` | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 3 | Bit-manipulation - shifted-add | `B(Zba)` | `sh1add` `sh2add` `sh3add` | 3 +| Bit-manipulation - carry-less multiply | `B(Zbc)` | `clmul` `clmulh` `clmulr` | 3 + 32 |======================= [NOTE]
/neorv32/trunk/docs/datasheet/on_chip_debugger.adoc
434,6 → 434,12
* a data buffer to transfer data between the processor and the debugger host
* a status register to communicate debugging requests
 
.DM Register Access
[IMPORTANT]
All memory-mapped registers of the DM can only be accessed by the CPU if it is actually _in_ debug mode.
Hence, the DM registers are not "visible" for normal CPU operations.
Any access outside of debug mode will raise a bus error exception.
 
.Park Loop Code Sources
[NOTE]
The assembly sources of the **park loop code** are available in `sw/ocd-firmware/park_loop.S`. Please note, that these
/neorv32/trunk/docs/datasheet/overview.adoc
38,77 → 38,11
 
<<<
// ####################################################################################################################
:sectnums:
=== Rationale
 
**Why did you make this?**
include::rationale.adoc[]
 
I am fascinated by processor and CPU architecture design: it is the magic frontier where software meets hardware.
This project has started as something like a _journey_ into this magic realm to understand how things actually work
down on this very low level.
 
But there is more! When I started to dive into the emerging RISC-V ecosystem I felt overwhelmed by the complexity.
As a beginner it is hard to get an overview - especially when you want to setup a minimal platform to tinker with:
Which core to use? How to get the right toolchain? What features do I need? How does the booting work? How do I
create an actual executable? How to get that into the hardware? How to customize things? **_Where to start???_**
 
So this project aims to provides a _simple to understand_ and _easy to use_ yet _powerful_ and _flexible_ platform
that targets FPGA and RISC-V beginners as well as advanced users. Join me and us on this journey! 🙃
 
 
**Why a _soft_-core processor?**
 
As a matter of fact soft-core processors _cannot_ compete with discrete or FPGA hard-macro processors in terms
of performance, energy and size. But they do fill a niche in FPGA design space. For example, soft-core processors
allow to implement the _control flow part_ of certain applications (like communication protocol handling) using
software like plain C. This provides high flexibility as software can be easily changed, re-compiled and
re-uploaded again.
 
Furthermore, the concept of flexibility applies to all aspects of a soft-core processor. The user can add
_exactly_ the features that are required by the application: additional memories, custom interfaces, specialized
IP and even user-defined instructions.
 
 
**Why RISC-V?**
 
[quote, RISC-V International, https://riscv.org/about/]
____
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
____
 
I love the idea of open-source. **Knowledge can help best if it is freely available.**
While open-source has already become quite popular in _software_, hardware projects still need to catch up.
Admittedly, there has been quite a development, but mainly in terms of _platforms_ and _applications_ (so
schematics, PCBs, etc.). Although processors and CPUs are the heart of almost every digital system, having a true
open-source silicon is still a rarity. RISC-V aims to change that. Even it is _just one approach_, it helps paving
the road for future development.
 
Furthermore, I welcome the community aspect of RISC-V. The ISA and everything beyond is developed with direct
contact to the community: this includes businesses and professionals but also hobbyist, amateurs and people
that are just curious. Everyone can join discussions and contribute to RISC-V in their very own way.
 
Finally, I really like the RISC-V ISA itself. It aims to be a clean, orthogonal and "intuitive" ISA that
resembles with the basic concepts of _RISC_: simple yet effective.
 
 
**Yet another RISC-V core? What makes it special?**
 
The NEORV32 is not based on another RISC-V core. It was build entirely from ground up (just following the official
ISA specs) having a different design goal in mind. The project does not intend to replace certain RISC-V cores or
just beat existing ones like https://github.com/SpinalHDL/VexRiscv[VexRISC] in terms of performance or
https://github.com/olofk/serv[SERV] in terms of size.
 
The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
RISC-V compatibility, _customization_ and _ease of use_. See the <<_project_key_features>> below.
 
Furthermore, the NEORV32 pays special focus on _execution safety_ using <<_full_virtualization>>. The CPU aims to
provide fall-backs for _everything that could go wrong_. This includes malformed instruction words, privilege escalations
and even memory accesses that are checked for address space holes and deterministic response times from memory-mapped
devices. Precise exceptions allow a defined and fully-synchronized state of the CPU at every time.
 
 
 
// ####################################################################################################################
:sectnums:
=== Project Key Features
167,9 → 101,6
│├system_integration - System wrappers for advanced connectivity
│└test_setups - Minimal test setup "SoCs" used in the User Guide
│
├setups - Example setups for various FPGAs, boards and toolchains
│└...
│
├sim - Simulation files (see User Guide)
│
â””sw - Software framework
347,7 → 278,7
:sectnums:
==== Exemplary Setups
 
Check out the `setups` folder (@GitHub: https://github.com/stnolting/neorv32/tree/master/setups),
Check out the `neorv32-setups` repository (@GitHub: https://github.com/stnolting/neorv32-setups),
which provides several demo setups for various FPGA boards and toolchains.
 
 
389,6 → 320,10
| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54**
|=======================
 
[IMPORTANT]
The CoreMark results were generated using a `rv32i` toolchain. This toolchain supports standard extensions
like `M` and `C` but the built-in libraries only use the base `I` ISA.
 
[NOTE]
The "_performance_" CPU configuration uses the <<_fast_mul_en>> and <<_fast_shift_en>> options.
 
/neorv32/trunk/docs/datasheet/rationale.adoc
0,0 → 1,68
:sectnums:
=== Rationale
 
**Why did you make this?**
 
Processor and CPU architecture designs are fascinating things: they are the magic frontier where software meets hardware.
This project started as something like a _journey_ into this magic realm to understand how things actually work
down on this very low level and evolved over time to a capable system on chip.
 
But there is more: when I started to dive into the emerging RISC-V ecosystem I felt overwhelmed by the complexity.
As a beginner it is hard to get an overview - especially when you want to setup a minimal platform to tinker with...
Which core to use? How to get the right toolchain? What features do I need? How does booting work? How do I
create an actual executable? How to get that into the hardware? How to customize things? **_Where to start???_**
 
This project aims to provide a _simple to understand_ and _easy to use_ yet _powerful_ and _flexible_ platform
that targets FPGA and RISC-V beginners as well as advanced users.
 
 
**Why a _soft-core_ processor?**
 
As a matter of fact soft-core processors _cannot_ compete with discrete (like FPGA hard-macro) processors in terms
of performance, energy efficiency and size. But they do fill a niche in FPGA design space: for example, soft-core processors
allow to implement the _control flow part_ of certain applications (e.g. communication protocol handling) using
software like plain C. This provides high flexibility as software can be easily changed, re-compiled and
re-uploaded again.
 
Furthermore, the concept of flexibility applies to all aspects of a soft-core processor. The user can add
_exactly_ the features that are required by the application: additional memories, custom interfaces, specialized
co-processors and even user-defined instructions.
 
 
**Why RISC-V?**
 
[quote, RISC-V International, https://riscv.org/about/]
____
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
____
 
Open-source is a great thing!
While open-source has already become quite popular in _software_, hardware-focused projects still need to catch up.
Admittedly, there has been quite a development, but mainly in terms of _platforms_ and _applications_ (so
schematics, PCBs, etc.). Although processors and CPUs are the heart of almost every digital system, having a true
open-source silicon is still a rarity. RISC-V aims to change that - and even it is _just one approach_, it helps paving
the road for future development.
 
Furthermore, I highly appreciate the community aspect of RISC-V. The ISA and everything beyond is developed in direct
contact with the community: this includes businesses and professionals but also hobbyist, amateurs and people
that are just curious. Everyone can join discussions and contribute to RISC-V in their very own way.
 
Finally, I really like the RISC-V ISA itself. It aims to be a clean, orthogonal and "intuitive" ISA that
resembles with the basic concepts of _RISC_: simple yet effective.
 
 
**Yet another RISC-V core? What makes it special?**
 
The NEORV32 is not based on another RISC-V core. It was build entirely from ground up (just following the official
ISA specs). The project does not intend to replace certain RISC-V cores or
just beat existing ones like https://github.com/SpinalHDL/VexRiscv[VexRISC] in terms of performance or
https://github.com/olofk/serv[SERV] in terms of size. It was build having a different design goal in mind.
 
The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
RISC-V compatibility, _customization_ and _ease of use_ (see the <<_project_key_features>> below).
 
Furthermore, the NEORV32 pays special focus on _execution safety_ using <<_full_virtualization>>. The CPU aims to
provide fall-backs for _everything that could go wrong_. This includes malformed instruction words, privilege escalations
and even memory accesses that are checked for address space holes and deterministic response times of memory-mapped
devices. Precise exceptions allow a defined and fully-synchronized state of the CPU at every time an in every situation.
/neorv32/trunk/docs/datasheet/soc_cfs.adoc
19,9 → 19,9
 
**Theory of Operation**
 
The custom functions subsystem is meant for implementing application-specific user-defined co-processors
IP footnote:[Intellectual IP; proprietary circuit blocks.] blocks. The CFS provides up to 32x 32-bit memory-mapped
registers (`REG`, see register map table below) that can be accessed by the CPU via normal load/store operations.
The custom functions subsystem is meant for implementing custom and application-specific logic.
The CFS provides up to 32x 32-bit memory-mapped
registers (`REG`, see register map below) that can be accessed by the CPU via normal load/store operations.
The actual functionality of these register has to be defined by the hardware designer. Furthermore, the CFS
provides two IO conduits to implement custom module- or chip-external interfaces.
 
52,10 → 52,13
uint32_t temp = NEORV32_CFS.REG[20]; // read from CFS register 20
----
 
[TIP]
A very simple example program that uses the _default_ CFS hardware module can be found in `sw/example/cfs_demo`.
 
 
**CFS Interrupt**
 
The CFS provides a single rising-edge-triggered interrupt request signal mapped to the CPU's fast interrupt channel 1.
The CFS provides a single high-level-triggered interrupt request signal mapped to the CPU's fast interrupt channel 1.
Once triggered, the interrupt becomes pending (if enabled in the `mis` CSR) and has to be explicitly cleared again by setting
the according `mip` CSR bit. See section <<_processor_interrupts>> for more information.
 
64,7 → 67,7
 
By default, the CFS provides a single 32-bit `std_(u)logic_vector` configuration generic _IO_CFS_CONFIG_
that is available in the processor's top entity. This generic can be used to pass custom configuration options
from the top entity directly down to the CFS. The actual definition of the generics and it'S usage inside the
from the top entity directly down to the CFS. The actual definition of the generic and it's usage inside the
CFS is left to the hardware designer.
 
 
72,7 → 75,7
 
By default, the CFS also provides two unidirectional input and output conduits `cfs_in_i` and `cfs_out_o`.
These signals are directly propagated to the processor's top entity. These conduits can be used to implement
application-specific interfaces like memory or network connections. The actual use case of these signals
application-specific interfaces like memory or peripheral connections. The actual use case of these signals
has to be defined by the hardware designer.
 
The size of the input signal conduit `cfs_in_i` is defined via the top's _IO_CFS_IN_SIZE_ configuration
/neorv32/trunk/docs/datasheet/soc_icache.adoc
48,6 → 48,11
By executing the `ifence.i` instruction (`Zifencei` CPU extension) the cache is cleared and a reload from
main memory is triggered. Among other things this allows to implement self-modifying code.
 
.Retrieve Cache Configuration from Software
[TIP]
Software can retrieve the cache configuration from the <<_sysinfo_cache_configuration>> register.
 
 
**Bus Access Fault Handling**
 
The cache always loads a complete cache block (_ICACHE_BLOCK_SIZE_ bytes) aligned to it's size every time a
/neorv32/trunk/docs/userguide/application_program_compilation.adoc
39,6 → 39,10
3188
----
 
[NOTE]
Make sure the size of the `text` segment (3176 bytes here) does not overflow the size of the processor's
IMEM (if used at all) - otherwise there will be an error during synthesis or during bootloader upload.
 
[start=5]
. That's it. The `exe` target has created the actual executable `neorv32_exe.bin` in the current folder
that is ready to be uploaded to the processor.
/neorv32/trunk/docs/userguide/content.adoc
5,10 → 5,13
follow these guides step by step and eventually in the presented order.
 
[TIP]
This guide uses the minimalistic and platform/toolchain agnostic SoC test setups from
This guide uses the minimalistic and platform/toolchain agnostic SoC **test setups** from
`rtl/test_setups` for illustration. You can use one of the provided test setups for
your first FPGA tests. Alternatively, have a look at the `setups` folder,
which provides more sophisticated example setups for various FPGAs/FPGA boards and toolchains.
your first FPGA tests. +
+
For more sophisticated example setups have a look at the
https://github.com/stnolting/neorv32-setups[neorv32-setups] repository,
which provides **SoC setups** for various FPGAs, boards and toolchains.
 
 
include::sw_toolchain_setup.adoc[]
/neorv32/trunk/docs/userguide/general_hw_setup.adoc
43,7 → 43,7
(IMEM and DMEM). These are located in `rtl/core/mem` so make sure to add the files to your project, too. +
+
If synthesis cannot efficiently map those default memory descriptions to the available memory resources, you can later replace the
default memory architectures by optimized platform-specific memory architectures. **Example:** The `setups/radiant/UPduino_v3`
default memory architectures by optimized platform-specific memory architectures. **Example:** The `neorv32-setups/radiant/UPduino_v3`
example setup uses optimized memory primitives. Hence, it does not include the default memory architectures from
`rtl/core/mem` as these are replaced by device-specific implementations. However, it still has to include the entity
definitions from `rtl/core`.
/neorv32/trunk/docs/userguide/sw_toolchain_setup.adoc
71,7 → 71,7
 
[source,bash]
----
$ export PATH:$PATH:/opt/riscv/bin
$ export PATH=$PATH:/opt/riscv/bin
----
 
You should add this command to your `.bashrc` (if you are using bash) to automatically add the RISC-V
/neorv32/trunk/docs/README.md
0,0 → 1,29
## Project Documentation
 
 
### [`datasheet`](https://github.com/stnolting/neorv32/tree/master/docs/datasheet)
 
AsciiDoc sources for the NEORV32 data sheet. The online version of the data sheet is
available at [https://stnolting.github.io/neorv32](https://stnolting.github.io/neorv32).
 
 
### [`figures`](https://github.com/stnolting/neorv32/tree/master/docs/figures`)
 
Figures and images used by the data sheet, user guide and the webpage(s). The according
license(s) are listed in [`figures/license.md`](https://github.com/stnolting/neorv32/blob/master/docs/figures/license.md).
 
 
### [`icons`](https://github.com/stnolting/neorv32/tree/master/docs/icons`)
 
Icons used by the data sheet and the user guide.
 
 
### [`references`](https://github.com/stnolting/neorv32/tree/master/docs/references`)
 
Reference material like RISC-V and Wishbone specifications.
 
 
### [`userguide`](https://github.com/stnolting/neorv32/tree/master/docs/userguide)
 
AsciiDoc sources for the NEORV32 user guide. The online version of the user guide is
available at [https://stnolting.github.io/neorv32/ug](https://stnolting.github.io/neorv32/ug).
/neorv32/trunk/docs/attrs.adoc
2,7 → 2,7
:email: stnolting@gmail.com
:keywords: neorv32, risc-v, riscv, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.6.6
:revnumber: v1.6.7
:doctype: book
:sectnums:
:stem:
/neorv32/trunk/rtl/core/neorv32_application_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin>
-- Size: 3448 bytes
-- Size: 3424 bytes
 
library ieee;
use ieee.std_logic_1164.all;
67,7 → 67,7
00000053 => x"00158593",
00000054 => x"ff5ff06f",
00000055 => x"00001597",
00000056 => x"c9c58593",
00000056 => x"c8458593",
00000057 => x"80000617",
00000058 => x"f1c60613",
00000059 => x"80000697",
114,15 → 114,15
00000100 => x"b0050513",
00000101 => x"00112623",
00000102 => x"088000ef",
00000103 => x"768000ef",
00000103 => x"750000ef",
00000104 => x"00050c63",
00000105 => x"714000ef",
00000105 => x"6fc000ef",
00000106 => x"00001537",
00000107 => x"ab050513",
00000107 => x"a9850513",
00000108 => x"134000ef",
00000109 => x"020000ef",
00000110 => x"00001537",
00000111 => x"a8c50513",
00000111 => x"a7450513",
00000112 => x"124000ef",
00000113 => x"00c12083",
00000114 => x"00100513",
133,14 → 133,14
00000119 => x"00000593",
00000120 => x"00112623",
00000121 => x"00812423",
00000122 => x"72c000ef",
00000122 => x"714000ef",
00000123 => x"00000513",
00000124 => x"00150413",
00000125 => x"00000593",
00000126 => x"0ff57513",
00000127 => x"718000ef",
00000127 => x"700000ef",
00000128 => x"0c800513",
00000129 => x"164000ef",
00000129 => x"14c000ef",
00000130 => x"00040513",
00000131 => x"fe5ff06f",
00000132 => x"fe802503",
157,7 → 157,7
00000143 => x"00151593",
00000144 => x"00078513",
00000145 => x"00060493",
00000146 => x"798000ef",
00000146 => x"780000ef",
00000147 => x"01051513",
00000148 => x"000017b7",
00000149 => x"01055513",
218,661 → 218,655
00000204 => x"00048513",
00000205 => x"f99ff0ef",
00000206 => x"fc9ff06f",
00000207 => x"ff010113",
00000208 => x"c81026f3",
00000209 => x"c0102773",
00000210 => x"c81027f3",
00000211 => x"fed79ae3",
00000212 => x"00e12023",
00000213 => x"00f12223",
00000214 => x"00012503",
00000215 => x"00412583",
00000216 => x"01010113",
00000217 => x"00008067",
00000218 => x"fd010113",
00000219 => x"00a12623",
00000220 => x"fe002503",
00000221 => x"3e800593",
00000222 => x"02112623",
00000223 => x"02812423",
00000224 => x"02912223",
00000225 => x"03212023",
00000226 => x"01312e23",
00000227 => x"654000ef",
00000228 => x"00c12603",
00000229 => x"00000693",
00000230 => x"00000593",
00000231 => x"5ac000ef",
00000232 => x"00050413",
00000233 => x"00058993",
00000234 => x"f95ff0ef",
00000235 => x"00058913",
00000236 => x"00050493",
00000237 => x"f89ff0ef",
00000238 => x"00b96663",
00000239 => x"05259263",
00000240 => x"04a4f063",
00000241 => x"008484b3",
00000242 => x"0084b433",
00000243 => x"01390933",
00000244 => x"01240433",
00000245 => x"f69ff0ef",
00000246 => x"fe85eee3",
00000247 => x"00b41463",
00000248 => x"fe956ae3",
00000249 => x"02c12083",
00000250 => x"02812403",
00000251 => x"02412483",
00000252 => x"02012903",
00000253 => x"01c12983",
00000254 => x"03010113",
00000255 => x"00008067",
00000256 => x"01c99913",
00000257 => x"00445413",
00000258 => x"00896433",
00000259 => x"00040a63",
00000260 => x"00040863",
00000261 => x"fff40413",
00000262 => x"00000013",
00000263 => x"ff1ff06f",
00000264 => x"fc5ff06f",
00000265 => x"fc010113",
00000266 => x"02112e23",
00000267 => x"02512c23",
00000268 => x"02612a23",
00000269 => x"02712823",
00000270 => x"02a12623",
00000271 => x"02b12423",
00000272 => x"02c12223",
00000273 => x"02d12023",
00000274 => x"00e12e23",
00000275 => x"00f12c23",
00000276 => x"01012a23",
00000277 => x"01112823",
00000278 => x"01c12623",
00000279 => x"01d12423",
00000280 => x"01e12223",
00000281 => x"01f12023",
00000282 => x"34102773",
00000283 => x"34071073",
00000284 => x"342027f3",
00000285 => x"0407c463",
00000286 => x"00071683",
00000287 => x"00300593",
00000288 => x"0036f693",
00000289 => x"00270613",
00000290 => x"00b69463",
00000291 => x"00470613",
00000292 => x"34161073",
00000293 => x"00b00713",
00000294 => x"00f77663",
00000295 => x"69000793",
00000296 => x"0500006f",
00000297 => x"00001737",
00000298 => x"00279793",
00000299 => x"acc70713",
00000300 => x"00e787b3",
00000301 => x"0007a783",
00000302 => x"00078067",
00000303 => x"80000737",
00000304 => x"ffd74713",
00000207 => x"c81027f3",
00000208 => x"c0102573",
00000209 => x"c81025f3",
00000210 => x"fef59ae3",
00000211 => x"00008067",
00000212 => x"fd010113",
00000213 => x"00a12623",
00000214 => x"fe002503",
00000215 => x"3e800593",
00000216 => x"02112623",
00000217 => x"02812423",
00000218 => x"02912223",
00000219 => x"03212023",
00000220 => x"01312e23",
00000221 => x"654000ef",
00000222 => x"00c12603",
00000223 => x"00000693",
00000224 => x"00000593",
00000225 => x"5ac000ef",
00000226 => x"00050413",
00000227 => x"00058993",
00000228 => x"fadff0ef",
00000229 => x"00058913",
00000230 => x"00050493",
00000231 => x"fa1ff0ef",
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00000233 => x"05259263",
00000234 => x"04a4f063",
00000235 => x"008484b3",
00000236 => x"0084b433",
00000237 => x"01390933",
00000238 => x"01240433",
00000239 => x"f81ff0ef",
00000240 => x"fe85eee3",
00000241 => x"00b41463",
00000242 => x"fe956ae3",
00000243 => x"02c12083",
00000244 => x"02812403",
00000245 => x"02412483",
00000246 => x"02012903",
00000247 => x"01c12983",
00000248 => x"03010113",
00000249 => x"00008067",
00000250 => x"01c99913",
00000251 => x"00445413",
00000252 => x"00896433",
00000253 => x"00040a63",
00000254 => x"00040863",
00000255 => x"fff40413",
00000256 => x"00000013",
00000257 => x"ff1ff06f",
00000258 => x"fc5ff06f",
00000259 => x"fc010113",
00000260 => x"02112e23",
00000261 => x"02512c23",
00000262 => x"02612a23",
00000263 => x"02712823",
00000264 => x"02a12623",
00000265 => x"02b12423",
00000266 => x"02c12223",
00000267 => x"02d12023",
00000268 => x"00e12e23",
00000269 => x"00f12c23",
00000270 => x"01012a23",
00000271 => x"01112823",
00000272 => x"01c12623",
00000273 => x"01d12423",
00000274 => x"01e12223",
00000275 => x"01f12023",
00000276 => x"34102773",
00000277 => x"34071073",
00000278 => x"342027f3",
00000279 => x"0407c463",
00000280 => x"00071683",
00000281 => x"00300593",
00000282 => x"0036f693",
00000283 => x"00270613",
00000284 => x"00b69463",
00000285 => x"00470613",
00000286 => x"34161073",
00000287 => x"00b00713",
00000288 => x"00f77663",
00000289 => x"67800793",
00000290 => x"0500006f",
00000291 => x"00001737",
00000292 => x"00279793",
00000293 => x"ab470713",
00000294 => x"00e787b3",
00000295 => x"0007a783",
00000296 => x"00078067",
00000297 => x"80000737",
00000298 => x"ffd74713",
00000299 => x"00e787b3",
00000300 => x"01c00713",
00000301 => x"fcf768e3",
00000302 => x"00001737",
00000303 => x"00279793",
00000304 => x"ae470713",
00000305 => x"00e787b3",
00000306 => x"01c00713",
00000307 => x"fcf768e3",
00000308 => x"00001737",
00000309 => x"00279793",
00000310 => x"afc70713",
00000311 => x"00e787b3",
00000312 => x"0007a783",
00000313 => x"00078067",
00000314 => x"800007b7",
00000315 => x"0007a783",
00000316 => x"000780e7",
00000317 => x"03c12083",
00000318 => x"03812283",
00000319 => x"03412303",
00000320 => x"03012383",
00000321 => x"02c12503",
00000322 => x"02812583",
00000323 => x"02412603",
00000324 => x"02012683",
00000325 => x"01c12703",
00000326 => x"01812783",
00000327 => x"01412803",
00000328 => x"01012883",
00000329 => x"00c12e03",
00000330 => x"00812e83",
00000331 => x"00412f03",
00000332 => x"00012f83",
00000333 => x"04010113",
00000334 => x"30200073",
00000335 => x"800007b7",
00000336 => x"0047a783",
00000337 => x"fadff06f",
00000338 => x"8081a783",
00000339 => x"fa5ff06f",
00000340 => x"80c1a783",
00000341 => x"f9dff06f",
00000342 => x"8101a783",
00000343 => x"f95ff06f",
00000344 => x"8141a783",
00000345 => x"f8dff06f",
00000346 => x"8181a783",
00000347 => x"f85ff06f",
00000348 => x"81c1a783",
00000349 => x"f7dff06f",
00000350 => x"8201a783",
00000351 => x"f75ff06f",
00000352 => x"8241a783",
00000353 => x"f6dff06f",
00000354 => x"8281a783",
00000355 => x"f65ff06f",
00000356 => x"82c1a783",
00000357 => x"f5dff06f",
00000358 => x"8301a783",
00000359 => x"f55ff06f",
00000360 => x"8341a783",
00000361 => x"f4dff06f",
00000362 => x"8381a783",
00000363 => x"f45ff06f",
00000364 => x"83c1a783",
00000365 => x"f3dff06f",
00000366 => x"8401a783",
00000367 => x"f35ff06f",
00000368 => x"8441a783",
00000369 => x"f2dff06f",
00000370 => x"8481a783",
00000371 => x"f25ff06f",
00000372 => x"84c1a783",
00000373 => x"f1dff06f",
00000374 => x"8501a783",
00000375 => x"f15ff06f",
00000376 => x"8541a783",
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00000378 => x"8581a783",
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00000381 => x"efdff06f",
00000382 => x"8601a783",
00000383 => x"ef5ff06f",
00000384 => x"8641a783",
00000385 => x"eedff06f",
00000386 => x"8681a783",
00000387 => x"ee5ff06f",
00000388 => x"86c1a783",
00000389 => x"eddff06f",
00000390 => x"8701a783",
00000391 => x"ed5ff06f",
00000392 => x"fe010113",
00000393 => x"01212823",
00000394 => x"00050913",
00000395 => x"00001537",
00000396 => x"00912a23",
00000397 => x"b7050513",
00000398 => x"000014b7",
00000399 => x"00812c23",
00000400 => x"01312623",
00000401 => x"00112e23",
00000402 => x"01c00413",
00000403 => x"c99ff0ef",
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00000405 => x"ffc00993",
00000406 => x"008957b3",
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00000408 => x"00f487b3",
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00000411 => x"c61ff0ef",
00000412 => x"ff3414e3",
00000413 => x"01c12083",
00000414 => x"01812403",
00000415 => x"01412483",
00000416 => x"01012903",
00000417 => x"00c12983",
00000418 => x"02010113",
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00000421 => x"00112623",
00000422 => x"00812423",
00000423 => x"00912223",
00000424 => x"b71ff0ef",
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00000428 => x"c35ff0ef",
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00000436 => x"0087ee63",
00000437 => x"00001737",
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00000440 => x"00e787b3",
00000441 => x"0007a783",
00000442 => x"00078067",
00000443 => x"800007b7",
00000444 => x"00b78713",
00000445 => x"14e40e63",
00000446 => x"02876a63",
00000447 => x"00378713",
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00000451 => x"00001537",
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00000703 => x"00000484",
00000704 => x"00000484",
00000705 => x"00000580",
00000706 => x"00000484",
00000707 => x"00000484",
00000708 => x"00000484",
00000709 => x"00000484",
00000710 => x"00000588",
00000711 => x"00000590",
00000712 => x"00000598",
00000713 => x"000005a0",
00000714 => x"000005a8",
00000715 => x"000005b0",
00000716 => x"000005b8",
00000717 => x"000005c0",
00000718 => x"000005c8",
00000719 => x"000005d0",
00000720 => x"000005d8",
00000721 => x"000005e0",
00000722 => x"000005e8",
00000723 => x"000005f0",
00000724 => x"000005f8",
00000725 => x"00000600",
00000726 => x"00007830",
00000727 => x"4554523c",
00000728 => x"0000203e",
00000729 => x"74736e49",
00000730 => x"74637572",
00000731 => x"206e6f69",
00000732 => x"72646461",
00000733 => x"20737365",
00000734 => x"6173696d",
00000735 => x"6e67696c",
00000736 => x"00006465",
00000737 => x"74736e49",
00000738 => x"74637572",
00000739 => x"206e6f69",
00000740 => x"65636361",
00000741 => x"66207373",
00000742 => x"746c7561",
00000743 => x"00000000",
00000744 => x"656c6c49",
00000745 => x"206c6167",
00000746 => x"74736e69",
00000747 => x"74637572",
00000748 => x"006e6f69",
00000749 => x"61657242",
00000750 => x"696f706b",
00000751 => x"0000746e",
00000752 => x"64616f4c",
00000753 => x"64646120",
00000754 => x"73736572",
00000755 => x"73696d20",
00000756 => x"67696c61",
00000757 => x"0064656e",
00000758 => x"64616f4c",
00000759 => x"64646120",
00000760 => x"73736572",
00000761 => x"73696d20",
00000762 => x"67696c61",
00000763 => x"0064656e",
00000764 => x"64616f4c",
00000765 => x"63636120",
00000766 => x"20737365",
00000767 => x"6c756166",
00000768 => x"00000074",
00000769 => x"726f7453",
00000770 => x"64612065",
00000771 => x"73657264",
00000772 => x"696d2073",
00000773 => x"696c6173",
00000774 => x"64656e67",
00000775 => x"00000000",
00000776 => x"726f7453",
00000777 => x"63612065",
00000778 => x"73736563",
00000779 => x"75616620",
00000780 => x"0000746c",
00000781 => x"69766e45",
00000782 => x"6d6e6f72",
00000783 => x"20746e65",
00000784 => x"6c6c6163",
00000785 => x"6f726620",
00000786 => x"2d55206d",
00000787 => x"65646f6d",
00000788 => x"00000000",
00000789 => x"69766e45",
00000790 => x"6d6e6f72",
00000791 => x"20746e65",
00000792 => x"6c6c6163",
00000793 => x"6f726620",
00000794 => x"2d4d206d",
00000795 => x"65646f6d",
00000796 => x"00000000",
00000797 => x"6863614d",
00000798 => x"20656e69",
00000799 => x"74666f73",
00000800 => x"65726177",
00000801 => x"746e6920",
00000802 => x"75727265",
00000803 => x"00007470",
00000759 => x"63636120",
00000760 => x"20737365",
00000761 => x"6c756166",
00000762 => x"00000074",
00000763 => x"726f7453",
00000764 => x"64612065",
00000765 => x"73657264",
00000766 => x"696d2073",
00000767 => x"696c6173",
00000768 => x"64656e67",
00000769 => x"00000000",
00000770 => x"726f7453",
00000771 => x"63612065",
00000772 => x"73736563",
00000773 => x"75616620",
00000774 => x"0000746c",
00000775 => x"69766e45",
00000776 => x"6d6e6f72",
00000777 => x"20746e65",
00000778 => x"6c6c6163",
00000779 => x"6f726620",
00000780 => x"2d55206d",
00000781 => x"65646f6d",
00000782 => x"00000000",
00000783 => x"69766e45",
00000784 => x"6d6e6f72",
00000785 => x"20746e65",
00000786 => x"6c6c6163",
00000787 => x"6f726620",
00000788 => x"2d4d206d",
00000789 => x"65646f6d",
00000790 => x"00000000",
00000791 => x"6863614d",
00000792 => x"20656e69",
00000793 => x"74666f73",
00000794 => x"65726177",
00000795 => x"746e6920",
00000796 => x"75727265",
00000797 => x"00007470",
00000798 => x"6863614d",
00000799 => x"20656e69",
00000800 => x"656d6974",
00000801 => x"6e692072",
00000802 => x"72726574",
00000803 => x"00747075",
00000804 => x"6863614d",
00000805 => x"20656e69",
00000806 => x"656d6974",
00000807 => x"6e692072",
00000808 => x"72726574",
00000809 => x"00747075",
00000810 => x"6863614d",
00000811 => x"20656e69",
00000812 => x"65747865",
00000813 => x"6c616e72",
00000814 => x"746e6920",
00000815 => x"75727265",
00000816 => x"00007470",
00000817 => x"74736146",
00000818 => x"746e6920",
00000819 => x"75727265",
00000820 => x"00207470",
00000821 => x"6e6b6e55",
00000822 => x"206e776f",
00000823 => x"70617274",
00000824 => x"75616320",
00000825 => x"203a6573",
00000826 => x"00000000",
00000827 => x"49545b20",
00000828 => x"554f454d",
00000829 => x"52455f54",
00000830 => x"00005d52",
00000831 => x"45445b20",
00000832 => x"45434956",
00000833 => x"5252455f",
00000834 => x"0000005d",
00000835 => x"4d505b20",
00000836 => x"52455f50",
00000837 => x"00005d52",
00000838 => x"50204020",
00000839 => x"00003d43",
00000840 => x"544d202c",
00000841 => x"3d4c4156",
00000842 => x"00000000",
00000843 => x"522f3c20",
00000844 => x"0a3e4554",
00000845 => x"00000000",
00000846 => x"000007a0",
00000847 => x"000007b0",
00000848 => x"000007d8",
00000849 => x"000007e4",
00000850 => x"000007f0",
00000851 => x"000007fc",
00000852 => x"00000808",
00000853 => x"00000814",
00000854 => x"00000820",
00000855 => x"0000070c",
00000856 => x"0000070c",
00000857 => x"0000082c",
00000858 => x"33323130",
00000859 => x"37363534",
00000860 => x"42413938",
00000861 => x"46454443"
00000806 => x"65747865",
00000807 => x"6c616e72",
00000808 => x"746e6920",
00000809 => x"75727265",
00000810 => x"00007470",
00000811 => x"74736146",
00000812 => x"746e6920",
00000813 => x"75727265",
00000814 => x"00207470",
00000815 => x"6e6b6e55",
00000816 => x"206e776f",
00000817 => x"70617274",
00000818 => x"75616320",
00000819 => x"203a6573",
00000820 => x"00000000",
00000821 => x"49545b20",
00000822 => x"554f454d",
00000823 => x"52455f54",
00000824 => x"00005d52",
00000825 => x"45445b20",
00000826 => x"45434956",
00000827 => x"5252455f",
00000828 => x"0000005d",
00000829 => x"4d505b20",
00000830 => x"52455f50",
00000831 => x"00005d52",
00000832 => x"50204020",
00000833 => x"00003d43",
00000834 => x"544d202c",
00000835 => x"3d4c4156",
00000836 => x"00000000",
00000837 => x"522f3c20",
00000838 => x"0a3e4554",
00000839 => x"00000000",
00000840 => x"00000788",
00000841 => x"00000798",
00000842 => x"000007c0",
00000843 => x"000007cc",
00000844 => x"000007d8",
00000845 => x"000007e4",
00000846 => x"000007f0",
00000847 => x"000007fc",
00000848 => x"00000808",
00000849 => x"000006f4",
00000850 => x"000006f4",
00000851 => x"00000814",
00000852 => x"33323130",
00000853 => x"37363534",
00000854 => x"42413938",
00000855 => x"46454443"
);
 
end neorv32_application_image;
/neorv32/trunk/rtl/core/neorv32_bootloader_image.vhd
1,6 → 1,6
-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32
-- Auto-generated memory init file (for BOOTLOADER) from source file <bootloader/main.bin>
-- Size: 4040 bytes
-- Size: 4016 bytes
 
library ieee;
use ieee.std_logic_1164.all;
51,7 → 51,7
00000037 => x"00158593",
00000038 => x"ff5ff06f",
00000039 => x"00001597",
00000040 => x"f2c58593",
00000040 => x"f1458593",
00000041 => x"80010617",
00000042 => x"f5c60613",
00000043 => x"80010697",
111,13 → 111,13
00000097 => x"00000613",
00000098 => x"00000593",
00000099 => x"00200513",
00000100 => x"369000ef",
00000101 => x"3fd000ef",
00000100 => x"351000ef",
00000101 => x"3e5000ef",
00000102 => x"00048493",
00000103 => x"00050863",
00000104 => x"00100513",
00000105 => x"00000593",
00000106 => x"429000ef",
00000106 => x"411000ef",
00000107 => x"00005537",
00000108 => x"00000613",
00000109 => x"00000593",
136,46 → 136,46
00000122 => x"30479073",
00000123 => x"30046073",
00000124 => x"ffff1537",
00000125 => x"ef850513",
00000125 => x"ee050513",
00000126 => x"27d000ef",
00000127 => x"f1302573",
00000128 => x"23c000ef",
00000129 => x"ffff1537",
00000130 => x"f3050513",
00000130 => x"f1850513",
00000131 => x"269000ef",
00000132 => x"fe002503",
00000133 => x"228000ef",
00000134 => x"ffff1537",
00000135 => x"f3850513",
00000135 => x"f2050513",
00000136 => x"255000ef",
00000137 => x"30102573",
00000138 => x"214000ef",
00000139 => x"ffff1537",
00000140 => x"f4050513",
00000140 => x"f2850513",
00000141 => x"241000ef",
00000142 => x"fe402503",
00000143 => x"ffff1437",
00000144 => x"1fc000ef",
00000145 => x"ffff1537",
00000146 => x"f4850513",
00000146 => x"f3050513",
00000147 => x"229000ef",
00000148 => x"fe802503",
00000149 => x"1e8000ef",
00000150 => x"ffff1537",
00000151 => x"f5050513",
00000151 => x"f3850513",
00000152 => x"215000ef",
00000153 => x"ff802503",
00000154 => x"1d4000ef",
00000155 => x"f5840513",
00000155 => x"f4040513",
00000156 => x"205000ef",
00000157 => x"ff002503",
00000158 => x"1c4000ef",
00000159 => x"ffff1537",
00000160 => x"f6450513",
00000160 => x"f4c50513",
00000161 => x"1f1000ef",
00000162 => x"ffc02503",
00000163 => x"1b0000ef",
00000164 => x"f5840513",
00000164 => x"f4040513",
00000165 => x"1e1000ef",
00000166 => x"ff402503",
00000167 => x"1a0000ef",
182,7 → 182,7
00000168 => x"0bd000ef",
00000169 => x"06050663",
00000170 => x"ffff1537",
00000171 => x"f6c50513",
00000171 => x"f5450513",
00000172 => x"1c5000ef",
00000173 => x"219000ef",
00000174 => x"fe002403",
199,13 → 199,13
00000185 => x"00100513",
00000186 => x"4c8000ef",
00000187 => x"ffff1537",
00000188 => x"f9450513",
00000188 => x"f7c50513",
00000189 => x"181000ef",
00000190 => x"0d4000ef",
00000191 => x"16d000ef",
00000192 => x"fc050ae3",
00000193 => x"ffff1537",
00000194 => x"f9850513",
00000194 => x"f8050513",
00000195 => x"169000ef",
00000196 => x"0b0000ef",
00000197 => x"ffff19b7",
216,12 → 216,12
00000202 => x"07300c13",
00000203 => x"ffff1937",
00000204 => x"ffff1cb7",
00000205 => x"fa498513",
00000205 => x"f8c98513",
00000206 => x"13d000ef",
00000207 => x"11d000ef",
00000208 => x"00050413",
00000209 => x"0e1000ef",
00000210 => x"f94a0513",
00000210 => x"f7ca0513",
00000211 => x"129000ef",
00000212 => x"0ed000ef",
00000213 => x"fe051ee3",
246,19 → 246,19
00000232 => x"00f41c63",
00000233 => x"0004a783",
00000234 => x"f40798e3",
00000235 => x"ea0c8513",
00000235 => x"e88c8513",
00000236 => x"0c5000ef",
00000237 => x"f81ff06f",
00000238 => x"fac90513",
00000238 => x"f9490513",
00000239 => x"ff5ff06f",
00000240 => x"ffff1537",
00000241 => x"de050513",
00000241 => x"dc850513",
00000242 => x"0ad0006f",
00000243 => x"ff010113",
00000244 => x"00112623",
00000245 => x"30047073",
00000246 => x"ffff1537",
00000247 => x"e4450513",
00000247 => x"e2c50513",
00000248 => x"095000ef",
00000249 => x"059000ef",
00000250 => x"fe051ee3",
269,7 → 269,7
00000255 => x"00812423",
00000256 => x"00050413",
00000257 => x"ffff1537",
00000258 => x"e5450513",
00000258 => x"e3c50513",
00000259 => x"00112623",
00000260 => x"065000ef",
00000261 => x"03040513",
276,11 → 276,11
00000262 => x"0ff57513",
00000263 => x"009000ef",
00000264 => x"30047073",
00000265 => x"16d000ef",
00000265 => x"155000ef",
00000266 => x"00050863",
00000267 => x"00100513",
00000268 => x"00000593",
00000269 => x"19d000ef",
00000269 => x"185000ef",
00000270 => x"0000006f",
00000271 => x"fe010113",
00000272 => x"01212823",
287,7 → 287,7
00000273 => x"00050913",
00000274 => x"ffff1537",
00000275 => x"00912a23",
00000276 => x"e6050513",
00000276 => x"e4850513",
00000277 => x"ffff14b7",
00000278 => x"00812c23",
00000279 => x"01312623",
294,7 → 294,7
00000280 => x"00112e23",
00000281 => x"01c00413",
00000282 => x"00d000ef",
00000283 => x"fb848493",
00000283 => x"fa048493",
00000284 => x"ffc00993",
00000285 => x"008957b3",
00000286 => x"00f7f793",
333,10 → 333,10
00000319 => x"800007b7",
00000320 => x"00778793",
00000321 => x"08f49463",
00000322 => x"089000ef",
00000322 => x"071000ef",
00000323 => x"00050663",
00000324 => x"00000513",
00000325 => x"08d000ef",
00000325 => x"075000ef",
00000326 => x"644000ef",
00000327 => x"02050063",
00000328 => x"7ac000ef",
376,7 → 376,7
00000362 => x"5dc000ef",
00000363 => x"04050263",
00000364 => x"ffff1537",
00000365 => x"e6450513",
00000365 => x"e4c50513",
00000366 => x"6bc000ef",
00000367 => x"00048513",
00000368 => x"e7dff0ef",
389,7 → 389,7
00000375 => x"34302573",
00000376 => x"e5dff0ef",
00000377 => x"ffff1537",
00000378 => x"e6c50513",
00000378 => x"e5450513",
00000379 => x"688000ef",
00000380 => x"00440413",
00000381 => x"34141073",
398,14 → 398,14
00000384 => x"00000513",
00000385 => x"00112623",
00000386 => x"00812423",
00000387 => x"72c000ef",
00000387 => x"714000ef",
00000388 => x"09e00513",
00000389 => x"768000ef",
00000389 => x"750000ef",
00000390 => x"00000513",
00000391 => x"760000ef",
00000391 => x"748000ef",
00000392 => x"00050413",
00000393 => x"00000513",
00000394 => x"730000ef",
00000394 => x"718000ef",
00000395 => x"00c12083",
00000396 => x"0ff47513",
00000397 => x"00812403",
415,15 → 415,15
00000401 => x"00112623",
00000402 => x"00812423",
00000403 => x"00000513",
00000404 => x"6e8000ef",
00000404 => x"6d0000ef",
00000405 => x"00500513",
00000406 => x"724000ef",
00000406 => x"70c000ef",
00000407 => x"00000513",
00000408 => x"71c000ef",
00000408 => x"704000ef",
00000409 => x"00050413",
00000410 => x"00147413",
00000411 => x"00000513",
00000412 => x"6e8000ef",
00000412 => x"6d0000ef",
00000413 => x"fc041ce3",
00000414 => x"00c12083",
00000415 => x"00812403",
432,13 → 432,13
00000418 => x"ff010113",
00000419 => x"00000513",
00000420 => x"00112623",
00000421 => x"6a4000ef",
00000421 => x"68c000ef",
00000422 => x"00600513",
00000423 => x"6e0000ef",
00000423 => x"6c8000ef",
00000424 => x"00c12083",
00000425 => x"00000513",
00000426 => x"01010113",
00000427 => x"6ac0006f",
00000427 => x"6940006f",
00000428 => x"ff010113",
00000429 => x"00812423",
00000430 => x"00050413",
445,30 → 445,30
00000431 => x"01055513",
00000432 => x"0ff57513",
00000433 => x"00112623",
00000434 => x"6b4000ef",
00000434 => x"69c000ef",
00000435 => x"00845513",
00000436 => x"0ff57513",
00000437 => x"6a8000ef",
00000437 => x"690000ef",
00000438 => x"0ff47513",
00000439 => x"00812403",
00000440 => x"00c12083",
00000441 => x"01010113",
00000442 => x"6940006f",
00000442 => x"67c0006f",
00000443 => x"ff010113",
00000444 => x"00812423",
00000445 => x"00050413",
00000446 => x"00000513",
00000447 => x"00112623",
00000448 => x"638000ef",
00000448 => x"620000ef",
00000449 => x"00300513",
00000450 => x"674000ef",
00000450 => x"65c000ef",
00000451 => x"00040513",
00000452 => x"fa1ff0ef",
00000453 => x"00000513",
00000454 => x"664000ef",
00000454 => x"64c000ef",
00000455 => x"00050413",
00000456 => x"00000513",
00000457 => x"634000ef",
00000457 => x"61c000ef",
00000458 => x"00c12083",
00000459 => x"0ff47513",
00000460 => x"00812403",
521,7 → 521,7
00000507 => x"80418a13",
00000508 => x"02051863",
00000509 => x"ffff1537",
00000510 => x"e7050513",
00000510 => x"e5850513",
00000511 => x"478000ef",
00000512 => x"080005b7",
00000513 => x"00040513",
532,7 → 532,7
00000518 => x"00000513",
00000519 => x"01c0006f",
00000520 => x"ffff1537",
00000521 => x"e9050513",
00000521 => x"e7850513",
00000522 => x"44c000ef",
00000523 => x"dd1ff0ef",
00000524 => x"fc0518e3",
558,7 → 558,7
00000544 => x"00200513",
00000545 => x"fa049ae3",
00000546 => x"ffff1537",
00000547 => x"e9c50513",
00000547 => x"e8450513",
00000548 => x"3e4000ef",
00000549 => x"02c12083",
00000550 => x"02812403",
590,15 → 590,15
00000576 => x"00050493",
00000577 => x"d85ff0ef",
00000578 => x"00000513",
00000579 => x"42c000ef",
00000579 => x"414000ef",
00000580 => x"00200513",
00000581 => x"468000ef",
00000581 => x"450000ef",
00000582 => x"00048513",
00000583 => x"d95ff0ef",
00000584 => x"00040513",
00000585 => x"458000ef",
00000585 => x"440000ef",
00000586 => x"00000513",
00000587 => x"42c000ef",
00000587 => x"414000ef",
00000588 => x"00812403",
00000589 => x"00c12083",
00000590 => x"00412483",
632,13 → 632,13
00000618 => x"00050413",
00000619 => x"cddff0ef",
00000620 => x"00000513",
00000621 => x"384000ef",
00000621 => x"36c000ef",
00000622 => x"0d800513",
00000623 => x"3c0000ef",
00000623 => x"3a8000ef",
00000624 => x"00040513",
00000625 => x"cedff0ef",
00000626 => x"00000513",
00000627 => x"38c000ef",
00000627 => x"374000ef",
00000628 => x"00812403",
00000629 => x"00c12083",
00000630 => x"01010113",
655,7 → 655,7
00000641 => x"01512223",
00000642 => x"02041863",
00000643 => x"ffff1537",
00000644 => x"ea050513",
00000644 => x"e8850513",
00000645 => x"01812403",
00000646 => x"01c12083",
00000647 => x"01412483",
666,17 → 666,17
00000652 => x"02010113",
00000653 => x"2400006f",
00000654 => x"ffff1537",
00000655 => x"ebc50513",
00000655 => x"ea450513",
00000656 => x"234000ef",
00000657 => x"00040513",
00000658 => x"9f5ff0ef",
00000659 => x"ffff1537",
00000660 => x"ec450513",
00000660 => x"eac50513",
00000661 => x"220000ef",
00000662 => x"08000537",
00000663 => x"9e1ff0ef",
00000664 => x"ffff1537",
00000665 => x"edc50513",
00000665 => x"ec450513",
00000666 => x"20c000ef",
00000667 => x"1ec000ef",
00000668 => x"00050493",
688,7 → 688,7
00000674 => x"00300513",
00000675 => x"96dff0ef",
00000676 => x"ffff1537",
00000677 => x"ee850513",
00000677 => x"ed050513",
00000678 => x"01045493",
00000679 => x"1d8000ef",
00000680 => x"00148493",
718,7 → 718,7
00000704 => x"412005b3",
00000705 => x"e41ff0ef",
00000706 => x"ffff1537",
00000707 => x"e9c50513",
00000707 => x"e8450513",
00000708 => x"f05ff06f",
00000709 => x"00090513",
00000710 => x"e85ff0ef",
830,197 → 830,191
00000816 => x"00048513",
00000817 => x"f61ff0ef",
00000818 => x"fc9ff06f",
00000819 => x"ff010113",
00000820 => x"c81026f3",
00000821 => x"c0102773",
00000822 => x"c81027f3",
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00001000 => x"33323130",
00001001 => x"37363534",
00001002 => x"62613938",
00001003 => x"66656463"
);
 
end neorv32_bootloader_image;
/neorv32/trunk/rtl/core/neorv32_cfs.vhd
244,15 → 244,16
 
-- CFS Function Core ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
 
-- This is where the actual functionality can be implemented.
-- In this example we are just implementing four r/w registers that invert any value written to them.
 
-- The logic below is just a very simple example that transforms data
-- from an inpout register into data in an output register.
cfs_core_logic: process(cfs_reg_wr)
begin
cfs_reg_rd(0) <= not cfs_reg_wr(0);
cfs_reg_rd(1) <= not cfs_reg_wr(1);
cfs_reg_rd(2) <= not cfs_reg_wr(2);
cfs_reg_rd(3) <= not cfs_reg_wr(3);
cfs_reg_rd(0) <= bin_to_gray_f(cfs_reg_wr(0)); -- convert binary to gray code
cfs_reg_rd(1) <= gray_to_bin_f(cfs_reg_wr(1)); -- convert gray to binary code
cfs_reg_rd(2) <= bit_rev_f(cfs_reg_wr(2)); -- bit reversal
cfs_reg_rd(3) <= bswap32_f(cfs_reg_wr(3)); -- byte swap (endianness conversion)
end process cfs_core_logic;
 
 
/neorv32/trunk/rtl/core/neorv32_cpu.vhd
91,44 → 91,44
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
debug_o : out std_ulogic; -- cpu is in debug mode when set
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
debug_o : out std_ulogic; -- cpu is in debug mode when set
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_lock_o : out std_ulogic; -- exclusive access request
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_lock_o : out std_ulogic; -- exclusive access request
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
-- data bus interface --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_lock_o : out std_ulogic; -- exclusive access request
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_lock_o : out std_ulogic; -- exclusive access request
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic;-- machine software interrupt
mext_irq_i : in std_ulogic;-- machine external interrupt
mtime_irq_i : in std_ulogic;-- machine timer interrupt
msw_irq_i : in std_ulogic;-- machine software interrupt
mext_irq_i : in std_ulogic;-- machine external interrupt
mtime_irq_i : in std_ulogic;-- machine timer interrupt
-- fast interrupts (custom) --
firq_i : in std_ulogic_vector(15 downto 0);
firq_i : in std_ulogic_vector(15 downto 0);
-- debug mode (halt) request --
db_halt_req_i : in std_ulogic
db_halt_req_i : in std_ulogic
);
end neorv32_cpu;
 
194,6 → 194,9
assert not (dedicated_reset_c = true) report "NEORV32 CPU CONFIG NOTE: Implementing defined hardware reset for uncritical registers (non-default, reset-to-zero, might increase area)." severity note;
assert not ((def_rst_val_c /= '-') and (def_rst_val_c /= '0')) report "NEORV32 CPU CONFIG ERROR! Invalid configuration of package <def_rst_val_c> constant (has to be '-' or '0')." severity error;
 
-- CPU boot address alignment --
assert not (CPU_BOOT_ADDR(1 downto 0) /= "00") report "NEORV32 CPU CONFIG ERROR! <CPU_BOOT_ADDR> has to be 32-bit aligned." severity error;
 
-- CSR system --
assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/privileged features available when <CPU_EXTENSION_RISCV_Zicsr> = false." severity warning;
 
207,9 → 210,6
-- Instruction prefetch buffer size --
assert not (is_power_of_two_f(CPU_IPB_ENTRIES) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <CPU_IPB_ENTRIES> has to be a power of two." severity error;
 
-- Co-processor timeout counter (for debugging only) --
assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
 
-- PMP regions check --
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error;
-- PMP granularity --
387,53 → 387,53
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl, -- main control bus
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl, -- main control bus
-- cpu instruction fetch interface --
fetch_pc_i => fetch_pc, -- PC for instruction fetch
instr_o => instr, -- instruction
i_wait_o => bus_i_wait, -- wait for fetch to complete
fetch_pc_i => fetch_pc, -- PC for instruction fetch
instr_o => instr, -- instruction
i_wait_o => bus_i_wait, -- wait for fetch to complete
--
ma_instr_o => ma_instr, -- misaligned instruction address
be_instr_o => be_instr, -- bus error on instruction access
ma_instr_o => ma_instr, -- misaligned instruction address
be_instr_o => be_instr, -- bus error on instruction access
-- cpu data access interface --
addr_i => alu_add, -- ALU.add result -> access address
wdata_i => rs2, -- write data
rdata_o => mem_rdata, -- read data
mar_o => mar, -- current memory address register
d_wait_o => bus_d_wait, -- wait for access to complete
addr_i => alu_add, -- ALU.add result -> access address
wdata_i => rs2, -- write data
rdata_o => mem_rdata, -- read data
mar_o => mar, -- current memory address register
d_wait_o => bus_d_wait, -- wait for access to complete
--
excl_state_o => excl_state, -- atomic/exclusive access status
ma_load_o => ma_load, -- misaligned load data address
ma_store_o => ma_store, -- misaligned store data address
be_load_o => be_load, -- bus error on load data access
be_store_o => be_store, -- bus error on store data access
excl_state_o => excl_state, -- atomic/exclusive access status
ma_load_o => ma_load, -- misaligned load data address
ma_store_o => ma_store, -- misaligned store data address
be_load_o => be_load, -- bus error on load data access
be_store_o => be_store, -- bus error on store data access
-- physical memory protection --
pmp_addr_i => pmp_addr, -- addresses
pmp_ctrl_i => pmp_ctrl, -- configurations
pmp_addr_i => pmp_addr, -- addresses
pmp_ctrl_i => pmp_ctrl, -- configurations
-- instruction bus --
i_bus_addr_o => i_bus_addr_o, -- bus access address
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
i_bus_ben_o => i_bus_ben_o, -- byte enable
i_bus_we_o => i_bus_we_o, -- write enable
i_bus_re_o => i_bus_re_o, -- read enable
i_bus_lock_o => i_bus_lock_o, -- exclusive access request
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
i_bus_err_i => i_bus_err_i, -- bus transfer error
i_bus_fence_o => i_bus_fence_o, -- fence operation
i_bus_addr_o => i_bus_addr_o, -- bus access address
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
i_bus_ben_o => i_bus_ben_o, -- byte enable
i_bus_we_o => i_bus_we_o, -- write enable
i_bus_re_o => i_bus_re_o, -- read enable
i_bus_lock_o => i_bus_lock_o, -- exclusive access request
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
i_bus_err_i => i_bus_err_i, -- bus transfer error
i_bus_fence_o => i_bus_fence_o, -- fence operation
-- data bus --
d_bus_addr_o => d_bus_addr_o, -- bus access address
d_bus_rdata_i => d_bus_rdata_i, -- bus read data
d_bus_wdata_o => d_bus_wdata_o, -- bus write data
d_bus_ben_o => d_bus_ben_o, -- byte enable
d_bus_we_o => d_bus_we_o, -- write enable
d_bus_re_o => d_bus_re_o, -- read enable
d_bus_lock_o => d_bus_lock_o, -- exclusive access request
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
d_bus_err_i => d_bus_err_i, -- bus transfer error
d_bus_fence_o => d_bus_fence_o -- fence operation
d_bus_addr_o => d_bus_addr_o, -- bus access address
d_bus_rdata_i => d_bus_rdata_i, -- bus read data
d_bus_wdata_o => d_bus_wdata_o, -- bus write data
d_bus_ben_o => d_bus_ben_o, -- byte enable
d_bus_we_o => d_bus_we_o, -- write enable
d_bus_re_o => d_bus_re_o, -- read enable
d_bus_lock_o => d_bus_lock_o, -- exclusive access request
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
d_bus_err_i => d_bus_err_i, -- bus transfer error
d_bus_fence_o => d_bus_fence_o -- fence operation
);
 
-- current privilege level --
/neorv32/trunk/rtl/core/neorv32_cpu_alu.vhd
91,18 → 91,17
 
-- co-processor arbiter and interface --
type cp_ctrl_t is record
cmd : std_ulogic;
cmd_ff : std_ulogic;
start : std_ulogic;
busy : std_ulogic;
timeout : std_ulogic_vector(9 downto 0);
cmd : std_ulogic;
cmd_ff : std_ulogic;
start : std_ulogic;
end record;
signal cp_ctrl : cp_ctrl_t;
 
-- co-processor interface --
signal cp_start : std_ulogic_vector(3 downto 0); -- trigger co-processor i
signal cp_valid : std_ulogic_vector(3 downto 0); -- co-processor i done
type cp_data_if_t is array (0 to 7) of std_ulogic_vector(data_width_c-1 downto 0);
signal cp_result : cp_data_if_t; -- co-processor result
signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
signal cp_valid : std_ulogic_vector(7 downto 0); -- co-processor i done
 
begin
 
182,36 → 181,21
 
 
-- **************************************************************************************************************************
-- Co-Processors
-- CPU Co-Processors
-- **************************************************************************************************************************
 
-- Co-Processor Interface --
-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
 
-- Co-Processor Arbiter -------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Interface:
-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
cp_arbiter: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
cp_ctrl.cmd_ff <= '0';
cp_ctrl.busy <= '0';
cp_ctrl.timeout <= (others => '0');
cp_ctrl.cmd_ff <= '0';
elsif rising_edge(clk_i) then
cp_ctrl.cmd_ff <= cp_ctrl.cmd;
-- timeout counter --
if (cp_ctrl.start = '1') then
cp_ctrl.busy <= '1';
elsif (or_reduce_f(cp_valid) = '1') then
cp_ctrl.busy <= '0';
end if;
if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then
cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1);
else
cp_ctrl.timeout <= (others => '0');
end if;
if (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
end if;
end if;
end process cp_arbiter;
 
219,17 → 203,21
cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_copro_c) else '0';
cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
 
-- co-processor select / star trigger --
cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0';
cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0';
-- co-processor select / start trigger --
cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "000") else '0';
cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "001") else '0';
cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "010") else '0';
cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "011") else '0';
cp_start(4) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "100") else '0';
cp_start(5) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "101") else '0';
cp_start(6) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "110") else '0';
cp_start(7) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "111") else '0';
 
-- co-processor operation done? --
idone_o <= or_reduce_f(cp_valid);
 
-- co-processor result - only the *actually selected* co-processor may output data != 0 --
cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3);
cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3) or cp_result(4) or cp_result(5) or cp_result(6) or cp_result(7);
 
 
-- Co-Processor 0: Shifter (CPU Core ISA) --------------------------------------------------
280,7 → 268,7
neorv32_cpu_cp_muldiv_inst_false:
if (CPU_EXTENSION_RISCV_M = false) and (CPU_EXTENSION_RISCV_Zmmul = false) generate
cp_result(1) <= (others => '0');
cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
cp_valid(1) <= '0';
end generate;
 
 
312,7 → 300,7
neorv32_cpu_cp_bitmanip_inst_false:
if (CPU_EXTENSION_RISCV_B = false) generate
cp_result(2) <= (others => '0');
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
cp_valid(2) <= '0';
end generate;
 
 
342,8 → 330,32
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
cp_result(3) <= (others => '0');
fpu_flags_o <= (others => '0');
cp_valid(3) <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access
cp_valid(3) <= '0';
end generate;
 
 
-- Co-Processor 4: Reserved ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
cp_result(4) <= (others => '0');
cp_valid(4) <= '0';
 
 
-- Co-Processor 5: Reserved ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
cp_result(5) <= (others => '0');
cp_valid(5) <= '0';
 
 
-- Co-Processor 6: Reserved ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
cp_result(6) <= (others => '0');
cp_valid(6) <= '0';
 
 
-- Co-Processor 7: Reserved ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
cp_result(7) <= (others => '0');
cp_valid(7) <= '0';
 
 
end neorv32_cpu_cpu_rtl;
/neorv32/trunk/rtl/core/neorv32_cpu_bus.vhd
193,14 → 193,12
end if;
end process mem_adr_reg;
 
-- read-back for exception controller --
-- address read-back for exception controller --
mar_o <= mar;
 
-- alignment check --
misaligned_d_check: process(mar, ctrl_i)
begin
-- check data access --
d_misaligned <= '0'; -- default
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
when "00" => -- byte
d_misaligned <= '0';
207,10 → 205,14
when "01" => -- half-word
if (mar(0) /= '0') then
d_misaligned <= '1';
else
d_misaligned <= '0';
end if;
when others => -- word
if (mar(1 downto 0) /= "00") then
d_misaligned <= '1';
else
d_misaligned <= '0';
end if;
end case;
end process misaligned_d_check;
230,14 → 232,14
end process mem_do_reg;
 
-- byte enable and output data alignment --
byte_enable: process(mar, mdo, ctrl_i)
write_align: process(mar, mdo, ctrl_i)
begin
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
when "00" => -- byte
d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
d_bus_wdata(07 downto 00) <= mdo(7 downto 0);
d_bus_wdata(15 downto 08) <= mdo(7 downto 0);
d_bus_wdata(23 downto 16) <= mdo(7 downto 0);
d_bus_wdata(31 downto 24) <= mdo(7 downto 0);
case mar(1 downto 0) is
when "00" => d_bus_ben <= "0001";
when "01" => d_bus_ben <= "0010";
245,8 → 247,8
when others => d_bus_ben <= "1000";
end case;
when "01" => -- half-word
d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
d_bus_wdata(31 downto 16) <= mdo(15 downto 0);
d_bus_wdata(15 downto 00) <= mdo(15 downto 0);
if (mar(1) = '0') then
d_bus_ben <= "0011"; -- low half-word
else
256,7 → 258,7
d_bus_wdata <= mdo;
d_bus_ben <= "1111"; -- full word
end case;
end process byte_enable;
end process write_align;
 
 
-- Data Interface: Read Data --------------------------------------------------------------
274,26 → 276,25
 
-- input data alignment and sign extension --
read_align: process(mdi, mar, ctrl_i)
variable byte_in_v : std_ulogic_vector(07 downto 0);
variable hword_in_v : std_ulogic_vector(15 downto 0);
variable shifted_data_v : std_ulogic_vector(31 downto 0);
begin
-- sub-word input --
-- align input word --
case mar(1 downto 0) is
when "00" => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0
when "01" => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0
when "10" => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1
when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1
when "00" => shifted_data_v := mdi(31 downto 00);
when "01" => shifted_data_v := x"00" & mdi(31 downto 08);
when "10" => shifted_data_v := x"0000" & mdi(31 downto 16);
when others => shifted_data_v := x"000000" & mdi(31 downto 24);
end case;
-- actual data size --
-- actual data size and sign-extension --
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
when "00" => -- byte
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension
rdata_align(07 downto 00) <= byte_in_v;
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and shifted_data_v(7))); -- sign extension
rdata_align(07 downto 00) <= shifted_data_v(07 downto 00);
when "01" => -- half-word
rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension
rdata_align(15 downto 00) <= hword_in_v; -- high half-word
rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and shifted_data_v(15))); -- sign extension
rdata_align(15 downto 00) <= shifted_data_v(15 downto 00); -- high half-word
when others => -- word
rdata_align <= mdi; -- full word
rdata_align <= shifted_data_v; -- full word
end case;
end process read_align;
 
319,8 → 320,7
d_arbiter.err_bus <= '0';
else -- in progress
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
d_arbiter.err_bus <= (d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and
(not ctrl_i(ctrl_bus_derr_ack_c));
d_arbiter.err_bus <= (d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and (not ctrl_i(ctrl_bus_derr_ack_c));
if ((d_bus_ack_i = '1') and (d_bus_err_i = '0')) or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
d_arbiter.wr_req <= '0';
d_arbiter.rd_req <= '0';
407,7 → 407,7
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
i_arbiter.err_align <= i_misaligned;
i_arbiter.err_bus <= '0';
else -- in progres
else -- in progress
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
i_arbiter.err_bus <= (i_arbiter.err_bus or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c));
if ((i_bus_ack_i = '1') and (i_bus_err_i = '0')) or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
/neorv32/trunk/rtl/core/neorv32_cpu_control.vhd
1,11 → 1,14
-- #################################################################################################
-- # << NEORV32 - CPU Control >> #
-- # << NEORV32 - CPU Operations Control Unit >> #
-- # ********************************************************************************************* #
-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an #
-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction #
-- # words) and an execute engine (responsible for actually executing the instructions), a trap #
-- # handling controller and the RISC-V status and control register set (CSRs) including the #
-- # hardware performance monitor counters. #
-- # CPU operations are controlled by several "engines" (modules). These engines operate in #
-- # parallel to implement a simple pipeline: #
-- # + Fetch engine: Fetches 32-bit chunks of instruction words #
-- # + Issue engine: Decodes compressed instructions, aligns and queues instruction words #
-- # + Execute engine: Multi-cycle execution of instructions (generate control signals) #
-- # + Trap engine: Handles interrupts and exceptions #
-- # + CSR module: Read/write accesses to CSRs & HW counters #
-- # + Debug module: CPU debug mode handling (on-chip debugger) #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
166,14 → 169,13
signal ci_illegal : std_ulogic;
 
-- instruction issue engine --
type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN);
type issue_engine_t is record
state : issue_engine_state_t;
state_nxt : issue_engine_state_t;
align : std_ulogic;
align_nxt : std_ulogic;
buf : std_ulogic_vector(2+15 downto 0);
buf_nxt : std_ulogic_vector(2+15 downto 0);
realign : std_ulogic;
realign_nxt : std_ulogic;
align : std_ulogic;
align_nxt : std_ulogic;
buf : std_ulogic_vector(2+15 downto 0);
buf_nxt : std_ulogic_vector(2+15 downto 0);
end record;
signal issue_engine : issue_engine_t;
 
186,17 → 188,17
 
-- instruction decoding helper logic --
type decode_aux_t is record
is_atomic_lr : std_ulogic;
is_atomic_sc : std_ulogic;
is_float_op : std_ulogic;
sys_env_cmd : std_ulogic_vector(11 downto 0);
is_m_mul : std_ulogic;
is_m_div : std_ulogic;
is_bitmanip_imm : std_ulogic;
is_bitmanip_reg : std_ulogic;
rs1_zero : std_ulogic;
rs2_zero : std_ulogic;
rd_zero : std_ulogic;
is_a_lr : std_ulogic;
is_a_sc : std_ulogic;
is_f_op : std_ulogic;
sys_env_cmd : std_ulogic_vector(11 downto 0);
is_m_mul : std_ulogic;
is_m_div : std_ulogic;
is_b_imm : std_ulogic;
is_b_reg : std_ulogic;
rs1_zero : std_ulogic;
rs2_zero : std_ulogic;
rd_zero : std_ulogic;
end record;
signal decode_aux : decode_aux_t;
 
238,7 → 240,7
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
exc_ack : std_ulogic; -- acknowledge all exceptions
exc_clr : std_ulogic; -- clear all buffered exceptions
cause : std_ulogic_vector(6 downto 0); -- trap ID for mcause CSR
cause_nxt : std_ulogic_vector(6 downto 0);
db_irq_fire : std_ulogic; -- set if there is a valid IRQ source in the "enter debug mode" trap buffer
251,8 → 253,8
instr_be : std_ulogic; -- instruction fetch bus error
instr_ma : std_ulogic; -- instruction fetch misaligned address
instr_il : std_ulogic; -- illegal instruction
env_call : std_ulogic;
break_point : std_ulogic;
env_call : std_ulogic; -- ecall instruction
break_point : std_ulogic; -- ebreak instruction
end record;
signal trap_ctrl : trap_ctrl_t;
424,30 → 426,24
ipb.clear <= fetch_engine.restart; -- clear instruction buffer while being reset
 
-- state machine --
case fetch_engine.state is
if (fetch_engine.state = IFETCH_REQUEST) then -- IFETCH_REQUEST: request new 32-bit-aligned instruction word
-- ------------------------------------------------------------
if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request?
bus_fast_ir <= '1'; -- fast instruction fetch request
fetch_engine.state_nxt <= IFETCH_ISSUE;
end if;
fetch_engine.restart_nxt <= '0';
 
when IFETCH_REQUEST => -- request new 32-bit-aligned instruction word
-- ------------------------------------------------------------
if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request?
bus_fast_ir <= '1'; -- fast instruction fetch request
fetch_engine.state_nxt <= IFETCH_ISSUE;
end if;
fetch_engine.restart_nxt <= '0';
 
when IFETCH_ISSUE => -- store instruction data to prefetch buffer
-- ------------------------------------------------------------
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
fetch_engine.state_nxt <= IFETCH_REQUEST;
end if;
 
when others => -- undefined
-- ------------------------------------------------------------
else -- IFETCH_ISSUE: store instruction data to prefetch buffer
-- ------------------------------------------------------------
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
fetch_engine.state_nxt <= IFETCH_REQUEST;
end if;
 
end case;
end if;
end process fetch_engine_fsm_comb;
 
 
490,22 → 486,22
-- -------------------------------------------------------------------------------------------
issue_engine_fsm_sync: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
issue_engine.state <= ISSUE_ACTIVE;
issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary
issue_engine.buf <= (others => '0');
if (rstn_i = '0') then -- always start aligned after reset
issue_engine.align <= '0';
issue_engine.realign <= '0';
issue_engine.buf <= (others => def_rst_val_c);
elsif rising_edge(clk_i) then
if (ipb.clear = '1') then
if (CPU_EXTENSION_RISCV_C = true) and (execute_engine.pc(1) = '1') then -- branch to unaligned address?
issue_engine.state <= ISSUE_REALIGN;
issue_engine.align <= '1'; -- aligned on 16-bit boundary
issue_engine.align <= '1'; -- aligned on 16-bit boundary
issue_engine.realign <= '1';
else
issue_engine.state <= issue_engine.state_nxt;
issue_engine.align <= '0'; -- aligned on 32-bit boundary
issue_engine.align <= '0'; -- aligned on 32-bit boundary
issue_engine.realign <= '0';
end if;
else
issue_engine.state <= issue_engine.state_nxt;
issue_engine.align <= issue_engine.align_nxt;
issue_engine.align <= issue_engine.align_nxt;
issue_engine.realign <= issue_engine.realign_nxt;
end if;
issue_engine.buf <= issue_engine.buf_nxt;
end if;
517,67 → 513,70
issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)
begin
-- arbiter defaults --
issue_engine.state_nxt <= issue_engine.state;
issue_engine.align_nxt <= issue_engine.align;
issue_engine.buf_nxt <= issue_engine.buf;
issue_engine.realign_nxt <= issue_engine.realign;
issue_engine.align_nxt <= issue_engine.align;
issue_engine.buf_nxt <= issue_engine.buf;
 
-- instruction prefetch buffer interface defaults --
ipb.re <= '0';
 
-- instruction issue interface defaults --
-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
cmd_issue.valid <= '0';
 
 
-- construct instruction data --
-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
else -- compressed
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
end if;
else -- not 32-bit aligned
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed
cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
else -- compressed
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
end if;
end if;
 
 
-- store high half-word - we might need it for an unaligned uncompressed instruction --
if (execute_engine.state = DISPATCH) and (ipb.avail = '1') and (CPU_EXTENSION_RISCV_C = true) then
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
end if;
 
 
-- state machine --
case issue_engine.state is
if (ipb.avail = '1') then -- instruction data available?
 
when ISSUE_ACTIVE => -- issue instruction if available
if (issue_engine.realign = '0') then -- issue instruction if available
-- ------------------------------------------------------------
if (ipb.avail = '1') then -- instructions available?
 
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
ipb.re <= '1';
cmd_issue.valid <= '1';
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
else -- compressed
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
issue_engine.align_nxt <= '1';
end if;
cmd_issue.valid <= '1';
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
ipb.re <= '1';
if (ipb.rdata(1 downto 0) /= "11") and (CPU_EXTENSION_RISCV_C = true) then -- compressed
issue_engine.align_nxt <= '1';
end if;
 
else -- begin check in HIGH instruction half-word
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
cmd_issue.valid <= '1';
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"
ipb.re <= '1';
cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
else -- compressed
-- do not read from ipb here!
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
issue_engine.align_nxt <= '0';
end if;
end if;
else -- begin check in HIGH instruction half-word
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and unaligned
ipb.re <= '1';
else -- compressed - do not read from ipb here!
issue_engine.align_nxt <= '0';
end if;
end if;
end if;
 
when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address
else -- re-align input fifo and half-word buffer after a branch to an unaligned address
-- ------------------------------------------------------------
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
if (ipb.avail = '1') then -- instructions available?
ipb.re <= '1';
issue_engine.state_nxt <= ISSUE_ACTIVE;
end if;
ipb.re <= '1';
issue_engine.realign_nxt <= '0';
end if;
 
when others => -- undefined
-- ------------------------------------------------------------
issue_engine.state_nxt <= ISSUE_ACTIVE;
 
end case;
end if;
end process issue_engine_fsm_comb;
 
-- 16-bit instructions: half-word select --
671,10 → 670,8
execute_engine.branch_taken <= not cmp_i(cmp_equal_c);
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
execute_engine.branch_taken <= cmp_i(cmp_less_c);
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
when others => -- branch if greater or equal (signed/unsigned), invalid funct3 are checked by illegal instr. logic
execute_engine.branch_taken <= not cmp_i(cmp_less_c);
when others => -- invalid
execute_engine.branch_taken <= '0';
end case;
end process branch_check;
 
813,21 → 810,21
variable sys_env_cmd_mask_v : std_ulogic_vector(11 downto 0);
begin
-- defaults --
decode_aux.is_atomic_lr <= '0';
decode_aux.is_atomic_sc <= '0';
decode_aux.is_float_op <= '0';
decode_aux.is_m_mul <= '0';
decode_aux.is_m_div <= '0';
decode_aux.is_bitmanip_imm <= '0';
decode_aux.is_bitmanip_reg <= '0';
decode_aux.rs1_zero <= '0';
decode_aux.rs2_zero <= '0';
decode_aux.rd_zero <= '0';
decode_aux.is_a_lr <= '0';
decode_aux.is_a_sc <= '0';
decode_aux.is_f_op <= '0';
decode_aux.is_m_mul <= '0';
decode_aux.is_m_div <= '0';
decode_aux.is_b_imm <= '0';
decode_aux.is_b_reg <= '0';
decode_aux.rs1_zero <= '0';
decode_aux.rs2_zero <= '0';
decode_aux.rd_zero <= '0';
 
-- is atomic load-reservate/store-conditional? --
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
decode_aux.is_atomic_lr <= not execute_engine.i_reg(instr_funct5_lsb_c);
decode_aux.is_atomic_sc <= execute_engine.i_reg(instr_funct5_lsb_c);
decode_aux.is_a_lr <= not execute_engine.i_reg(instr_funct5_lsb_c);
decode_aux.is_a_sc <= execute_engine.i_reg(instr_funct5_lsb_c);
end if;
 
-- is BITMANIP instruction? --
844,13 → 841,24
) or
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00111")) or -- ORCB
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "11000")) then -- REV8
decode_aux.is_bitmanip_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- REV8
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BCLRI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- BEXTI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BINVI
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) then -- BSETI
decode_aux.is_b_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
end if;
-- register operation --
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U]
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- ZEXTH
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BCLR
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- BEXT
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BINV
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BSET
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- CLMUL
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "011")) or -- CLMULH
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010")) or -- CLMULR
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and
(
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN
865,7 → 873,7
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") -- SH3ADD
)
) then
decode_aux.is_bitmanip_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
decode_aux.is_b_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
end if;
 
-- floating-point operations (Zfinx) --
877,7 → 885,7
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "10100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FEQ.S / FLT.S / FLE.S
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11010") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) or -- FCVT.S.W*
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11000") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.W*.S
decode_aux.is_float_op <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- FPU implemented at all?
decode_aux.is_f_op <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- FPU implemented at all?
end if;
 
-- system/environment instructions --
946,7 → 954,7
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
end if;
-- atomic store-conditional instruction (evaluate lock status) --
ctrl_nxt(ctrl_bus_ch_lock_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A) and decode_aux.is_atomic_sc;
ctrl_nxt(ctrl_bus_ch_lock_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A) and decode_aux.is_a_sc;
 
 
-- state machine --
1036,20 → 1044,20
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_and_c;
end case;
 
-- co-processor MULDIV operation (multi-cycle)? --
-- co-processor MULDIV operation (multi-cycle) --
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
execute_engine.state_nxt <= ALU_WAIT;
-- co-processor BIT-MANIPULATION operation (multi-cycle)? --
-- co-processor BIT-MANIPULATION operation (multi-cycle) --
elsif (CPU_EXTENSION_RISCV_B = true) and
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- register operation
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_b_reg = '1')) or -- register operation
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_b_imm = '1'))) then -- immediate operation
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
execute_engine.state_nxt <= ALU_WAIT;
-- co-processor SHIFT operation (multi-cycle)? --
-- co-processor SHIFT operation (multi-cycle) --
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- use SHIFTER CP (only relevant for shift operations)
1099,7 → 1107,7
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
ctrl_nxt(ctrl_bus_fence_c) <= '1';
execute_engine.state_nxt <= SYS_WAIT;
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
execute_engine.branched_nxt <= '1'; -- this is an actual branch
execute_engine.state_nxt <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (PC <= PC)
1108,19 → 1116,6
end if;
 
 
when opcode_syscsr_c => -- system/csr access
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zicsr = true) then
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
execute_engine.state_nxt <= SYS_ENV;
else -- CSR access
execute_engine.state_nxt <= CSR_ACCESS;
end if;
else
execute_engine.state_nxt <= SYS_WAIT;
end if;
 
 
when opcode_fop_c => -- floating-point operations
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zfinx = true) then
1132,14 → 1127,22
end if;
 
 
when others => -- illegal opcode
when others => -- system/csr access OR illegal opcode - nothing bad (= no commits) will happen here if there is an illegal opcode
-- ------------------------------------------------------------
execute_engine.state_nxt <= SYS_WAIT;
if (CPU_EXTENSION_RISCV_Zicsr = true) then
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
execute_engine.state_nxt <= SYS_ENV;
else -- CSR access
execute_engine.state_nxt <= CSR_ACCESS;
end if;
else
execute_engine.state_nxt <= SYS_WAIT;
end if;
 
end case;
 
 
when SYS_ENV => -- system environment operation - execution
when SYS_ENV => -- system environment operation - no action if illegal instruction
-- ------------------------------------------------------------
execute_engine.state_nxt <= SYS_WAIT; -- default
if (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction
1155,18 → 1158,17
NULL; -- executed as NOP (and raise illegal instruction exception)
end if;
when funct12_wfi_c => -- WFI
if (CPU_EXTENSION_RISCV_DEBUG = true) and
((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then -- act as NOP when in debug-mode or during single-stepping
if (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then -- NOP when in debug-mode or during single-stepping
NULL; -- executed as NOP
else
execute_engine.sleep_nxt <= '1'; -- go to sleep mode
end if;
when others => NULL; -- undefined / execute as NOP
when others => NULL; -- undefined, execute as NOP
end case;
end if;
 
 
when CSR_ACCESS => -- read & write status and control register (CSR)
when CSR_ACCESS => -- read & write status and control register (CSR) - no read/write if illegal instruction
-- ------------------------------------------------------------
-- CSR write access --
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
1184,7 → 1186,8
when ALU_WAIT => -- wait for multi-cycle ALU operation (co-processor) to finish
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then -- completed or exception
-- wait for completion or abort on illegal instruction exception (the co-processor will also terminate operations)
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
execute_engine.state_nxt <= DISPATCH;
end if;
1210,11 → 1213,11
 
when LOADSTORE_0 => -- trigger memory request
-- ------------------------------------------------------------
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_atomic_lr; -- atomic.LR: set lock
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') then -- normal load or atomic load-reservate
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_a_lr; -- atomic.LR: set lock
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_a_lr = '1') then -- normal load or atomic load-reservate
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
else -- store
if (decode_aux.is_atomic_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request
if (decode_aux.is_a_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request
ctrl_nxt(ctrl_bus_wr_c) <= '1';
else -- evaluate lock state
ctrl_nxt(ctrl_bus_wr_c) <= excl_state_i; -- write request if lock is still ok
1239,12 → 1242,12
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
-- data write-back --
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load
(decode_aux.is_atomic_lr = '1') or -- atomic load-reservate
(decode_aux.is_atomic_sc = '1') then -- atomic store-conditional
(decode_aux.is_a_lr = '1') or -- atomic load-reservate
(decode_aux.is_a_sc = '1') then -- atomic store-conditional
ctrl_nxt(ctrl_rf_wb_en_c) <= '1';
end if;
-- remove atomic lock if this is NOT the LR.W instruction used to SET the lock --
if (decode_aux.is_atomic_lr = '0') then -- execute and evaluate atomic store-conditional
if (decode_aux.is_a_lr = '0') then -- execute and evaluate atomic store-conditional
ctrl_nxt(ctrl_bus_de_lock_c) <= '1';
end if;
execute_engine.state_nxt <= DISPATCH;
1260,7 → 1263,7
 
 
-- ****************************************************************************************************************************
-- Invalid Instruction / CSR access check
-- Illegal Instruction and CSR Access Check
-- ****************************************************************************************************************************
 
-- CSR Access Check -----------------------------------------------------------------------
1386,7 → 1389,7
-- ------------------------------------------------------------
illegal_instruction <= '0';
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and execute_engine.i_reg(instr_rd_msb_c);
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
 
when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
-- ------------------------------------------------------------
1404,13 → 1407,13
illegal_instruction <= '0';
elsif (CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1') then -- valid DIV instruction?
illegal_instruction <= '0';
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_reg = '1') then -- valid BITMANIP instruction?
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_reg = '1') then -- valid BITMANIP instruction?
illegal_instruction <= '0';
else
illegal_instruction <= '1';
end if;
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c));
illegal_register <= execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c);
 
when opcode_alui_c => -- check ALUI.funct7
-- ------------------------------------------------------------
1425,13 → 1428,13
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and -- shift right
((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0'))) then -- valid base ALUI instruction?
illegal_instruction <= '0';
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_imm = '1') then -- valid BITMANIP immediate instruction?
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_imm = '1') then -- valid BITMANIP immediate instruction?
illegal_instruction <= '0';
else
illegal_instruction <= '1';
end if;
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
 
when opcode_load_c => -- check LOAD.funct3
-- ------------------------------------------------------------
1445,7 → 1448,7
illegal_instruction <= '1';
end if;
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
 
when opcode_store_c => -- check STORE.funct3
-- ------------------------------------------------------------
1457,7 → 1460,7
illegal_instruction <= '1';
end if;
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c));
illegal_register <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c);
 
when opcode_atomic_c => -- atomic instructions
-- ------------------------------------------------------------
1465,11 → 1468,11
if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00010") then -- LR
illegal_instruction <= '0';
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
elsif (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00011") then -- SC
illegal_instruction <= '0';
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
else
illegal_instruction <= '1';
end if;
1490,7 → 1493,7
illegal_instruction <= '1';
end if;
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c));
illegal_register <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c);
 
when opcode_jalr_c => -- check JALR.funct3
-- ------------------------------------------------------------
1500,7 → 1503,7
illegal_instruction <= '1';
end if;
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
 
when opcode_fence_c => -- check FENCE.funct3
-- ------------------------------------------------------------
1510,8 → 1513,7
else
illegal_instruction <= '1';
end if;
-- illegal E-CPU register? --
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
-- NOTE: ignore all remaining bit fields here
 
when opcode_syscsr_c => -- check system instructions
-- ------------------------------------------------------------
1525,14 → 1527,12
(csr_acc_valid = '1') then -- valid CSR access?
illegal_instruction <= '0';
-- illegal E-CPU register? --
if (CPU_EXTENSION_RISCV_E = true) then
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
else -- reg-imm CSR
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
end if;
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
else -- reg-imm CSR
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
end if;
-- ecall, ebreak, mret, wfi, dret --
-- system: ecall, ebreak, mret, wfi, dret --
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") and
(decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') and
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
1549,7 → 1549,7
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented
(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
(decode_aux.is_float_op = '1') then -- is correct/supported floating-point instruction
(decode_aux.is_f_op = '1') then -- is correct/supported floating-point instruction
illegal_instruction <= '0';
else
illegal_instruction <= '1';
1556,7 → 1556,7
end if;
-- illegal E-CPU register? --
-- FIXME: rs2 is not checked!
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
 
when others => -- undefined instruction -> illegal!
-- ------------------------------------------------------------
1572,11 → 1572,14
end process illegal_instruction_check;
 
-- any illegal condition? --
trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed;
trap_ctrl.instr_il <= illegal_opcode_lsbs or -- illegal opcode MSB bits
illegal_instruction or -- illegal instruction format/layout
(bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and illegal_register) or -- illegal register access in E extension
illegal_compressed; -- illegal compressed instruction
 
 
-- ****************************************************************************************************************************
-- Exception and Interrupt (= Trap) Control
-- Exception and Interrupt (= Traps) Control
-- ****************************************************************************************************************************
 
-- Trap Controller ------------------------------------------------------------------------
1587,7 → 1590,7
if (rstn_i = '0') then
trap_ctrl.exc_buf <= (others => '0');
trap_ctrl.irq_buf <= (others => '0');
trap_ctrl.exc_ack <= '0';
trap_ctrl.exc_clr <= '0';
trap_ctrl.env_start <= '0';
trap_ctrl.cause <= (others => '0');
elsif rising_edge(clk_i) then
1594,31 → 1597,31
if (CPU_EXTENSION_RISCV_Zicsr = true) then
 
-- exception queue: misaligned load/store/instruction address --
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_clr);
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_clr);
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_clr);
 
-- exception queue: load/store/instruction bus access error --
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_clr);
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_clr);
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_clr);
 
-- exception queue: illegal instruction / environment calls --
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_clr);
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_clr);
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_clr);
 
-- exception queue: break point --
if (CPU_EXTENSION_RISCV_DEBUG = true) then
trap_ctrl.exc_buf(exception_break_c) <= (not trap_ctrl.exc_ack) and (trap_ctrl.exc_buf(exception_break_c) or
((trap_ctrl.break_point and csr.priv_m_mode and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- enable break to machine-trap-handler when in machine mode on "ebreak"
(trap_ctrl.break_point and csr.priv_u_mode and (not csr.dcsr_ebreaku) and (not debug_ctrl.running)))); -- enable break to machine-trap-handler when in user mode on "ebreak"
trap_ctrl.exc_buf(exception_break_c) <= (not trap_ctrl.exc_clr) and (trap_ctrl.exc_buf(exception_break_c) or
(trap_ctrl.break_point and csr.priv_m_mode and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- break to machine-trap-handler when in machine mode on "ebreak"
(trap_ctrl.break_point and csr.priv_u_mode and (not csr.dcsr_ebreaku) and (not debug_ctrl.running))); -- break to machine-trap-handler when in user mode on "ebreak"
else
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_clr);
end if;
 
-- exception buffer: enter debug mode --
trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_ack);
-- exception/interrupt buffer: enter debug mode --
trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_clr);
trap_ctrl.irq_buf(interrupt_db_halt_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_halt;
trap_ctrl.irq_buf(interrupt_db_step_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_step;
 
1635,12 → 1638,12
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception triggered!
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
trap_ctrl.exc_ack <= '1'; -- clear exceptions (no ack mask: these have highest priority and are always evaluated first!)
trap_ctrl.exc_clr <= '1'; -- clear exceptions (no ack mask: these have highest priority and are always evaluated first!)
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
end if;
else -- trap waiting to get started
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
trap_ctrl.exc_ack <= '0';
trap_ctrl.exc_clr <= '0';
trap_ctrl.env_start <= '0';
end if;
end if;
1661,12 → 1664,6
-- -------------------------------------------------------------------------------------------
trap_priority: process(trap_ctrl)
begin
-- defaults --
trap_ctrl.cause_nxt <= (others => '0');
 
-- NOTE: Synchronous exceptions (from trap_ctrl.exc_buf) have higher priority than asynchronous
-- exceptions (from trap_ctrl.irq_buf).
 
-- ----------------------------------------------------------------------------------------
-- the following traps are caused by *synchronous* exceptions; we do not need a
-- specific acknowledge mask since only _one_ exception (the one with highest priority)
1715,7 → 1712,6
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
trap_ctrl.cause_nxt <= trap_lbe_c;
 
 
-- ----------------------------------------------------------------------------------------
-- (re-)enter debug mode requests: basically, these are standard traps that have some
-- special handling - they have the highest INTERRUPT priority in order to go to debug when requested
1722,25 → 1718,22
-- even if other IRQs are pending right now
-- ----------------------------------------------------------------------------------------
 
-- break instruction --
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.exc_buf(exception_db_break_c) = '1') then
-- break instruction (sync) --
elsif (trap_ctrl.exc_buf(exception_db_break_c) = '1') then
trap_ctrl.cause_nxt <= trap_db_break_c;
 
-- external halt request --
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_halt_c) = '1') then
-- external halt request (async) --
elsif (trap_ctrl.irq_buf(interrupt_db_halt_c) = '1') then
trap_ctrl.cause_nxt <= trap_db_halt_c;
 
-- single stepping --
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_step_c) = '1') then
-- single stepping (async) --
elsif (trap_ctrl.irq_buf(interrupt_db_step_c) = '1') then
trap_ctrl.cause_nxt <= trap_db_step_c;
 
 
-- ----------------------------------------------------------------------------------------
-- the following traps are caused by *asynchronous* exceptions (= interrupts)
-- custom FAST interrupts (*asynchronous* exceptions)
-- ----------------------------------------------------------------------------------------
 
-- custom FAST interrupt requests --
 
-- interrupt: 1.16 fast interrupt channel 0 --
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
trap_ctrl.cause_nxt <= trap_firq0_c;
1805,9 → 1798,10
elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then
trap_ctrl.cause_nxt <= trap_firq15_c;
 
-- ----------------------------------------------------------------------------------------
-- standard RISC-V interrupts (*asynchronous* exceptions)
-- ----------------------------------------------------------------------------------------
 
-- standard RISC-V interrupts --
 
-- interrupt: 1.11 machine external interrupt --
elsif (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
trap_ctrl.cause_nxt <= trap_mei_c;
1817,7 → 1811,7
trap_ctrl.cause_nxt <= trap_msi_c;
 
-- interrupt: 1.7 machine timer interrupt --
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
else--if (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then -- last condition, so NO IF required
trap_ctrl.cause_nxt <= trap_mti_c;
 
end if;
1828,23 → 1822,22
-- Control and Status Registers (CSRs)
-- ****************************************************************************************************************************
 
-- Control and Status Registers Write Data ------------------------------------------------
-- Control and Status Registers - Write Data ----------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i)
variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0);
variable csr_imm_v : std_ulogic_vector(data_width_c-1 downto 0);
begin
-- CSR operand source --
if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate
csr_operand_v := (others => '0');
csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
else -- register
csr_operand_v := rs1_i;
end if;
-- tiny ALU for CSR write operations --
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
-- tiny ALU to compute CSR write data --
csr_imm_v := (others => '0');
csr_imm_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
when funct3_csrrw_c => csr.wdata <= rs1_i;
when funct3_csrrs_c => csr.wdata <= csr.rdata or rs1_i;
when funct3_csrrc_c => csr.wdata <= csr.rdata and (not rs1_i);
when funct3_csrrwi_c => csr.wdata <= csr_imm_v;
when funct3_csrrsi_c => csr.wdata <= csr.rdata or csr_imm_v;
when funct3_csrrci_c => csr.wdata <= csr.rdata and (not csr_imm_v);
when others => csr.wdata <= (others => '-'); -- undefined
end case;
end process csr_write_data;
 
1854,8 → 1847,8
csr_write_access: process(rstn_i, clk_i)
variable cause_v : std_ulogic_vector(6 downto 0);
begin
-- NOTE: If <dedicated_reset_c> = true then <def_rst_val_c> evaluates to '-'. Register that reset to <def_rst_val_c> do
-- NOT actually have a real reset by default (def_rst_val_c = '-') and have to be explicitly initialized by software!
-- NOTE: If <dedicated_reset_c> = true then <def_rst_val_c> evaluates to '-'. Registers that reset to <def_rst_val_c>
-- do NOT actually have a real reset by default and have to be explicitly initialized by software!
-- see: https://forums.xilinx.com/t5/General-Technical-Discussion/quot-Don-t-care-quot-reset-value/td-p/412845
if (rstn_i = '0') then
csr.we <= '0';
1979,7 → 1972,7
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
end if;
-- R/W: mip - machine interrupt pending --
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
csr.mip_clr <= csr.wdata(31 downto 16);
end if;
end if;
2080,7 → 2073,7
csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags")
end if;
 
-- mcause, mepc, mtval: write machine trap cause, PC and trap value register --
-- TRAP ENTER: write machine trap cause, PC and trap value register --
-- --------------------------------------------------------------------
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
 
2431,7 → 2424,7
variable csr_addr_v : std_ulogic_vector(11 downto 0);
begin
if rising_edge(clk_i) then
csr.rdata <= (others => '0'); -- default output
csr.rdata <= (others => '0'); -- default output, unimplemented CSRs are hardwired to zero
if (CPU_EXTENSION_RISCV_Zicsr = true) then
csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) registers ONLY !!!
2737,6 → 2730,10
csr_rdata_o <= csr.rdata;
 
 
-- ****************************************************************************************************************************
-- CPU Debug Mode (Part of the On-Chip Debugger)
-- ****************************************************************************************************************************
 
-- Debug Control --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
debug_control: process(rstn_i, clk_i)
2800,29 → 2797,21
 
-- Debug Control and Status Register (dcsr) - Read-Back -----------------------------------
-- -------------------------------------------------------------------------------------------
dcsr_readback_false:
if (CPU_EXTENSION_RISCV_DEBUG = false) generate
csr.dcsr_rd <= (others => '-');
end generate;
csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec
csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME/TODO ???
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual FIXME/TODO ???
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause
csr.dcsr_rd(05) <= '0'; -- reserved
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode
csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered
 
dcsr_readback_true:
if (CPU_EXTENSION_RISCV_DEBUG = true) generate
csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec
csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME ???
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause
csr.dcsr_rd(05) <= '0'; -- reserved
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
csr.dcsr_rd(03) <= '0'; -- nmip: pending non-maskable interrupt
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode
csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered
end generate;
 
 
end neorv32_cpu_control_rtl;
/neorv32/trunk/rtl/core/neorv32_cpu_cp_bitmanip.vhd
1,18 → 1,18
-- #################################################################################################
-- # << NEORV32 - CPU Co-Processor: Bit-Manipulation Co-Processor Unit (RISC-V "B" Extension) >> #
-- # ********************************************************************************************* #
-- # The bit manipulation unit is implemented as co-processor that has a processing latency of 1 #
-- # cycle for logic/arithmetic operations and 3+shamt (=shift amount) cycles for shift(-related) #
-- # operations. Use the FAST_SHIFT_EN option to reduce shift-related instruction's latency to a #
-- # fixed value of 3 cycles latency (using barrel shifters). #
-- # Supported B sub-extensions (Zb*): #
-- # - Zba: Address-generation instructions #
-- # - Zbb: Basic bit-manipulation instructions #
-- # - Zbs: Single-bit instructions #
-- # - Zbc: Carry-less multiplication instructions #
-- # #
-- # Supported sub-extensions (Zb*): #
-- # - Zba: Address generation instructions #
-- # - Zbb: Basic bit-manipulation instructions #
-- # NOTE: This is a first implementation of the bit-manipulation co-processor that supports all #
-- # sub-sets of the B extension. Hence, it is not yet optimized for area, latency or speed. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
71,43 → 71,55
 
architecture neorv32_cpu_cp_bitmanip_rtl of neorv32_cpu_cp_bitmanip is
 
-- Sub-extension configuration --
-- Sub-extension configuration ----------------------------
-- Note that this configurations does NOT effect the CPU's (illegal) instruction decoding logic!
constant zbb_en_c : boolean := true;
constant zba_en_c : boolean := true;
-- --------------------------- --
constant zbc_en_c : boolean := true;
constant zbs_en_c : boolean := true;
-- --------------------------------------------------------
 
-- commands: Zbb - logic with negate --
-- Zbb - logic with negate --
constant op_andn_c : natural := 0;
constant op_orn_c : natural := 1;
constant op_xnor_c : natural := 2;
-- commands: Zbb - count leading/trailing zero bits --
-- Zbb - count leading/trailing zero bits --
constant op_clz_c : natural := 3;
constant op_ctz_c : natural := 4;
-- commands: Zbb - count population --
-- Zbb - count population --
constant op_cpop_c : natural := 5;
-- commands: Zbb - integer minimum/maximum --
-- Zbb - integer minimum/maximum --
constant op_max_c : natural := 6; -- signed/unsigned
constant op_min_c : natural := 7; -- signed/unsigned
-- commands: Zbb - sign- and zero-extension --
-- Zbb - sign- and zero-extension --
constant op_sextb_c : natural := 8;
constant op_sexth_c : natural := 9;
constant op_zexth_c : natural := 10;
-- commands: Zbb - bitwise rotation --
-- Zbb - bitwise rotation --
constant op_rol_c : natural := 11;
constant op_ror_c : natural := 12; -- rori
-- commands: Zbb - or-combine --
constant op_ror_c : natural := 12; -- also rori
-- Zbb - or-combine --
constant op_orcb_c : natural := 13;
-- commands: Zbb - byte-reverse --
-- Zbb - byte-reverse --
constant op_rev8_c : natural := 14;
-- commands: Zba - shifted add --
-- Zba - shifted-add --
constant op_sh1add_c : natural := 15;
constant op_sh2add_c : natural := 16;
constant op_sh3add_c : natural := 17;
-- Zbs - single-bit operations --
constant op_bclr_c : natural := 18;
constant op_bext_c : natural := 19;
constant op_binv_c : natural := 20;
constant op_bset_c : natural := 21;
-- Zbc - carry-less multiplication --
constant op_clmul_c : natural := 22;
constant op_clmulh_c : natural := 23;
constant op_clmulr_c : natural := 24;
--
constant op_width_c : natural := 18;
constant op_width_c : natural := 25;
 
-- controller --
type ctrl_state_t is (S_IDLE, S_START_SHIFT, S_BUSY_SHIFT);
type ctrl_state_t is (S_IDLE, S_START_SHIFT, S_BUSY_SHIFT, S_START_CLMUL, S_BUSY_CLMUL);
signal ctrl_state : ctrl_state_t;
signal cmd, cmd_buf : std_ulogic_vector(op_width_c-1 downto 0);
signal valid : std_ulogic;
140,14 → 152,29
-- shifted-add unit --
signal adder_core : std_ulogic_vector(data_width_c-1 downto 0);
 
-- one-hot shifter --
signal one_hot_core : std_ulogic_vector(data_width_c-1 downto 0);
 
-- carry-less multiplier --
type clmultiplier_t is record
start : std_ulogic;
busy : std_ulogic;
rs2 : std_ulogic_vector(data_width_c-1 downto 0);
cnt : std_ulogic_vector(index_size_f(data_width_c) downto 0);
prod : std_ulogic_vector(2*data_width_c-1 downto 0);
end record;
signal clmul : clmultiplier_t;
 
begin
 
-- Sub-Extension Configuration ------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report
"Implementing bit-manipulation (B) sub-extensions: " &
cond_sel_string_f(zbb_en_c, "Zbb", "") &
cond_sel_string_f(zba_en_c, "Zba", "") &
"NEORV32 CPU: Implementing bit-manipulation (B) sub-extensions " &
cond_sel_string_f(zba_en_c, "Zba ", "") &
cond_sel_string_f(zbb_en_c, "Zbb ", "") &
cond_sel_string_f(zbc_en_c, "Zbc ", "") &
cond_sel_string_f(zbs_en_c, "Zbs ", "") &
""
severity note;
 
154,28 → 181,28
 
-- Instruction Decoding (One-Hot) ---------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- a minimal decoding logic is used here -> just to distinguish between B.Zbb instructions
-- a more specific decoding and instruction check is done by the CPU control unit
-- a minimal decoding logic is used here just to distinguish between the different B instruction
-- a more precise decoding and valid-instruction check is done by the CPU control unit
 
-- Zbb - Basic bit-manipulation instructions --
cmd(op_andn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "11") else '0';
cmd(op_orn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "10") else '0';
cmd(op_xnor_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "00") else '0';
cmd(op_andn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "11") else '0';
cmd(op_orn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "10") else '0';
cmd(op_xnor_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "00") else '0';
--
cmd(op_max_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_1_c) = '1') else '0';
cmd(op_min_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_1_c) = '0') else '0';
cmd(op_max_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "11") else '0';
cmd(op_min_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "10") else '0';
cmd(op_zexth_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '0') else '0';
--
cmd(op_orcb_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') else '0';
cmd(op_orcb_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0';
--
cmd(op_clz_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "000") else '0';
cmd(op_ctz_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "001") else '0';
cmd(op_cpop_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "010") else '0';
cmd(op_cpop_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "010") and (ctrl_i(ctrl_ir_opcode7_5_c) = '0') else '0';
cmd(op_sextb_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "100") else '0';
cmd(op_sexth_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "101") else '0';
cmd(op_rol_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_opcode7_5_c) = '1') else '0';
cmd(op_ror_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0';
cmd(op_rev8_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') else '0';
cmd(op_rev8_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0';
 
-- Zba - Address generation instructions --
cmd(op_sh1add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "01") else '0';
182,7 → 209,18
cmd(op_sh2add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "10") else '0';
cmd(op_sh3add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "11") else '0';
 
-- Zbs - Single-bit instructions --
cmd(op_bclr_c) <= '1' when (zbs_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') else '0';
cmd(op_bext_c) <= '1' when (zbs_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c) = '1') else '0';
cmd(op_binv_c) <= '1' when (zbs_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') else '0';
cmd(op_bset_c) <= '1' when (zbs_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') else '0';
 
-- Zbc - Carry-less multiplication instructions --
cmd(op_clmul_c) <= '1' when (zbc_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") else '0';
cmd(op_clmulh_c) <= '1' when (zbc_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "011") else '0';
cmd(op_clmulr_c) <= '1' when (zbc_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "010") else '0';
 
 
-- Co-Processor Controller ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
coprocessor_ctrl: process(rstn_i, clk_i)
194,11 → 232,13
rs2_reg <= (others => def_rst_val_c);
sha_reg <= (others => def_rst_val_c);
less_ff <= def_rst_val_c;
clmul.start <= '0';
shifter.start <= '0';
valid <= '0';
elsif rising_edge(clk_i) then
-- defaults --
shifter.start <= '0';
clmul.start <= '0';
valid <= '0';
 
-- fsm --
219,6 → 259,9
else -- full-parallel computation
ctrl_state <= S_BUSY_SHIFT;
end if;
elsif (zbc_en_c = true) and ((cmd(op_clmul_c) or cmd(op_clmulh_c) or cmd(op_clmulr_c)) = '1') then -- multi-cycle clmul operation
clmul.start <= '1';
ctrl_state <= S_START_CLMUL;
else
valid <= '1';
ctrl_state <= S_IDLE;
231,11 → 274,22
 
when S_BUSY_SHIFT => -- wait for multi-cycle shift operation to finish
-- ------------------------------------------------------------
if (shifter.run = '0') then
if (shifter.run = '0') or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap
valid <= '1';
ctrl_state <= S_IDLE;
end if;
 
when S_START_CLMUL => -- one cycle delay to start clmul operation
-- ------------------------------------------------------------
ctrl_state <= S_BUSY_CLMUL;
 
when S_BUSY_CLMUL => -- wait for multi-cycle clmul operation to finish
-- ------------------------------------------------------------
if (clmul.busy = '0') or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap
valid <= '1';
ctrl_state <= S_IDLE;
end if;
 
when others => -- undefined
-- ------------------------------------------------------------
ctrl_state <= S_IDLE;
366,18 → 420,65
when "01" => opb_v := rs1_reg(rs1_reg'left-1 downto 0) & '0'; -- << 1
when "10" => opb_v := rs1_reg(rs1_reg'left-2 downto 0) & "00"; -- << 2
when "11" => opb_v := rs1_reg(rs1_reg'left-3 downto 0) & "000"; -- << 3
when others => opb_v := rs1_reg(rs1_reg'left-1 downto 0) & '0'; -- undefined
when others => opb_v := (others => '-'); -- undefined
end case;
adder_core <= std_ulogic_vector(unsigned(rs2_reg) + unsigned(opb_v));
end process shift_adder;
 
 
-- One-Hot Generator Core -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shift_one_hot: process(sha_reg)
begin
one_hot_core <= (others => '0');
if (zbs_en_c = true) then
one_hot_core(to_integer(unsigned(sha_reg))) <= '1';
end if;
end process shift_one_hot;
 
 
-- Carry-Less Multiplication Core ---------------------------------------------------------
-- -------------------------------------------------------------------------------------------
clmul_core: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
clmul.cnt <= (others => def_rst_val_c);
clmul.prod <= (others => def_rst_val_c);
elsif rising_edge(clk_i) then
if (clmul.start = '1') then -- start new multiplication
clmul.cnt <= (others => '0');
clmul.cnt(clmul.cnt'left) <= '1';
clmul.prod(63 downto 32) <= (others => '0');
if (cmd_buf(op_clmulr_c) = '1') then -- reverse input operands?
clmul.prod(31 downto 00) <= bit_rev_f(rs1_reg);
else
clmul.prod(31 downto 00) <= rs1_reg;
end if;
elsif (clmul.busy = '1') then -- processing
clmul.cnt <= std_ulogic_vector(unsigned(clmul.cnt) - 1);
if (clmul.prod(0) = '1') then
clmul.prod(62 downto 31) <= clmul.prod(63 downto 32) xor clmul.rs2;
else
clmul.prod(62 downto 31) <= clmul.prod(63 downto 32);
end if;
clmul.prod(30 downto 00) <= clmul.prod(31 downto 1);
end if;
end if;
end process clmul_core;
 
-- reverse input operands? --
clmul.rs2 <= bit_rev_f(rs2_reg) when (cmd_buf(op_clmulr_c) = '1') else rs2_reg;
 
-- multiplier busy? --
clmul.busy <= or_reduce_f(clmul.cnt);
 
 
-- Operation Results ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- logic with negate --
res_int(op_andn_c) <= rs1_reg and (not rs2_reg); -- logical and-not
res_int(op_orn_c) <= rs1_reg or (not rs2_reg); -- logical or-not
res_int(op_xnor_c) <= rs1_reg xor (not rs2_reg); -- logical xor-not
res_int(op_andn_c) <= rs1_reg and (not rs2_reg);
res_int(op_orn_c) <= rs1_reg or (not rs2_reg);
res_int(op_xnor_c) <= rs1_reg xor (not rs2_reg);
 
-- count leading/trailing zeros --
res_int(op_clz_c)(data_width_c-1 downto shifter.cnt'left+1) <= (others => '0');
418,7 → 519,19
res_int(op_sh2add_c) <= (others => '0'); -- unused/redundant
res_int(op_sh3add_c) <= (others => '0'); -- unused/redundant
 
-- single-bit instructions --
res_int(op_bclr_c) <= rs1_reg and (not one_hot_core);
res_int(op_bext_c)(data_width_c-1 downto 1) <= (others => '0');
res_int(op_bext_c)(0) <= or_reduce_f(rs1_reg and one_hot_core);
res_int(op_binv_c) <= rs1_reg xor one_hot_core;
res_int(op_bset_c) <= rs1_reg or one_hot_core;
 
-- carry-less multiplication instructions --
res_int(op_clmul_c) <= clmul.prod(31 downto 00);
res_int(op_clmulh_c) <= clmul.prod(63 downto 32);
res_int(op_clmulr_c) <= bit_rev_f(clmul.prod(31 downto 00));
 
 
-- Output Selector ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
res_out(op_andn_c) <= res_int(op_andn_c) when (cmd_buf(op_andn_c) = '1') else (others => '0');
440,6 → 553,15
res_out(op_sh1add_c) <= res_int(op_sh1add_c) when ((cmd_buf(op_sh1add_c) or cmd_buf(op_sh2add_c) or cmd_buf(op_sh3add_c)) = '1') else (others => '0');
res_out(op_sh2add_c) <= (others => '0'); -- unused/redundant
res_out(op_sh3add_c) <= (others => '0'); -- unused/redundant
--
res_out(op_bclr_c) <= res_int(op_bclr_c) when (cmd_buf(op_bclr_c) = '1') else (others => '0');
res_out(op_bext_c) <= res_int(op_bext_c) when (cmd_buf(op_bext_c) = '1') else (others => '0');
res_out(op_binv_c) <= res_int(op_binv_c) when (cmd_buf(op_binv_c) = '1') else (others => '0');
res_out(op_bset_c) <= res_int(op_bset_c) when (cmd_buf(op_bset_c) = '1') else (others => '0');
--
res_out(op_clmul_c) <= res_int(op_clmul_c) when (cmd_buf(op_clmul_c) = '1') else (others => '0');
res_out(op_clmulh_c) <= res_int(op_clmulh_c) when (cmd_buf(op_clmulh_c) = '1') else (others => '0');
res_out(op_clmulr_c) <= res_int(op_clmulr_c) when (cmd_buf(op_clmulr_c) = '1') else (others => '0');
 
 
-- Output Gate ----------------------------------------------------------------------------
451,13 → 573,15
elsif rising_edge(clk_i) then
res_o <= (others => '0');
if (valid = '1') then
res_o <= res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or
res_out(op_clz_c) or res_out(op_cpop_c) or -- res_out(op_ctz_c) is unused here
res_out(op_min_c) or -- res_out(op_max_c) is unused here
res_out(op_sextb_c) or res_out(op_sexth_c) or res_out(op_zexth_c) or
res_out(op_ror_c) or res_out(op_rol_c) or
res_out(op_orcb_c) or res_out(op_rev8_c) or
res_out(op_sh1add_c); -- res_out(op_sh2add_c) and res_out(op_sh3add_c) are unused here
res_o <= res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or
res_out(op_clz_c) or res_out(op_cpop_c) or -- res_out(op_ctz_c) is unused here
res_out(op_min_c) or -- res_out(op_max_c) is unused here
res_out(op_sextb_c) or res_out(op_sexth_c) or res_out(op_zexth_c) or
res_out(op_ror_c) or res_out(op_rol_c) or
res_out(op_orcb_c) or res_out(op_rev8_c) or
res_out(op_sh1add_c) or -- res_out(op_sh2add_c) and res_out(op_sh3add_c) are unused here
res_out(op_bclr_c) or res_out(op_bext_c) or res_out(op_binv_c) or res_out(op_bset_c) or
res_out(op_clmul_c) or res_out(op_clmulh_c) or res_out(op_clmulr_c);
end if;
end if;
end process output_gate;
/neorv32/trunk/rtl/core/neorv32_cpu_cp_fpu.vhd
19,7 → 19,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
384,7 → 384,7
 
when S_BUSY => -- operation in progress (multi-cycle)
-- -----------------------------------------------------------
if (fu_core_done = '1') then -- processing done?
if (fu_core_done = '1') or (ctrl_i(ctrl_trap_c) = '1') then -- processing done? abort if trap
ctrl_engine.valid <= '1';
ctrl_engine.state <= S_IDLE;
end if;
/neorv32/trunk/rtl/core/neorv32_cpu_cp_muldiv.vhd
10,7 → 10,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
174,7 → 174,7
 
when PROCESSING =>
cnt <= std_ulogic_vector(unsigned(cnt) - 1);
if (cnt = "00000") then
if (cnt = "00000") or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap
valid_o <= '1';
state <= FINALIZE;
end if;
/neorv32/trunk/rtl/core/neorv32_cpu_cp_shifter.vhd
7,7 → 7,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
97,7 → 97,7
shifter.busy_ff <= shifter.busy;
if (start_i = '1') then
shifter.busy <= '1';
elsif (shifter.done = '1') then
elsif (shifter.done = '1') or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap
shifter.busy <= '0';
end if;
--
/neorv32/trunk/rtl/core/neorv32_debug_dm.vhd
19,7 → 19,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
72,6 → 72,7
dmi_resp_data_o : out std_ulogic_vector(31 downto 0);
dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error
-- CPU bus access --
cpu_debug_i : in std_ulogic; -- CPU is in debug mode
cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address
cpu_rden_i : in std_ulogic; -- read enable
cpu_wren_i : in std_ulogic; -- write enable
240,14 → 241,14
begin
if rising_edge(clk_i) then
if (dm_reg.dmcontrol_dmactive = '0') or (dmi_rstn_i = '0') then -- DM reset / DM disabled
dm_ctrl.state <= CMD_IDLE;
dm_ctrl.ldsw_progbuf <= (others => '-');
dci.execute_req <= '0';
dm_ctrl.pbuf_en <= '-';
dm_ctrl.state <= CMD_IDLE;
dm_ctrl.ldsw_progbuf <= (others => '-');
dci.execute_req <= '0';
dm_ctrl.pbuf_en <= '-';
--
dm_ctrl.illegal_cmd <= '-';
dm_ctrl.illegal_state <= '-';
dm_ctrl.cmderr <= "000";
dm_ctrl.illegal_cmd <= '-';
dm_ctrl.illegal_state <= '-';
dm_ctrl.cmderr <= "000";
--
dm_ctrl.hart_reset <= '0';
dm_ctrl.hart_halted <= '0';
668,8 → 669,8
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (cpu_addr_i(hi_abb_c downto lo_abb_c) = dm_base_c(hi_abb_c downto lo_abb_c)) else '0';
maddr <= cpu_addr_i(lo_abb_c-1 downto lo_abb_c-2); -- (sub-)module select address
rden <= acc_en and cpu_rden_i;
wren <= acc_en and cpu_wren_i;
rden <= acc_en and cpu_debug_i and cpu_rden_i; -- allow access only when in debug mode
wren <= acc_en and cpu_debug_i and cpu_wren_i; -- allow access only when in debug mode
 
 
-- Write Access ---------------------------------------------------------------------------
/neorv32/trunk/rtl/core/neorv32_fifo.vhd
3,7 → 3,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
96,8 → 96,8
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
fifo.re <= re_i when (FIFO_SAFE = false) else (re_i and fifo.avail); -- read only if data available
fifo.we <= we_i when (FIFO_SAFE = false) else (we_i and fifo.free); -- write only if space left
fifo.re <= re_i when (FIFO_SAFE = false) else (re_i and fifo.avail); -- SAFE = read only if data available
fifo.we <= we_i when (FIFO_SAFE = false) else (we_i and fifo.free); -- SAFE = write only if space left
 
 
-- FIFO Control ---------------------------------------------------------------------------
163,7 → 163,7
end if;
end process fifo_memory_write;
 
-- asynchronous read --
-- "asynchronous" read --
fifo_read_async:
if (FIFO_RSYNC = false) generate
rdata_o <= fifo.datas when (FIFO_DEPTH = 1) else fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
/neorv32/trunk/rtl/core/neorv32_mtime.vhd
6,7 → 6,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
104,6 → 104,9
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- bus handshake --
ack_o <= rden or wren;
 
-- mtimecmp --
if (wren = '1') then
if (addr = mtime_cmp_lo_addr_c) then
114,10 → 117,18
end if;
end if;
 
-- mtime access buffer --
-- wdata_buf <= data_i; -- not required, CPU wdata (=data_i) is stable until transfer is acknowledged
mtime_lo_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_lo_addr_c));
mtime_hi_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_hi_addr_c));
-- mtime write access buffer --
if (wren = '1') and (addr = mtime_time_lo_addr_c) then
mtime_lo_we <= '1';
else
mtime_lo_we <= '0';
end if;
--
if (wren = '1') and (addr = mtime_time_hi_addr_c) then
mtime_hi_we <= '1';
else
mtime_hi_we <= '0';
end if;
 
-- mtime low --
if (mtime_lo_we = '1') then -- write access
145,14 → 156,13
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= rden or wren;
data_o <= (others => '0'); -- default
if (rden = '1') then
case addr(3 downto 2) is
when "00" => data_o <= mtime_lo; -- mtime LOW
when "01" => data_o <= mtime_hi; -- mtime HIGH
when "10" => data_o <= mtimecmp_lo; -- mtimecmp LOW
when others => data_o <= mtimecmp_hi; -- mtimecmp HIGH
when "00" => data_o <= mtime_lo; -- mtime low
when "01" => data_o <= mtime_hi; -- mtime high
when "10" => data_o <= mtimecmp_lo; -- mtimecmp low
when others => data_o <= mtimecmp_hi; -- mtimecmp high
end case;
end if;
end if;
/neorv32/trunk/rtl/core/neorv32_package.vhd
46,7 → 46,6
 
-- CPU core --
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
 
-- "critical" number of implemented PMP regions --
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
64,7 → 63,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060600"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060700"; -- no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
 
-- Check if we're inside the Matrix -------------------------------------------------------
90,7 → 89,6
-- -------------------------------------------------------------------------------------------
type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
type cp_data_if_t is array (0 to 3) of std_ulogic_vector(data_width_c-1 downto 0);
 
-- Internal Memory Types Configuration Types ----------------------------------------------
-- -------------------------------------------------------------------------------------------
106,6 → 104,8
function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic;
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
function bool_to_ulogic_f(cond : boolean) return std_ulogic;
function bin_to_gray_f(input : std_ulogic_vector) return std_ulogic_vector;
function gray_to_bin_f(input : std_ulogic_vector) return std_ulogic_vector;
function or_reduce_f(a : std_ulogic_vector) return std_ulogic;
function and_reduce_f(a : std_ulogic_vector) return std_ulogic;
function xor_reduce_f(a : std_ulogic_vector) return std_ulogic;
369,38 → 369,39
constant ctrl_bus_ch_lock_c : natural := 44; -- evaluate atomic/exclusive lock (SC operation)
-- co-processors --
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select ID lsb
constant ctrl_cp_id_msb_c : natural := 46; -- cp select ID msb
constant ctrl_cp_id_hsb_c : natural := 46; -- cp select ID "half" significant bit
constant ctrl_cp_id_msb_c : natural := 47; -- cp select ID msb
-- instruction's control blocks (used by cpu co-processors) --
constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0
constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1
constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2
constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0
constant ctrl_ir_funct12_1_c : natural := 51; -- funct12 bit 1
constant ctrl_ir_funct12_2_c : natural := 52; -- funct12 bit 2
constant ctrl_ir_funct12_3_c : natural := 53; -- funct12 bit 3
constant ctrl_ir_funct12_4_c : natural := 54; -- funct12 bit 4
constant ctrl_ir_funct12_5_c : natural := 55; -- funct12 bit 5
constant ctrl_ir_funct12_6_c : natural := 56; -- funct12 bit 6
constant ctrl_ir_funct12_7_c : natural := 57; -- funct12 bit 7
constant ctrl_ir_funct12_8_c : natural := 58; -- funct12 bit 8
constant ctrl_ir_funct12_9_c : natural := 59; -- funct12 bit 9
constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
constant ctrl_ir_opcode7_0_c : natural := 62; -- opcode7 bit 0
constant ctrl_ir_opcode7_1_c : natural := 63; -- opcode7 bit 1
constant ctrl_ir_opcode7_2_c : natural := 64; -- opcode7 bit 2
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6
constant ctrl_ir_funct3_0_c : natural := 48; -- funct3 bit 0
constant ctrl_ir_funct3_1_c : natural := 49; -- funct3 bit 1
constant ctrl_ir_funct3_2_c : natural := 50; -- funct3 bit 2
constant ctrl_ir_funct12_0_c : natural := 51; -- funct12 bit 0
constant ctrl_ir_funct12_1_c : natural := 52; -- funct12 bit 1
constant ctrl_ir_funct12_2_c : natural := 53; -- funct12 bit 2
constant ctrl_ir_funct12_3_c : natural := 54; -- funct12 bit 3
constant ctrl_ir_funct12_4_c : natural := 55; -- funct12 bit 4
constant ctrl_ir_funct12_5_c : natural := 56; -- funct12 bit 5
constant ctrl_ir_funct12_6_c : natural := 57; -- funct12 bit 6
constant ctrl_ir_funct12_7_c : natural := 58; -- funct12 bit 7
constant ctrl_ir_funct12_8_c : natural := 59; -- funct12 bit 8
constant ctrl_ir_funct12_9_c : natural := 60; -- funct12 bit 9
constant ctrl_ir_funct12_10_c : natural := 61; -- funct12 bit 10
constant ctrl_ir_funct12_11_c : natural := 62; -- funct12 bit 11
constant ctrl_ir_opcode7_0_c : natural := 63; -- opcode7 bit 0
constant ctrl_ir_opcode7_1_c : natural := 64; -- opcode7 bit 1
constant ctrl_ir_opcode7_2_c : natural := 65; -- opcode7 bit 2
constant ctrl_ir_opcode7_3_c : natural := 66; -- opcode7 bit 3
constant ctrl_ir_opcode7_4_c : natural := 67; -- opcode7 bit 4
constant ctrl_ir_opcode7_5_c : natural := 68; -- opcode7 bit 5
constant ctrl_ir_opcode7_6_c : natural := 69; -- opcode7 bit 6
-- CPU status --
constant ctrl_priv_lvl_lsb_c : natural := 69; -- privilege level lsb
constant ctrl_priv_lvl_msb_c : natural := 70; -- privilege level msb
constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode
constant ctrl_trap_c : natural := 72; -- set when CPU is entering trap execution
constant ctrl_debug_running_c : natural := 73; -- CPU is in debug mode when set
constant ctrl_priv_lvl_lsb_c : natural := 70; -- privilege level lsb
constant ctrl_priv_lvl_msb_c : natural := 71; -- privilege level msb
constant ctrl_sleep_c : natural := 72; -- set when CPU is in sleep mode
constant ctrl_trap_c : natural := 73; -- set when CPU is entering trap execution
constant ctrl_debug_running_c : natural := 74; -- CPU is in debug mode when set
-- control bus size --
constant ctrl_width_c : natural := 74; -- control bus size
constant ctrl_width_c : natural := 75; -- control bus size
 
-- Comparator Bus -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
775,10 → 776,14
 
-- Co-Processor IDs -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant cp_sel_shifter_c : std_ulogic_vector(1 downto 0) := "00"; -- shift operations (base ISA)
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "01"; -- multiplication/division operations ('M' extensions)
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extensions)
constant cp_sel_fpu_c : std_ulogic_vector(1 downto 0) := "11"; -- floating-point unit ('Zfinx' extension)
constant cp_sel_shifter_c : std_ulogic_vector(2 downto 0) := "000"; -- CP0: shift operations (base ISA)
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- CP1: multiplication/division operations ('M' extensions)
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- CP2: bit manipulation ('B' extensions)
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- CP3: floating-point unit ('Zfinx' extension)
--constant cp_sel_res0_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: reserved
--constant cp_sel_res1_c : std_ulogic_vector(2 downto 0) := "101"; -- CP5: reserved
--constant cp_sel_res2_c : std_ulogic_vector(2 downto 0) := "110"; -- CP6: reserved
--constant cp_sel_res3_c : std_ulogic_vector(2 downto 0) := "111"; -- CP7: reserved
 
-- ALU Function Codes ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
1114,44 → 1119,44
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
debug_o : out std_ulogic; -- cpu is in debug mode when set
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
debug_o : out std_ulogic; -- cpu is in debug mode when set
-- instruction bus interface --
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_lock_o : out std_ulogic; -- exclusive access request
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
i_bus_we_o : out std_ulogic; -- write enable
i_bus_re_o : out std_ulogic; -- read enable
i_bus_lock_o : out std_ulogic; -- exclusive access request
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
i_bus_err_i : in std_ulogic; -- bus transfer error
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
-- data bus interface --
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_lock_o : out std_ulogic; -- exclusive access request
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
d_bus_we_o : out std_ulogic; -- write enable
d_bus_re_o : out std_ulogic; -- read enable
d_bus_lock_o : out std_ulogic; -- exclusive access request
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
d_bus_err_i : in std_ulogic; -- bus transfer error
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
-- system time input from MTIME --
time_i : in std_ulogic_vector(63 downto 0); -- current system time
time_i : in std_ulogic_vector(63 downto 0); -- current system time
-- interrupts (risc-v compliant) --
msw_irq_i : in std_ulogic; -- machine software interrupt
mext_irq_i : in std_ulogic; -- machine external interrupt
mtime_irq_i : in std_ulogic; -- machine timer interrupt
msw_irq_i : in std_ulogic; -- machine software interrupt
mext_irq_i : in std_ulogic; -- machine external interrupt
mtime_irq_i : in std_ulogic; -- machine timer interrupt
-- fast interrupts (custom) --
firq_i : in std_ulogic_vector(15 downto 0);
firq_i : in std_ulogic_vector(15 downto 0);
-- debug mode (halt) request --
db_halt_req_i : in std_ulogic
db_halt_req_i : in std_ulogic
);
end component;
 
2119,6 → 2124,7
dmi_resp_data_o : out std_ulogic_vector(31 downto 0);
dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error
-- CPU bus access --
cpu_debug_i : in std_ulogic; -- CPU is in debug mode
cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address
cpu_rden_i : in std_ulogic; -- read enable
cpu_wren_i : in std_ulogic; -- write enable
2245,6 → 2251,30
end if;
end function bool_to_ulogic_f;
 
-- Function: Convert binary to gray -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function bin_to_gray_f(input : std_ulogic_vector) return std_ulogic_vector is
variable tmp_v : std_ulogic_vector(input'range);
begin
tmp_v(input'length-1) := input(input'length-1); -- keep MSB
for i in input'length-2 downto 0 loop
tmp_v(i) := input(i) xor input(i+1);
end loop; -- i
return tmp_v;
end function bin_to_gray_f;
 
-- Function: Convert gray to binary -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function gray_to_bin_f(input : std_ulogic_vector) return std_ulogic_vector is
variable tmp_v : std_ulogic_vector(input'range);
begin
tmp_v(input'length-1) := input(input'length-1); -- keep MSB
for i in input'length-2 downto 0 loop
tmp_v(i) := tmp_v(i+1) xor input(i);
end loop; -- i
return tmp_v;
end function gray_to_bin_f;
 
-- Function: OR-reduce all bits -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function or_reduce_f(a : std_ulogic_vector) return std_ulogic is
/neorv32/trunk/rtl/core/neorv32_top.vhd
686,6 → 686,8
rdata_v := (others => '0');
ack_v := '0';
err_v := '0';
-- OR all module's response signals: only the module that is actually
-- been accessed is allowed to set it's bus output signals
for i in resp_bus'range loop
rdata_v := rdata_v or resp_bus(i).rdata; -- read data
ack_v := ack_v or resp_bus(i).ack; -- acknowledge
940,8 → 942,7
-- -------------------------------------------------------------------------------------------
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
io_rden <= io_acc and p_bus.re and (not p_bus.src); -- PMA: no_execute for IO region
-- the default NEORV32 peripheral/IO devices in the IO area can only be written in word mode (reduces HW complexity)
io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben) and (not p_bus.src); -- PMA: write32 only, no_execute for IO region
io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben); -- only full-word write accesses are allowed (reduces HW complexity)
 
 
-- Custom Functions Subsystem (CFS) -------------------------------------------------------
1580,6 → 1581,7
dmi_resp_data_o => dmi.resp_data,
dmi_resp_err_o => dmi.resp_err, -- 0=ok, 1=error
-- CPU bus access --
cpu_debug_i => debug_mode, -- CPU is in debug mode
cpu_addr_i => p_bus.addr, -- address
cpu_rden_i => p_bus.re, -- read enable
cpu_wren_i => p_bus.we, -- write enable
/neorv32/trunk/rtl/README.md
1,4 → 1,4
## VHDL Source Folders
## HArdware RTL Sources
 
 
### [`core`](https://github.com/stnolting/neorv32/tree/master/rtl/core)
/neorv32/trunk/sim/README.md
1,4 → 1,4
# Simulation Source Folder
# Simulation Sources
 
 
## [simple](simple)
/neorv32/trunk/sw/example/bitmanip_test/main.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
51,6 → 51,14
#define BAUD_RATE (19200)
//** Number of test cases for each instruction */
#define NUM_TEST_CASES (1000000)
//** Enable Zbb tests when 1 */
#define ENABLE_ZBB (1)
//** Enable Zba tests when 1 */
#define ENABLE_ZBA (1)
//** Enable Zbs tests when 1 */
#define ENABLE_ZBS (1)
//** Enable Zbc tests when 1 */
#define ENABLE_ZBC (1)
/**@}*/
 
 
61,7 → 69,7
 
 
/**********************************************************************//**
* Main function; test all available operations of the NEORV32 'Zbb' extensions
* Main function; test all available operations of the NEORV32 'B' extension
* using bit manipulation intrinsics and software-only reference functions (emulation).
*
* @note This program requires the bit-manipulation CPU extension.
77,7 → 85,7
// capture all exceptions and give debug info via UART
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, ho hw flow control
// init UART at default baud rate, no parity bits, no hw flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// Disable compilation by default
91,22 → 99,23
#endif
 
// intro
neorv32_uart0_printf("NEORV32 Bit-Manipulation Extension Test (Zba, Zbb)\n\n");
neorv32_uart0_printf("<<< NEORV32 Bit-Manipulation Extension ('B') Test >>>\n\n");
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
 
// check if Zbb extension is implemented at all
// check if B extension is implemented at all
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_B)) == 0) {
neorv32_uart0_print("Error! <B> extension not synthesized!\n");
neorv32_uart0_print("Error! B extension not synthesized!\n");
return 1;
}
 
neorv32_uart0_printf("Starting bit-manipulation extension tests (%i test cases per instruction)...\n\n", num_tests);
 
neorv32_uart0_printf("-----------------------------------------\n");
#if (ENABLE_ZBB != 0)
neorv32_uart0_printf("--------------------------------------------\n");
neorv32_uart0_printf("Zbb - Basic bit-manipulation instructions\n");
neorv32_uart0_printf("-----------------------------------------\n");
neorv32_uart0_printf("--------------------------------------------\n");
 
// ANDN
neorv32_uart0_printf("\nANDN:\n");
328,13 → 337,14
err_cnt += check_result(i, opa, 0, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
#endif
 
 
 
#if (ENABLE_ZBA != 0)
neorv32_uart0_printf("\n\n");
neorv32_uart0_printf("-----------------------------------------\n");
neorv32_uart0_printf("Zba - Address generation instructions\n");
neorv32_uart0_printf("-----------------------------------------\n");
neorv32_uart0_printf("--------------------------------------------\n");
neorv32_uart0_printf("Zba - Address-generation instructions\n");
neorv32_uart0_printf("--------------------------------------------\n");
 
// SH1ADD
neorv32_uart0_printf("\nSH1ADD:\n");
370,16 → 380,168
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
#endif
 
 
neorv32_uart0_printf("\nBit manipulation extension tests done.\n");
#if (ENABLE_ZBS != 0)
neorv32_uart0_printf("\n\n");
neorv32_uart0_printf("--------------------------------------------\n");
neorv32_uart0_printf("Zbs - Single-bit instructions\n");
neorv32_uart0_printf("--------------------------------------------\n");
 
// BCLR
neorv32_uart0_printf("\nBCLR:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_bclr(opa, opb);
res_hw = riscv_intrinsic_bclr(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// BCLRI
neorv32_uart0_printf("\nBCLRI (imm=20):\n"); // FIXME: static immediate
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
res_sw = riscv_emulate_bclr(opa, 20);
res_hw = riscv_intrinsic_bclri20(opa);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
 
 
// BEXT
neorv32_uart0_printf("\nBEXT:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_bext(opa, opb);
res_hw = riscv_intrinsic_bext(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// BEXTI
neorv32_uart0_printf("\nBEXTI (imm=20):\n"); // FIXME: static immediate
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
res_sw = riscv_emulate_bext(opa, 20);
res_hw = riscv_intrinsic_bexti20(opa);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
 
 
// BINV
neorv32_uart0_printf("\nBINV:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_binv(opa, opb);
res_hw = riscv_intrinsic_binv(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// BINVI
neorv32_uart0_printf("\nBINVI (imm=20):\n"); // FIXME: static immediate
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
res_sw = riscv_emulate_binv(opa, 20);
res_hw = riscv_intrinsic_binvi20(opa);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
 
 
// BSET
neorv32_uart0_printf("\nBSET:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_bset(opa, opb);
res_hw = riscv_intrinsic_bset(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// BSETI
neorv32_uart0_printf("\nBSETI (imm=20):\n"); // FIXME: static immediate
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
res_sw = riscv_emulate_bset(opa, 20);
res_hw = riscv_intrinsic_bseti20(opa);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
#endif
 
 
#if (ENABLE_ZBC != 0)
neorv32_uart0_printf("\n\n");
neorv32_uart0_printf("--------------------------------------------\n");
neorv32_uart0_printf("Zbc - Carry-less multiplication instructions\n");
neorv32_uart0_printf("--------------------------------------------\n");
 
neorv32_uart0_printf("\nNOTE: The emulation functions will take quite some time to execute.\n");
 
// CLMUL
neorv32_uart0_printf("\nCLMUL:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_clmul(opa, opb);
res_hw = riscv_intrinsic_clmul(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// CLMULH
neorv32_uart0_printf("\nCLMULH:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_clmulh(opa, opb);
res_hw = riscv_intrinsic_clmulh(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// CLMULR
neorv32_uart0_printf("\nCLMULR:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_clmulr(opa, opb);
res_hw = riscv_intrinsic_clmulr(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
#endif
 
 
neorv32_uart0_printf("\n\nB extension tests completed.\n");
return 0;
}
 
 
/**********************************************************************//**
* Pseudo-Random Number Generator (to generate test vectors).
* Pseudo-Random Number Generator (to generate deterministic test vectors).
*
* @return Random data (32-bit).
**************************************************************************/
435,3 → 597,17
neorv32_uart0_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
}
}
 
 
/**********************************************************************//**
* "after-main" handler that is executed after the application's
* main function returns (called by crt0.S start-up code)
**************************************************************************/
int __neorv32_crt0_after_main(int32_t return_code) {
 
if (return_code) {
neorv32_uart0_printf("\n<RTE> main function returned with exit code (%i) </RTE>\n", return_code);
}
 
return 0;
}
/neorv32/trunk/sw/example/bitmanip_test/neorv32_b_extension_intrinsics.h
6,7 → 6,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
61,21 → 61,12
/**********************************************************************//**
* Intrinsic: Bit manipulation CLZ (count leading zeros) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Number of leading zeros in source operand.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clz(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// clz a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00000, a0, 0b001, a0, 0b0010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00000, rs1, 0b001, 0b0010011);
}
 
 
82,21 → 73,12
/**********************************************************************//**
* Intrinsic: Bit manipulation CTZ (count trailing zeros) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Number of trailing zeros in source operand.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_ctz(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// ctz a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00001, a0, 0b001, a0, 0b0010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00001, rs1, 0b001, 0b0010011);
}
 
 
103,21 → 85,12
/**********************************************************************//**
* Intrinsic: Bit manipulation CPOP (count set bits) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Number of set bits in source operand.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_cpop(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// cpop a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00010, a0, 0b001, a0, 0b0010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00010, rs1, 0b001, 0b0010011);
}
 
 
124,21 → 97,12
/**********************************************************************//**
* Intrinsic: Bit manipulation SEXT.B (sign-extend byte) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Sign extended byte (operand(7:0)).
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sextb(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// sext.b a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00100, a0, 0b001, a0, 0b0010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00100, rs1, 0b001, 0b0010011);
}
 
 
145,21 → 109,12
/**********************************************************************//**
* Intrinsic: Bit manipulation SEXT.H (sign-extend half-word) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Sign-extended half-word (operand(15:0)).
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sexth(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// sext.h a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00101, a0, 0b001, a0, 0b0010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00101, rs1, 0b001, 0b0010011);
}
 
 
166,21 → 121,12
/**********************************************************************//**
* Intrinsic: Bit manipulation ZEXT.H (zero-extend half-word) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Zero-extended half-word (operand(15:0)).
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_zexth(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// sext.h a0, a0
CUSTOM_INSTR_R1_TYPE(0b0000100, 0b00000, a0, 0b100, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0000100, 0b00000, rs1, 0b100, 0b0110011);
}
 
 
187,23 → 133,13
/**********************************************************************//**
* Intrinsic: Bit manipulation MIN (select signed minimum) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Signed minimum.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_min(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// min a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b100, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b100, 0b0110011);
}
 
 
210,23 → 146,13
/**********************************************************************//**
* Intrinsic: Bit manipulation MINU (select unsigned minimum) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Unsigned minimum.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_minu(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// minu a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b101, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b101, 0b0110011);
}
 
 
233,23 → 159,13
/**********************************************************************//**
* Intrinsic: Bit manipulation MAX (select signed maximum) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Signed maximum.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_max(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// max a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b110, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b110, 0b0110011);
}
 
 
256,23 → 172,13
/**********************************************************************//**
* Intrinsic: Bit manipulation MAXU (select unsigned maximum) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Unsigned maximum.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_maxu(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// maxu a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b111, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b111, 0b0110011);
}
 
 
279,23 → 185,13
/**********************************************************************//**
* Intrinsic: Bit manipulation ANDN (logical and-negate) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 1 AND NOT operand 2.
**************************************************************************/
inline inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_andn(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// andn a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b111, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0100000, rs2, rs1, 0b111, 0b0110011);
}
 
 
302,23 → 198,13
/**********************************************************************//**
* Intrinsic: Bit manipulation ORN (logical or-negate) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 1 OR NOT operand 2.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_orn(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// orn a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b110, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0100000, rs2, rs1, 0b110, 0b0110011);
}
 
 
325,23 → 211,13
/**********************************************************************//**
* Intrinsic: Bit manipulation XNOR (logical xor-negate) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 1 XOR NOT operand 2.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_xnor(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// xnor a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b100, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0100000, rs2, rs1, 0b100, 0b0110011);
}
 
 
348,23 → 224,13
/**********************************************************************//**
* Intrinsic: Bit manipulation ROL (rotate-left) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 1 rotated left by operand_2(4:0) positions.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rol(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// rol a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0110000, a1, a0, 0b001, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0110000, rs2, rs1, 0b001, 0b0110011);
}
 
 
371,23 → 237,13
/**********************************************************************//**
* Intrinsic: Bit manipulation ROR (rotate-right) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 1 rotated right by operand_2(4:0) positions.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_ror(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// ror a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0110000, a1, a0, 0b101, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0110000, rs2, rs1, 0b101, 0b0110011);
}
 
 
395,21 → 251,12
* Intrinsic: Bit manipulation RORI (rotate-right) by 20 positions. [B.Zbb]
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Operand 1 rotated right by 20 positions.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rori20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// rori a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b10100, a0, 0b101, a0, 0b0010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0110000, 0b10100, rs1, 0b101, 0b0010011);
}
 
 
416,21 → 263,12
/**********************************************************************//**
* Intrinsic: Bit manipulation ORC.B (or-combine byte) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return OR-combined bytes of operand 1.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_orcb(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// gorci a0, a0, 7 (pseudo-instruction: orc.b a0, a0)
CUSTOM_INSTR_R1_TYPE(0b0010100, 0b00111, a0, 0b101, a0, 0b0010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0010100, 0b00111, rs1, 0b101, 0b0010011);
}
 
 
437,48 → 275,29
/**********************************************************************//**
* Intrinsic: Bit manipulation REV8 (byte-swap) [B.Zbb]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Byte swap of operand 1
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rev8(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// grevi a0, a0, -8 (pseudo-instruction: rev8 a0, a0)
CUSTOM_INSTR_R1_TYPE(0b0110100, 0b11000, a0, 0b101, a0, 0b0010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b0110100, 0b11000, rs1, 0b101, 0b0010011);
}
 
 
// ================================================================================================
// Zbb - Base instructions
// Zba - Address-generation instructions
// ================================================================================================
 
/**********************************************************************//**
* Intrinsic: Address generation instructions SH1ADD (add with logical-1-shift) [B.Zba]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 2 + (Operand 1 << 1)
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh1add(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// sh1add a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b010, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0010000, rs2, rs1, 0b010, 0b0110011);
}
 
 
485,49 → 304,181
/**********************************************************************//**
* Intrinsic: Address generation instructions SH2ADD (add with logical-2-shift) [B.Zba]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 2 + (Operand 1 << 2)
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh2add(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// sh2add a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b100, a0, 0b0110011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b0010000, rs2, rs1, 0b100, 0b0110011);
}
 
/**********************************************************************//**
* Intrinsic: Address generation instructions SH1ADD (add with logical-3-shift) [B.Zba]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 2 + (Operand 1 << 3)
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh3add(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
return CUSTOM_INSTR_R2_TYPE(0b0010000, rs2, rs1, 0b110, 0b0110011);
}
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// sh3add a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b110, a0, 0b0110011);
// ================================================================================================
// Zbs - Single-bit instructions
// ================================================================================================
 
return result;
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BCLR (bit-clear) [B.Zbs]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Operand 1 with bit cleared indexed by operand_2(4:0).
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bclr(uint32_t rs1, uint32_t rs2) {
 
return CUSTOM_INSTR_R2_TYPE(0b0100100, rs2, rs1, 0b001, 0b0110011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BCLRI (bit-clear) by 20 positions. [B.Zbs]
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1.
* @return Operand 1 with bit cleared at position 20.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bclri20(uint32_t rs1) {
 
return CUSTOM_INSTR_R1_TYPE(0b0100100, 0b10100, rs1, 0b001, 0b0010011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BEXT (bit-extract) [B.Zbs]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Extract bit from Operand 1 indexed by operand_2(4:0).
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bext(uint32_t rs1, uint32_t rs2) {
 
return CUSTOM_INSTR_R2_TYPE(0b0100100, rs2, rs1, 0b101, 0b0110011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BEXTI (bit-extract) by 20 positions. [B.Zbs]
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1.
* @return Extract bit from Operand 1 at position 20.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bexti20(uint32_t rs1) {
 
return CUSTOM_INSTR_R1_TYPE(0b0100100, 0b10100, rs1, 0b101, 0b0010011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BINV (bit-invert) [B.Zbs]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Invert bit from Operand 1 indexed by operand_2(4:0).
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_binv(uint32_t rs1, uint32_t rs2) {
 
return CUSTOM_INSTR_R2_TYPE(0b0110100, rs2, rs1, 0b001, 0b0110011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BINVI (bit-invert) by 20 positions. [B.Zbs]
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1.
* @return Invert bit from Operand 1 at position 20.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_binvi20(uint32_t rs1) {
 
return CUSTOM_INSTR_R1_TYPE(0b0110100, 0b10100, rs1, 0b001, 0b0010011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BSET (bit-set) [B.Zbs]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return set bit from Operand 1 indexed by operand_2(4:0).
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bset(uint32_t rs1, uint32_t rs2) {
 
return CUSTOM_INSTR_R2_TYPE(0b0010100, rs2, rs1, 0b001, 0b0110011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BSETI (bit-set) by 20 positions. [B.Zbs]
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1.
* @return Set bit from Operand 1 at position 20.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_bseti20(uint32_t rs1) {
 
return CUSTOM_INSTR_R1_TYPE(0b0010100, 0b10100, rs1, 0b001, 0b0010011);
}
 
 
// ================================================================================================
// Zbc - Carry-less multiplication instructions
// ================================================================================================
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation CLMUL (carry-less multiplication, low-part) [B.Zbc]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Carry-less product, low part.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clmul(uint32_t rs1, uint32_t rs2) {
 
return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b001, 0b0110011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation CLMULH (carry-less multiplication, high-part) [B.Zbc]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Carry-less product, high part.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clmulh(uint32_t rs1, uint32_t rs2) {
 
return CUSTOM_INSTR_R2_TYPE(0b0000101, rs2, rs1, 0b011, 0b0110011);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation CLMULR (carry-less multiplication, reversed) [B.Zbc]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Carry-less product, low part, reversed.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clmulr(uint32_t rs1, uint32_t rs2) {
 
return CUSTOM_INSTR_R2_TYPE(0b0000101, rs1, rs2, 0b010, 0b0110011);
}
 
 
// ################################################################################################
// Emulation functions
// ################################################################################################
541,7 → 492,7
/**********************************************************************//**
* Intrinsic: Bit manipulation CLZ (count leading zeros) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Number of leading zeros in source operand.
**************************************************************************/
uint32_t riscv_emulate_clz(uint32_t rs1) {
566,7 → 517,7
/**********************************************************************//**
* Intrinsic: Bit manipulation CTZ (count trailing zeros) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Number of trailing zeros in source operand.
**************************************************************************/
uint32_t riscv_emulate_ctz(uint32_t rs1) {
591,7 → 542,7
/**********************************************************************//**
* Intrinsic: Bit manipulation CPOP (population count) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Number of set bits in source operand.
**************************************************************************/
uint32_t riscv_emulate_cpop(uint32_t rs1) {
614,7 → 565,7
/**********************************************************************//**
* Intrinsic: Bit manipulation SEXT.B (sign-extend byte) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Sign-extended byte (operand(7:0)).
**************************************************************************/
uint32_t riscv_emulate_sextb(uint32_t rs1) {
632,7 → 583,7
/**********************************************************************//**
* Intrinsic: Bit manipulation SEXT.H (sign-extend half-word) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Sign-extended half-word (operand(15:0)).
**************************************************************************/
uint32_t riscv_emulate_sexth(uint32_t rs1) {
650,7 → 601,7
/**********************************************************************//**
* Intrinsic: Bit manipulation ZEXT.H (zero-extend half-word) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Zero-extended half-word (operand(15:0)).
**************************************************************************/
uint32_t riscv_emulate_zexth(uint32_t rs1) {
662,8 → 613,8
/**********************************************************************//**
* Intrinsic: Bit manipulation MIN (select signed minimum) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Signed minimum.
**************************************************************************/
uint32_t riscv_emulate_min(uint32_t rs1, uint32_t rs2) {
683,8 → 634,8
/**********************************************************************//**
* Intrinsic: Bit manipulation MINU (select unsigned minimum) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Unsigned minimum.
**************************************************************************/
uint32_t riscv_emulate_minu(uint32_t rs1, uint32_t rs2) {
701,8 → 652,8
/**********************************************************************//**
* Intrinsic: Bit manipulation MAX (select signed maximum) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Signed maximum.
**************************************************************************/
uint32_t riscv_emulate_max(uint32_t rs1, uint32_t rs2) {
722,8 → 673,8
/**********************************************************************//**
* Intrinsic: Bit manipulation MAXU (select unsigned maximum) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Unsigned maximum.
**************************************************************************/
uint32_t riscv_emulate_maxu(uint32_t rs1, uint32_t rs2) {
740,8 → 691,8
/**********************************************************************//**
* Intrinsic: Bit manipulation ANDN (logical and-negate) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 1 AND NOT operand 2.
**************************************************************************/
uint32_t riscv_emulate_andn(uint32_t rs1, uint32_t rs2) {
753,8 → 704,8
/**********************************************************************//**
* Intrinsic: Bit manipulation ORN (logical or-negate) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 1 OR NOT operand 2.
**************************************************************************/
uint32_t riscv_emulate_orn(uint32_t rs1, uint32_t rs2) {
766,8 → 717,8
/**********************************************************************//**
* Intrinsic: Bit manipulation XNOR (logical xor-negate) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 1 XOR NOT operand 2.
**************************************************************************/
uint32_t riscv_emulate_xnor(uint32_t rs1, uint32_t rs2) {
779,8 → 730,8
/**********************************************************************//**
* Intrinsic: Bit manipulation ROL (rotate-left) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 1 rotated left by operand_2(4:0) positions.
**************************************************************************/
uint32_t riscv_emulate_rol(uint32_t rs1, uint32_t rs2) {
797,8 → 748,8
/**********************************************************************//**
* Intrinsic: Bit manipulation ROR (rotate-right) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 1 rotated right by operand_2(4:0) positions.
**************************************************************************/
uint32_t riscv_emulate_ror(uint32_t rs1, uint32_t rs2) {
815,7 → 766,7
/**********************************************************************//**
* Intrinsic: Bit manipulation REV8 (byte swap) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Operand 1 byte swapped.
**************************************************************************/
uint32_t riscv_emulate_rev8(uint32_t rs1) {
832,7 → 783,7
/**********************************************************************//**
* Intrinsic: Bit manipulation ORCB (or-combine bytes) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return OR-combined bytes of operand 1.
**************************************************************************/
uint32_t riscv_emulate_orcb(uint32_t rs1) {
864,8 → 815,8
/**********************************************************************//**
* Intrinsic: Address generation instructions SH1ADD (add with logical-1-shift) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 2 + (Operand 1 << 1)
**************************************************************************/
uint32_t riscv_emulate_sh1add(uint32_t rs1, uint32_t rs2) {
877,8 → 828,8
/**********************************************************************//**
* Intrinsic: Address generation instructions SH2ADD (add with logical-2-shift) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 2 + (Operand 1 << 2)
**************************************************************************/
uint32_t riscv_emulate_sh2add(uint32_t rs1, uint32_t rs2) {
890,8 → 841,8
/**********************************************************************//**
* Intrinsic: Address generation instructions SH3ADD (add with logical-3-shift) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 2 + (Operand 1 << 3)
**************************************************************************/
uint32_t riscv_emulate_sh3add(uint32_t rs1, uint32_t rs2) {
900,4 → 851,187
}
 
 
// ================================================================================================
// Zbs - Single-bit instructions
// ================================================================================================
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BCLR (bit-clear) [emulation]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Operand 1 with cleared bit indexed by operand_2(4:0).
**************************************************************************/
uint32_t riscv_emulate_bclr(uint32_t rs1, uint32_t rs2) {
 
uint32_t shamt = rs2 & 0x1f;
uint32_t tmp = 1 << shamt;
 
return rs1 & (~tmp);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BEXT (bit-extract) [emulation]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Extract bit from operand 1 indexed by operand_2(4:0).
**************************************************************************/
uint32_t riscv_emulate_bext(uint32_t rs1, uint32_t rs2) {
 
uint32_t shamt = rs2 & 0x1f;
uint32_t tmp = rs1 >> shamt;
 
return tmp & 1;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BINV (bit-invert) [emulation]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Invert bit from operand 1 indexed by operand_2(4:0).
**************************************************************************/
uint32_t riscv_emulate_binv(uint32_t rs1, uint32_t rs2) {
 
uint32_t shamt = rs2 & 0x1f;
uint32_t tmp = 1 << shamt;
 
return rs1 ^ tmp;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation BSET (bit-set) [emulation]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Set bit from operand 1 indexed by operand_2(4:0).
**************************************************************************/
uint32_t riscv_emulate_bset(uint32_t rs1, uint32_t rs2) {
 
uint32_t shamt = rs2 & 0x1f;
uint32_t tmp = 1 << shamt;
 
return rs1 | tmp;
}
 
 
// ================================================================================================
// Zbc - Carry-less multiplication instructions
// ================================================================================================
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation CLMUL (carry-less multiply, low-part) [emulation]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Carry-less multiplication product, low part
**************************************************************************/
uint32_t riscv_emulate_clmul(uint32_t rs1, uint32_t rs2) {
 
uint32_t i;
uint64_t tmp;
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} res;
 
res.uint64 = 0;
for (i=0; i<32; i++) {
if ((rs2 >> i) & 1) {
tmp = (uint64_t)rs1;
tmp = tmp << i;
res.uint64 = res.uint64 ^ tmp;
}
}
 
return res.uint32[0];
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation CLMULH (carry-less multiply, high-part) [emulation]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Carry-less multiplication product, high part
**************************************************************************/
uint32_t riscv_emulate_clmulh(uint32_t rs1, uint32_t rs2) {
 
uint32_t i;
uint64_t tmp;
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} res;
 
res.uint64 = 0;
for (i=0; i<32; i++) {
if ((rs2 >> i) & 1) {
tmp = (uint64_t)rs1;
tmp = tmp << i;
res.uint64 = res.uint64 ^ tmp;
}
}
 
return res.uint32[1];
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation CLMUR (carry-less multiply, reversed) [emulation]
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 1.
* @return Carry-less multiplication product, low part, reversed
**************************************************************************/
uint32_t riscv_emulate_clmulr(uint32_t rs1, uint32_t rs2) {
 
uint32_t i;
uint64_t tmp;
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} res;
 
// bit-reversal of input operands
uint32_t rs1_rev = 0, rs2_rev = 0;
for (i=0; i<32; i++) {
rs1_rev <<= 1;
if ((rs1 >> i) & 1) {
rs1_rev |= 1;
}
rs2_rev <<= 1;
if ((rs2 >> i) & 1) {
rs2_rev |= 1;
}
}
 
res.uint64 = 0;
for (i=0; i<32; i++) {
if ((rs2_rev >> i) & 1) {
tmp = (uint64_t)rs1_rev;
tmp = tmp << i;
res.uint64 = res.uint64 ^ tmp;
}
}
 
// bit-reversal of result
uint32_t result = 0;
for (i=0; i<32; i++) {
result <<= 1;
if ((res.uint32[0] >> i) & 1) {
result |= 1;
}
}
 
return result;
}
 
 
#endif // neorv32_b_extension_intrinsics_h
/neorv32/trunk/sw/example/coremark/core_portme.c
225,7 → 225,7
// show executed instructions, required cycles and resulting average CPI
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} exe_instructions, exe_time;
 
exe_time.uint64 = (uint64_t)get_time();
/neorv32/trunk/sw/example/demo_cfs/main.c
0,0 → 1,153
// #################################################################################################
// # << NEORV32 - CFS Demo Program >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file demo_cfs/main.c
* @author Stephan Nolting
* @brief Simple demo program for the _default_ custom functions subsystem (CFS) module.
**************************************************************************/
 
#include <neorv32.h>
 
 
/**********************************************************************//**
* @name User configuration
**************************************************************************/
/**@{*/
/** UART BAUD rate */
#define BAUD_RATE 19200
/** Number of test cases per CFS function */
#define TESTCASES 4
/**@}*/
 
 
/**********************************************************************//**
* @name Prototypes
**************************************************************************/
uint32_t xorshift32(void);
 
 
/**********************************************************************//**
* Main function
*
* @note This program requires the CFS and UART0.
*
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
uint32_t i, tmp;
 
 
// init UART0 at default baud rate, no parity bits, no HW flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// capture all exceptions and give debug info via UART0
// this is not required, but keeps us safe
neorv32_rte_setup();
 
 
// check if CFS is implemented at all
if (neorv32_cfs_available() == 0) {
neorv32_uart0_printf("Error! No CFS synthesized!\n");
return 1;
}
 
 
// intro
neorv32_uart0_printf("<<< NEORV32 Custom Functions Subsystem (CFS) Demo Program >>>\n\n");
 
neorv32_uart0_printf("NOTE: This program assumes the _default_ CFS hardware module, which implements\n"
" simple data conversion functions using four memory-mapped registers.\n\n");
 
neorv32_uart0_printf("Default CFS memory-mapped registers:\n"
" * NEORV32_CFS.REG[0] (r/w): convert binary to gray code\n"
" * NEORV32_CFS.REG[1] (r/w): convert gray to binary code\n"
" * NEORV32_CFS.REG[2] (r/w): bit reversal\n"
" * NEORV32_CFS.REG[3] (r/w): byte swap\n"
"The remaining 28 CFS registers are unused and will return 0 when read.\n");
 
 
// function examples
neorv32_uart0_printf("\n--- CFS 'binary to gray' function ---\n");
for (i=0; i<TESTCASES; i++) {
tmp = xorshift32(); // get random test data
NEORV32_CFS.REG[0] = tmp; // write to CFS memory-mapped register 0
neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS.REG[0]); // read from CFS memory-mapped register 0
}
 
neorv32_uart0_printf("\n--- CFS 'gray to binary' function ---\n");
for (i=0; i<TESTCASES; i++) {
tmp = xorshift32(); // get random test data
NEORV32_CFS.REG[1] = tmp; // write to CFS memory-mapped register 1
neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS.REG[1]); // read from CFS memory-mapped register 1
}
 
neorv32_uart0_printf("\n--- CFS 'bit reversal' function ---\n");
for (i=0; i<TESTCASES; i++) {
tmp = xorshift32(); // get random test data
NEORV32_CFS.REG[2] = tmp; // write to CFS memory-mapped register 2
neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS.REG[2]); // read from CFS memory-mapped register 2
}
 
neorv32_uart0_printf("\n--- CFS 'byte swap' function ---\n");
for (i=0; i<TESTCASES; i++) {
tmp = xorshift32(); // get random test data
NEORV32_CFS.REG[3] = tmp; // write to CFS memory-mapped register 3
neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS.REG[3]); // read from CFS memory-mapped register 3
}
 
 
neorv32_uart0_printf("\nCFS demo program completed.\n");
 
return 0;
}
 
 
/**********************************************************************//**
* Pseudo-Random Number Generator (to generate deterministic test vectors).
*
* @return Random data (32-bit).
**************************************************************************/
uint32_t xorshift32(void) {
 
static uint32_t x32 = 314159265;
 
x32 ^= x32 << 13;
x32 ^= x32 >> 17;
x32 ^= x32 << 5;
 
return x32;
}
/neorv32/trunk/sw/example/demo_cfs/makefile
0,0 → 1,40
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
# #
# 1. Redistributions of source code must retain the above copyright notice, this list of #
# conditions and the following disclaimer. #
# #
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
# conditions and the following disclaimer in the documentation and/or other materials #
# provided with the distribution. #
# #
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
# endorse or promote products derived from this software without specific prior written #
# permission. #
# #
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
# OF THE POSSIBILITY OF SUCH DAMAGE. #
# ********************************************************************************************* #
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
#################################################################################################
 
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../../..
 
include $(NEORV32_HOME)/sw/common/common.mk
/neorv32/trunk/sw/example/demo_xip/main.c
168,7 → 168,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} data;
 
while (1) {
/neorv32/trunk/sw/example/dhrystone/dhrystone.sh
1,7 → 2,7
make USER_FLAGS+=-DRUN_DHRYSTONE USER_FLAGS+=-DDHRY_ITERS=2000000 USER_FLAGS+=-DNOENUM MARCH=rv32imc EFFORT=-O3 clean_all exe
echo "Generating dhrystone executable..."
make USER_FLAGS+="-DRUN_DHRYSTONE -DDHRY_ITERS=2000000 -DNOENUM" MARCH=rv32imc EFFORT=-O3 clean_all exe
/neorv32/trunk/sw/example/floating_point_test/neorv32_zfinx_extension_intrinsics.h
6,7 → 6,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
167,8 → 167,8
/**********************************************************************//**
* Single-precision floating-point addition
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fadds(float rs1, float rs2) {
177,17 → 177,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fadd.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000000, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0000000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
return res.float_value;
}
 
195,8 → 185,8
/**********************************************************************//**
* Single-precision floating-point subtraction
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fsubs(float rs1, float rs2) {
205,17 → 195,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsub.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000100, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0000100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
return res.float_value;
}
 
223,8 → 203,8
/**********************************************************************//**
* Single-precision floating-point multiplication
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fmuls(float rs1, float rs2) {
233,17 → 213,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmul.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0001000, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0001000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
return res.float_value;
}
 
251,8 → 221,8
/**********************************************************************//**
* Single-precision floating-point minimum
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fmins(float rs1, float rs2) {
261,17 → 231,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmin.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
return res.float_value;
}
 
279,8 → 239,8
/**********************************************************************//**
* Single-precision floating-point maximum
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fmaxs(float rs1, float rs2) {
289,17 → 249,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmax.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b001, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010100, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
return res.float_value;
}
 
307,7 → 257,7
/**********************************************************************//**
* Single-precision floating-point convert float to unsigned integer
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_wus(float rs1) {
315,16 → 265,7
float_conv_t opa;
opa.float_value = rs1;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fcvt.wu.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1100000, x1, a0, 0b000, a0, 0b1010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b1100000, 0b00001, opa.binary_value, 0b000, 0b1010011);
}
 
 
331,7 → 272,7
/**********************************************************************//**
* Single-precision floating-point convert float to signed integer
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
inline int32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_ws(float rs1) {
339,16 → 280,7
float_conv_t opa;
opa.float_value = rs1;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fcvt.w.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1100000, x0, a0, 0b000, a0, 0b1010011);
 
return (int32_t)result;
return (int32_t)CUSTOM_INSTR_R1_TYPE(0b1100000, 0b00000, opa.binary_value, 0b000, 0b1010011);
}
 
 
355,7 → 287,7
/**********************************************************************//**
* Single-precision floating-point convert unsigned integer to float
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fcvt_swu(uint32_t rs1) {
362,16 → 294,7
 
float_conv_t res;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fcvt.s.wu a0, a0
CUSTOM_INSTR_R2_TYPE(0b1101000, x1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R1_TYPE(0b1101000, 0b00001, rs1, 0b000, 0b1010011);
return res.float_value;
}
 
379,7 → 302,7
/**********************************************************************//**
* Single-precision floating-point convert signed integer to float
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fcvt_sw(int32_t rs1) {
386,16 → 309,7
 
float_conv_t res;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = (uint32_t)rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fcvt.s.w a0, a0
CUSTOM_INSTR_R2_TYPE(0b1101000, x0, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R1_TYPE(0b1101000, 0b00000, rs1, 0b000, 0b1010011);
return res.float_value;
}
 
403,8 → 317,8
/**********************************************************************//**
* Single-precision floating-point equal comparison
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_feqs(float rs1, float rs2) {
413,17 → 327,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// feq.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b010, a0, 0b1010011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b010, 0b1010011);
}
 
 
430,8 → 334,8
/**********************************************************************//**
* Single-precision floating-point less-than comparison
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_flts(float rs1, float rs2) {
440,17 → 344,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// flt.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b001, a0, 0b1010011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
}
 
 
457,8 → 351,8
/**********************************************************************//**
* Single-precision floating-point less-than-or-equal comparison
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fles(float rs1, float rs2) {
467,17 → 361,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fle.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b000, a0, 0b1010011);
 
return result;
return CUSTOM_INSTR_R2_TYPE(0b1010000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
}
 
 
484,8 → 368,8
/**********************************************************************//**
* Single-precision floating-point sign-injection
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjs(float rs1, float rs2) {
494,17 → 378,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnj.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
return res.float_value;
}
 
512,8 → 386,8
/**********************************************************************//**
* Single-precision floating-point sign-injection NOT
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjns(float rs1, float rs2) {
522,17 → 396,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnjn.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b001, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b001, 0b1010011);
return res.float_value;
}
 
540,8 → 404,8
/**********************************************************************//**
* Single-precision floating-point sign-injection XOR
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjxs(float rs1, float rs2) {
550,17 → 414,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnjx.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b010, a0, 0b1010011);
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0010000, opb.binary_value, opa.binary_value, 0b010, 0b1010011);
return res.float_value;
}
 
568,7 → 422,7
/**********************************************************************//**
* Single-precision floating-point number classification
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fclasss(float rs1) {
576,16 → 430,7
float_conv_t opa;
opa.float_value = rs1;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a));
 
// fclass.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1110000, x0, a0, 0b001, a0, 0b1010011);
 
return result;
return CUSTOM_INSTR_R1_TYPE(0b1110000, 0b00000, opa.binary_value, 0b001, 0b1010011);
}
 
 
598,8 → 443,8
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fdivs(float rs1, float rs2) {
608,20 → 453,7
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fdiv.s a0, a0, x1
CUSTOM_INSTR_R2_TYPE(0b0001100, a1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R2_TYPE(0b0001100, opb.binary_value, opa.binary_value, 0b000, 0b1010011);
return res.float_value;
}
 
631,7 → 463,7
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fsqrts(float rs1) {
639,19 → 471,7
float_conv_t opa, res;
opa.float_value = rs1;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// fsqrt.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0101100, a1, a0, 0b000, a0, 0b1010011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R1_TYPE(0b0101100, 0b00000, opa.binary_value, 0b000, 0b1010011);
return res.float_value;
}
 
661,9 → 481,9
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0)
* @param[in] rs2 Source operand 2 (a1)
* @param[in] rs3 Source operand 3 (a2)
* @param[in] rs1 Source operand 1
* @param[in] rs2 Source operand 2
* @param[in] rs3 Source operand 3
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fmadds(float rs1, float rs2, float rs3) {
673,22 → 493,7
opb.float_value = rs2;
opc.float_value = rs3;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
register uint32_t tmp_c __asm__ ("a2") = opc.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c));
 
// fmadd.s a0, a0, a1, a2
CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1000011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R3_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1000011);
return res.float_value;
}
 
698,9 → 503,9
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0)
* @param[in] rs2 Source operand 2 (a1)
* @param[in] rs3 Source operand 3 (a2)
* @param[in] rs1 Source operand 1
* @param[in] rs2 Source operand 2
* @param[in] rs3 Source operand 3
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fmsubs(float rs1, float rs2, float rs3) {
710,22 → 515,7
opb.float_value = rs2;
opc.float_value = rs3;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
register uint32_t tmp_c __asm__ ("a2") = opc.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c));
 
// fmsub.s a0, a0, a1, a2
CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1000111);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R3_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1000111);
return res.float_value;
}
 
735,9 → 525,9
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0)
* @param[in] rs2 Source operand 2 (a1)
* @param[in] rs3 Source operand 3 (a2)
* @param[in] rs1 Source operand 1
* @param[in] rs2 Source operand 2
* @param[in] rs3 Source operand 3
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fnmsubs(float rs1, float rs2, float rs3) {
747,22 → 537,7
opb.float_value = rs2;
opc.float_value = rs3;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
register uint32_t tmp_c __asm__ ("a2") = opc.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c));
 
// fnmsub.s a0, a0, a1, a2
CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1001011);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R3_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1001011);
return res.float_value;
}
 
772,9 → 547,9
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0)
* @param[in] rs2 Source operand 2 (a1)
* @param[in] rs3 Source operand 3 (a2)
* @param[in] rs1 Source operand 1
* @param[in] rs2 Source operand 2
* @param[in] rs3 Source operand 3
* @return Result.
**************************************************************************/
inline float __attribute__ ((always_inline)) riscv_intrinsic_fnmadds(float rs1, float rs2, float rs3) {
784,22 → 559,7
opb.float_value = rs2;
opc.float_value = rs3;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
register uint32_t tmp_c __asm__ ("a2") = opc.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c));
 
// fnmadd.s a0, a0, a1, a2
CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1001111);
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) );
 
res.binary_value = result;
res.binary_value = CUSTOM_INSTR_R3_TYPE(opc.binary_value, opb.binary_value, opa.binary_value, 0b000, 0b1001111);
return res.float_value;
}
 
1289,8 → 1049,6
/**********************************************************************//**
* Single-precision floating-point fused multiply-add
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @warning This instruction is not supported!
*
* @param[in] rs1 Source operand 1
/neorv32/trunk/sw/example/processor_check/main.c
562,15 → 562,15
 
cnt_test++;
 
// illegal 32-bit instruction (malformed SUB)
// illegal 32-bit instruction (malformed SRA)
asm volatile (".align 4 \n"
".word 0x80000033");
".word 0xC0000033");
 
// make sure this has cause an illegal exception
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
// make sure this is really the instruction that caused the exception
// -> for illegal instructions MTVAL contains the faulting instruction word
if (neorv32_cpu_csr_read(CSR_MTVAL) == 0x80000033) {
if (neorv32_cpu_csr_read(CSR_MTVAL) == 0xC0000033) {
test_ok();
}
else {
/neorv32/trunk/sw/example/processor_check/run_check.sh
1,15 → 2,15
echo "Starting processor check simulation..."
make USER_FLAGS+="-DRUN_CHECK -DUART0_SIM_MODE -DUART1_SIM_MODE -g" MARCH=rv32imac clean_all sim
/neorv32/trunk/sw/lib/include/neorv32_intrinsics.h
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
35,7 → 35,7
 
/**********************************************************************//**
* @file neorv32_intrinsics.h
* @author Stephan Nolting
* @author Stephan Nolting, SaxonSoc contributors, Google-CFU
* @brief Helper functions and macros for custom "intrinsics" / instructions.
**************************************************************************/
 
42,125 → 42,226
#ifndef neorv32_intrinsics_h
#define neorv32_intrinsics_h
 
 
// ****************************************************************************************************************************
// Custom Instruction Intrinsics
// Derived from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h
// Original license header:
//
// From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h
//
// Copyright (c) 2019 SaxonSoc contributors
//
// MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE
//
// LICENSE:
// MIT License
//
// Copyright (c) 2019 SaxonSoc contributors
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
// ****************************************************************************************************************************
 
/**********************************************************************//**
* @name Custom instructions / intrinsics helper macros
* @name Custom Instruction Intrinsics
* @note Copied from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h
* Original license header:
* // From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h
* //
* // Copyright (c) 2019 SaxonSoc contributors
* //
* // MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE
**************************************************************************/
/**@{*/
asm(".set regnum_x0 , 0");
asm(".set regnum_x1 , 1");
asm(".set regnum_x2 , 2");
asm(".set regnum_x3 , 3");
asm(".set regnum_x4 , 4");
asm(".set regnum_x5 , 5");
asm(".set regnum_x6 , 6");
asm(".set regnum_x7 , 7");
asm(".set regnum_x8 , 8");
asm(".set regnum_x9 , 9");
asm(".set regnum_x10 , 10");
asm(".set regnum_x11 , 11");
asm(".set regnum_x12 , 12");
asm(".set regnum_x13 , 13");
asm(".set regnum_x14 , 14");
asm(".set regnum_x15 , 15");
asm(".set regnum_x16 , 16");
asm(".set regnum_x17 , 17");
asm(".set regnum_x18 , 18");
asm(".set regnum_x19 , 19");
asm(".set regnum_x20 , 20");
asm(".set regnum_x21 , 21");
asm(".set regnum_x22 , 22");
asm(".set regnum_x23 , 23");
asm(".set regnum_x24 , 24");
asm(".set regnum_x25 , 25");
asm(".set regnum_x26 , 26");
asm(".set regnum_x27 , 27");
asm(".set regnum_x28 , 28");
asm(".set regnum_x29 , 29");
asm(".set regnum_x30 , 30");
asm(".set regnum_x31 , 31");
 
//** Selection helper macro */
#define STR1(x) #x
//** Selection helper macro 2 */
#define STR(x) STR1(x)
asm(".set regnum_zero, 0");
asm(".set regnum_ra , 1");
asm(".set regnum_sp , 2");
asm(".set regnum_gp , 3");
asm(".set regnum_tp , 4");
asm(".set regnum_t0 , 5");
asm(".set regnum_t1 , 6");
asm(".set regnum_t2 , 7");
asm(".set regnum_s0 , 8");
asm(".set regnum_s1 , 9");
asm(".set regnum_a0 , 10");
asm(".set regnum_a1 , 11");
asm(".set regnum_a2 , 12");
asm(".set regnum_a3 , 13");
asm(".set regnum_a4 , 14");
asm(".set regnum_a5 , 15");
asm(".set regnum_a6 , 16");
asm(".set regnum_a7 , 17");
asm(".set regnum_s2 , 18");
asm(".set regnum_s3 , 19");
asm(".set regnum_s4 , 20");
asm(".set regnum_s5 , 21");
asm(".set regnum_s6 , 22");
asm(".set regnum_s7 , 23");
asm(".set regnum_s8 , 24");
asm(".set regnum_s9 , 25");
asm(".set regnum_s10 , 26");
asm(".set regnum_s11 , 27");
asm(".set regnum_t3 , 28");
asm(".set regnum_t4 , 29");
asm(".set regnum_t5 , 30");
asm(".set regnum_t6 , 31");
/**@}*/
 
//** Register address converter */
#define GET_REG_ADDR(x) REG_ADDR_##x
 
#define REG_ADDR_x0 0 /**< register 0 */
#define REG_ADDR_x1 1 /**< register 1 */
#define REG_ADDR_x2 2 /**< register 2 */
#define REG_ADDR_x3 3 /**< register 3 */
#define REG_ADDR_x4 4 /**< register 4 */
#define REG_ADDR_x5 5 /**< register 5 */
#define REG_ADDR_x6 6 /**< register 6 */
#define REG_ADDR_x7 7 /**< register 7 */
#define REG_ADDR_x8 8 /**< register 8 */
#define REG_ADDR_x9 9 /**< register 9 */
#define REG_ADDR_x10 10 /**< register 10 */
#define REG_ADDR_x11 11 /**< register 11 */
#define REG_ADDR_x12 12 /**< register 12 */
#define REG_ADDR_x13 13 /**< register 13 */
#define REG_ADDR_x14 14 /**< register 14 */
#define REG_ADDR_x15 15 /**< register 15 */
#define REG_ADDR_x16 16 /**< register 16 */
#define REG_ADDR_x17 17 /**< register 17 */
#define REG_ADDR_x18 18 /**< register 18 */
#define REG_ADDR_x19 19 /**< register 19 */
#define REG_ADDR_x20 20 /**< register 20 */
#define REG_ADDR_x21 21 /**< register 21 */
#define REG_ADDR_x22 22 /**< register 22 */
#define REG_ADDR_x23 23 /**< register 23 */
#define REG_ADDR_x24 24 /**< register 24 */
#define REG_ADDR_x25 25 /**< register 25 */
#define REG_ADDR_x26 26 /**< register 26 */
#define REG_ADDR_x27 27 /**< register 27 */
#define REG_ADDR_x28 28 /**< register 28 */
#define REG_ADDR_x29 29 /**< register 29 */
#define REG_ADDR_x30 30 /**< register 30 */
#define REG_ADDR_x31 31 /**< register 31 */
#define REG_ADDR_zero 0 /**< register 0 - according to calling convention */
#define REG_ADDR_ra 1 /**< register 1 - according to calling convention */
#define REG_ADDR_sp 2 /**< register 2 - according to calling convention */
#define REG_ADDR_gp 3 /**< register 3 - according to calling convention */
#define REG_ADDR_tp 4 /**< register 4 - according to calling convention */
#define REG_ADDR_t0 5 /**< register 5 - according to calling convention */
#define REG_ADDR_t1 6 /**< register 6 - according to calling convention */
#define REG_ADDR_t2 7 /**< register 7 - according to calling convention */
#define REG_ADDR_s0 8 /**< register 8 - according to calling convention */
#define REG_ADDR_s1 9 /**< register 9 - according to calling convention */
#define REG_ADDR_a0 10 /**< register 10 - according to calling convention */
#define REG_ADDR_a1 11 /**< register 11 - according to calling convention */
#define REG_ADDR_a2 12 /**< register 12 - according to calling convention */
#define REG_ADDR_a3 13 /**< register 13 - according to calling convention */
#define REG_ADDR_a4 14 /**< register 14 - according to calling convention */
#define REG_ADDR_a5 15 /**< register 15 - according to calling convention */
#define REG_ADDR_a6 16 /**< register 16 - according to calling convention */
#define REG_ADDR_a7 17 /**< register 17 - according to calling convention */
#define REG_ADDR_s2 18 /**< register 18 - according to calling convention */
#define REG_ADDR_s3 19 /**< register 19 - according to calling convention */
#define REG_ADDR_s4 20 /**< register 20 - according to calling convention */
#define REG_ADDR_s5 21 /**< register 21 - according to calling convention */
#define REG_ADDR_s6 22 /**< register 22 - according to calling convention */
#define REG_ADDR_s7 23 /**< register 23 - according to calling convention */
#define REG_ADDR_s8 24 /**< register 24 - according to calling convention */
#define REG_ADDR_s9 25 /**< register 25 - according to calling convention */
#define REG_ADDR_s10 26 /**< register 26 - according to calling convention */
#define REG_ADDR_s11 27 /**< register 27 - according to calling convention */
#define REG_ADDR_t3 28 /**< register 28 - according to calling convention */
#define REG_ADDR_t4 29 /**< register 29 - according to calling convention */
#define REG_ADDR_t5 30 /**< register 30 - according to calling convention */
#define REG_ADDR_t6 31 /**< register 31 - according to calling convention */
/**********************************************************************//**
* @name Custom instruction R1-type format
**************************************************************************/
#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, opcode) \
({ \
register uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1) \
); \
asm volatile( \
".word ( \
(((" #funct7 ") & 0x7f) << 25) | \
(((" #funct5 ") & 0x1f) << 20) | \
((( regnum_%1 ) & 0x1f) << 15) | \
(((" #funct3 ") & 0x07) << 12) | \
((( regnum_%0 ) & 0x1f) << 7) | \
(((" #opcode ") & 0x7f) << 0) \
);" \
: [rd] "=r" (__return) \
: "r" (rs1) \
); \
__return; \
})
 
//** Construct instruction word (32-bit) for R2-type instruction */
#define CMD_WORD_R2_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
( (opcode & 0x7f) << 0 ) + \
( (rd & 0x1f) << 7 ) + \
( (funct3 & 0x1f) << 12 ) + \
( (rs1 & 0x1f) << 15 ) + \
( (rs2 & 0x1f) << 20 ) + \
( (funct7 & 0x7f) << 25 )
 
//** Construct instruction word (32-bit) for R3-type instruction */
#define CMD_WORD_R3_TYPE(rs3, rs2, rs1, funct3, rd, opcode) \
( (opcode & 0x7f) << 0 ) + \
( (rd & 0x1f) << 7 ) + \
( (funct3 & 0x1f) << 12 ) + \
( (rs1 & 0x1f) << 15 ) + \
( (rs2 & 0x1f) << 20 ) + \
( (rs3 & 0x1f) << 27 )
/**********************************************************************//**
* @name Custom instruction R2-type format
**************************************************************************/
#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, opcode) \
({ \
register uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), [input_j] "r" (rs2) \
); \
asm volatile ( \
".word ( \
(((" #funct7 ") & 0x7f) << 25) | \
((( regnum_%2 ) & 0x1f) << 20) | \
((( regnum_%1 ) & 0x1f) << 15) | \
(((" #funct3 ") & 0x07) << 12) | \
((( regnum_%0 ) & 0x1f) << 7) | \
(((" #opcode ") & 0x7f) << 0) \
);" \
: [rd] "=r" (__return) \
: "r" (rs1), "r" (rs2) \
); \
__return; \
})
 
//** Construct instruction word (32-bit) for I-type instruction */
#define CMD_WORD_I_TYPE(imm12, rs1_f5, funct3, rd, opcode) \
( (opcode & 0x7f) << 0 ) + \
( (rd & 0x1f) << 7 ) + \
( (funct3 & 0x1f) << 12 ) + \
( (rs1_f5 & 0x1f) << 15 ) + \
( (imm12 & 0xfff) << 20 )
 
//** Construct custom R3-type instruction (4 registers, funct3, opcode) */
#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, rd, opcode) \
asm volatile (".word " STR(CMD_WORD_R3_TYPE(GET_REG_ADDR(rs3), GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
/**********************************************************************//**
* @name Custom instruction R3-type format
**************************************************************************/
#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, opcode) \
({ \
register uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1), [input_j] "r" (rs2), [input_k] "r" (rs3) \
); \
asm volatile ( \
".word ( \
((( regnum_%3 ) & 0x1f) << 25) | \
((( regnum_%2 ) & 0x1f) << 20) | \
((( regnum_%1 ) & 0x1f) << 15) | \
(((" #funct3 ") & 0x07) << 12) | \
((( regnum_%0 ) & 0x1f) << 7) | \
(((" #opcode ") & 0x7f) << 0) \
);" \
: [rd] "=r" (__return) \
: "r" (rs1), "r" (rs2), "r" (rs3) \
); \
__return; \
})
 
//** Construct custom R2-type instruction (3 registers, funct3, funct7, opcode) */
#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
asm volatile (".word " STR(CMD_WORD_R2_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
 
//** Construct custom R1-type instruction (2 registers, funct3, funct7, funct5, opcode) */
#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, rd, opcode) \
asm volatile (".word " STR(CMD_WORD_R2_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
//** Construct custom I-type instruction (2 registers, funct3, imm12, opcode) */
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, rd, opcode) \
asm volatile (".word " STR(CMD_WORD_I_TYPE(imm12, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
/**@}*/
/**********************************************************************//**
* @name Custom instruction I-type format
**************************************************************************/
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) \
({ \
register uint32_t __return; \
asm volatile ( \
"" \
: [output] "=r" (__return) \
: [input_i] "r" (rs1) \
); \
asm volatile ( \
".word ( \
(((" #imm12 ") & 0xfff) << 20) | \
((( regnum_%1 ) & 0x1f) << 15) | \
(((" #funct3 ") & 0x07) << 12) | \
((( regnum_%0 ) & 0x1f) << 7) | \
(((" #opcode ") & 0x7f) << 0) \
);" \
: [rd] "=r" (__return) \
: "r" (rs1) \
); \
__return; \
})
 
 
#endif // neorv32_intrinsics_h
/neorv32/trunk/sw/lib/source/neorv32_cpu.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
148,7 → 148,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
register uint32_t tmp1, tmp2, tmp3;
177,7 → 177,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
cycles.uint64 = value;
199,7 → 199,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
register uint32_t tmp1, tmp2, tmp3;
228,7 → 228,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
cycles.uint64 = value;
250,7 → 250,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
register uint32_t tmp1, tmp2, tmp3;
/neorv32/trunk/sw/lib/source/neorv32_gpio.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
143,7 → 143,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} data;
 
data.uint64 = port_data;
161,7 → 161,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} data;
 
data.uint32[0] = NEORV32_GPIO.INPUT_LO;
/neorv32/trunk/sw/lib/source/neorv32_mtime.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
72,7 → 72,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
cycles.uint64 = time;
95,7 → 95,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
uint32_t tmp1, tmp2, tmp3;
127,7 → 127,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
cycles.uint64 = timecmp;
147,7 → 147,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} cycles;
 
cycles.uint32[0] = NEORV32_MTIME.TIMECMP_LO;
/neorv32/trunk/sw/lib/source/neorv32_rte.c
323,7 → 323,7
else {
neorv32_uart0_printf("unknown");
}
 
// CPU extensions
neorv32_uart0_printf("\nISA extensions: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
358,10 → 358,12
if (tmp & (1<<SYSINFO_CPU_ZXSCNT)) {
neorv32_uart0_printf("Zxscnt(!) ");
}
 
if (tmp & (1<<SYSINFO_CPU_DEBUGMODE)) {
neorv32_uart0_printf("Debug ");
}
 
// CPU extension options
neorv32_uart0_printf("\nExtension options: ");
if (tmp & (1<<SYSINFO_CPU_FASTMUL)) {
neorv32_uart0_printf("FAST_MUL ");
}
582,10 → 584,8
return; // cannot output anything if UART0 is not implemented
}
 
neorv32_uart0_print("The NEORV32 RISC-V Processor\n"
"(c) 2021, Stephan Nolting\n"
"BSD 3-Clause License\n"
"https://github.com/stnolting/neorv32\n\n");
neorv32_uart0_print("The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32\n"
"(c) 2022 by Stephan Nolting, BSD 3-Clause License\n\n");
}
 
 
648,7 → 648,7
"\n"
"BSD 3-Clause License\n"
"\n"
"Copyright (c) 2021, Stephan Nolting. All rights reserved.\n"
"Copyright (c) 2022, Stephan Nolting. All rights reserved.\n"
"\n"
"Redistribution and use in source and binary forms, with or without modification, are\n"
"permitted provided that the following conditions are met:\n"
/neorv32/trunk/sw/lib/source/neorv32_xip.c
197,7 → 197,7
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
} data;
 
data.uint64 = *rtx_data;
/neorv32/trunk/sw/README.md
1,4 → 1,4
# NEORV32 Software Framework
# Software Framework
 
This folder provides the core of the NEORV32 software framework.
This is a short description of the main folders.
/neorv32/trunk/.gitignore
34,10 → 34,6
*.cf
*.o
 
# example bitstreams
/setups/examples/*.bit
/setups/examples/*.svf
 
# riscv-arch-test
 
/sim/work/
/neorv32/trunk/CHANGELOG.md
26,6 → 26,17
 
| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 28.01.2022 |[**:rocket:1.6.7**](https://github.com/stnolting/neorv32/releases/tag/v1.6.7) | **New release** |
| 28.01.2022 | 1.6.6.10 | :bug: fixed bug in **bit-manipulation co-processor**: decoding collision between `cpop` and `rol` instructions; :bug: fixed bug in co-processor arbitration when an illegal instruction is detected; added four additional (yet unused) **CPU** co-processor slots; [PR #262](https://github.com/stnolting/neorv32/pull/262) |
| 27.01.2022 | 1.6.6.9 | reworked **CFS** "user" logic; added CFS demo program; see [PR #261](https://github.com/stnolting/neorv32/pull/261) |
| 27.01.2022 | 1.6.6.8 | :sparkles: added support for RISC-V bit-manipulation (`B`) **carry-less multiplication instructions `Zbc`** sub-extension; added test cases and intrinsics; the NEORV32 bit-manipulation ISA extension (`B`) now fully complies to the RISC-V specs. v0.93; see [PR #260](https://github.com/stnolting/neorv32/pull/260) |
| 26.01.2022 | 1.6.6.7 | :sparkles: added support for RISC-V bit-manipulation (`B`) **single-bit instructions `Zbs`** sub-extension; added test cases and intrinsics; see [PR #259](https://github.com/stnolting/neorv32/pull/259) |
| 26.01.2022 | 1.6.6.6 | minor logic optimizations in **CPU control unit** |
| 25.01.2022 | 1.6.6.5 | :lock: **on-chip debugger:** the memory-mapped registers of the debug module (DM) are only accessible/visible when the CPU is actually in debug mode; any access outside of debug mode will now raise a bus exception |
| 22.01.2022 | 1.6.6.4 | minor logic optimizations in **CPU control unit**, minor improvement of critical path |
| 21.01.2022 | 1.6.6.3 | reworked **CPU's instruction issue engine** (area optimization: ~100 LUTs less on an Intel Cyclone IV), [PR #256](https://github.com/stnolting/neorv32/pull/256); minor CPU control unit code clean-ups and logic optimizations |
| 18.01.2022 | 1.6.6.2 | :warning: moved `setups` folder to new [neorv32-setups](https://github.com/stnolting/neorv32-setups) repository, [PR #254](https://github.com/stnolting/neorv32/pull/254) |
| 18.01.2022 | 1.6.6.1 | minor **MTIME** VHDL code clean-up; minor logic optimization of **CPU's bus unit** |
| 17.01.2022 |[**:rocket:1.6.6**](https://github.com/stnolting/neorv32/releases/tag/v1.6.6) | **New release** |
| 14.01.2022 | 1.6.5.9 | **GPIO** module: write accesses to the GPIO module's "input" registers will now raise a bus exception; [PR #255](https://github.com/stnolting/neorv32/pull/255) |
| 11.01.2022 | 1.6.5.8 | minor rtl code clean-ups and edits in `rtl/core`; any write access to the SYSINFO module will now show up as a BUSKEEPER's "DEVICE_ERR" |
/neorv32/trunk/README.md
27,7 → 27,8
 
![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
 
The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** that is based on the RISC-V NEORV32 CPU.
The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** that is based on the
[RISC-V](https://riscv.org/) NEORV32 CPU.
The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz.
 
42,7 → 43,7
:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
To see the changes between _official releases_ visit the project's [release page](https://github.com/stnolting/neorv32/releases).
 
:package: [Exemplary setups](https://github.com/stnolting/neorv32/tree/master/setups) targeting
:package: [**Exemplary setups**](https://github.com/stnolting/neorv32-setups) targeting
various FPGA boards and toolchains to get you started.
 
:kite: Supported by upstream [Zephyr OS](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) and FreeRTOS.
70,12 → 71,10
 
[![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases)
[![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32)
\
[![Documentation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Documentation/master?longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
\
[![riscv-arch-test](https://img.shields.io/github/workflow/status/stnolting/neorv32/riscv-arch-test/master?longCache=true&style=flat-square&label=riscv-arch-test&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
[![Processor](https://img.shields.io/github/workflow/status/stnolting/neorv32/Processor/master?longCache=true&style=flat-square&label=Processor&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
[![Implementation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Implementation/master?longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
[![Windows](https://img.shields.io/github/workflow/status/stnolting/neorv32/Windows/master?longCache=true&style=flat-square&label=Windows&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows)
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
 
141,10 → 140,10
of the online datasheet shows the resource utilization of each optional processor module to allow an
estimation of the actual setup's hardware requirements.
 
The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
:bulb: The [`neorv32-setups`](https://github.com/stnolting/neorv32-setups) repository provides exemplary FPGA
setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
SoC configurations. The latest utilization reports for those setups can be found in the report of the
[Implementation Workflow](https://github.com/stnolting/neorv32/actions/workflows/Implementation.yml).
[Implementation Workflow](https://github.com/stnolting/neorv32-setups/actions/workflows/Implementation.yml).
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
 
171,7 → 170,7
### Available ISA Extensions
 
Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
documentation section). Note that the `X` extension is always enabled.
documentation section).
 
**RV32
[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
191,8 → 190,9
[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
 
:warning: The `B`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic libraries_ for these extensions.
:warning: The `B`, `Zfinx` and `Zmmul` RISC-V are frozen and officially ratified but there is no
upstream gcc support yet. To circumvent this, the NEORV32 software framework provides _intrinsic libraries_ for the
`B` and `Zfinx` extensions.
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
 
208,7 → 208,7
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
 
:information_source: An incremental list of CPU extension's hardware utilization can found in the
:bulb: An incremental list of CPU extension's hardware utilization can found in the
[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
220,8 → 220,9
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
available CPU extensions.
 
The following table shows the performance results (scores and average CPI) for _exemplary_ CPU configurations executing
2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) CPU benchmark.
The following table shows the performance results (scores and average CPI) for exemplary CPU configurations executing
2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) CPU benchmark
(using plain rv32i built-in libraries only!).
 
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
|:------------------------------------------------|:-----:|:----------:|:--------:|
229,7 → 230,7
| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
 
:information_source: More information regarding the CPU performance can be found in the
:bulb: More information regarding the CPU performance can be found in the
[_Data Sheet: CPU Performance_](https://stnolting.github.io/neorv32/#_cpu_performance).
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
246,7 → 247,7
* runtime environment for handling traps
* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life
* doxygen-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future: "Verilog-to-Routing") - both, software and hardware can be
* supports implementation using open source tooling ([GHDL](https://github.com/ghdl/ghdl), Yosys, nextpnr, ...) - both, software and hardware can be
developed and debugged with open source tooling
* [continuous integration](https://github.com/stnolting/neorv32/actions) is available for:
* allowing users to see the expected execution/output of the tools
318,18 → 319,9
(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/master/LICENSE)).
Please quote it appropriately. :+1:
 
We (the community) and I highly appreciate _any_ kind of feedback! Feel free to start a new "show & tell"
[discussion](https://github.com/stnolting/neorv32/discussions), write some lines on our [gitter channel](https://gitter.im/neorv32/community)
or directly get in [contact](mailto:stnolting@gmail.com) with me.
 
[[back to top](#The-NEORV32-RISC-V-Processor)]
 
 
---------------------------------------
 
## Acknowledgements
 
**A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
 
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
 
Continuous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).

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