URL
https://opencores.org/ocsvn/spi_boot/spi_boot/trunk
Subversion Repositories spi_boot
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/tags/rel_3_1_rev_C/doc/spi_boot.pdf
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Index: tags/rel_3_1_rev_C/doc/spi_boot_schematic.pdf
===================================================================
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Index: tags/rel_3_1_rev_C/doc/spi_boot_schematic.pdf
===================================================================
--- tags/rel_3_1_rev_C/doc/spi_boot_schematic.pdf (nonexistent)
+++ tags/rel_3_1_rev_C/doc/spi_boot_schematic.pdf (revision 71)
tags/rel_3_1_rev_C/doc/spi_boot_schematic.pdf
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Index: tags/rel_3_1_rev_C/KNOWN_BUGS
===================================================================
--- tags/rel_3_1_rev_C/KNOWN_BUGS (nonexistent)
+++ tags/rel_3_1_rev_C/KNOWN_BUGS (revision 71)
@@ -0,0 +1,52 @@
+
+Known bugs of the spi_boot core
+===============================
+Version: $Date: 2007-08-08 00:40:46 $
+$Name: not supported by cvs2svn $
+
+
+Release 3.1, Rev C
+------------------
+
+*******************************************************************************
+CMD55 assumed to be nonexistent for MMC
+
+The controller FSM assumes that MMC cards result with
+"Illegal Command" from CMD55. The card will be detected as an MMC once CMD55
+has been accepted. However, the MMC standard defines this command,
+thus it is not save to rely on its nonexistence. Instead also a path from
+ACMD41 to CMD1 should be established.
+
+Fixed in:
+spi_boot.vhd 1.11
+Fix will be included in next release.
+
+
+
+Release 3.0, Rev C
+------------------
+
+*******************************************************************************
+CMD55 assumed to be nonexistent for MMC
+
+See above.
+
+
+
+Release 2.0, Rev B
+------------------
+
+*******************************************************************************
+CMD55 assumed to be nonexistent for MMC
+
+See above.
+
+
+
+Release 1.0, Rev A
+------------------
+
+*******************************************************************************
+CMD55 assumed to be nonexistent for MMC
+
+See above.
Index: tags/rel_3_1_rev_C/README
===================================================================
--- tags/rel_3_1_rev_C/README (nonexistent)
+++ tags/rel_3_1_rev_C/README (revision 71)
@@ -0,0 +1,170 @@
+
+README for the spi_boot core
+============================
+Version: $Date: 2005-04-14 21:32:58 $
+
+
+Description
+-----------
+
+The SD/MMC Bootloader is a CPLD design that manages configuration and
+bootstrapping of FPGAs. It is able to retrieve the required data from
+SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA
+configuration process. SD cards as well as MMCs are operated in SPI mode which
+is part of both standards thus eliminating the need for dedicated
+implementations. The SD/MMC Bootloader fits both. Beyond configuration, this
+core supports a bootstrapping strategy where multiple images are stored on one
+single memory card.
+For example consider a system completely based on SRAM. The bootloader
+provides the initial configuration data from the first image to the FPGA. This
+image contains a design which pulls the next image from the memory card and
+transfers this data to SRAM. In the third step the final FPGA design is loaded
+from the third image.
+These images are clustered in sets which can be selected by external switches
+for example. Several configuration sets can be stored on one memory card
+allowing you to provide a number of applications which are downloaded quickly
+to the FPGA.
+The schematic (rev. B) shows how the core can be used with an FPGA board. I
+use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300
+board. SV2 fits the "SERIAL MODE" connector on this board but you will have to
+add a separate wire from R6 to attach INIT. Please check the proper use of the
+pull-up resistors for your specific board.
+
+
+Features
+--------
+
+* Configuration mode: configures SRAM based FPGAs via slave serial mode
+ (Xilinx and Altera)
+* Data mode: provides stored data over a simple synchronous serial interface
+* Broad compatability using SPI mode
+ + SecureDigital cards using dedicated initialization command
+ + MultiMediaCards (see below)
+* Operation triggerd by power-up or card insertion
+* Multiple configuration sets stored on on single memory card
+
+
+Compatability
+-------------
+
+These cards have been tested with the SD/MMC Bootloader:
+
+ * Hama 64 MB SD
+ * SanDisk 128 MB SD
+ * SanDisk 64 MB MMC
+ * Panasonic 32 MB SD
+
+Some MMC might fail with this core as not all cards support CMD18
+(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific
+model. In case your MMC does not implement CMD18 you might want to have a look
+at the FPGA MMC-Card Config project.
+
+
+Tools
+-----
+
+Downloading the configuration data to the card is a straight forward
+process. The images have to be written starting at dedicated locations. For
+the provided toplevel designs, these locations are multiples of 256 K. I.e. 0,
+0x40000, 0x80000 and so forth.
+
+dd (part of the GNU coreutils) serves this purpose:
+$ dd if=ram_loader.bin of=/dev/sdX bs=512
+$ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512
+$ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024
+
+The name of the device node depends on how the card reader is attached to the
+kernel. For Linux systems this is most often something like /dev/sdX with X
+ranging from a-z. Please note that it is essential to use the device without
+any trailing numbers as they refer to partitions leading to wrong offsets for
+data written to the card.
+All this works perfectly for my Spartan IIe device as this FPGA expects the
+configuration data as it is delivered from the card: Consecutive bytes each
+with its most significant bit first. Altera devices like the FLEX family are
+different here. They expect the bytes with least significant bit
+first. Therefore, the configuration data has to be swapped bitwise before it
+is written to the card.
+
+
+Verification
+------------
+
+The spi_boot core comes with a simple testbench that simulates an SD/MMC
+card. All four implementations of the core are verified there in parallel
+while transferring the data for several sets.
+You should normally not need to run the testbench. But in case you modified
+the VHDL code the testbench gives some hints if the design has been broken.
+
+
+Directory Structure
+-------------------
+
+The core's directory structure follows the proposal of OpenCores.org.
+
+spi_boot
+ |
+ \--+-- doc : Documentation
+ | |
+ | \-- src : Source files of documentation
+ |
+ +-- rtl
+ | |
+ | \-- vhdl : VHDL code containing the RTL description
+ | of the core.
+ |
+ +-- bench
+ | |
+ | \-- vhdl : VHDL testbench code.
+ |
+ \-- sim
+ |
+ \-- rtl_sim : Directory for running simulations.
+
+
+RAM Loader
+----------
+
+Directory rtl/vhdl/ram_loader contains the sample design which loads the next
+image from the card and stores its contents to external asynchronous
+RAM. After reading 64 KB it triggers a new configuration process for the final
+FPGA design.
+Refer to the code for the mechanisms involved.
+
+
+Compiling the VHDL Code
+-----------------------
+
+VHDL compilation and simulation tasks take place inside in sim/rtl_sim
+directory. The project setup supports only the GHDL simulator (see
+http://ghdl.free.fr).
+
+To compile the code simply type at the shell
+
+$ make
+
+This should result in a file called tb_behav_c0 which can be executed as any
+other executable.
+
+The basic simple sequence list can be found in COMPILE_LIST. This can be
+useful to quickly set up the analyze stage of any compiler or
+synthesizer. Especially when synthesizing the code, you want to skip the VHDL
+configurations in *-c.vhd and everything below the bench/ directory.
+
+
+References
+----------
+
+ * SanDisk SD Card Product Manual
+ http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf
+
+ * SanDisk MMC Product Manual
+ http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf
+
+ * Toshiba SD Card Specification
+ http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf
+
+ * BurchED
+ http://burched.biz/
+
+ * FPGA MMC-Card Config project
+ http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview
Index: tags/rel_3_1_rev_C/COMPILE_LIST
===================================================================
--- tags/rel_3_1_rev_C/COMPILE_LIST (nonexistent)
+++ tags/rel_3_1_rev_C/COMPILE_LIST (revision 71)
@@ -0,0 +1,33 @@
+
+Compile list for the spi_boot core
+==================================
+Version: $Date: 2005-04-14 21:26:22 $
+
+bench/vhdl/tb.vhd
+rtl/vhdl/spi_boot_pack-p.vhd
+bench/vhdl/tb_pack-p.vhd
+bench/vhdl/tb_elem.vhd
+rtl/vhdl/chip-e.vhd
+rtl/vhdl/chip-full-a.vhd
+rtl/vhdl/spi_boot.vhd
+rtl/vhdl/spi_counter.vhd
+rtl/vhdl/spi_counter-c.vhd
+rtl/vhdl/spi_boot-c.vhd
+rtl/vhdl/chip-full-c.vhd
+bench/vhdl/card.vhd
+bench/vhdl/card-c.vhd
+bench/vhdl/tb_elem-full-c.vhd
+rtl/vhdl/chip-mmc-a.vhd
+rtl/vhdl/chip-mmc-c.vhd
+bench/vhdl/tb_elem-mmc-c.vhd
+rtl/vhdl/chip-sd-a.vhd
+rtl/vhdl/chip-sd-c.vhd
+bench/vhdl/tb_elem-sd-c.vhd
+rtl/vhdl/chip-minimal-a.vhd
+rtl/vhdl/chip-minimal-c.vhd
+bench/vhdl/tb_elem-minimal-c.vhd
+bench/vhdl/tb-c.vhd
+bench/vhdl/tb_rl.vhd
+rtl/vhdl/sample/ram_loader.vhd
+rtl/vhdl/sample/ram_loader-c.vhd
+bench/vhdl/tb_rl-c.vhd
Index: tags/rel_3_1_rev_C/sim/rtl_sim/Makefile
===================================================================
--- tags/rel_3_1_rev_C/sim/rtl_sim/Makefile (nonexistent)
+++ tags/rel_3_1_rev_C/sim/rtl_sim/Makefile (revision 71)
@@ -0,0 +1,159 @@
+##############################################################################
+#
+# Makefile for the spi_boot project.
+#
+# The dependencies for all VHDL source files are stored here.
+#
+# Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+#
+# All rights reserved
+#
+##############################################################################
+
+
+PROJECT_DIR = ../..
+RTL_DIR = $(PROJECT_DIR)/rtl/vhdl
+BENCH_DIR = $(PROJECT_DIR)/bench/vhdl
+
+
+
+ANALYZE=ghdl -a --std=87 --workdir=work
+ELABORATE=ghdl -e --std=87 --workdir=work
+
+.PHONY: all
+all: work elaborate
+
+work:
+ mkdir work
+
+work/spi_boot_pack-p.o: $(RTL_DIR)/spi_boot_pack-p.vhd
+ $(ANALYZE) $(RTL_DIR)/spi_boot_pack-p.vhd
+
+work/spi_counter.o: $(RTL_DIR)/spi_counter.vhd \
+ work/spi_boot_pack-p.o
+ $(ANALYZE) $(RTL_DIR)/spi_counter.vhd
+work/spi_counter-c.o: $(RTL_DIR)/spi_counter-c.vhd \
+ work/spi_counter.o
+ $(ANALYZE) $(RTL_DIR)/spi_counter-c.vhd
+
+work/spi_boot.o: $(RTL_DIR)/spi_boot.vhd \
+ work/spi_boot_pack-p.o
+ $(ANALYZE) $(RTL_DIR)/spi_boot.vhd
+work/spi_boot-c.o: $(RTL_DIR)/spi_boot-c.vhd \
+ work/spi_boot.o \
+ work/spi_counter-c.o
+ $(ANALYZE) $(RTL_DIR)/spi_boot-c.vhd
+
+work/chip-e.o: $(RTL_DIR)/chip-e.vhd
+ $(ANALYZE) $(RTL_DIR)/chip-e.vhd
+
+work/chip-full-a.o: $(RTL_DIR)/chip-full-a.vhd \
+ work/chip-e.o
+ $(ANALYZE) $(RTL_DIR)/chip-full-a.vhd
+work/chip-full-c.o: $(RTL_DIR)/chip-full-c.vhd \
+ work/chip-full-a.o \
+ work/spi_boot-c.o
+ $(ANALYZE) $(RTL_DIR)/chip-full-c.vhd
+
+work/chip-mmc-a.o: $(RTL_DIR)/chip-mmc-a.vhd \
+ work/chip-e.o
+ $(ANALYZE) $(RTL_DIR)/chip-mmc-a.vhd
+work/chip-mmc-c.o: $(RTL_DIR)/chip-mmc-c.vhd \
+ work/chip-mmc-a.o \
+ work/spi_boot-c.o
+ $(ANALYZE) $(RTL_DIR)/chip-mmc-c.vhd
+
+work/chip-sd-a.o: $(RTL_DIR)/chip-sd-a.vhd \
+ work/chip-e.o
+ $(ANALYZE) $(RTL_DIR)/chip-sd-a.vhd
+work/chip-sd-c.o: $(RTL_DIR)/chip-sd-c.vhd \
+ work/chip-sd-a.o \
+ work/spi_boot-c.o
+ $(ANALYZE) $(RTL_DIR)/chip-sd-c.vhd
+
+work/chip-minimal-a.o: $(RTL_DIR)/chip-minimal-a.vhd \
+ work/chip-e.o
+ $(ANALYZE) $(RTL_DIR)/chip-minimal-a.vhd
+work/chip-minimal-c.o: $(RTL_DIR)/chip-minimal-c.vhd \
+ work/chip-minimal-a.o \
+ work/spi_boot-c.o
+ $(ANALYZE) $(RTL_DIR)/chip-minimal-c.vhd
+
+work/ram_loader.o: $(RTL_DIR)/sample/ram_loader.vhd
+ $(ANALYZE) $(RTL_DIR)/sample/ram_loader.vhd
+work/ram_loader-c.o: $(RTL_DIR)/sample/ram_loader-c.vhd \
+ work/ram_loader.o
+ $(ANALYZE) $(RTL_DIR)/sample/ram_loader-c.vhd
+
+work/tb_pack-p.o: $(BENCH_DIR)/tb_pack-p.vhd
+ $(ANALYZE) $(BENCH_DIR)/tb_pack-p.vhd
+
+work/card.o: $(BENCH_DIR)/card.vhd \
+ work/tb_pack-p.o
+ $(ANALYZE) $(BENCH_DIR)/card.vhd
+work/card-c.o: $(BENCH_DIR)/card-c.vhd \
+ work/card.o
+ $(ANALYZE) $(BENCH_DIR)/card-c.vhd
+
+work/tb_elem.o: $(BENCH_DIR)/tb_elem.vhd \
+ work/spi_boot_pack-p.o \
+ work/tb_pack-p.o
+ $(ANALYZE) $(BENCH_DIR)/tb_elem.vhd
+work/tb_elem-full-c.o: $(BENCH_DIR)/tb_elem-full-c.vhd \
+ work/tb_elem.o \
+ work/chip-full-c.o \
+ work/card-c.o
+ $(ANALYZE) $(BENCH_DIR)/tb_elem-full-c.vhd
+work/tb_elem-mmc-c.o: $(BENCH_DIR)/tb_elem-mmc-c.vhd \
+ work/tb_elem.o \
+ work/chip-mmc-c.o \
+ work/card-c.o
+ $(ANALYZE) $(BENCH_DIR)/tb_elem-mmc-c.vhd
+work/tb_elem-sd-c.o: $(BENCH_DIR)/tb_elem-sd-c.vhd \
+ work/tb_elem.o \
+ work/chip-sd-c.o \
+ work/card-c.o
+ $(ANALYZE) $(BENCH_DIR)/tb_elem-sd-c.vhd
+work/tb_elem-minimal-c.o: $(BENCH_DIR)/tb_elem-minimal-c.vhd \
+ work/tb_elem.o \
+ work/chip-minimal-c.o \
+ work/card-c.o
+ $(ANALYZE) $(BENCH_DIR)/tb_elem-minimal-c.vhd
+
+work/tb.o: $(BENCH_DIR)/tb.vhd
+ $(ANALYZE) $(BENCH_DIR)/tb.vhd
+work/tb-c.o: $(BENCH_DIR)/tb-c.vhd \
+ work/tb.o \
+ work/tb_elem-full-c.o \
+ work/tb_elem-mmc-c.o \
+ work/tb_elem-sd-c.o \
+ work/tb_elem-minimal-c.o
+ $(ANALYZE) $(BENCH_DIR)/tb-c.vhd
+
+work/tb_rl.o: $(BENCH_DIR)/tb_rl.vhd
+ $(ANALYZE) $(BENCH_DIR)/tb_rl.vhd
+work/tb_rl-c.o: $(BENCH_DIR)/tb_rl-c.vhd \
+ work/tb_rl.o \
+ work/chip-full-c.o \
+ work/card-c.o \
+ work/ram_loader-c.o
+ $(ANALYZE) $(BENCH_DIR)/tb_rl-c.vhd
+
+
+.PHONY: elaborate
+elaborate: tb_behav_c0 tb_rl_behav_c0
+
+tb_behav_c0: work/tb-c.o
+ $(ELABORATE) tb_behav_c0; \
+ strip tb_behav_c0
+
+tb_rl_behav_c0: work/tb_rl-c.o
+ $(ELABORATE) tb_rl_behav_c0; \
+ strip tb_rl_behav_c0
+
+.PHONY: analyze
+analyze: work/tb-c.o work/tb_rl-c.o
+
+.PHONY: clean
+clean:
+ rm -rf work tb_behav_c0 tb_rl_behav_c0 *~
Index: tags/rel_3_1_rev_C/bench/vhdl/tb_rl-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb_rl-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb_rl-c.vhd (revision 71)
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_rl-c.vhd,v 1.1 2005-04-10 18:07:26 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_rl_behav_c0 of tb_rl is
+
+ for behav
+
+ for dut_b : chip
+ use configuration work.chip_full_c0;
+ end for;
+
+ for card_b : card
+ use configuration work.card_behav_c0;
+ end for;
+
+ for rl_b : ram_loader
+ use configuration work.ram_loader_rtl_c0;
+ end for;
+
+ end for;
+
+end tb_rl_behav_c0;
Index: tags/rel_3_1_rev_C/bench/vhdl/tb_rl.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb_rl.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb_rl.vhd (revision 71)
@@ -0,0 +1,256 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Testbench for ram_loader
+--
+-- $Id: tb_rl.vhd,v 1.1 2005-04-10 18:07:25 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+entity tb_rl is
+
+end tb_rl;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_rl is
+
+ component chip
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ set_sel_n_i : in std_logic_vector(3 downto 0);
+ spi_clk_o : out std_logic;
+ spi_cs_n_o : out std_logic;
+ spi_data_in_i : in std_logic;
+ spi_data_out_o : out std_logic;
+ start_i : in std_logic;
+ mode_i : in std_logic;
+ config_n_o : out std_logic;
+ detached_o : out std_logic;
+ cfg_init_n_i : in std_logic;
+ cfg_done_i : in std_logic;
+ dat_done_i : in std_logic;
+ cfg_clk_o : out std_logic;
+ cfg_dat_o : out std_logic
+ );
+ end component;
+
+ component card
+ generic (
+ card_type_g : string := "none";
+ is_sd_card_g : integer := 1
+ );
+ port (
+ spi_clk_i : in std_logic;
+ spi_cs_n_i : in std_logic;
+ spi_data_i : in std_logic;
+ spi_data_o : out std_logic
+ );
+ end component;
+
+ component ram_loader
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ lamp_o : out std_logic;
+ cfg_clk_i : in std_logic;
+ cfg_data_i : in std_logic;
+ start_o : out std_logic;
+ mode_o : out std_logic;
+ done_o : out std_logic;
+ detached_i : in std_logic;
+ ram_addr_o : out std_logic_vector(15 downto 0);
+ ram_data_b : out std_logic_vector( 7 downto 0);
+ ram_ce_no : out std_logic_vector( 3 downto 0);
+ ram_oe_no : out std_logic;
+ ram_we_no : out std_logic
+ );
+ end component;
+
+ constant period_c : time := 100 ns;
+ constant rl_period_c : time := 20 ns;
+ constant reset_level_c : integer := 0;
+
+ signal clk_s : std_logic;
+ signal rl_clk_s: std_logic;
+ signal reset_s : std_logic;
+
+ -- SPI interface signals
+ signal spi_clk_s : std_logic;
+ signal spi_data_to_card_s : std_logic;
+ signal spi_data_from_card_s : std_logic;
+ signal spi_cs_n_s : std_logic;
+
+ -- config related signals
+ signal start_s : std_logic;
+ signal mode_s : std_logic;
+ signal config_n_s : std_logic;
+ signal cfg_init_n_s : std_logic;
+ signal cfg_done_s : std_logic;
+ signal dat_done_s : std_logic;
+ signal cfg_clk_s : std_logic;
+ signal cfg_dat_s : std_logic;
+ signal detached_s : std_logic;
+
+ signal set_sel_n_s : std_logic_vector(3 downto 0);
+
+begin
+
+ set_sel_n_s <= (others => '1');
+ cfg_init_n_s <= '1';
+ cfg_done_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ dut_b : chip
+ port map (
+ clk_i => clk_s,
+ reset_i => reset_s,
+ set_sel_n_i => set_sel_n_s,
+ spi_clk_o => spi_clk_s,
+ spi_cs_n_o => spi_cs_n_s,
+ spi_data_in_i => spi_data_from_card_s,
+ spi_data_out_o => spi_data_to_card_s,
+ start_i => start_s,
+ mode_i => mode_s,
+ config_n_o => config_n_s,
+ detached_o => detached_s,
+ cfg_init_n_i => cfg_init_n_s,
+ cfg_done_i => cfg_done_s,
+ dat_done_i => dat_done_s,
+ cfg_clk_o => cfg_clk_s,
+ cfg_dat_o => cfg_dat_s
+ );
+
+ card_b : card
+ generic map (
+ card_type_g => "Full Chip",
+ is_sd_card_g => 1
+ )
+ port map (
+ spi_clk_i => spi_clk_s,
+ spi_cs_n_i => spi_cs_n_s,
+ spi_data_i => spi_data_to_card_s,
+ spi_data_o => spi_data_from_card_s
+ );
+
+ rl_b : ram_loader
+ port map (
+ clk_i => rl_clk_s,
+ reset_i => reset_s,
+ lamp_o => open,
+ cfg_clk_i => cfg_clk_s,
+ cfg_data_i => cfg_dat_s,
+ start_o => start_s,
+ mode_o => mode_s,
+ done_o => dat_done_s,
+ detached_i => detached_s,
+ ram_addr_o => open,
+ ram_data_b => open,
+ ram_ce_no => open,
+ ram_oe_no => open,
+ ram_we_no => open
+ );
+
+ -----------------------------------------------------------------------------
+ -- Clock Generator
+ -----------------------------------------------------------------------------
+ clk: process
+ begin
+ clk_s <= '0';
+ wait for period_c / 2;
+ clk_s <= '1';
+ wait for period_c / 2;
+ end process clk;
+
+ rl_clk: process
+ begin
+ rl_clk_s <= '0';
+ wait for rl_period_c / 2;
+ rl_clk_s <= '1';
+ wait for rl_period_c / 2;
+ end process rl_clk;
+
+
+ -----------------------------------------------------------------------------
+ -- Reset Generator
+ -----------------------------------------------------------------------------
+ reset: process
+ begin
+ if reset_level_c = 0 then
+ reset_s <= '0';
+ else
+ reset_s <= '1';
+ end if;
+
+ wait for period_c * 4 + 10 ns;
+
+ reset_s <= not reset_s;
+
+ wait;
+ end process reset;
+
+
+ -----------------------------------------------------------------------------
+ -- End of Simulation
+ -----------------------------------------------------------------------------
+ eos: process
+ begin
+ wait for 4 ms;
+ assert false
+ report "No checks have been performed. Investigate waveforms."
+ severity note;
+ assert false
+ report "End of simulation."
+ severity failure;
+ end process eos;
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/bench/vhdl/tb_elem.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb_elem.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb_elem.vhd (revision 71)
@@ -0,0 +1,373 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Generic testbench element for a specific feature set
+--
+-- $Id: tb_elem.vhd,v 1.7 2005-04-07 20:43:36 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity tb_elem is
+
+ generic (
+ chip_type_g : string := "none";
+ has_sd_card_g : integer := 1
+ );
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ eos_o : out boolean
+ );
+
+end tb_elem;
+
+
+library ieee;
+use ieee.numeric_std.all;
+library std;
+use std.textio.all;
+
+use work.spi_boot_pack.all;
+use work.tb_pack.all;
+
+architecture behav of tb_elem is
+
+ component chip
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ set_sel_n_i : in std_logic_vector(3 downto 0);
+ spi_clk_o : out std_logic;
+ spi_cs_n_o : out std_logic;
+ spi_data_in_i : in std_logic;
+ spi_data_out_o : out std_logic;
+ start_i : in std_logic;
+ mode_i : in std_logic;
+ config_n_o : out std_logic;
+ detached_o : out std_logic;
+ cfg_init_n_i : in std_logic;
+ cfg_done_i : in std_logic;
+ dat_done_i : in std_logic;
+ cfg_clk_o : out std_logic;
+ cfg_dat_o : out std_logic
+ );
+ end component;
+
+ component card
+ generic (
+ card_type_g : string := "none";
+ is_sd_card_g : integer := 1
+ );
+ port (
+ spi_clk_i : in std_logic;
+ spi_cs_n_i : in std_logic;
+ spi_data_i : in std_logic;
+ spi_data_o : out std_logic
+ );
+ end component;
+
+ signal reset_s : std_logic;
+
+ -- SPI interface signals
+ signal spi_clk_s : std_logic;
+ signal spi_data_to_card_s : std_logic;
+ signal spi_data_from_card_s : std_logic;
+ signal spi_cs_n_s : std_logic;
+
+ -- config related signals
+ signal start_s : std_logic;
+ signal mode_s : std_logic;
+ signal config_n_s : std_logic;
+ signal cfg_init_n_s : std_logic;
+ signal cfg_done_s : std_logic;
+ signal dat_done_s : std_logic;
+ signal cfg_clk_s : std_logic;
+ signal cfg_dat_s : std_logic;
+ signal data_s : unsigned(7 downto 0);
+
+ signal set_sel_n_s : std_logic_vector(3 downto 0);
+
+ constant verbose_c : boolean := false;
+
+begin
+
+ -- weak pull-ups
+ spi_clk_s <= 'H';
+ spi_cs_n_s <= 'H';
+ spi_data_to_card_s <= 'H';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ dut_b : chip
+ port map (
+ clk_i => clk_i,
+ reset_i => reset_s,
+ set_sel_n_i => set_sel_n_s,
+ spi_clk_o => spi_clk_s,
+ spi_cs_n_o => spi_cs_n_s,
+ spi_data_in_i => spi_data_from_card_s,
+ spi_data_out_o => spi_data_to_card_s,
+ start_i => start_s,
+ mode_i => mode_s,
+ config_n_o => config_n_s,
+ detached_o => open,
+ cfg_init_n_i => cfg_init_n_s,
+ cfg_done_i => cfg_done_s,
+ dat_done_i => dat_done_s,
+ cfg_clk_o => cfg_clk_s,
+ cfg_dat_o => cfg_dat_s
+ );
+
+ card_b : card
+ generic map (
+ card_type_g => chip_type_g,
+ is_sd_card_g => has_sd_card_g
+ )
+ port map (
+ spi_clk_i => spi_clk_s,
+ spi_cs_n_i => spi_cs_n_s,
+ spi_data_i => spi_data_to_card_s,
+ spi_data_o => spi_data_from_card_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- DUT Stimuli
+ --
+ stim: process
+
+ procedure rise_cfg_clk(num : integer) is
+ begin
+ for i in 1 to num loop
+ wait until cfg_clk_s'event and cfg_clk_s = '1';
+ end loop;
+ end rise_cfg_clk;
+
+-- procedure fall_cfg_clk(num : integer) is
+-- begin
+-- for i in 1 to num loop
+-- wait until cfg_clk_s'event and cfg_clk_s = '0';
+-- end loop;
+-- end fall_cfg_clk;
+
+ procedure rise_clk(num : integer) is
+ begin
+ for i in 1 to num loop
+ wait until clk_i'event and clk_i = '1';
+ end loop;
+ end rise_clk;
+
+ procedure read_check_byte(ref : unsigned(7 downto 0)) is
+ variable byte_v : unsigned(7 downto 0);
+ variable dump_line : line;
+ begin
+ for bit in 7 downto 0 loop
+ rise_cfg_clk(1);
+ byte_v(bit) := cfg_dat_s;
+ end loop;
+ data_s <= byte_v;
+
+ if byte_v /= ref then
+ write(dump_line, chip_type_g);
+ write(dump_line, string'(" at "));
+ write(dump_line, now);
+ write(dump_line, string'(": read_check_byte failed "));
+ write(dump_line, to_integer(byte_v));
+ write(dump_line, string'(" "));
+ write(dump_line, to_integer(ref));
+ writeline(output, dump_line);
+ end if;
+ end read_check_byte;
+
+ variable dump_line : line;
+ variable addr_v : unsigned(31 downto 0);
+ variable temp_v : unsigned( 7 downto 0);
+ variable set_sel_v : unsigned(3 downto 0);
+
+ begin
+ -- default assignments
+ -- these defaults show the required pull resistors
+ -- except start_i as this must be pulled high for automatic start
+ start_s <= '0';
+ mode_s <= '1';
+ cfg_init_n_s <= '1';
+ cfg_done_s <= '0';
+ dat_done_s <= '1';
+ data_s <= (others => '1');
+ addr_v := (others => '0');
+ eos_o <= false;
+ set_sel_n_s <= (others => '1');
+ reset_s <= '0';
+
+ -- loop through some sets
+ for set in 0 to 3 loop
+ set_sel_v := to_unsigned(set, 4);
+ addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g
+ -- plus width_img_cnt_g
+ set_sel_n_s <= not std_logic_vector(set_sel_v);
+
+ assert not verbose_c
+ report chip_type_g & ": Processing set " & to_string(set)
+ severity note;
+
+ wait for 100 us;
+ reset_s <= '1';
+
+ assert not verbose_c
+ report chip_type_g & ": Requesting image 0"
+ severity note;
+
+ -- signal start
+ start_s <= '1';
+ mode_s <= '1';
+ cfg_done_s <= '0';
+ addr_v(19 downto 0) := (others => '0');
+ wait until config_n_s = '0';
+ -- run through configuration sequence
+ rise_clk(1);
+ cfg_init_n_s <= '0';
+ rise_clk(3);
+ cfg_init_n_s <= '1';
+
+ -- and receive 32 bytes from image 0
+ for i in 1 to 32 loop
+ temp_v := addr_v(0) & calc_crc(addr_v);
+ read_check_byte(temp_v);
+ addr_v := addr_v + 1;
+ end loop;
+ start_s <= '0';
+ cfg_done_s <= '1';
+
+ rise_clk(10);
+
+ assert not verbose_c
+ report chip_type_g & ": Requesting image 1"
+ severity note;
+
+ -- request next image
+ mode_s <= '0';
+ start_s <= '1';
+ addr_v(17 downto 0) := (others => '0');
+ addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd
+ dat_done_s <= '0';
+
+ -- receive another 32 bytes from image 1
+ for i in 1 to 32 loop
+ temp_v := addr_v(0) & calc_crc(addr_v);
+ read_check_byte(temp_v);
+ addr_v := addr_v + 1;
+ end loop;
+ start_s <= '0';
+ dat_done_s <= '1';
+
+
+ rise_clk(10);
+
+ assert not verbose_c
+ report chip_type_g & ": Requesting image 2"
+ severity note;
+
+ -- request next image
+ mode_s <= '1';
+ start_s <= '1';
+ addr_v(17 downto 0) := (others => '0');
+ addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd
+
+ wait until config_n_s = '0';
+ -- run through configuration sequence
+ rise_clk(1);
+ cfg_done_s <= '0';
+ cfg_init_n_s <= '0';
+ rise_clk(3);
+ cfg_init_n_s <= '1';
+
+ -- receive another 32 bytes from image 2
+ for i in 1 to 32 loop
+ temp_v := addr_v(0) & calc_crc(addr_v);
+ read_check_byte(temp_v);
+ addr_v := addr_v + 1;
+ end loop;
+ start_s <= '0';
+ cfg_done_s <= '1';
+
+ -- give dut a chance to stop current transfer
+ wait until spi_cs_n_s = '1';
+ rise_clk(10);
+
+ reset_s <= '0';
+ end loop;
+
+ eos_o <= true;
+ wait;
+ end process stim;
+ --
+ -----------------------------------------------------------------------------
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.6 2005/03/09 19:48:04 arniml
+-- make verbosity level switchable
+--
+-- Revision 1.5 2005/03/08 22:06:21 arniml
+-- added set selection
+--
+-- Revision 1.4 2005/02/17 18:59:23 arniml
+-- clarify wording for images
+--
+-- Revision 1.3 2005/02/16 19:34:56 arniml
+-- add weak pull-ups for SPI lines
+--
+-- Revision 1.2 2005/02/13 17:14:03 arniml
+-- change dat_done handling
+--
+-- Revision 1.1 2005/02/08 21:09:20 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/bench/vhdl/tb_pack-p.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb_pack-p.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb_pack-p.vhd (revision 71)
@@ -0,0 +1,90 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_pack-p.vhd,v 1.2 2005-03-08 22:06:39 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package tb_pack is
+
+ function calc_crc(payload : in std_logic_vector) return std_logic_vector;
+ function calc_crc(payload : in unsigned) return unsigned;
+
+ function to_string(value : in integer) return string;
+
+end tb_pack;
+
+
+package body tb_pack is
+
+ function calc_crc(payload : in std_logic_vector) return std_logic_vector is
+
+ variable crc_v : std_logic_vector(6 downto 0);
+ variable temp_v : std_logic;
+
+ begin
+
+ crc_v := (others => '0');
+
+ for i in payload'high downto payload'low loop
+ temp_v := payload(i) xor crc_v(6);
+
+ crc_v(6 downto 4) := crc_v(5 downto 3);
+ crc_v(3) := crc_v(2) xor temp_v;
+ crc_v(2 downto 1) := crc_v(1 downto 0);
+ crc_v(0) := temp_v;
+ end loop;
+
+ return crc_v;
+ end calc_crc;
+
+ function calc_crc(payload : in unsigned) return unsigned is
+ begin
+ return unsigned(calc_crc(std_logic_vector(payload)));
+ end calc_crc;
+
+ function to_string(value : in integer) return string is
+ variable str: string (11 downto 1);
+ variable val: integer := value;
+ variable digit: natural;
+ variable index: natural := 0;
+ begin
+ -- Taken from:
+ -- textio package body. This file is part of GHDL.
+ -- Copyright (C) 2002 Tristan Gingold.
+ -- Note: the absolute value of VAL cannot be directly taken, since
+ -- it may be greather that the maximum value of an INTEGER.
+ loop
+ -- LRM93 7.2.6
+ -- (A rem B) has the sign of A and an absolute value less then
+ -- the absoulte value of B.
+ digit := abs (val rem 10);
+ val := val / 10;
+ index := index + 1;
+ str (index) := character'val(48 + digit);
+ exit when val = 0;
+ end loop;
+ if value < 0 then
+ index := index + 1;
+ str(index) := '-';
+ end if;
+
+ return str;
+ end to_string;
+
+end tb_pack;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2005/02/08 21:09:20 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/bench/vhdl/card.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/card.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/card.vhd (revision 71)
@@ -0,0 +1,443 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Simple SD and MMC model
+--
+-- $Id: card.vhd,v 1.2 2005-02-13 17:06:22 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity card is
+
+ generic (
+ card_type_g : string := "none";
+ is_sd_card_g : integer := 1
+ );
+
+ port (
+ spi_clk_i : in std_logic;
+ spi_cs_n_i : in std_logic;
+ spi_data_i : in std_logic;
+ spi_data_o : out std_logic
+ );
+
+end card;
+
+
+library ieee;
+use ieee.numeric_std.all;
+library std;
+use std.textio.all;
+
+use work.tb_pack.all;
+
+architecture behav of card is
+
+ signal power_on_n_s : std_logic;
+ signal soft_res_n_s : std_logic;
+ signal res_n_s : std_logic;
+
+ signal rx_s : std_logic_vector(47 downto 0);
+
+ signal set_spi_mode_s,
+ spi_mode_q : boolean;
+ signal set_idle_mode_s,
+ poll_idle_mode_s : boolean;
+ signal idle_mode_q : natural;
+
+ signal block_len_q,
+ block_len_s : unsigned(31 downto 0);
+ signal set_block_len_s : boolean;
+
+ signal new_read_addr_s,
+ read_addr_q : unsigned(31 downto 0);
+ signal set_read_addr_s,
+ inc_read_addr_s : boolean;
+
+ signal cmd_spi_data_s,
+ read_spi_data_s : std_logic;
+ signal start_read_s : boolean;
+ signal reading_s : boolean;
+
+ procedure rise_clk is
+ begin
+ wait until spi_clk_i'event and to_X01(spi_clk_i) = '1';
+ end rise_clk;
+
+-- procedure rise_clk(num : natural) is
+-- begin
+-- for i in 1 to num loop
+-- rise_clk;
+-- end loop;
+-- end rise_clk;
+
+ procedure fall_clk is
+ begin
+ wait until spi_clk_i'event and to_X01(spi_clk_i) = '0';
+ end fall_clk;
+
+ procedure fall_clk(num : natural) is
+ begin
+ for i in 1 to num loop
+ fall_clk;
+ end loop;
+ end fall_clk;
+
+begin
+
+ res_n_s <= power_on_n_s and soft_res_n_s;
+
+ -----------------------------------------------------------------------------
+ -- Power on reset
+ -----------------------------------------------------------------------------
+ por: process
+ begin
+ power_on_n_s <= '0';
+ wait for 200 ns;
+ power_on_n_s <= '1';
+ wait;
+ end process por;
+
+
+ -----------------------------------------------------------------------------
+ --
+ ctrl: process
+
+ function check_crc(payload : in std_logic_vector(47 downto 0))
+ return boolean is
+
+ begin
+
+ return calc_crc(payload(47 downto 8)) = payload(7 downto 1);
+ end check_crc;
+
+ variable rx_v : std_logic_vector(47 downto 0);
+ variable cmd_v : std_logic_vector( 5 downto 0);
+ variable arg_v : std_logic_vector(31 downto 0);
+ variable crc_v : std_logic_vector( 6 downto 0);
+ variable wrong_v : std_logic;
+ variable read_data_v : boolean;
+
+ begin
+ rx_s <= (others => '0');
+ set_spi_mode_s <= false;
+ set_idle_mode_s <= false;
+ poll_idle_mode_s <= false;
+ cmd_spi_data_s <= '1';
+ soft_res_n_s <= '1';
+ set_block_len_s <= false;
+ block_len_s <= (others => '0');
+ new_read_addr_s <= (others => '0');
+ set_read_addr_s <= false;
+ start_read_s <= false;
+ read_data_v := false;
+
+ loop
+
+ rise_clk;
+ -- wait for startbit of command
+ while to_X01(spi_data_i) = '1' loop
+ rise_clk;
+ end loop;
+ rx_v(47) := '0';
+
+ -- read remaining 47 bits of command
+ for i in 46 downto 0 loop
+ rise_clk;
+ rx_v(i) := to_X01(spi_data_i);
+ end loop;
+ rx_s <= rx_v;
+
+ -- dissect received data
+ cmd_v := rx_v(45 downto 40);
+ arg_v := rx_v(39 downto 8);
+ crc_v := rx_v( 7 downto 1);
+
+ assert spi_mode_q or check_crc(payload => rx_v)
+ report "CRC mismatch"
+ severity error;
+
+ wrong_v := '0';
+ case cmd_v is
+ -- CMD0: GO_IDLE_STATE ------------------------------------------------
+ when "000000" =>
+ set_spi_mode_s <= true;
+ set_idle_mode_s <= true;
+ -- CMD1: SEND_OP_COND -------------------------------------------------
+ when "000001" =>
+ poll_idle_mode_s <= true;
+ -- CMD12: STOP_TRANSMISSION -------------------------------------------
+ when "001100" =>
+ start_read_s <= false;
+ read_data_v := false;
+ -- CMD16: SET_BLOCKLEN ------------------------------------------------
+ when "010000" =>
+ block_len_s <= unsigned(arg_v);
+ set_block_len_s <= true;
+ -- CMD18: READ_MULTIPLE_BLOCK -----------------------------------------
+ when "010010" =>
+ new_read_addr_s <= unsigned(arg_v);
+ set_read_addr_s <= true;
+ read_data_v := true;
+ -- CMD55: APPL_CMD ----------------------------------------------------
+ when "110111" =>
+ -- command only available for SD card
+ if is_sd_card_g /= 1 then
+ wrong_v := '1';
+ end if;
+ -- ACMD41: SEND_OP_COND -----------------------------------------------
+ when "101001" =>
+ -- command only available for SD card
+ if is_sd_card_g /= 1 then
+ wrong_v := '1';
+ else
+ poll_idle_mode_s <= true;
+ end if;
+
+ when others =>
+ wrong_v := '1';
+ null;
+ end case;
+
+
+ -- spend some time before removing control signals
+ fall_clk(2);
+ poll_idle_mode_s <= false;
+ set_idle_mode_s <= false;
+ fall_clk(6);
+ set_spi_mode_s <= false;
+ set_block_len_s <= false;
+ set_read_addr_s <= false;
+
+ if reading_s then
+ wait until not reading_s;
+ end if;
+
+
+ -- wait for a total two "bytes" before sending out response
+ for i in 1 to 8 loop
+ fall_clk;
+ end loop;
+
+ for i in 7 downto 0 loop
+ fall_clk;
+ case i is
+ when 2 =>
+ cmd_spi_data_s <= wrong_v;
+ when 0 =>
+ if idle_mode_q = 0 then
+ cmd_spi_data_s <= '0';
+ else
+ cmd_spi_data_s <= '1';
+ end if;
+ when others =>
+ cmd_spi_data_s <= '0';
+ end case;
+ end loop;
+ fall_clk;
+ cmd_spi_data_s <= '1';
+
+ -- transmit data if requested
+ start_read_s <= read_data_v;
+
+ end loop;
+ end process ctrl;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ --
+ seq: process (res_n_s,
+ spi_clk_i,
+ set_spi_mode_s,
+ set_idle_mode_s,
+ poll_idle_mode_s,
+ set_block_len_s,
+ block_len_s)
+
+ begin
+ if res_n_s = '0' then
+ spi_mode_q <= false;
+ idle_mode_q <= 5;
+ block_len_q <= (others => '0');
+ read_addr_q <= (others => '0');
+
+ elsif spi_clk_i'event and spi_clk_i = '1' then
+ if set_spi_mode_s then
+ spi_mode_q <= true;
+ end if;
+
+ if set_idle_mode_s then
+ idle_mode_q <= 5;
+ elsif poll_idle_mode_s then
+ if idle_mode_q > 0 then
+ idle_mode_q <= idle_mode_q - 1;
+ end if;
+ end if;
+
+ if set_block_len_s then
+ block_len_q <= block_len_s;
+ end if;
+
+ if set_read_addr_s then
+ read_addr_q <= new_read_addr_s;
+ elsif inc_read_addr_s then
+ read_addr_q <= read_addr_q + 1;
+ end if;
+
+ end if;
+ end process seq;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ --
+ read_block: process
+
+ variable t_v : unsigned(7 downto 0);
+
+ begin
+ -- default assignments
+ inc_read_addr_s <= false;
+ reading_s <= false;
+ read_spi_data_s <= '1';
+
+ loop
+ if not start_read_s then
+ wait until start_read_s;
+ end if;
+
+ reading_s <= true;
+
+ fall_clk(8); -- delay for one "byte"
+
+ -- send data token
+ fall_clk(7); -- 7 ones in a data token
+ read_spi_data_s <= '0';
+
+ -- send payload
+ payload: for i in 0 to to_integer(block_len_q)-1 loop
+ t_v := read_addr_q(0) & calc_crc(read_addr_q);
+ for bit in 7 downto 0 loop
+ fall_clk;
+ read_spi_data_s <= t_v(bit);
+
+ exit payload when not start_read_s;
+ end loop;
+ inc_read_addr_s <= true;
+ rise_clk;
+ inc_read_addr_s <= false;
+ wait for 10 ns;
+ end loop;
+
+ if start_read_s then
+ -- send crc
+ for i in 0 to 15 loop
+ fall_clk;
+ t_v := to_unsigned(i, 8);
+ read_spi_data_s <= t_v(0);
+ end loop;
+ fall_clk;
+ end if;
+
+ read_spi_data_s <= '1';
+ reading_s <= false;
+ -- loop for one "byte"
+ fall_clk(8);
+
+ end loop;
+ end process read_block;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ --
+ clk_check: process (spi_clk_i)
+
+ variable last_rising_v : time := 0 ns;
+ variable dump_line : line;
+
+ begin
+ if spi_clk_i'event and spi_clk_i = '1' then
+ if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and
+ idle_mode_q > 0 then
+ if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then
+ write(dump_line, card_type_g);
+ write(dump_line, string'(" @ "));
+ write(dump_line, now);
+ write(dump_line, string'(": Last rising edge of SPI clock "));
+ write(dump_line, now - last_rising_v);
+ write(dump_line, string'(" ago."));
+ writeline(output, dump_line);
+ end if;
+
+ last_rising_v := now;
+ end if;
+ end if;
+ end process clk_check;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output Mapping
+ -----------------------------------------------------------------------------
+ spi_data_o <= cmd_spi_data_s and read_spi_data_s
+ when spi_cs_n_i = '0' else
+ 'Z';
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.1 2005/02/08 21:09:20 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/bench/vhdl/tb_elem-mmc-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb_elem-mmc-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb_elem-mmc-c.vhd (revision 71)
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-mmc-c.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_mmc of tb_elem is
+
+ for behav
+
+ for dut_b : chip
+ use configuration work.chip_mmc_c0;
+ end for;
+
+ for card_b : card
+ use configuration work.card_behav_c0;
+ end for;
+
+ end for;
+
+end tb_elem_behav_mmc;
Index: tags/rel_3_1_rev_C/bench/vhdl/tb-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb-c.vhd (revision 71)
@@ -0,0 +1,31 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb-c.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_behav_c0 of tb is
+
+ for behav
+
+ for tb_elem_full_b : tb_elem
+ use configuration work.tb_elem_behav_full;
+ end for;
+
+ for tb_elem_mmc_b : tb_elem
+ use configuration work.tb_elem_behav_mmc;
+ end for;
+
+ for tb_elem_sd_b : tb_elem
+ use configuration work.tb_elem_behav_sd;
+ end for;
+
+ for tb_elem_minimal_b : tb_elem
+ use configuration work.tb_elem_behav_minimal;
+ end for;
+
+ end for;
+
+end tb_behav_c0;
Index: tags/rel_3_1_rev_C/bench/vhdl/tb.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb.vhd (revision 71)
@@ -0,0 +1,198 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Testbench
+--
+-- $Id: tb.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+entity tb is
+
+end tb;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb is
+
+ component tb_elem
+ generic (
+ chip_type_g : string := "none";
+ has_sd_card_g : integer := 1
+ );
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ eos_o : out boolean
+ );
+ end component;
+
+ constant period_c : time := 100 ns;
+ constant reset_level_c : integer := 0;
+
+ signal clk_s : std_logic;
+ signal reset_s : std_logic;
+
+ signal eos_full_s,
+ eos_mmc_s,
+ eos_sd_s,
+ eos_minimal_s : boolean;
+
+begin
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench element including full featured chip
+ -----------------------------------------------------------------------------
+ tb_elem_full_b : tb_elem
+ generic map (
+ chip_type_g => "Full Chip",
+ has_sd_card_g => 1
+ )
+ port map (
+ clk_i => clk_s,
+ reset_i => reset_s,
+ eos_o => eos_full_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench element including MMC chip
+ -----------------------------------------------------------------------------
+ tb_elem_mmc_b : tb_elem
+ generic map (
+ chip_type_g => "MMC Chip",
+ has_sd_card_g => 0
+ )
+ port map (
+ clk_i => clk_s,
+ reset_i => reset_s,
+ eos_o => eos_mmc_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench element including SD chip
+ -----------------------------------------------------------------------------
+ tb_elem_sd_b : tb_elem
+ generic map (
+ chip_type_g => "SD Chip",
+ has_sd_card_g => 1
+ )
+ port map (
+ clk_i => clk_s,
+ reset_i => reset_s,
+ eos_o => eos_sd_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench element including cip with minimal features
+ -----------------------------------------------------------------------------
+ tb_elem_minimal_b : tb_elem
+ generic map (
+ chip_type_g => "Minimal Chip",
+ has_sd_card_g => 0
+ )
+ port map (
+ clk_i => clk_s,
+ reset_i => reset_s,
+ eos_o => eos_minimal_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Clock Generator
+ -----------------------------------------------------------------------------
+ clk: process
+ begin
+ clk_s <= '0';
+ wait for period_c / 2;
+ clk_s <= '1';
+ wait for period_c / 2;
+ end process clk;
+
+
+ -----------------------------------------------------------------------------
+ -- Reset Generator
+ -----------------------------------------------------------------------------
+ reset: process
+ begin
+ if reset_level_c = 0 then
+ reset_s <= '0';
+ else
+ reset_s <= '1';
+ end if;
+
+ wait for period_c * 4 + 10 ns;
+
+ reset_s <= not reset_s;
+
+ wait;
+ end process reset;
+
+
+ -----------------------------------------------------------------------------
+ -- End Of Simulation Detection
+ -----------------------------------------------------------------------------
+ eos: process (eos_full_s,
+ eos_mmc_s,
+ eos_sd_s,
+ eos_minimal_s)
+ begin
+
+ if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then
+ assert false
+ report "End of Simulation."
+ severity failure;
+ end if;
+
+ end process eos;
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/bench/vhdl/tb_elem-full-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb_elem-full-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb_elem-full-c.vhd (revision 71)
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-full-c.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_full of tb_elem is
+
+ for behav
+
+ for dut_b : chip
+ use configuration work.chip_full_c0;
+ end for;
+
+ for card_b : card
+ use configuration work.card_behav_c0;
+ end for;
+
+ end for;
+
+end tb_elem_behav_full;
Index: tags/rel_3_1_rev_C/bench/vhdl/card-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/card-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/card-c.vhd (revision 71)
@@ -0,0 +1,14 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: card-c.vhd,v 1.1 2005-02-08 21:09:18 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration card_behav_c0 of card is
+
+ for behav
+ end for;
+
+end card_behav_c0;
Index: tags/rel_3_1_rev_C/bench/vhdl/tb_elem-minimal-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb_elem-minimal-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb_elem-minimal-c.vhd (revision 71)
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-minimal-c.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_minimal of tb_elem is
+
+ for behav
+
+ for dut_b : chip
+ use configuration work.chip_minimal_c0;
+ end for;
+
+ for card_b : card
+ use configuration work.card_behav_c0;
+ end for;
+
+ end for;
+
+end tb_elem_behav_minimal;
Index: tags/rel_3_1_rev_C/bench/vhdl/tb_elem-sd-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/bench/vhdl/tb_elem-sd-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/bench/vhdl/tb_elem-sd-c.vhd (revision 71)
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-sd-c.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_sd of tb_elem is
+
+ for behav
+
+ for dut_b : chip
+ use configuration work.chip_sd_c0;
+ end for;
+
+ for card_b : card
+ use configuration work.card_behav_c0;
+ end for;
+
+ end for;
+
+end tb_elem_behav_sd;
Index: tags/rel_3_1_rev_C/rtl/vhdl/sample/ram_loader-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/sample/ram_loader-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/sample/ram_loader-c.vhd (revision 71)
@@ -0,0 +1,10 @@
+-------------------------------------------------------------------------------
+-- $Id: ram_loader-c.vhd,v 1.1 2005-04-10 18:02:32 arniml Exp $
+-------------------------------------------------------------------------------
+
+configuration ram_loader_rtl_c0 of ram_loader is
+
+ for rtl
+ end for;
+
+end ram_loader_rtl_c0;
Index: tags/rel_3_1_rev_C/rtl/vhdl/sample/ram_loader.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/sample/ram_loader.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/sample/ram_loader.vhd (revision 71)
@@ -0,0 +1,355 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Sample client for loading an image to asynchronous SRAM
+--
+-- $Id: ram_loader.vhd,v 1.2 2005-04-10 17:17:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity ram_loader is
+
+ port (
+ -- Global Interface -------------------------------------------------------
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ lamp_o : out std_logic;
+ -- Config Interface -------------------------------------------------------
+ cfg_clk_i : in std_logic;
+ cfg_data_i : in std_logic;
+ start_o : out std_logic;
+ mode_o : out std_logic;
+ done_o : out std_logic;
+ detached_i : in std_logic;
+ -- Asynchronous RAM Interface ---------------------------------------------
+ ram_addr_o : out std_logic_vector(15 downto 0);
+ ram_data_b : out std_logic_vector( 7 downto 0);
+ ram_ce_no : out std_logic_vector( 3 downto 0);
+ ram_oe_no : out std_logic;
+ ram_we_no : out std_logic
+ );
+
+end ram_loader;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of ram_loader is
+
+ signal addr_q : unsigned(17 downto 0);
+ signal inc_addr_s : boolean;
+
+ signal shift_dat_q : std_logic_vector(7 downto 0);
+ signal ser_dat_q : std_logic_vector(7 downto 0);
+ signal bit_q : unsigned(2 downto 0);
+ signal bit_ovfl_q : boolean;
+
+ type fsm_t is (IDLE,
+ WE_ON,
+ WE_OFF,
+ INC_ADDR1, INC_ADDR2,
+ FINISHED);
+ signal fsm_s,
+ fsm_q : fsm_t;
+ signal done_q : std_logic;
+ signal done_s : boolean;
+ signal mode_q,
+ mode_s : std_logic;
+
+ signal ram_we_n_q,
+ ram_we_n_s : std_logic;
+ signal ram_ce_n_q,
+ ram_ce_n_s : std_logic_vector(3 downto 0);
+
+ type start_fsm_t is (WAIT_DETACH,
+ CHECK_NO_DONE,
+ WAIT_DONE);
+ signal start_fsm_s,
+ start_fsm_q : start_fsm_t;
+
+ signal start_s,
+ start_q : std_logic;
+ signal enable_s,
+ enable_q : boolean;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process seq
+ --
+ -- Purpose:
+ -- Implements the sequential elements clocked with cfg_clk_i.
+ --
+ seq: process (cfg_clk_i, reset_i)
+ begin
+ if reset_i = '0' then
+ addr_q <= (others => '0');
+ shift_dat_q <= (others => '0');
+ ser_dat_q <= (others => '0');
+ bit_q <= (others => '0');
+ bit_ovfl_q <= false;
+ fsm_q <= IDLE;
+ ram_we_n_q <= '1';
+ ram_ce_n_q <= (others => '1');
+ done_q <= '0';
+ mode_q <= '0';
+
+ elsif cfg_clk_i'event and cfg_clk_i = '1' then
+ if inc_addr_s then
+ addr_q <= addr_q + 1;
+ end if;
+
+ if enable_q then
+ bit_q <= bit_q + 1;
+ bit_ovfl_q <= bit_q = 7;
+
+ shift_dat_q(0) <= cfg_data_i;
+ shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0);
+ end if;
+
+ -- update register when 8 serial bits have been shifted in
+ if bit_ovfl_q then
+ ser_dat_q <= shift_dat_q;
+ end if;
+
+ fsm_q <= fsm_s;
+
+ ram_we_n_q <= ram_we_n_s;
+ ram_ce_n_q <= ram_ce_n_s;
+
+ -- done only settable once
+ if done_s then
+ done_q <= '1';
+ end if;
+
+ mode_q <= mode_s;
+
+ end if;
+ end process seq;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process fsm
+ --
+ -- Purpose:
+ -- Implements the combinational logic of the RAM loader FSM.
+ --
+ fsm: process (fsm_q,
+ bit_ovfl_q,
+ start_q,
+ addr_q)
+ begin
+ -- default assignments
+ inc_addr_s <= false;
+ ram_we_n_s <= '1';
+ done_s <= false;
+ fsm_s <= IDLE;
+ lamp_o <= '1';
+ mode_s <= '0';
+
+ case fsm_q is
+ when IDLE =>
+ lamp_o <= '0';
+ if start_q = '1' then
+ if bit_ovfl_q then
+ fsm_s <= WE_ON;
+ end if;
+ end if;
+
+ when WE_ON =>
+ ram_we_n_s <= '0';
+ fsm_s <= WE_OFF;
+
+ when WE_OFF =>
+ fsm_s <= INC_ADDR1;
+
+ when INC_ADDR1 =>
+ fsm_s <= INC_ADDR2;
+
+ when INC_ADDR2 =>
+ if addr_q = "001111111111111111" then -- load only 64k
+ fsm_s <= FINISHED;
+ done_s <= true;
+ mode_s <= '1';
+ else
+ inc_addr_s <= true;
+ fsm_s <= IDLE;
+ end if;
+
+ when FINISHED =>
+ fsm_s <= FINISHED;
+ lamp_o <= '1';
+ mode_s <= '1';
+
+ when others =>
+ end case;
+
+ end process fsm;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process ce_gen
+ --
+ -- Purpose:
+ -- Generates the four CE signals for the external RAM chips.
+ --
+ ce_gen: process (addr_q)
+ begin
+ ram_ce_n_s <= (others => '1');
+ ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0';
+ end process ce_gen;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process start_seq
+ --
+ -- Purpose:
+ -- Implements the sequential elements clocked with clk_i.
+ --
+ start_seq: process (clk_i, reset_i)
+ begin
+ if reset_i = '0' then
+ start_fsm_q <= WAIT_DETACH;
+ start_q <= '0';
+ enable_q <= false;
+
+ elsif clk_i'event and clk_i = '1' then
+ start_fsm_q <= start_fsm_s;
+
+ enable_q <= enable_s;
+
+ start_q <= start_s;
+
+ end if;
+ end process start_seq;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process start_comb
+ --
+ -- Purpose:
+ -- Implements the combinational logic of the start FSM.
+ --
+ start_comb: process (start_fsm_q,
+ detached_i,
+ done_q,
+ enable_q,
+ start_q)
+ begin
+ -- default assignments
+ start_fsm_s <= WAIT_DETACH;
+ enable_s <= enable_q;
+ start_s <= start_q;
+
+ case start_fsm_q is
+ -- Wait for detached_i to become '1'
+ -- This state is entered/left twice:
+ -- 1. after reset to start the data download
+ -- 2. after data download to start the next configuration cycle
+ when WAIT_DETACH =>
+ if detached_i = '1' then
+ start_fsm_s <= CHECK_NO_DONE;
+ enable_s <= true;
+ start_s <= '1';
+
+ else
+ start_fsm_s <= WAIT_DETACH;
+ end if;
+
+ -- Wait until done_q is '0'
+ -- This ensures that the FSM stalls when it has started the configuration
+ -- download. There must be no further action in this case.
+ when CHECK_NO_DONE =>
+ if done_q = '0' then
+ start_fsm_s <= WAIT_DONE;
+ else
+ start_fsm_s <= CHECK_NO_DONE;
+ end if;
+
+ -- Wait until done_q is '1'
+ -- done_q is the signal that the main FSM has finished its work. We
+ -- need to start the configuration download.
+ when WAIT_DONE =>
+ if done_q = '1' then
+ start_fsm_s <= WAIT_DETACH;
+ enable_s <= false;
+ start_s <= '0';
+ else
+ start_fsm_s <= WAIT_DONE;
+ end if;
+
+ when others =>
+ null;
+
+ end case;
+
+ end process start_comb;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output Mapping
+ -----------------------------------------------------------------------------
+ start_o <= start_q;
+ mode_o <= mode_q;
+ done_o <= done_q
+ when start_q = '1' else
+ '1';
+ ram_addr_o <= std_logic_vector(addr_q(15 downto 0));
+ ram_data_b <= ser_dat_q;
+ ram_oe_no <= '1';
+ ram_ce_no <= ram_ce_n_q;
+ ram_we_no <= ram_we_n_q;
+
+end rtl;
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-full-a.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-full-a.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-full-a.vhd (revision 71)
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with full feature set
+--
+-- $Id: chip-full-a.vhd,v 1.6 2005-04-07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture full of chip is
+
+ component spi_boot
+ generic (
+ width_set_sel_g : integer := 4;
+ width_bit_cnt_g : integer := 6;
+ width_img_cnt_g : integer := 2;
+ num_bits_per_img_g : integer := 18;
+ sd_init_g : integer := 0;
+ mmc_compat_clk_div_g : integer := 0;
+ width_mmc_clk_div_g : integer := 0;
+ reset_level_g : integer := 0
+ );
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
+ spi_clk_o : out std_logic;
+ spi_cs_n_o : out std_logic;
+ spi_data_in_i : in std_logic;
+ spi_data_out_o : out std_logic;
+ spi_en_outs_o : out std_logic;
+ start_i : in std_logic;
+ mode_i : in std_logic;
+ config_n_o : out std_logic;
+ detached_o : out std_logic;
+ cfg_init_n_i : in std_logic;
+ cfg_done_i : in std_logic;
+ dat_done_i : in std_logic;
+ cfg_clk_o : out std_logic;
+ cfg_dat_o : out std_logic
+ );
+ end component;
+
+ signal spi_clk_s : std_logic;
+ signal spi_cs_n_s : std_logic;
+ signal spi_data_out_s : std_logic;
+ signal spi_en_outs_s : std_logic;
+
+ signal set_sel_s : std_logic_vector(3 downto 0);
+
+begin
+
+ set_sel_s <= not set_sel_n_i;
+
+ spi_boot_b : spi_boot
+ generic map (
+ width_set_sel_g => 4, -- 16 sets
+ width_bit_cnt_g => 12, -- 512 bytes per block
+ width_img_cnt_g => 2, -- 4 images
+ num_bits_per_img_g => 18, -- 256 kByte per image
+ sd_init_g => 1, -- use SD specific initialization
+ mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2)
+ width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider
+ )
+ port map (
+ clk_i => clk_i,
+ reset_i => reset_i,
+ set_sel_i => set_sel_s,
+ spi_clk_o => spi_clk_s,
+ spi_cs_n_o => spi_cs_n_s,
+ spi_data_in_i => spi_data_in_i,
+ spi_data_out_o => spi_data_out_s,
+ spi_en_outs_o => spi_en_outs_s,
+ start_i => start_i,
+ mode_i => mode_i,
+ config_n_o => config_n_o,
+ detached_o => detached_o,
+ cfg_init_n_i => cfg_init_n_i,
+ cfg_done_i => cfg_done_i,
+ dat_done_i => dat_done_i,
+ cfg_clk_o => cfg_clk_o,
+ cfg_dat_o => cfg_dat_o
+ );
+
+ -----------------------------------------------------------------------------
+ -- Three state drivers for SPI outputs.
+ -----------------------------------------------------------------------------
+ spi_clk_o <= spi_clk_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+ spi_cs_n_o <= spi_cs_n_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+ spi_data_out_o <= spi_data_out_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+
+end full;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.5 2005/03/09 19:48:34 arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4 2005/03/08 22:07:12 arniml
+-- added set selection
+--
+-- Revision 1.3 2005/02/18 06:42:11 arniml
+-- clarify wording for images
+--
+-- Revision 1.2 2005/02/16 18:54:37 arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1 2005/02/08 20:41:31 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-e.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-e.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-e.vhd (revision 71)
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel
+--
+-- $Id: chip-e.vhd,v 1.3 2005-04-07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity chip is
+
+ port (
+ -- System Interface -------------------------------------------------------
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ set_sel_n_i : in std_logic_vector(3 downto 0);
+ -- SD Card Interface ------------------------------------------------------
+ spi_clk_o : out std_logic;
+ spi_cs_n_o : out std_logic;
+ spi_data_in_i : in std_logic;
+ spi_data_out_o : out std_logic;
+ -- FPGA Configuration Interface -------------------------------------------
+ start_i : in std_logic;
+ mode_i : in std_logic;
+ config_n_o : out std_logic;
+ detached_o : out std_logic;
+ cfg_init_n_i : in std_logic;
+ cfg_done_i : in std_logic;
+ dat_done_i : in std_logic;
+ cfg_clk_o : out std_logic;
+ cfg_dat_o : out std_logic
+ );
+
+end chip;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.2 2005/03/08 22:07:11 arniml
+-- added set selection
+--
+-- Revision 1.1 2005/02/08 20:41:30 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-minimal-a.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-minimal-a.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-minimal-a.vhd (revision 71)
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with minimal feature set
+--
+-- $Id: chip-minimal-a.vhd,v 1.6 2005-04-07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture minimal of chip is
+
+ component spi_boot
+ generic (
+ width_set_sel_g : integer := 4;
+ width_bit_cnt_g : integer := 6;
+ width_img_cnt_g : integer := 2;
+ num_bits_per_img_g : integer := 18;
+ sd_init_g : integer := 0;
+ mmc_compat_clk_div_g : integer := 0;
+ width_mmc_clk_div_g : integer := 0;
+ reset_level_g : integer := 0
+ );
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
+ spi_clk_o : out std_logic;
+ spi_cs_n_o : out std_logic;
+ spi_data_in_i : in std_logic;
+ spi_data_out_o : out std_logic;
+ spi_en_outs_o : out std_logic;
+ start_i : in std_logic;
+ mode_i : in std_logic;
+ config_n_o : out std_logic;
+ detached_o : out std_logic;
+ cfg_init_n_i : in std_logic;
+ cfg_done_i : in std_logic;
+ dat_done_i : in std_logic;
+ cfg_clk_o : out std_logic;
+ cfg_dat_o : out std_logic
+ );
+ end component;
+
+ signal spi_clk_s : std_logic;
+ signal spi_cs_n_s : std_logic;
+ signal spi_data_out_s : std_logic;
+ signal spi_en_outs_s : std_logic;
+
+ signal set_sel_s : std_logic_vector(3 downto 0);
+
+begin
+
+ set_sel_s <= not set_sel_n_i;
+
+ spi_boot_b : spi_boot
+ generic map (
+ width_set_sel_g => 4, -- 16 sets
+ width_bit_cnt_g => 6, -- 8 bytes per block
+ width_img_cnt_g => 2, -- 4 images
+ num_bits_per_img_g => 18, -- 256 kByte per image
+ sd_init_g => 0, -- no SD specific initialization
+ mmc_compat_clk_div_g => 0, -- no MMC compatibility
+ width_mmc_clk_div_g => 0 -- no MMC compatibility
+ )
+ port map (
+ clk_i => clk_i,
+ reset_i => reset_i,
+ set_sel_i => set_sel_s,
+ spi_clk_o => spi_clk_s,
+ spi_cs_n_o => spi_cs_n_s,
+ spi_data_in_i => spi_data_in_i,
+ spi_data_out_o => spi_data_out_s,
+ spi_en_outs_o => spi_en_outs_s,
+ start_i => start_i,
+ mode_i => mode_i,
+ config_n_o => config_n_o,
+ detached_o => detached_o,
+ cfg_init_n_i => cfg_init_n_i,
+ cfg_done_i => cfg_done_i,
+ dat_done_i => dat_done_i,
+ cfg_clk_o => cfg_clk_o,
+ cfg_dat_o => cfg_dat_o
+ );
+
+ -----------------------------------------------------------------------------
+ -- Three state drivers for SPI outputs.
+ -----------------------------------------------------------------------------
+ spi_clk_o <= spi_clk_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+ spi_cs_n_o <= spi_cs_n_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+ spi_data_out_o <= spi_data_out_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+
+end minimal;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.5 2005/03/09 19:48:34 arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4 2005/03/08 22:07:12 arniml
+-- added set selection
+--
+-- Revision 1.3 2005/02/18 06:42:12 arniml
+-- clarify wording for images
+--
+-- Revision 1.2 2005/02/16 18:54:39 arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1 2005/02/08 20:41:31 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-sd-a.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-sd-a.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-sd-a.vhd (revision 71)
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with SD feature set
+--
+-- $Id: chip-sd-a.vhd,v 1.6 2005-04-07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture sd of chip is
+
+ component spi_boot
+ generic (
+ width_set_sel_g : integer := 4;
+ width_bit_cnt_g : integer := 6;
+ width_img_cnt_g : integer := 2;
+ num_bits_per_img_g : integer := 18;
+ sd_init_g : integer := 0;
+ mmc_compat_clk_div_g : integer := 0;
+ width_mmc_clk_div_g : integer := 0;
+ reset_level_g : integer := 0
+ );
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
+ spi_clk_o : out std_logic;
+ spi_cs_n_o : out std_logic;
+ spi_data_in_i : in std_logic;
+ spi_data_out_o : out std_logic;
+ spi_en_outs_o : out std_logic;
+ start_i : in std_logic;
+ mode_i : in std_logic;
+ config_n_o : out std_logic;
+ detached_o : out std_logic;
+ cfg_init_n_i : in std_logic;
+ cfg_done_i : in std_logic;
+ dat_done_i : in std_logic;
+ cfg_clk_o : out std_logic;
+ cfg_dat_o : out std_logic
+ );
+ end component;
+
+ signal spi_clk_s : std_logic;
+ signal spi_cs_n_s : std_logic;
+ signal spi_data_out_s : std_logic;
+ signal spi_en_outs_s : std_logic;
+
+ signal set_sel_s : std_logic_vector(3 downto 0);
+
+begin
+
+ set_sel_s <= not set_sel_n_i;
+
+ spi_boot_b : spi_boot
+ generic map (
+ width_set_sel_g => 4, -- 16 sets
+ width_bit_cnt_g => 12, -- 512 bytes per block
+ width_img_cnt_g => 2, -- 4 images
+ num_bits_per_img_g => 18, -- 256 kByte per image
+ sd_init_g => 1, -- SD specific initialization
+ mmc_compat_clk_div_g => 0, -- no MMC compatibility
+ width_mmc_clk_div_g => 0 -- no MMC compatibility
+ )
+ port map (
+ clk_i => clk_i,
+ reset_i => reset_i,
+ set_sel_i => set_sel_s,
+ spi_clk_o => spi_clk_s,
+ spi_cs_n_o => spi_cs_n_s,
+ spi_data_in_i => spi_data_in_i,
+ spi_data_out_o => spi_data_out_s,
+ spi_en_outs_o => spi_en_outs_s,
+ start_i => start_i,
+ mode_i => mode_i,
+ config_n_o => config_n_o,
+ detached_o => detached_o,
+ cfg_init_n_i => cfg_init_n_i,
+ cfg_done_i => cfg_done_i,
+ dat_done_i => dat_done_i,
+ cfg_clk_o => cfg_clk_o,
+ cfg_dat_o => cfg_dat_o
+ );
+
+ -----------------------------------------------------------------------------
+ -- Three state drivers for SPI outputs.
+ -----------------------------------------------------------------------------
+ spi_clk_o <= spi_clk_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+ spi_cs_n_o <= spi_cs_n_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+ spi_data_out_o <= spi_data_out_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+
+end sd;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.5 2005/03/09 19:48:34 arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4 2005/03/08 22:07:12 arniml
+-- added set selection
+--
+-- Revision 1.3 2005/02/18 06:42:14 arniml
+-- clarify wording for images
+--
+-- Revision 1.2 2005/02/16 18:54:39 arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1 2005/02/08 20:41:32 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-mmc-a.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-mmc-a.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-mmc-a.vhd (revision 71)
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with MMC feature set
+--
+-- $Id: chip-mmc-a.vhd,v 1.6 2005-04-07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture mmc of chip is
+
+ component spi_boot
+ generic (
+ width_set_sel_g : integer := 4;
+ width_bit_cnt_g : integer := 6;
+ width_img_cnt_g : integer := 2;
+ num_bits_per_img_g : integer := 18;
+ sd_init_g : integer := 0;
+ mmc_compat_clk_div_g : integer := 0;
+ width_mmc_clk_div_g : integer := 0;
+ reset_level_g : integer := 0
+ );
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
+ spi_clk_o : out std_logic;
+ spi_cs_n_o : out std_logic;
+ spi_data_in_i : in std_logic;
+ spi_data_out_o : out std_logic;
+ spi_en_outs_o : out std_logic;
+ start_i : in std_logic;
+ mode_i : in std_logic;
+ config_n_o : out std_logic;
+ detached_o : out std_logic;
+ cfg_init_n_i : in std_logic;
+ cfg_done_i : in std_logic;
+ dat_done_i : in std_logic;
+ cfg_clk_o : out std_logic;
+ cfg_dat_o : out std_logic
+ );
+ end component;
+
+ signal spi_clk_s : std_logic;
+ signal spi_cs_n_s : std_logic;
+ signal spi_data_out_s : std_logic;
+ signal spi_en_outs_s : std_logic;
+
+ signal set_sel_s : std_logic_vector(3 downto 0);
+
+begin
+
+ set_sel_s <= not set_sel_n_i;
+
+ spi_boot_b : spi_boot
+ generic map (
+ width_set_sel_g => 4, -- 16 sets
+ width_bit_cnt_g => 12, -- 512 bytes per block
+ width_img_cnt_g => 2, -- 4 images
+ num_bits_per_img_g => 18, -- 256 kByte per image
+ sd_init_g => 0, -- no SD specific initialization
+ mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2)
+ width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider
+ )
+ port map (
+ clk_i => clk_i,
+ reset_i => reset_i,
+ set_sel_i => set_sel_s,
+ spi_clk_o => spi_clk_s,
+ spi_cs_n_o => spi_cs_n_s,
+ spi_data_in_i => spi_data_in_i,
+ spi_data_out_o => spi_data_out_s,
+ spi_en_outs_o => spi_en_outs_s,
+ start_i => start_i,
+ mode_i => mode_i,
+ config_n_o => config_n_o,
+ detached_o => detached_o,
+ cfg_init_n_i => cfg_init_n_i,
+ cfg_done_i => cfg_done_i,
+ dat_done_i => dat_done_i,
+ cfg_clk_o => cfg_clk_o,
+ cfg_dat_o => cfg_dat_o
+ );
+
+ -----------------------------------------------------------------------------
+ -- Three state drivers for SPI outputs.
+ -----------------------------------------------------------------------------
+ spi_clk_o <= spi_clk_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+ spi_cs_n_o <= spi_cs_n_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+ spi_data_out_o <= spi_data_out_s
+ when spi_en_outs_s = '1' else
+ 'Z';
+
+end mmc;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.5 2005/03/09 19:48:34 arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4 2005/03/08 22:07:12 arniml
+-- added set selection
+--
+-- Revision 1.3 2005/02/18 06:42:13 arniml
+-- clarify wording for images
+--
+-- Revision 1.2 2005/02/16 18:54:39 arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1 2005/02/08 20:41:32 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/rtl/vhdl/spi_boot.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/spi_boot.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/spi_boot.vhd (revision 71)
@@ -0,0 +1,966 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot.vhd,v 1.7 2005-04-07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity spi_boot is
+
+ generic (
+ -- width of set selection
+ width_set_sel_g : integer := 4;
+ -- width of bit counter: minimum 6, maximum 12
+ width_bit_cnt_g : integer := 6;
+ -- width of image counter: minimum 0, maximum n
+ width_img_cnt_g : integer := 2;
+ -- number of bits required to address one image
+ num_bits_per_img_g : integer := 18;
+ -- SD specific initialization
+ sd_init_g : integer := 0;
+ -- clock divider to reach 400 kHz for MMC compatibility
+ mmc_compat_clk_div_g : integer := 0;
+ width_mmc_clk_div_g : integer := 0;
+ -- active level of reset_i
+ reset_level_g : integer := 0
+ );
+
+ port (
+ -- System Interface -------------------------------------------------------
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
+ -- Card Interface ---------------------------------------------------------
+ spi_clk_o : out std_logic;
+ spi_cs_n_o : out std_logic;
+ spi_data_in_i : in std_logic;
+ spi_data_out_o : out std_logic;
+ spi_en_outs_o : out std_logic;
+ -- FPGA Configuration Interface -------------------------------------------
+ start_i : in std_logic;
+ mode_i : in std_logic;
+ config_n_o : out std_logic;
+ detached_o : out std_logic;
+ cfg_init_n_i : in std_logic;
+ cfg_done_i : in std_logic;
+ dat_done_i : in std_logic;
+ cfg_clk_o : out std_logic;
+ cfg_dat_o : out std_logic
+ );
+
+end spi_boot;
+
+
+library ieee;
+use ieee.numeric_std.all;
+use work.spi_boot_pack.all;
+
+architecture rtl of spi_boot is
+
+ component spi_counter
+ generic (
+ cnt_width_g : integer := 4;
+ cnt_max_g : integer := 15;
+ reset_level_g : integer := 0
+ );
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ cnt_en_i : in boolean;
+ cnt_o : out std_logic_vector(cnt_width_g-1 downto 0);
+ cnt_ovfl_o : out boolean
+ );
+ end component;
+
+
+ -----------------------------------------------------------------------------
+ -- States of the controller FSM
+ --
+ type ctrl_states_t is (POWER_UP1, POWER_UP2,
+ CMD0,
+ CMD1,
+ CMD55, ACMD41,
+ CMD16,
+ WAIT_START,
+ WAIT_INIT_LOW, WAIT_INIT_HIGH,
+ CMD18, CMD18_DATA,
+ CMD12,
+ INC_IMG_CNT);
+ --
+ signal ctrl_fsm_q,
+ ctrl_fsm_s : ctrl_states_t;
+ --
+ -----------------------------------------------------------------------------
+
+ -----------------------------------------------------------------------------
+ -- States of the command FSM
+ --
+ type cmd_states_t is (CMD, START, R1, PAUSE);
+ --
+ signal cmd_fsm_q,
+ cmd_fsm_s : cmd_states_t;
+ --
+ -----------------------------------------------------------------------------
+
+ subtype op_r is integer range 5 downto 0;
+ type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7);
+ signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0);
+ signal res_bc_s : res_bc_t;
+ signal upper_bitcnt_zero_s : boolean;
+
+ signal cfg_dat_q : std_logic;
+
+ signal spi_clk_q : std_logic;
+ signal spi_clk_rising_q : boolean;
+ signal spi_clk_falling_q : boolean;
+ signal spi_dat_q,
+ spi_dat_s : std_logic;
+ signal spi_cs_n_q,
+ spi_cs_n_s : std_logic;
+
+ signal cfg_clk_q : std_logic;
+
+ signal start_q : std_logic;
+
+ signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0);
+ signal cnt_en_img_s : boolean;
+ signal mmc_cnt_ovfl_s : boolean;
+ signal mmc_compat_s : boolean;
+
+ signal cmd_finished_s : boolean;
+
+ signal r1_result_q : std_logic;
+ signal done_q,
+ send_cmd12_q : boolean;
+
+ signal en_outs_s,
+ en_outs_q : boolean;
+
+ signal true_s : boolean;
+
+begin
+
+ true_s <= true;
+
+ -----------------------------------------------------------------------------
+ -- Process seq
+ --
+ -- Purpose:
+ -- Implements several sequential elements.
+ --
+ seq: process (clk_i, reset_i)
+
+ variable bit_cnt_v : unsigned(1 downto 0);
+
+ begin
+ if reset_i = reset_level_g then
+ -- reset bit counter to 63 for power up
+ bit_cnt_q <= (others => '0');
+ bit_cnt_q(op_r) <= "111111";
+ spi_dat_q <= '1';
+ spi_cs_n_q <= '1';
+ cfg_dat_q <= '1';
+ start_q <= '0';
+ done_q <= false;
+ send_cmd12_q <= false;
+ ctrl_fsm_q <= POWER_UP1;
+ cmd_fsm_q <= CMD;
+ r1_result_q <= '0';
+ en_outs_q <= true;
+
+ elsif clk_i'event and clk_i = '1' then
+ -- bit counter control
+ if spi_clk_rising_q then
+ case res_bc_s is
+ when NONE =>
+ bit_cnt_q <= bit_cnt_q - 1;
+ when RES_MAX =>
+ bit_cnt_q <= (others => '1');
+ when RES_47 =>
+ bit_cnt_q <= (others => '0');
+ bit_cnt_q(op_r) <= "101111";
+ when RES_15 =>
+ bit_cnt_q <= (others => '0');
+ bit_cnt_q(op_r) <= "001111";
+ when RES_7 =>
+ bit_cnt_q <= (others => '0');
+ bit_cnt_q(op_r) <= "000111";
+ when others =>
+ bit_cnt_q <= (others => '0');
+ end case;
+ end if;
+
+ -- Card data output register
+ -- spi_clk_falling_q acts as enable during MMC clock compatibility mode.
+ -- As soon as this mode is left, the register must start latching.
+ -- There is no explicit relation to spi_clk_q anymore in normal mode.
+ -- Instead, spi_dat_s is operated by bit_cnt_q above which changes its
+ -- value after the rising edge of spi_clk_q.
+ -- -> spi_dat_q changes upon falling edge of spi_clk_q
+ if spi_clk_falling_q or not mmc_compat_s then
+ spi_dat_q <= spi_dat_s;
+ end if;
+
+ -- config data output register
+ -- a new value is loaded when config clock is high,
+ -- i.e. input data is sampled with rising spi_clk
+ -- while output value changes on falling edge of cfg_clk
+ if cfg_clk_q = '1' and spi_clk_rising_q then
+ cfg_dat_q <= spi_data_in_i;
+ end if;
+
+ -- Controller FSM state
+ ctrl_fsm_q <= ctrl_fsm_s;
+
+ -- Command FSM state
+ cmd_fsm_q <= cmd_fsm_s;
+
+ -- CS signal for SPI card
+ if spi_clk_q = '1' then
+ spi_cs_n_q <= spi_cs_n_s;
+ end if;
+
+ -- Extract flags from R1 response
+ if cmd_fsm_q = R1 then
+ bit_cnt_v := bit_cnt_q(1 downto 0);
+ case bit_cnt_v(1 downto 0) is
+ when "10" =>
+ -- always save "Illegal Command" flag
+ r1_result_q <= to_X01(spi_data_in_i);
+ when "00" =>
+ -- overwrite with "Idle State" flag when not in CMD55
+ if ctrl_fsm_q /= CMD55 then
+ r1_result_q <= to_X01(spi_data_in_i);
+ end if;
+ when others =>
+ null;
+ end case;
+ end if;
+
+ -- Start trigger register for rising edge detection
+ -- the reset value is '0' thus a rising edge will always be detected
+ -- after reset even though start_i is tied to '1'
+ if start_i = '0' then
+ start_q <= '0';
+ elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then
+ start_q <= start_i;
+ end if;
+
+ -- Marker for cfg_done and dat_done
+ if ctrl_fsm_q = CMD18_DATA then
+ if cfg_done_i = '1' and dat_done_i = '1' then
+ done_q <= true;
+ end if;
+
+ if done_q and
+ (not upper_bitcnt_zero_s or cmd_fsm_q = START) then
+ -- activate sending of CMD12 when it is safe:
+ -- * upper bits of bit counter are not zero
+ -- -> transmission of CMD12 is not running
+ -- * cmd FSM is in START state
+ -- -> also no transmission running
+ send_cmd12_q <= true;
+ end if;
+ elsif ctrl_fsm_q = WAIT_START then
+ -- reset done_q when WAIT_START has been reached
+ -- this is necessary to let the stop transmission process come to
+ -- an end without interruption or generation of unwanted cfg_clk_q
+ done_q <= false;
+ send_cmd12_q <= false;
+ end if;
+
+ -- output enable
+ if spi_clk_rising_q then
+ en_outs_q <= en_outs_s;
+ end if;
+
+ end if;
+
+ end process seq;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process upper_bits
+ --
+ -- Purpose:
+ -- Detects that the upper bits of the bit counter are zero.
+ -- Upper bits = n downto 6, i.e. the optional part that is not required for
+ -- commands but for extension of data blocks.
+ --
+ upper_bits: process (bit_cnt_q)
+ variable zero_v : boolean;
+ begin
+
+ zero_v := true;
+ for i in bit_cnt_q'high downto 6 loop
+ if bit_cnt_q(i) = '1' then
+ zero_v := false;
+ end if;
+ end loop;
+
+ upper_bitcnt_zero_s <= zero_v;
+
+ end process upper_bits;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process clk_gen
+ --
+ -- Purpose:
+ -- Generates clocks for card and FPGA configuration.
+ -- The card clock is free running with a divide by two of clk_i.
+ -- The clock for FPGA config has an enable and is stopped on high level.
+ -- There is a phase shift of half a period between spi_clk and cfg_clk.
+ --
+ clk_gen: process (clk_i, reset_i)
+ begin
+ if reset_i = reset_level_g then
+ spi_clk_q <= '0';
+ cfg_clk_q <= '1';
+
+ elsif clk_i'event and clk_i = '1' then
+
+ -- spi_clk_q rises according to the flag
+ -- it falls with overflow indication
+ -- the resulting duty cycle is not exactly 50:50,
+ -- high time is a bit longer
+ if mmc_compat_s then
+ -- MMC clock compatibility mode:
+ -- spi_clk_q rises when flagged by spi_clk_rising_q
+ if spi_clk_rising_q then
+ spi_clk_q <= '1';
+ elsif mmc_cnt_ovfl_s then
+ -- upon counter overflow spi_clk_q falls in case it does not rise
+ spi_clk_q <= '0';
+ end if;
+ else
+ -- normal mode
+ -- spi_clk_q follows spi_clk_rising_q
+ if spi_clk_rising_q then
+ spi_clk_q <= '1';
+ else
+ spi_clk_q <= '0';
+ end if;
+ end if;
+
+ -- clock for FPGA config must be enabled and follows spi_clk
+ if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and
+ not done_q then
+ cfg_clk_q <= spi_clk_q;
+ else
+ cfg_clk_q <= '1';
+ end if;
+
+ end if;
+
+ end process clk_gen;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Indication flags for rising and falling spi_clk_q.
+ -- Essential for MMC clock compatibility mode.
+ -----------------------------------------------------------------------------
+ mmc_comap: if mmc_compat_clk_div_g > 0 generate
+ mmc_compat_sig: process (clk_i, reset_i)
+ begin
+ if reset_i = reset_level_g then
+ spi_clk_rising_q <= false;
+ spi_clk_falling_q <= false;
+
+ elsif clk_i'event and clk_i = '1' then
+ if mmc_compat_s then
+ -- MMC clock compatibility mode:
+ -- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q
+ -- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q
+ if mmc_cnt_ovfl_s then
+ spi_clk_rising_q <= spi_clk_q = '0';
+ spi_clk_falling_q <= spi_clk_q = '1';
+ else
+ spi_clk_rising_q <= false;
+ spi_clk_falling_q <= false;
+ end if;
+ else
+ -- normal mode
+ spi_clk_rising_q <= not spi_clk_rising_q;
+ spi_clk_falling_q <= true;
+ end if;
+
+ end if;
+ end process mmc_compat_sig;
+ end generate;
+
+ no_mmc_compat: if mmc_compat_clk_div_g = 0 generate
+ -- SPI clock rising whenever spi_clk_q is '0'
+ spi_clk_rising_q <= spi_clk_q = '0';
+ -- SPI clock falling whenever spi_clk_q is '1'
+ spi_clk_falling_q <= spi_clk_q = '1';
+ end generate;
+
+
+ -----------------------------------------------------------------------------
+ -- Process ctrl_fsm
+ --
+ -- Purpose:
+ -- Implements the controller FSM.
+ --
+ ctrl_fsm: process (ctrl_fsm_q,
+ cmd_finished_s, r1_result_q,
+ start_i, start_q, mode_i,
+ cfg_init_n_i)
+
+ variable mmc_compat_v : boolean;
+
+ begin
+ -- default assignments
+ ctrl_fsm_s <= POWER_UP1;
+ config_n_o <= '1';
+ cnt_en_img_s <= false;
+ spi_cs_n_s <= '0';
+ mmc_compat_v := false;
+ en_outs_s <= true;
+
+ case ctrl_fsm_q is
+ -- Let card finish power up, step 1 -------------------------------------
+ when POWER_UP1 =>
+ mmc_compat_v := true;
+ spi_cs_n_s <= '1';
+ if cmd_finished_s then
+ ctrl_fsm_s <= POWER_UP2;
+ else
+ ctrl_fsm_s <= POWER_UP1;
+ end if;
+
+
+ -- Let card finish power up, step 2 -------------------------------------
+ when POWER_UP2 =>
+ mmc_compat_v := true;
+ if cmd_finished_s then
+ ctrl_fsm_s <= CMD0;
+ else
+ spi_cs_n_s <= '1';
+ ctrl_fsm_s <= POWER_UP2;
+ end if;
+
+
+ -- Issue CMD0: GO_IDLE_STATE --------------------------------------------
+ when CMD0 =>
+ mmc_compat_v := true;
+ if cmd_finished_s then
+ if sd_init_g = 1 then
+ ctrl_fsm_s <= CMD55;
+ else
+ ctrl_fsm_s <= CMD1;
+ end if;
+ else
+ ctrl_fsm_s <= CMD0;
+ end if;
+
+
+ -- Issue CMD55: APP_CMD -------------------------------------------------
+ when CMD55 =>
+ if sd_init_g = 1 then
+
+ mmc_compat_v := true;
+ if cmd_finished_s then
+ if r1_result_q = '0' then
+ -- command accepted, it's an SD card
+ ctrl_fsm_s <= ACMD41;
+ else
+ -- command rejected, it's an MMC card
+ ctrl_fsm_s <= CMD1;
+ end if;
+ else
+ ctrl_fsm_s <= CMD55;
+ end if;
+
+ end if;
+
+
+ -- Issue ACMD41: SEND_OP_COND -------------------------------------------
+ when ACMD41 =>
+ if sd_init_g = 1 then
+
+ mmc_compat_v := true;
+ if cmd_finished_s then
+ if r1_result_q = '0' then
+ ctrl_fsm_s <= CMD16;
+ else
+ ctrl_fsm_s <= CMD55;
+ end if;
+ else
+ ctrl_fsm_s <= ACMD41;
+ end if;
+
+ end if;
+
+
+ -- Issue CMD1: SEND_OP_COND ---------------------------------------------
+ when CMD1 =>
+ mmc_compat_v := true;
+ if cmd_finished_s then
+ if r1_result_q = '0' then
+ ctrl_fsm_s <= CMD16;
+ else
+ ctrl_fsm_s <= CMD1;
+ end if;
+ else
+ ctrl_fsm_s <= CMD1;
+ end if;
+
+
+ -- Issue CMD16: SET_BLOCKLEN --------------------------------------------
+ when CMD16 =>
+ if cmd_finished_s then
+ ctrl_fsm_s <= WAIT_START;
+ else
+ ctrl_fsm_s <= CMD16;
+ end if;
+
+
+ -- Wait for configuration start request ---------------------------------
+ when WAIT_START =>
+ spi_cs_n_s <= '1';
+
+ -- detect rising edge of start_i
+ if start_i = '1' and start_q = '0' then
+ -- decide which mode is requested
+ if cmd_finished_s then
+ if mode_i = '0' then
+ ctrl_fsm_s <= CMD18;
+ else
+ ctrl_fsm_s <= WAIT_INIT_LOW;
+ end if;
+ else
+ en_outs_s <= false;
+ ctrl_fsm_s <= WAIT_START;
+ end if;
+ else
+ en_outs_s <= false;
+ ctrl_fsm_s <= WAIT_START;
+ end if;
+
+
+ -- Wait for INIT to become low ------------------------------------------
+ when WAIT_INIT_LOW =>
+ spi_cs_n_s <= '1';
+ -- activate FPGA configuration
+ config_n_o <= '0';
+
+ if cfg_init_n_i = '0' then
+ ctrl_fsm_s <= WAIT_INIT_HIGH;
+ else
+ ctrl_fsm_s <= WAIT_INIT_LOW;
+ end if;
+
+
+ -- Wait for INIT to become high -----------------------------------------
+ when WAIT_INIT_HIGH =>
+ spi_cs_n_s <= '1';
+
+ if cfg_init_n_i = '1' and cmd_finished_s then
+ ctrl_fsm_s <= CMD18;
+ else
+ ctrl_fsm_s <= WAIT_INIT_HIGH;
+ end if;
+
+
+ -- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------
+ when CMD18 =>
+ if cmd_finished_s then
+ ctrl_fsm_s <= CMD18_DATA;
+ else
+ ctrl_fsm_s <= CMD18;
+ end if;
+ --
+ -- receive a data block
+ when CMD18_DATA =>
+ if cmd_finished_s then
+ ctrl_fsm_s <= CMD12;
+ else
+ ctrl_fsm_s <= CMD18_DATA;
+ end if;
+
+
+ -- Issued CMD12: STOP_TRANSMISSION --------------------------------------
+ when CMD12 =>
+ if cmd_finished_s then
+ ctrl_fsm_s <= INC_IMG_CNT;
+ else
+ ctrl_fsm_s <= CMD12;
+ end if;
+
+
+ -- Increment Image Counter ----------------------------------------------
+ when INC_IMG_CNT =>
+ spi_cs_n_s <= '1';
+ ctrl_fsm_s <= WAIT_START;
+ cnt_en_img_s <= true;
+
+
+
+ when others =>
+ null;
+
+ end case;
+
+ -- mmc_compat_s is suppressed if MMC clock compatibility is not required
+ if mmc_compat_clk_div_g > 0 then
+ mmc_compat_s <= mmc_compat_v;
+ else
+ mmc_compat_s <= false;
+ end if;
+
+ end process ctrl_fsm;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process cmd_fsm
+ --
+ -- Purpose:
+ -- Implements the command FSM.
+ --
+ cmd_fsm: process (spi_clk_rising_q,
+ spi_data_in_i,
+ bit_cnt_q,
+ ctrl_fsm_q,
+ cmd_fsm_q,
+ send_cmd12_q)
+
+ variable cnt_zero_v : boolean;
+ variable spi_data_low_v : boolean;
+ variable no_startbit_v : boolean;
+
+ begin
+ -- default assignments
+ cmd_finished_s <= false;
+ cmd_fsm_s <= CMD;
+ res_bc_s <= NONE;
+
+ cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0;
+ spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0';
+
+ -- these are no real commands thus there will be no startbit
+ case ctrl_fsm_q is
+ when POWER_UP1 | POWER_UP2 |
+ WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW =>
+ no_startbit_v := true;
+ when others =>
+ no_startbit_v := false;
+ end case;
+
+
+ case cmd_fsm_q is
+ -- Send the command -----------------------------------------------------
+ when CMD =>
+ if cnt_zero_v then
+ if ctrl_fsm_q /= CMD18_DATA then
+ -- normal commands including CMD12 require startbit of R1 response
+ cmd_fsm_s <= START;
+ else
+ if not send_cmd12_q then
+ -- CMD18_DATA needs to read CRC
+ cmd_fsm_s <= R1;
+ res_bc_s <= RES_15;
+ else
+ -- CMD18_DATA finished, scan for startbit of response
+ cmd_finished_s <= true;
+ cmd_fsm_s <= START;
+ end if;
+ end if;
+ else
+ cmd_fsm_s <= CMD;
+ end if;
+
+ -- Wait for startbit of response ----------------------------------------
+ when START =>
+ -- startbit detection or skip of this check
+ if no_startbit_v and spi_clk_rising_q then
+ cmd_fsm_s <= R1;
+ res_bc_s <= RES_7;
+ elsif spi_data_low_v then
+ if ctrl_fsm_q /= CMD18_DATA then
+ cmd_fsm_s <= R1;
+ else
+ -- CMD18_DATA startbit detected, read payload
+ cmd_fsm_s <= CMD;
+ res_bc_s <= RES_MAX;
+ end if;
+ else
+ cmd_fsm_s <= START;
+ res_bc_s <= RES_7;
+ end if;
+
+ -- Read R1 response -----------------------------------------------------
+ when R1 =>
+ if cnt_zero_v then
+ res_bc_s <= RES_7;
+
+ if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then
+ cmd_fsm_s <= PAUSE;
+ else
+ -- CMD18 needs another startbit detection for the data token.
+ -- CMD18_DATA needs a startbit after having received the CRC, either
+ -- * next data token
+ -- * R1 response of CMD12
+ cmd_fsm_s <= START;
+
+ if ctrl_fsm_q = CMD18 then
+ -- CMD18 response received -> advance to CMD18_DATA
+ cmd_finished_s <= true;
+ end if;
+ end if;
+ else
+ cmd_fsm_s <= R1;
+ end if;
+
+ -- PAUSE state -> required for Nrc, card response to host command -------
+ when PAUSE =>
+ if cnt_zero_v then
+ cmd_fsm_s <= CMD;
+ res_bc_s <= RES_47;
+ cmd_finished_s <= true;
+ else
+ cmd_fsm_s <= PAUSE;
+ end if;
+
+ when others =>
+ null;
+
+ end case;
+
+ end process cmd_fsm;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process transmit
+ --
+ -- Purpose:
+ -- Generates the serial data output values based on the current FSM state
+ --
+ -- The local variable cmd_v is 64 bits wide in contrast to an SPI command
+ -- with 48 bits. There are two reasons for this:
+ -- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit
+ -- counter will start from 3F on its lowest 6 bits. Therefore, it is
+ -- necessary to provide all 64 positions in cmd_v.
+ -- * Reduces logic.
+ --
+ transmit: process (ctrl_fsm_q,
+ cmd_fsm_q,
+ bit_cnt_q,
+ img_cnt_s,
+ send_cmd12_q,
+ set_sel_i,
+ upper_bitcnt_zero_s)
+
+ subtype cmd_r is natural range 47 downto 0;
+ subtype cmd_t is std_logic_vector(cmd_r);
+ subtype ext_cmd_t is std_logic_vector(63 downto 0);
+ -- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS
+ constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101";
+ constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1";
+ constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1";
+ constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1";
+ constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1";
+ constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1";
+ constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1";
+
+ variable cmd_v : ext_cmd_t;
+ variable tx_v : boolean;
+
+ begin
+ -- default assignments
+ spi_dat_s <= '1';
+ cmd_v := (others => '1');
+ tx_v := false;
+
+ if cmd_fsm_q = CMD then
+ case ctrl_fsm_q is
+ when CMD0 =>
+ cmd_v(cmd_r) := cmd0_c;
+ tx_v := true;
+ when CMD1 =>
+ cmd_v(cmd_r) := cmd1_c;
+ tx_v := true;
+ when CMD16 =>
+ cmd_v(cmd_r) := cmd16_c;
+ cmd_v(8 + width_bit_cnt_g-3) := '1';
+ tx_v := true;
+ when CMD18 =>
+ cmd_v(cmd_r) := cmd18_c;
+ -- insert image counter
+ cmd_v(8 + num_bits_per_img_g + width_img_cnt_g
+ downto 8 + num_bits_per_img_g) := img_cnt_s;
+ -- insert set selection
+ cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1
+ downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i;
+ tx_v := true;
+ when CMD18_DATA =>
+ cmd_v(cmd_r) := cmd12_c;
+
+ if send_cmd12_q and upper_bitcnt_zero_s then
+ tx_v := true;
+ end if;
+ when CMD55 =>
+ cmd_v(cmd_r) := cmd55_c;
+ tx_v := true;
+ when ACMD41 =>
+ cmd_v(cmd_r) := acmd41_c;
+ tx_v := true;
+
+ when others =>
+ null;
+ end case;
+ end if;
+
+ if tx_v then
+ spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0)));
+ end if;
+
+ end process transmit;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Optional Image Counter
+ -----------------------------------------------------------------------------
+ img_cnt: if width_img_cnt_g > 0 generate
+ img_cnt_b : spi_counter
+ generic map (
+ cnt_width_g => width_img_cnt_g,
+ cnt_max_g => 2**width_img_cnt_g - 1,
+ reset_level_g => reset_level_g
+ )
+ port map (
+ clk_i => clk_i,
+ reset_i => reset_i,
+ cnt_en_i => cnt_en_img_s,
+ cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0),
+ cnt_ovfl_o => open
+ );
+ img_cnt_s(width_img_cnt_g) <= '0';
+ end generate;
+
+ no_img_cnt: if width_img_cnt_g = 0 generate
+ img_cnt_s <= (others => '0');
+ end generate;
+
+
+ -----------------------------------------------------------------------------
+ -- Optional MMC compatibility counter
+ -----------------------------------------------------------------------------
+ mmc_cnt: if mmc_compat_clk_div_g > 0 generate
+ mmc_cnt_b : spi_counter
+ generic map (
+ cnt_width_g => width_mmc_clk_div_g,
+ cnt_max_g => mmc_compat_clk_div_g,
+ reset_level_g => reset_level_g
+ )
+ port map (
+ clk_i => clk_i,
+ reset_i => reset_i,
+ cnt_en_i => true_s,
+ cnt_o => open,
+ cnt_ovfl_o => mmc_cnt_ovfl_s
+ );
+ end generate;
+
+ no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate
+ mmc_cnt_ovfl_s <= true;
+ end generate;
+
+
+ -----------------------------------------------------------------------------
+ -- Output Mapping
+ -----------------------------------------------------------------------------
+ spi_clk_o <= spi_clk_q;
+ spi_cs_n_o <= spi_cs_n_q;
+ spi_data_out_o <= spi_dat_q;
+ spi_en_outs_o <= '1'
+ when en_outs_q else
+ '0';
+ cfg_clk_o <= cfg_clk_q;
+ cfg_dat_o <= cfg_dat_q;
+ detached_o <= '0'
+ when en_outs_q else
+ '1';
+
+end rtl;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-- Revision 1.6 2005/03/09 19:48:34 arniml
+-- invert level of set_sel input
+--
+-- Revision 1.5 2005/03/08 22:07:12 arniml
+-- added set selection
+--
+-- Revision 1.4 2005/02/18 06:42:08 arniml
+-- clarify wording for images
+--
+-- Revision 1.3 2005/02/16 18:59:10 arniml
+-- include output enable control for SPI outputs
+--
+-- Revision 1.2 2005/02/13 17:25:51 arniml
+-- major update to fix several problems
+-- configuration/data download of multiple sets works now
+--
+-- Revision 1.1 2005/02/08 20:41:33 arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/rtl/vhdl/spi_boot-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/spi_boot-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/spi_boot-c.vhd (revision 71)
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot-c.vhd,v 1.2 2005-02-18 06:42:11 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration spi_boot_rtl_c0 of spi_boot is
+
+ for rtl
+
+ for img_cnt
+ for img_cnt_b : spi_counter
+ use configuration work.spi_counter_rtl_c0;
+ end for;
+ end for;
+
+ for mmc_cnt
+ for mmc_cnt_b : spi_counter
+ use configuration work.spi_counter_rtl_c0;
+ end for;
+ end for;
+
+ end for;
+
+end spi_boot_rtl_c0;
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-full-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-full-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-full-c.vhd (revision 71)
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-full-c.vhd,v 1.1 2005-02-08 20:41:31 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_full_c0 of chip is
+
+ for full
+
+ for spi_boot_b : spi_boot
+ use configuration work.spi_boot_rtl_c0;
+ end for;
+
+ end for;
+
+end chip_full_c0;
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-minimal-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-minimal-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-minimal-c.vhd (revision 71)
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-minimal-c.vhd,v 1.1 2005-02-08 20:41:32 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_minimal_c0 of chip is
+
+ for minimal
+
+ for spi_boot_b : spi_boot
+ use configuration work.spi_boot_rtl_c0;
+ end for;
+
+ end for;
+
+end chip_minimal_c0;
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-sd-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-sd-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-sd-c.vhd (revision 71)
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-sd-c.vhd,v 1.1 2005-02-08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_sd_c0 of chip is
+
+ for sd
+
+ for spi_boot_b : spi_boot
+ use configuration work.spi_boot_rtl_c0;
+ end for;
+
+ end for;
+
+end chip_sd_c0;
Index: tags/rel_3_1_rev_C/rtl/vhdl/spi_boot_pack-p.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/spi_boot_pack-p.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/spi_boot_pack-p.vhd (revision 71)
@@ -0,0 +1,51 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot_pack-p.vhd,v 1.1 2005-02-08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package spi_boot_pack is
+
+ function "=" (a : std_logic; b : integer) return boolean;
+
+end spi_boot_pack;
+
+package body spi_boot_pack is
+
+ function "=" (a : std_logic; b : integer) return boolean is
+ variable result_v : boolean;
+ begin
+ result_v := false;
+
+ case a is
+ when '0' =>
+ if b = 0 then
+ result_v := true;
+ end if;
+
+ when '1' =>
+ if b = 1 then
+ result_v := true;
+ end if;
+
+ when others =>
+ null;
+
+ end case;
+
+ return result_v;
+ end;
+
+end spi_boot_pack;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/rtl/vhdl/spi_counter-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/spi_counter-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/spi_counter-c.vhd (revision 71)
@@ -0,0 +1,14 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_counter-c.vhd,v 1.1 2005-02-08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration spi_counter_rtl_c0 of spi_counter is
+
+ for rtl
+ end for;
+
+end spi_counter_rtl_c0;
Index: tags/rel_3_1_rev_C/rtl/vhdl/spi_counter.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/spi_counter.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/spi_counter.vhd (revision 71)
@@ -0,0 +1,113 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Generic counter module
+--
+-- $Id: spi_counter.vhd,v 1.1 2005-02-08 20:41:33 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity spi_counter is
+
+ generic (
+ cnt_width_g : integer := 4;
+ cnt_max_g : integer := 15;
+ reset_level_g : integer := 0
+ );
+
+ port (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ cnt_en_i : in boolean;
+ cnt_o : out std_logic_vector(cnt_width_g-1 downto 0);
+ cnt_ovfl_o : out boolean
+ );
+
+end spi_counter;
+
+
+library ieee;
+use ieee.numeric_std.all;
+use work.spi_boot_pack.all;
+
+architecture rtl of spi_counter is
+
+ signal cnt_q : unsigned(cnt_width_g-1 downto 0);
+ signal cnt_ovfl_s : boolean;
+
+begin
+
+ cnt: process (clk_i, reset_i)
+ begin
+ if reset_i = reset_level_g then
+ cnt_q <= (others => '0');
+
+ elsif clk_i'event and clk_i = '1' then
+ if cnt_en_i then
+ if not cnt_ovfl_s then
+ cnt_q <= cnt_q + 1;
+ else
+ cnt_q <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process cnt;
+
+ cnt_ovfl_s <= cnt_q = cnt_max_g;
+
+
+ -----------------------------------------------------------------------------
+ -- Output Mapping
+ -----------------------------------------------------------------------------
+ cnt_ovfl_o <= cnt_ovfl_s;
+ cnt_o <= std_logic_vector(cnt_q);
+
+end rtl;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: not supported by cvs2svn $
+-------------------------------------------------------------------------------
Index: tags/rel_3_1_rev_C/rtl/vhdl/chip-mmc-c.vhd
===================================================================
--- tags/rel_3_1_rev_C/rtl/vhdl/chip-mmc-c.vhd (nonexistent)
+++ tags/rel_3_1_rev_C/rtl/vhdl/chip-mmc-c.vhd (revision 71)
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-mmc-c.vhd,v 1.1 2005-02-08 20:41:32 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_mmc_c0 of chip is
+
+ for mmc
+
+ for spi_boot_b : spi_boot
+ use configuration work.spi_boot_rtl_c0;
+ end for;
+
+ end for;
+
+end chip_mmc_c0;
Index: tags/rel_3_1_rev_C/COPYING
===================================================================
--- tags/rel_3_1_rev_C/COPYING (nonexistent)
+++ tags/rel_3_1_rev_C/COPYING (revision 71)
@@ -0,0 +1,340 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+ Finally, any free program is threatened constantly by software
+patents. We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary. To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License. The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language. (Hereinafter, translation is included without limitation in
+the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+ 1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+ 2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C) 19yy
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) 19yy name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ , 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Library General
+Public License instead of this License.