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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 704 to Rev 705
    ↔ Reverse comparison
  •

Rev 704 → Rev 705

/trunk/or1ksim/testbench/eth.c
35,24 → 35,43
eth_bd_base = (unsigned long *)(ETH_BASE + ETH_BD_BASE);
 
unsigned int_happend;
unsigned char r_packet[0x1000];
unsigned char r_packet[2000];
unsigned char s_packet[1003];
unsigned tx_bindex;
unsigned rx_bindex;
 
 
void interrupt_handler()
{
unsigned x;
unsigned i,len;
printf ("Int\n");
switch (*eth_int_source & 0xf) {
case 0x1: printf ("Transmit Error.\n"); break;
case 0x2: printf ("Receive Buffer\n");break;
case 0x4: printf ("Receive Frame\n");break;
case 0x8: printf ("Busy\n"); break;
case 0x0: printf ("Modem Status.\n"); break;
switch (*eth_int_source & 0x7f) {
case 0x2 : printf ("Transmit Error.\n"); break;
case 0x8 : printf ("Receive Error\n");break;
case 0x4 :
printf ("Receive Frame\n");
CLEAR_FLAG(*eth_moder, ETH_MODER, RXEN);
len = GET_FIELD(eth_bd_base[*eth_tx_bd_num + 2], ETH_RX_BD, LENGTH);
for (i=0; i<len; i++)
if (r_packet[i] != (unsigned char)i)
{
printf("Failed at byte %d. expect %d, received %d\n", i, i, r_packet[i]);
exit(1);
}
break;
case 0x10: printf ("Busy\n"); break;
case 0x1 :
printf ("Transmit Frame.\n");
CLEAR_FLAG(*eth_moder, ETH_MODER, RXEN);
break;
default:
printf ("Invalid iir @ %i\n", __LINE__);
printf ("Invalid int @ %0x\n", *eth_int_source & 0x1f);
exit (1);
}
*eth_int_source = 0;
 
mtspr(SPR_PICSR, 0);
int_happend = 1;
}
72,16 → 91,17
s_packet[i] = (unsigned char)i;
 
/* Set Ethernet BD */
SET_FIELD(eth_bd_base[0], ETH_TX_BD, LENGTH, sizeof(s_packet));
eth_bd_base[1] = (unsigned long)s_packet;
SET_FIELD(eth_bd_base[tx_bindex], ETH_TX_BD, LENGTH, sizeof(s_packet));
eth_bd_base[tx_bindex + 1] = (unsigned long)s_packet;
 
/* Start Ethernet */
SET_FLAG(eth_bd_base[0], ETH_TX_BD, READY);
SET_FLAG(eth_bd_base[tx_bindex], ETH_TX_BD, READY);
SET_FLAG(*eth_moder, ETH_MODER, TXEN);
/* Now wait till sent */
while ( TEST_FLAG( eth_bd_base[0], ETH_TX_BD, READY ) );
CLEAR_FLAG(*eth_moder, ETH_MODER, TXEN);
while ( TEST_FLAG( eth_bd_base[tx_bindex], ETH_TX_BD, READY ) );
CLEAR_FLAG(*eth_moder, ETH_MODER, TXEN);
*eth_int_source = 0;
}
 
static void transmit_one_packet_int( void )
88,16 → 108,20
{
unsigned i;
int_happend = 0;
/* Initialize packet */
printf("Init\n");
for ( i = 0; i < sizeof(s_packet); ++ i )
s_packet[i] = (unsigned char)i;
 
/* Set Ethernet BD */
SET_FIELD(eth_bd_base[2], ETH_TX_BD, LENGTH, sizeof(s_packet));
eth_bd_base[3] = (unsigned long)s_packet;
printf("Set BD\n");
SET_FIELD(eth_bd_base[tx_bindex], ETH_TX_BD, LENGTH, sizeof(s_packet));
eth_bd_base[tx_bindex + 1] = (unsigned long)s_packet;
 
/* Start Ethernet */
SET_FLAG(eth_bd_base[2], ETH_TX_BD, READY);
printf("Set Flags\n");
SET_FLAG(eth_bd_base[tx_bindex], ETH_TX_BD, READY);
SET_FLAG(*eth_moder, ETH_MODER, TXEN);
}
 
107,15 → 131,16
unsigned int i;
unsigned int len;
eth_bd_base[*eth_tx_bd_num + 1] = (unsigned long)r_packet;
eth_bd_base[rx_bindex + 1] = (unsigned long)r_packet;
SET_FLAG(eth_bd_base[*eth_tx_bd_num], ETH_RX_BD, READY);
SET_FLAG(eth_bd_base[rx_bindex], ETH_RX_BD, READY);
SET_FLAG(*eth_moder, ETH_MODER, RXEN);
 
while ( TEST_FLAG( eth_bd_base[*eth_tx_bd_num], ETH_RX_BD, READY ) );
while ( TEST_FLAG( eth_bd_base[rx_bindex], ETH_RX_BD, READY ) );
CLEAR_FLAG(*eth_moder, ETH_MODER, RXEN);
*eth_int_source = 0;
len = GET_FIELD(eth_bd_base[*eth_tx_bd_num], ETH_RX_BD, LENGTH);
len = GET_FIELD(eth_bd_base[rx_bindex], ETH_RX_BD, LENGTH);
for (i=0; i<len; i++)
if (r_packet[i] != (unsigned char)i)
{
126,24 → 151,13
 
static void receive_one_packet_int(void)
{
unsigned int i;
unsigned int len;
int_happend = 0;
printf("Set BD\n");
eth_bd_base[rx_bindex + 1] = (unsigned long)r_packet;
eth_bd_base[*eth_tx_bd_num + 3] = (unsigned long)r_packet;
SET_FLAG(eth_bd_base[*eth_tx_bd_num + 2], ETH_RX_BD, READY);
printf("SetFlags\n");
SET_FLAG(eth_bd_base[rx_bindex], ETH_RX_BD, READY);
SET_FLAG(*eth_moder, ETH_MODER, RXEN);
 
while ( TEST_FLAG( eth_bd_base[*eth_tx_bd_num + 2], ETH_RX_BD, READY ) );
CLEAR_FLAG(*eth_moder, ETH_MODER, RXEN);
len = GET_FIELD(eth_bd_base[*eth_tx_bd_num + 2], ETH_RX_BD, LENGTH);
for (i=0; i<len; i++)
if (r_packet[i] != (unsigned char)i)
{
printf("Failed at byte %d. expect %d, received %d\n", i, i, r_packet[i]);
exit(1);
}
}
 
int main()
150,26 → 164,46
{
printf( "Starting Ethernet test\n" );
 
tx_bindex = 0;
rx_bindex = *eth_tx_bd_num;
 
set_mac();
/*-------------------*/
/* non iterrupt test */
transmit_one_packet();
transmit_one_packet();
tx_bindex += 2;
receive_one_packet();
rx_bindex += 2;
transmit_one_packet();
tx_bindex += 2;
receive_one_packet();
rx_bindex += 2;
/* interrupt test */
excpt_int = (unsigned long)interrupt_handler;
/* Enable interrupts */
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
mtspr (SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << ETH_INT_LINE));
/*-------------------*/
/* interrupt test */
excpt_int = (unsigned long)interrupt_handler;
/* Enable interrup ts */
printf("enable ints\n");
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
mtspr (SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << ETH_INT_LINE));
printf("set mask flags\n");
SET_FLAG(*eth_int_mask, ETH_INT_MASK, TXB_M);
transmit_one_packet_int();
printf("waiting for int\n");
while (!int_happend);
CLEAR_FLAG(*eth_int_mask, ETH_INT_MASK, TXB_M);
transmit_one_packet_int();
/*
while (!int_happend);
printf("seting mask flagx RX\n");
SET_FLAG(*eth_int_mask, ETH_INT_MASK, RXB_M);
receive_one_packet_int();
printf("waiting for int RX\n");
while (!int_happend);
*/
CLEAR_FLAG(*eth_int_mask, ETH_INT_MASK, RXB_M);
printf( "Ending Ethernet test\n" );
report (0xdeaddead);
/trunk/or1ksim/peripheral/eth.c
76,7 → 76,7
if ( TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
/* wait for TxBuffer to be ready */
debug (3, "TX - entering state WAIT4BD\n");
debug (3, "TX - entering state WAIT4BD (%d)\n", eth->tx.bd_index);
eth->tx.state = ETH_TXSTATE_WAIT4BD;
}
break;
169,9 → 169,9
break;
case ETH_RTX_SOCK:
memset(&sll, 0, sizeof(sll));
sll.sll_ifindex = eth->ifr.ifr_ifindex;
nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
break;
sll.sll_ifindex = eth->ifr.ifr_ifindex;
nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
break;
}
/* set BD status */
179,7 → 179,7
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
debug (3, "TX - entering state IDLE\n");
debug (3, "TX - entering state IDLE\n");
eth->tx.state = ETH_TXSTATE_IDLE;
debug (3, "send (%d)bytes OK\n", nwritten);
}
238,7 → 238,7
switch (eth->rx.state) {
case ETH_RXSTATE_IDLE:
if ( TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) ) {
debug (3, "RX - entering state WAIT4BD\n");
debug (3, "RX - entering state WAIT4BD (%d)\n", eth->rx.bd_index);
eth->rx.state = ETH_RXSTATE_WAIT4BD;
}
break;
271,10 → 271,15
debug (3, "RX - entering state RECV\n");
eth->rx.state = ETH_RXSTATE_RECV;
}
else {
nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_PEEK);
if (nread > 0) {
else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
debug (3, "RX - entering state IDLE\n");
eth->rx.state = ETH_RXSTATE_IDLE;
}
else {
nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_PEEK | MSG_DONTWAIT);
if (nread > 0) {
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
report_interrupt(eth->mac_int);
}
}
break;
347,7 → 352,7
/* Write result to bd */
SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXF);
SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
if ( eth->rx.packet_length < GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) )
SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
358,11 → 363,11
/* advance to next BD */
if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
eth->tx.bd_index = eth->regs.tx_bd_num;
eth->rx.bd_index = eth->regs.tx_bd_num;
else
eth->tx.bd_index += 2;
eth->rx.bd_index += 2;
if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, RXF_M) ) {
if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, RXB_M) ) {
report_interrupt( eth->mac_int );
}
/trunk/or1ksim/peripheral/ethernet.h
79,15 → 79,19
#define ETH_MODER_RXEN_OFFSET 0
 
/* Field definitions for INT_SOURCE */
#define ETH_INT_SOURCE_RXC_OFFSET 6
#define ETH_INT_SOURCE_TXC_OFFSET 5
#define ETH_INT_SOURCE_BUSY_OFFSET 4
#define ETH_INT_SOURCE_RXF_OFFSET 3
#define ETH_INT_SOURCE_RXE_OFFSET 3
#define ETH_INT_SOURCE_RXB_OFFSET 2
#define ETH_INT_SOURCE_TXE_OFFSET 1
#define ETH_INT_SOURCE_TXB_OFFSET 0
 
/* Field definitions for INT_MASK */
#define ETH_INT_MASK_RXC_M_OFFSET 6
#define ETH_INT_MASK_TXC_M_OFFSET 5
#define ETH_INT_MASK_BUSY_M_OFFSET 4
#define ETH_INT_MASK_RXF_M_OFFSET 3
#define ETH_INT_MASK_RXE_M_OFFSET 3
#define ETH_INT_MASK_RXB_M_OFFSET 2
#define ETH_INT_MASK_TXE_M_OFFSET 1
#define ETH_INT_MASK_TXB_M_OFFSET 0
110,7 → 114,7
#define ETH_CMODER_PASSALL_OFFSET 0
 
/* Field definitions for MIIMODER */
#define ETH_MIIMODER_MRST_OFFSET 10
#define ETH_MIIMODER_MRST_OFFSET 9
#define ETH_MIIMODER_NOPRE_OFFSET 8
#define ETH_MIIMODER_CLKDIV_OFFSET 0
#define ETH_MIIMODER_CLKDIV_WIDTH 8
127,8 → 131,8
#define ETH_MIIADDR_FIAD_WIDTH 5
 
/* Field definitions for MIISTATUS */
#define ETH_MIISTAT_NVALID_OFFSET 9
#define ETH_MIISTAT_BUSY_OFFSET 8
#define ETH_MIISTAT_NVALID_OFFSET 1
#define ETH_MIISTAT_BUSY_OFFSET 1
#define ETH_MIISTAT_FAIL_OFFSET 0
 
/* Field definitions for TX buffer descriptors */

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