URL
https://opencores.org/ocsvn/rise/rise/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 71 to Rev 72
- ↔ Reverse comparison
Rev 71 → Rev 72
/trunk/vhdl/id_stage.vhd
11,8 → 11,8
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
use WORK.RISE_PACK.all; |
use work.RISE_PACK_SPECIFIC.all; |
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entity id_stage is |
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port ( |
134,13 → 134,13
id_ex_register_next.opcode <= OPCODE_NOP; |
-- decodes: OPCODE_LD_IMM, OPCODE_LD_IMM_HB |
elsif if_id_register.ir(15 downto 13) = "100" then |
id_ex_register_next.opcode <= if_id_register.ir(15 downto 13) & if_id_register.ir(12) & "0"; |
id_ex_register_next.opcode <= svector2opcode(if_id_register.ir(15 downto 13) & if_id_register.ir(12) & "0"); |
-- decodes: OPCODE_LD_DISP, OPCODE_LD_DISP_MS, OPCODE_ST_DISP |
elsif if_id_register.ir(15) = '1' then |
id_ex_register_next.opcode <= if_id_register.ir(15 downto 13) & "00"; |
id_ex_register_next.opcode <= svector2opcode(if_id_register.ir(15 downto 13) & "00"); |
-- decodes: OPCODE_XXX |
else |
id_ex_register_next.opcode <= if_id_register.ir(15 downto 11); |
id_ex_register_next.opcode <= svector2opcode(if_id_register.ir(15 downto 11)); |
end if; |
end process; |
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153,10 → 153,10
id_ex_register_next.cond <= COND_UNCONDITIONAL; |
-- decodes: OPCODE_LD_DISP, OPCODE_LD_DISP_MS, OPCODE_ST_DISP |
elsif if_id_register.ir(15) = '1' then |
id_ex_register_next.cond <= if_id_register.ir(12 downto 10); |
id_ex_register_next.cond <= svector2cond(if_id_register.ir(12 downto 10)); |
-- decodes: OPCODE_XXX |
else |
id_ex_register_next.cond <= if_id_register.ir(10 downto 8); |
id_ex_register_next.cond <= svector2cond(if_id_register.ir(10 downto 8)); |
end if; |
end process; |
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