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    from Rev 71 to Rev 72
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Rev 71 → Rev 72

/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
92,7 → 92,7
output async_rst_b, //
output sync_reset, //
input [415:0] read_risc_regs, // status register bits for WISHBONE Read bus
input [127:0] irq_bypass // IRQ status bits WISHBONE Read bus
input [127:1] irq_bypass // IRQ status bits WISHBONE Read bus
);
 
 
246,7 → 246,7
always @*
case ({wbs_racc, address}) // synopsys parallel_case
// 16 bit Bus, 16 bit Granularity
7'b110_0000: read_mux_irq = irq_bypass[ 15: 0];
7'b110_0000: read_mux_irq = {irq_bypass[ 15: 1], 1'b0};
7'b110_0001: read_mux_irq = irq_bypass[ 31: 16];
7'b110_0010: read_mux_irq = irq_bypass[ 47: 32];
7'b110_0011: read_mux_irq = irq_bypass[ 63: 48];
/xgate/trunk/rtl/verilog/xgate_irq_encode.v
42,14 → 42,14
module xgate_irq_encode #(parameter MAX_CHANNEL = 127) // Max XGATE Interrupt Channel Number
(
output reg [ 6:0] int_req, // Encoded interrupt request to RISC
output [MAX_CHANNEL:0] xgif, // Interrupt outputs to Host
output [MAX_CHANNEL:1] xgif, // Interrupt outputs to Host
 
input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt requests from peropherials
input [MAX_CHANNEL:0] chan_bypass, // XGATE Interrupt bypass
input [MAX_CHANNEL:0] xgif_status // Interrupt outputs from RISC core
input [MAX_CHANNEL:1] chan_req_i, // XGATE Interrupt requests from peropherials
input [MAX_CHANNEL:1] chan_bypass, // XGATE Interrupt bypass
input [MAX_CHANNEL:1] xgif_status // Interrupt outputs from RISC core
);
 
wire [MAX_CHANNEL:0] chan_ena_gate; // Ouptut of channel enable gating
wire [MAX_CHANNEL:1] chan_ena_gate; // Ouptut of channel enable gating
 
// Pass non-bypassed interrupt inputs to XGATE RISC
assign chan_ena_gate = ~chan_bypass & chan_req_i;
59,7 → 59,7
always @(chan_ena_gate)
begin
int_req = 0;
for (i = MAX_CHANNEL; i >= 0; i = i - 1)
for (i = MAX_CHANNEL; i >= 1; i = i - 1)
if (chan_ena_gate[i] == 1'b1)
int_req = i;
end
/xgate/trunk/rtl/verilog/xgate_regs.v
62,8 → 62,8
output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
output semaph_stat, // Return Status of Semaphore bit
output reg brk_irq_ena, // Enable BRK instruction to generate interrupt
output [MAX_CHANNEL:0] chan_bypass, // XGATE Interrupt enable or bypass
output reg [127:0] irq_bypass, // Register to hold irq bypass control state
output [MAX_CHANNEL:1] chan_bypass, // XGATE Interrupt enable or bypass
output reg [127:1] irq_bypass, // Register to hold irq bypass control state
 
input bus_clk, // Control register bus clock
input async_rst_b, // Async reset signal
96,7 → 96,7
integer k; // Loop counter for channel bypass counter assigments
 
// registers
reg [127:0] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register
reg [127:1] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register
 
// Wires
wire [ 1:0] write_any_xgif;
228,8 → 228,8
// Channel Bypass Register input bits
always @*
begin
k = 0;
for (j = 0; j <= 127; j = j + 1)
k = 1; // WISHBONE Bus bit counter [15:0]
for (j = 1; j <= 127; j = j + 1)
begin
if (j <= MAX_CHANNEL)
begin
266,12 → 266,12
if ((j >= 120) && (j < 128))
irq_bypass_d[j] = write_irw_en_7[1] ? write_bus[k] : irq_bypass[j];
end
else
irq_bypass_d[j] = 1'b0;
k = k + 1;
if (k > 15)
k = 0;
end
else
irq_bypass_d[j] = 1'b0;
k = k + 1;
if (k > 15)
k = 0;
end
end
 
// Channel Bypass Registers
278,13 → 278,12
// Synthesys should eliminate bits that with D input tied to zero
always @(posedge bus_clk or negedge async_rst_b)
if ( !async_rst_b )
irq_bypass <= {128{1'b1}};
irq_bypass <= {127{1'b1}};
else
irq_bypass <= irq_bypass_d;
 
// Alias the register name to the output pin name so only the used bit are carried out
// assign chan_bypass = {(MAX_CHANNEL+1){1'b1}};
assign chan_bypass = irq_bypass[MAX_CHANNEL:0];
assign chan_bypass = irq_bypass[MAX_CHANNEL:1];
 
endmodule // xgate_regs
 
/xgate/trunk/rtl/verilog/xgate_risc.v
57,7 → 57,7
output reg carry_flag,
output reg overflow_flag,
output reg [ 6:0] xgchid,
output reg [127:0] xgif_status, // XGATE Interrupt Flag
output reg [127:1] xgif_status, // XGATE Interrupt Flag
output xg_sw_irq, // Xgate Software interrupt
output [ 7:0] host_semap, // Semaphore status for host
output reg debug_active, // Latch to control debug mode in the RISC state machine
184,7 → 184,7
reg wrt_sel_xgr6; // Pseudo Register,
reg wrt_sel_xgr7; // Pseudo Register,
 
reg [127:0] xgif_d;
reg [127:1] xgif_d;
 
reg [15:0] shift_in;
wire [15:0] shift_out;
450,14 → 450,14
always @*
begin
xgif_d = 0;
j = 0;
while (j <= MAX_CHANNEL)
j = 1;
while (j <= MAX_CHANNEL) // while loop sets irq bit and maintains previously set bits
begin
xgif_d[j] = xgif_status[j] || (set_irq_flag == j);
j = j + 1;
end
if (clear_xgif_0)
xgif_d[15: 0] = ~clear_xgif_data & xgif_status[15: 0];
xgif_d[15: 1] = ~clear_xgif_data & xgif_status[15: 1];
if (clear_xgif_1)
xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16];
if (clear_xgif_2)
/xgate/trunk/rtl/verilog/xgate_top.v
68,8 → 68,8
// XGATE IO Signals
output [ 7:0] xgswt, // XGATE Software Trigger Register
output xg_sw_irq, // Xgate Software interrupt
output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag to Host
input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
output [MAX_CHANNEL:1] xgif, // XGATE Interrupt Flag to Host
input [MAX_CHANNEL:1] chan_req_i, // XGATE Interrupt request
input risc_clk, // Clock for RISC core
input debug_mode_i, // Force RISC core into debug mode
input secure_mode_i, // Limit host asscess to Xgate RISC registers
130,7 → 130,7
wire clear_xgif_1; // Strobe for decode to clear interrupt flag bank 1
wire clear_xgif_0; // Strobe for decode to clear interrupt flag bank 0
wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
wire [MAX_CHANNEL:0] chan_bypass; // XGATE Interrupt enable or bypass
wire [MAX_CHANNEL:1] chan_bypass; // XGATE Interrupt enable or bypass
 
wire xge; // XGATE Module Enable
wire xgfrz; // Stop XGATE in Freeze Mode
142,8 → 142,8
wire xgie; // XGATE Interrupt Enable
wire [ 6:0] int_req; // Encoded interrupt request
wire [ 6:0] xgchid; // Channel actively being processed
wire [127:0] xgif_status; // Status bits of interrupt output flags that have been set
wire [127:0] irq_bypass; // IRQ status bits WISHBONE Read bus
wire [127:1] xgif_status; // Status bits of interrupt output flags that have been set
wire [127:1] irq_bypass; // IRQ status bits WISHBONE Read bus
 
wire [15:1] xgvbr; // XGATE vector Base Address Register
wire brk_irq_ena; // Enable BRK instruction to generate interrupt
230,7 → 230,7
16'b0, // Reserved
{8'h00, host_semap}, // XGSEM
{8'h00, xgswt}, // XGSWT
xgif_status[ 15: 0], // XGIF_0
{xgif_status[ 15: 1], 1'b0}, // XGIF_0
xgif_status[ 31: 16], // XGIF_1
xgif_status[ 47: 32], // XGIF_2
xgif_status[ 63: 48], // XGIF_3

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