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URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 713 to Rev 714
    ↔ Reverse comparison
  •

Rev 713 → Rev 714

/trunk/gen_or1k_isa/sources/or32.c
1002,11 → 1002,11
{
case '\0':
return insn_len (insn);
 
case 'r':
dest = or32_print_register(dest, *++s, opcode->encoding, insn);
break;
 
default:
if (strchr (opcode->encoding, *s))
dest = or32_print_immediate (dest, *s, opcode->encoding, insn);
/trunk/gen_or1k_isa/sources/opcode/or32.c
1002,11 → 1002,11
{
case '\0':
return insn_len (insn);
 
case 'r':
dest = or32_print_register(dest, *++s, opcode->encoding, insn);
break;
 
default:
if (strchr (opcode->encoding, *s))
dest = or32_print_immediate (dest, *s, opcode->encoding, insn);
/trunk/insight/opcodes/or32.c
1002,11 → 1002,11
{
case '\0':
return insn_len (insn);
 
case 'r':
dest = or32_print_register(dest, *++s, opcode->encoding, insn);
break;
 
default:
if (strchr (opcode->encoding, *s))
dest = or32_print_immediate (dest, *s, opcode->encoding, insn);
/trunk/or1ksim/cpu/or32/execute.c
109,6 → 109,9
/* Number of total store cycles */
int sbuf_total_cyc = 0;
 
/* Whether we are doing statistical analysis */
int do_stats = 0;
 
/* Local data needed for execution. */
static int next_delay_insn;
static int breakpoint;
517,6 → 520,8
histexec[i] = histexec[i - 1];
histexec[0] = icomplet[0].insn_addr; /* add last insn */
}
 
if (config.sim.exe_log) dump_exe_log();
}
 
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
608,22 → 613,14
case EXE_LOG_SOFTWARE:
{
extern char *disassembled;
int labels = 0;
disassemble_index (iqueue[0].insn, iqueue[0].insn_index);
if (verify_memoryarea(i)) {
{
struct label_entry *entry;
entry = get_label(i);
if (entry) {
fprintf (runtime.sim.fexe_log, "%s: ", entry->name);
labels++;
}
} else {
fprintf (runtime.sim.fexe_log, "<invalid addr>: ");
labels++;
if (entry)
fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);
}
if (labels) fprintf (runtime.sim.fexe_log, "\n");
 
if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
int i;
for (i = 0; i < num_op; i++)
636,7 → 633,6
for (; i < 3; i++)
fprintf (runtime.sim.fexe_log, " ");
}
 
fprintf (runtime.sim.fexe_log, "%.8lx ", i);
fprintf (runtime.sim.fexe_log, "%s\n", disassembled);
}
756,8 → 752,7
}
decode_execute_wrapper (&iqueue[0]);
update_pc();
analysis(&iqueue[0]);
if (config.sim.exe_log) dump_exe_log();
if (do_stats) analysis(&iqueue[0]);
return 0;
}
 
/trunk/or1ksim/cpu/or32/or32.c
1002,11 → 1002,11
{
case '\0':
return insn_len (insn);
 
case 'r':
dest = or32_print_register(dest, *++s, opcode->encoding, insn);
break;
 
default:
if (strchr (opcode->encoding, *s))
dest = or32_print_immediate (dest, *s, opcode->encoding, insn);
/trunk/or1ksim/cpu/or32/generate.c
174,7 → 174,7
{
struct insn_op_struct *opd = op_start[insn_index];
int dis = 0;
int no = 0;
int no = 0, num_op;
int firstd = 1;
while (1)
205,27 → 205,34
{
if (dis && (opd->type & OPTYPE_REG)) {
if (MAX_GPRS == (1 << nbits)) {
SHIFT; fprintf (fo, "op[%i] = %c = data + reg [tmp];\n", no, 'a' + no);
}else {
SHIFT; fprintf (fo, "op[%i] = %c = data + eval_reg32 (tmp);\n", no, 'a' + no);
SHIFT; fprintf (fo, "%c = data + reg [tmp];\n", 'a' + no);
} else {
SHIFT; fprintf (fo, "%c = data + eval_reg32 (tmp);\n", 'a' + no);
}
} else {
SHIFT; fprintf (fo, "op[%i] = %c = tmp;\n", no, 'a' + no);
SHIFT; fprintf (fo, "%c = tmp;\n", 'a' + no);
}
SHIFT; fprintf (fo, "op[%i + MAX_OPERANDS] = 0x%08x;\n", no, opd->type | (dis ? OPTYPE_DIS : 0));
op[no] = opd->type | (dis ? OPTYPE_DIS : 0);
no++;
firstd = 1;
dis = 0;
}
if(opd->type & OPTYPE_LAST) {
SHIFT; fprintf (fo, "num_op = %i;\n", no);
num_op = no;
return;
}
if(opd->type & OPTYPE_LAST) goto last;
opd++;
}
last:
num_op = no;
SHIFT; fprintf (fo, "if (do_stats) {\n");
level++;
SHIFT; fprintf (fo, "num_op = %i;\n", no);
SHIFT; fprintf (fo, "insn_index = %i; /* \"%s\" */\n", insn_index, insn_name (insn_index));
for (no = 0; no < num_op; no++) {
SHIFT; fprintf (fo, "op[%i] = %c;\n", no, 'a' + no);
SHIFT; fprintf (fo, "op[%i + MAX_OPERANDS] = 0x%08x;\n", no, op[no]);
}
level--;
SHIFT; fprintf (fo, "}\n");
}
 
/* Generates decode and execute for one instruction instance */
241,10 → 248,14
}
write_to_reg = 0;
if (index >= 0) {
SHIFT; fprintf (fo, "insn_index = %i; /* \"%s\" */\n", index, insn_name (index));
gen_eval_operands (fo, index, level);
} else {
SHIFT; fprintf (fo, "if (do_stats) {\n");
level++;
SHIFT; fprintf (fo, "num_op = 0;\n");
SHIFT; fprintf (fo, "insn_index = -1;\n");
level--;
SHIFT; fprintf (fo, "}\n");
}
SHIFT;
if (index < 0) output_function (fo, "l_invalid", level);
/trunk/or1ksim/toplevel.c
57,7 → 57,7
#include "mprofiler.h"
 
/* CVS revision number. */
const char rcsrev[] = "$Revision: 1.77 $";
const char rcsrev[] = "$Revision: 1.78 $";
 
/* Continuos run versus single step tracing switch. */
int cont_run;
672,6 → 672,12
#endif /* !FAST_SIM */
printf("%s: Unknown command.\n", linestr);
{ /* Needed by execution */
extern int do_stats;
do_stats = config.cpu.dependstats || config.cpu.superscalar || config.cpu.dependstats
|| config.sim.history || config.sim.exe_log;
}
 
/* MM: 'run -1' means endless execution. */
while(cont_run) {
extern int mem_cycles;

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