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URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

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Rev 72 → Rev 73

/trunk/bench/verilog/dbg_tb.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2003/08/28 13:54:33 simons
// Three more chains added for cpu debug access.
//
// Revision 1.12 2002/05/07 14:44:52 mohor
// mon_cntl_o signals that controls monitor mux added.
//
116,12 → 119,13
reg [3:0] LsStatus;
reg [1:0] IStatus;
reg BS_CHAIN_I;
reg MBIST_I;
 
wire P_TDO;
wire [31:0] ADDR_RISC;
wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
wire [31:0] ADDR_CPU;
wire [31:0] DATAIN_CPU; // DATAIN_CPU is connect to DATAOUT
 
wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
wire [31:0] DATAOUT_CPU; // DATAOUT_CPU is connect to DATAIN
 
wire [`OPSELECTWIDTH-1:0] OpSelect;
 
141,6 → 145,7
wire UpdateDR;
wire UpdateDR_q;
wire CaptureDR;
wire SelectDRScan;
wire IDCODESelected;
wire CHAIN_SELECTSelected;
wire DEBUGSelected;
147,8 → 152,14
wire TDOData_dbg;
wire BypassRegister;
wire EXTESTSelected;
wire MBISTSelected;
wire [3:0] mon_cntl_o;
wire CpuDebugScanChain0;
wire CpuDebugScanChain1;
wire CpuDebugScanChain2;
wire CpuDebugScanChain3;
 
 
// Connecting TAP module
tap_top i_tap_top
(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
156,25 → 167,40
// TAP states
.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
.CaptureDR(CaptureDR),
.CaptureDR(CaptureDR), .SelectDRScan(SelectDRScan),
// Instructions
.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
.DEBUGSelected(DEBUGSelected), .EXTESTSelected(EXTESTSelected),
.MBISTSelected(MBISTSelected),
// TDO from dbg module
.TDOData_dbg(TDOData_dbg), .BypassRegister(BypassRegister),
// Boundary Scan Chain
.bs_chain_i(BS_CHAIN_I)
.bs_chain_i(BS_CHAIN_I),
 
// From Mbist Chain
.mbist_so_i(MBIST_I),
 
// Selected chains
.RegisterScanChain(RegisterScanChain),
.CpuDebugScanChain0(CpuDebugScanChain0),
.CpuDebugScanChain1(CpuDebugScanChain1),
.CpuDebugScanChain2(CpuDebugScanChain2),
.CpuDebugScanChain3(CpuDebugScanChain3),
.WishboneScanChain(WishboneScanChain)
 
);
 
 
 
dbg_top i_dbg_top
(
.risc_clk_i(Mclk), .risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC),
.risc_data_o(DATAIN_RISC), .wp_i(Wp), .bp_i(Bp), .opselect_o(OpSelect),
.lsstatus_i(LsStatus), .istatus_i(IStatus), .risc_stall_o(), .reset_o(),
.cpu_clk_i(Mclk), .cpu_addr_o(ADDR_CPU), .cpu_data_i(DATAOUT_CPU),
.cpu_data_o(DATAIN_CPU), .wp_i(Wp), .bp_i(Bp), .opselect_o(OpSelect),
.lsstatus_i(LsStatus), .istatus_i(IStatus), .cpu_stall_o(),
.cpu_stall_all_o(), .cpu_sel_o(), .reset_o(),
.wb_rst_i(wb_rst_i), .wb_clk_i(Mclk),
184,7 → 210,8
.wb_err_i(wb_err_o),
// TAP states
.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
.SelectDRScan(SelectDRScan),
// Instructions
.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
196,8 → 223,16
.BypassRegister(BypassRegister),
.mon_cntl_o(mon_cntl_o)
.mon_cntl_o(mon_cntl_o),
 
// Selected chains
.RegisterScanChain(RegisterScanChain),
.CpuDebugScanChain0(CpuDebugScanChain0),
.CpuDebugScanChain1(CpuDebugScanChain1),
.CpuDebugScanChain2(CpuDebugScanChain2),
.CpuDebugScanChain3(CpuDebugScanChain3),
.WishboneScanChain(WishboneScanChain)
 
);
reg TestEnabled;
211,6 → 246,7
P_TCK<=#Tp 'hz;
P_TDI<=#Tp 'hz;
BS_CHAIN_I = 0;
MBIST_I = 0;
 
Wp<=#Tp 0;
Bp<=#Tp 0;
224,24 → 260,24
 
 
wb_rst_i<=#Tp 0;
P_TRST<=#Tp 0;
#100 wb_rst_i<=#Tp 1;
P_TRST<=#Tp 1;
#100 wb_rst_i<=#Tp 1;
#100 wb_rst_i<=#Tp 0;
P_TRST<=#Tp 0;
#100 wb_rst_i<=#Tp 0;
P_TRST<=#Tp 1;
#Tp TestEnabled<=#Tp 1;
end
 
 
// Generating master clock (RISC clock) 200 MHz
// Generating master clock (cpu clock) 200 MHz
initial
begin
Mclk<=#Tp 0;
#1 forever #`RISC_CLOCK Mclk<=~Mclk;
#1 forever #`CPU_CLOCK Mclk<=~Mclk;
end
 
 
// Generating random number for use in DATAOUT_RISC[31:0]
// Generating random number for use in DATAOUT_CPU[31:0]
reg [31:0] RandNumb;
always @ (posedge Mclk or posedge wb_rst_i)
begin
252,162 → 288,189
end
 
 
assign DATAOUT_RISC[31:0] = RandNumb[31:0];
assign DATAOUT_CPU[31:0] = RandNumb[31:0];
 
 
always @ (posedge TestEnabled)
fork
 
begin
EnableWishboneSlave; // enabling WISHBONE slave
end
 
$display("//////////////////////////////////////////////////////////////////////////////////////");
$display("// //");
$display("// (%0t) dbg_tb starting //", $time);
$display("// //");
$display("//////////////////////////////////////////////////////////////////////////////////////");
 
begin
ResetTAP;
GotoRunTestIdle;
fork
 
// Testing read and write to WISHBONE
SetInstruction(`CHAIN_SELECT);
ChainSelect(`WISHBONE_SCAN_CHAIN, 8'h36); // {chain, crc}
SetInstruction(`DEBUG);
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
WriteRISCRegister(32'h18273645, 32'hbeefbeef, 8'haa); // {data, addr, crc}
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
ReadRISCRegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and RISC accesses are similar
//
 
// Testing read and write to RISC registers
SetInstruction(`CHAIN_SELECT);
ChainSelect(`RISC_DEBUG_CHAIN_2, 8'h38); // {chain, crc}
SetInstruction(`DEBUG);
begin
EnableWishboneSlave; // enabling WISHBONE slave
end
 
ReadRISCRegister(32'h12345ead, 8'hbf); // {addr, crc}
WriteRISCRegister(32'h11223344, 32'h12345678, 8'haf); // {data, addr, crc}
//
 
begin
ResetTAP;
GotoRunTestIdle;
// Testing read and write to WISHBONE (WB and CPU chain are the same)
SetInstruction(`CHAIN_SELECT);
ChainSelect(`WISHBONE_SCAN_CHAIN, 8'h36); // {chain, crc}
SetInstruction(`DEBUG);
WriteCPURegister(32'h18273645, 32'hbeefbeef, 8'haa); // {data, addr, crc}
 
// Testing read and write to internal registers
SetInstruction(`IDCODE);
ReadIDCode; // muten
#10000;
ReadCPURegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and CPU accesses are similar
ReadCPURegister(32'h87654321, 8'hfd); // {addr, crc} // Wishbone and CPU accesses are similar
 
SetInstruction(`CHAIN_SELECT);
ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
SetInstruction(`DEBUG);
// Testing read and write to CPU0 registers
#10000;
SetInstruction(`CHAIN_SELECT);
ChainSelect(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc}
SetInstruction(`DEBUG);
WriteCPURegister(32'h11001100, 32'h00110011, 8'h86); // {data, addr, crc}
ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}
ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}
// Testing read and write to CPU1 registers
#10000;
SetInstruction(`CHAIN_SELECT);
ChainSelect(`CPU_DEBUG_CHAIN_1, 8'h2a); // {chain, crc}
SetInstruction(`DEBUG);
WriteCPURegister(32'h22002200, 32'h00220022, 8'h10); // {data, addr, crc}
ReadCPURegister(32'h22002200, 8'hee); // {addr, crc}
ReadCPURegister(32'h22002200, 8'hee); // {addr, crc}
// Testing read and write to CPU2 registers
#10000;
SetInstruction(`CHAIN_SELECT);
ChainSelect(`CPU_DEBUG_CHAIN_2, 8'h38); // {chain, crc}
SetInstruction(`DEBUG);
WriteCPURegister(32'h33003300, 32'h00330033, 8'hf4); // {data, addr, crc}
ReadCPURegister(32'h33003300, 8'h35); // {addr, crc}
ReadCPURegister(32'h33003300, 8'h35); // {addr, crc}
// Testing read and write to CPU3 registers
#10000;
SetInstruction(`CHAIN_SELECT);
ChainSelect(`CPU_DEBUG_CHAIN_3, 8'h07); // {chain, crc}
SetInstruction(`DEBUG);
WriteCPURegister(32'h44004400, 32'h00440044, 8'h5b); // {data, addr, crc}
ReadCPURegister(32'h44004400, 8'h77); // {addr, crc}
ReadCPURegister(32'h44004400, 8'h77); // {addr, crc}
// Testing read and write to internal registers
#10000;
SetInstruction(`IDCODE);
ReadIDCode;
SetInstruction(`CHAIN_SELECT);
ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
SetInstruction(`DEBUG);
// Testing internal registers
WriteRegister(32'h00000001, `CPUOP_ADR, 8'h4a); // {data, addr, crc}
WriteRegister(32'h00000002, `CPUOP_ADR, 8'he0); // {data, addr, crc}
WriteRegister(32'h00000004, `CPUOP_ADR, 8'hb5); // {data, addr, crc}
WriteRegister(32'h00000000, `CPUSEL_ADR, 8'h1f); // {data, addr, crc}
WriteRegister(32'h00000001, `CPUSEL_ADR, 8'h2e); // {data, addr, crc}
WriteRegister(32'h00000002, `CPUSEL_ADR, 8'h84); // {data, addr, crc}
 
ReadRegister(`CPUOP_ADR, 8'h19); // {addr, crc}
ReadRegister(`CPUOP_ADR, 8'h19); // {addr, crc}
ReadRegister(`CPUSEL_ADR, 8'h7d); // {addr, crc}
ReadRegister(`CPUSEL_ADR, 8'h7d); // {addr, crc}
 
//
// Testing internal registers
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
 
WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
WriteRegister(32'h0000000d, `MON_CNTL_ADR, 8'h5a); // {data, addr, crc}
 
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
//
 
 
// testing trigger and qualifier
`ifdef TRACE_ENABLED
 
 
 
 
 
// Anything starts trigger and qualifier
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
#100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
// End: Anything starts trigger and qualifier //
 
 
/* Anything starts trigger, breakpoint starts qualifier
// Uncomment this part when you want to test it.
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
wait(dbg_tb.i_dbg_top.TraceEnable)
@ (posedge Mclk);
#1 Bp = 1; // Set breakpoint
repeat(8) @(posedge Mclk);
wait(dbg_tb.i_dbg_top.dbgTrace1.RiscStall)
#1 Bp = 0; // Clear breakpoint
// End: Anything starts trigger, breakpoint starts qualifier */
 
 
/* Anything starts qualifier, breakpoint starts trigger
// Uncomment this part when you want to test it.
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
wait(dbg_tb.i_dbg_top.TraceEnable)
@ (posedge Mclk)
Wp[4] = 1; // Set watchpoint[4]
LsStatus = 4'h5; // LsStatus[0] and LsStatus[2] are active
@ (posedge Mclk)
Wp[4] = 0; // Clear watchpoint[4]
LsStatus = 4'h0; // LsStatus[0] and LsStatus[2] are cleared
// End: Anything starts trigger and qualifier */
 
 
 
 
 
 
// Reading data from the trace buffer
SetInstruction(`CHAIN_SELECT);
ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
SetInstruction(`DEBUG);
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
 
 
`endif // TRACE_ENABLED
 
 
 
//ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
//ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
//ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
//ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
//ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
//ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
//ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
//ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
//WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
//WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
//WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
//WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
//WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
//WriteRegister(32'h0000000d, `MON_CNTL_ADR, 8'h5a); // {data, addr, crc}
// testing trigger and qualifier
`ifdef TRACE_ENABLED
// Anything starts trigger and qualifier
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
#100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
// End: Anything starts trigger and qualifier //
/* Anything starts trigger, breakpoint starts qualifier
// Uncomment this part when you want to test it.
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
wait(dbg_tb.i_dbg_top.TraceEnable)
@ (posedge Mclk);
#1 Bp = 1; // Set breakpoint
repeat(8) @(posedge Mclk);
wait(dbg_tb.i_dbg_top.dbgTrace1.CpuStall)
#1 Bp = 0; // Clear breakpoint
// End: Anything starts trigger, breakpoint starts qualifier */
/* Anything starts qualifier, breakpoint starts trigger
// Uncomment this part when you want to test it.
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
wait(dbg_tb.i_dbg_top.TraceEnable)
@ (posedge Mclk)
Wp[4] = 1; // Set watchpoint[4]
LsStatus = 4'h5; // LsStatus[0] and LsStatus[2] are active
@ (posedge Mclk)
Wp[4] = 0; // Clear watchpoint[4]
LsStatus = 4'h0; // LsStatus[0] and LsStatus[2] are cleared
// End: Anything starts trigger and qualifier */
// Reading data from the trace buffer
SetInstruction(`CHAIN_SELECT);
ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
SetInstruction(`DEBUG);
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
`endif // TRACE_ENABLED
#5000 GenClk(1); // One extra TCLK for debugging purposes
#1000 $stop;
 
end
join
end
join
 
 
// Generation of the TCLK signal
task GenClk;
input [7:0] Number;
425,6 → 488,7
// TAP reset
task ResetTAP;
begin
$display("(%0t) Task ResetTAP", $time);
P_TMS<=#Tp 1;
GenClk(7);
end
434,6 → 498,7
// Goes to RunTestIdle state
task GotoRunTestIdle;
begin
$display("(%0t) Task GotoRunTestIdle", $time);
P_TMS<=#Tp 0;
GenClk(1);
end
446,6 → 511,7
integer i;
begin
$display("(%0t) Task SetInstruction", $time);
P_TMS<=#Tp 1;
GenClk(2);
P_TMS<=#Tp 0;
475,6 → 541,7
integer i;
begin
$display("(%0t) Task ChainSelect", $time);
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
508,6 → 575,7
// Reads the ID code
task ReadIDCode;
begin
$display("(%0t) Task ReadIDCode", $time);
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
519,7 → 587,7
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
 
P_TDI<=#Tp 'hz; // tri-state
P_TDI<=#Tp 'hz; // tri-state
GenClk(1);
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
530,6 → 598,7
// Reads sample from the Trace Buffer
task ReadTraceBuffer;
begin
$display("(%0t) Task ReadTraceBuffer", $time);
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
547,13 → 616,14
endtask
 
 
// Reads the RISC register and latches the data so it is ready for reading
task ReadRISCRegister;
// Reads the CPU register and latches the data so it is ready for reading
task ReadCPURegister;
input [31:0] Address;
input [7:0] Crc;
integer i;
begin
$display("(%0t) Task ReadCPURegister", $time);
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
594,8 → 664,8
endtask
 
 
// Write the RISC register
task WriteRISCRegister;
// Write the CPU register
task WriteCPURegister;
input [31:0] Data;
input [31:0] Address;
input [`CRC_LENGTH-1:0] Crc;
602,6 → 672,7
integer i;
begin
$display("(%0t) Task WriteCPURegister", $time);
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
651,6 → 722,7
integer i;
begin
$display("(%0t) Task ReadRegister", $time);
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
700,6 → 772,7
integer i;
begin
$display("(%0t) Task WriteRegister", $time);
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
745,8 → 818,10
 
task EnableWishboneSlave;
begin
$display("(%0t) Task EnableWishboneSlave", $time);
while(1)
begin
@ (posedge Mclk);
if(wb_stb_i & wb_cyc_i) // WB access
// wait (wb_stb_i & wb_cyc_i) // WB access
begin
756,6 → 831,8
#1 wb_ack_o = 1;
if(~wb_we_i) // read
wb_dat_o = 32'hbeefdead;
wb_dat_o = {wb_adr_i[3:0], wb_adr_i[7:4], wb_adr_i[11:8], wb_adr_i[15:12],
wb_adr_i[19:16], wb_adr_i[23:20], wb_adr_i[27:24], wb_adr_i[31:28]};
if(wb_we_i & wb_stb_i & wb_cyc_i) // write
$display("\nWISHBONE write Data=%0h, Addr=%0h", wb_dat_i, wb_adr_i);
if(~wb_we_i & wb_stb_i & wb_cyc_i) // read
808,16 → 885,16
begin
if(UpdateIR_q)
case(dbg_tb.i_tap_top.LatchedJTAG_IR[`IR_LENGTH-1:0])
`EXTEST : $write("\n\tInstruction EXTEST");
`SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
`IDCODE : $write("\n\tInstruction IDCODE");
`CHAIN_SELECT : $write("\n\tInstruction CHAIN_SELECT");
`INTEST : $write("\n\tInstruction INTEST");
`CLAMP : $write("\n\tInstruction CLAMP");
`CLAMPZ : $write("\n\tInstruction CLAMPZ");
`HIGHZ : $write("\n\tInstruction HIGHZ");
`DEBUG : $write("\n\tInstruction DEBUG");
`BYPASS : $write("\n\tInstruction BYPASS");
`EXTEST : $write("\tInstruction EXTEST entered");
`SAMPLE_PRELOAD : $write("\tInstruction SAMPLE_PRELOAD entered");
`IDCODE : $write("\tInstruction IDCODE entered");
`CHAIN_SELECT : $write("\tInstruction CHAIN_SELECT entered");
`INTEST : $write("\tInstruction INTEST entered");
`CLAMP : $write("\tInstruction CLAMP entered");
`CLAMPZ : $write("\tInstruction CLAMPZ entered");
`HIGHZ : $write("\tInstruction HIGHZ entered");
`DEBUG : $write("\tInstruction DEBUG entered");
`BYPASS : $write("\tInstruction BYPASS entered");
default : $write("\n\tInstruction not valid. Instruction BYPASS activated !!!");
endcase
end
830,8 → 907,11
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected & dbg_tb.i_tap_top.UpdateDR_q)
case(dbg_tb.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
`RISC_DEBUG_CHAIN_2 : $write("\nChain RISC_DEBUG_CHAIN_2");
`RISC_TEST_CHAIN : $write("\nChain RISC_TEST_CHAIN");
`CPU_DEBUG_CHAIN_0 : $write("\nChain CPU_DEBUG_CHAIN_0");
`CPU_DEBUG_CHAIN_1 : $write("\nChain CPU_DEBUG_CHAIN_1");
`CPU_DEBUG_CHAIN_2 : $write("\nChain CPU_DEBUG_CHAIN_2");
`CPU_DEBUG_CHAIN_3 : $write("\nChain CPU_DEBUG_CHAIN_3");
`CPU_TEST_CHAIN : $write("\nChain CPU_TEST_CHAIN");
`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
`WISHBONE_SCAN_CHAIN : $write("\nChain WISHBONE_SCAN_CHAIN");
839,14 → 919,14
end
 
 
// print RISC registers read/write
// print CPU registers read/write
always @ (posedge Mclk)
begin
if(dbg_tb.i_dbg_top.RISCAccess & ~dbg_tb.i_dbg_top.RISCAccess_q & dbg_tb.i_dbg_top.RW)
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
if(dbg_tb.i_dbg_top.CPUAccess0 & ~dbg_tb.i_dbg_top.CPUAccess_q & dbg_tb.i_dbg_top.RW)
$write("\n\t\tWrite to CPU Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
else
if(dbg_tb.i_dbg_top.RISCAccess_q & ~dbg_tb.i_dbg_top.RISCAccess_q2 & ~dbg_tb.i_dbg_top.RW)
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.risc_data_i[31:0]);
if(dbg_tb.i_dbg_top.CPUAccess_q & ~dbg_tb.i_dbg_top.CPUAccess_q2 & ~dbg_tb.i_dbg_top.RW)
$write("\n\t\tRead from CPU Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.cpu_data_i[31:0]);
end
 
 
865,9 → 945,9
 
// print CRC error
`ifdef TRACE_ENABLED
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.CHAIN_SELECTSelected | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RegisterScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RiscDebugScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.WishboneScanChain));
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.CHAIN_SELECTSelected | dbg_tb.i_dbg_top.DEBUGSelected & RegisterScanChain | dbg_tb.i_dbg_top.DEBUGSelected & (CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.DEBUGSelected & WishboneScanChain));
`else // TRACE_ENABLED not enabled
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & (CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) | dbg_tb.i_tap_top.DEBUGSelected & WishboneScanChain));
`endif
 
always @ (posedge P_TCK)
877,12 → 957,12
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
else
if(dbg_tb.i_tap_top.RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
if(RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
else
if(dbg_tb.i_tap_top.RiscDebugScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
if((CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
if(dbg_tb.i_tap_top.WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
if(WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
if(CRCErrorReport)
890,6 → 970,7
$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! CrcIn should be: 0x%h\n", dbg_tb.i_dbg_top.CalculatedCrcIn);
#1000 $stop;
end
$display("\n");
end
end
 
904,7 → 985,13
TempData[31:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TempData[31:1]};
else
if(dbg_tb.i_tap_top.UpdateDR)
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
if (TempData[31:0] != `IDCODE_VALUE)
begin
$display("(%0t) ERROR: IDCODE not correct", $time);
$stop;
end
else
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
end
end
 
924,6 → 1011,22
end
 
 
// We never use following states: Exit2IR, Exit2DR, PauseIR or PauseDR
always @ (posedge P_TCK)
begin
if(dbg_tb.i_tap_top.Exit2IR | dbg_tb.i_tap_top.Exit2DR | dbg_tb.i_tap_top.PauseIR | dbg_tb.i_tap_top.PauseDR)
begin
$display("\n(%0t) ERROR: Exit2IR, Exit2DR, PauseIR or PauseDR state detected.", $time);
$display("(%0t) Simulation stopped !!!", $time);
$stop;
end
end
 
 
 
 
 
 
endmodule // TB
 
 
/trunk/rtl/verilog/dbg_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.32 2003/09/18 14:00:47 simons
// Lower two address lines must be always zero.
//
// Revision 1.31 2003/09/17 14:38:57 simons
// WB_CNTL register added, some syncronization fixes.
//
58,7 → 61,9
// Trst signal is not inverted here any more. Inverted on higher layer !!!.
//
// Revision 1.27 2002/10/10 02:42:55 mohor
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added).
// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value,
// wb_cyc_o is negated.
//
// Revision 1.26 2002/05/07 14:43:59 mohor
// mon_cntl_o signals that controls monitor mux added.
163,10 → 168,10
// Top module
module dbg_top(
// RISC signals
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
// CPU signals
cpu_clk_i, cpu_addr_o, cpu_data_i, cpu_data_o, wp_i,
bp_i, opselect_o, lsstatus_i, istatus_i,
risc_stall_o, risc_stall_all_o, risc_sel_o, reset_o,
cpu_stall_o, cpu_stall_all_o, cpu_sel_o, reset_o,
 
// WISHBONE common signals
wb_rst_i, wb_clk_i,
176,7 → 181,7
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
 
// TAP states
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, SelectDRScan,
// Instructions
IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
187,27 → 192,37
BypassRegister,
// Monitor mux control
mon_cntl_o
mon_cntl_o,
 
// Selected chains
RegisterScanChain,
CpuDebugScanChain0,
CpuDebugScanChain1,
CpuDebugScanChain2,
CpuDebugScanChain3,
WishboneScanChain
 
 
 
);
 
parameter Tp = 1;
 
 
// RISC signals
input risc_clk_i; // Master clock (RISC clock)
input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
// CPU signals
input cpu_clk_i; // Master clock (CPU clock)
input [31:0] cpu_data_i; // CPU data inputs (data that is written to the CPU registers)
input [10:0] wp_i; // Watchpoint inputs
input bp_i; // Breakpoint input
input [3:0] lsstatus_i; // Load/store status inputs
input [1:0] istatus_i; // Instruction status inputs
output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
output [31:0] risc_data_o; // RISC data output (data read from risc registers)
output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
output risc_stall_o; // Stalls the selected RISC
output risc_stall_all_o; // Stalls all the rest RISCs
output [`RISC_NUM-1:0] risc_sel_o; // Stalls all the rest RISCs
output reset_o; // Resets the RISC
output [31:0] cpu_addr_o; // CPU address output (for adressing registers within CPU)
output [31:0] cpu_data_o; // CPU data output (data read from cpu registers)
output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the cpu_data_i)
output cpu_stall_o; // Stalls the selected CPU
output cpu_stall_all_o; // Stalls all the rest CPUs
output [`CPU_NUM-1:0] cpu_sel_o; // Stalls all the rest CPUs
output reset_o; // Resets the CPU
 
 
// WISHBONE common signals
231,15 → 246,16
input Exit1DR;
input UpdateDR;
input UpdateDR_q;
input SelectDRScan;
 
input trst_in;
input tck;
input tdi;
input trst_in;
input tck;
input tdi;
 
input BypassRegister;
input BypassRegister;
 
output TDOData;
output [3:0] mon_cntl_o;
output TDOData;
output [3:0] mon_cntl_o;
 
// Defining which instruction is selected
input IDCODESelected;
246,29 → 262,38
input CHAIN_SELECTSelected;
input DEBUGSelected;
 
// Selected chains
output RegisterScanChain;
output CpuDebugScanChain0;
output CpuDebugScanChain1;
output CpuDebugScanChain2;
output CpuDebugScanChain3;
output WishboneScanChain;
 
reg wb_cyc_o;
 
reg [31:0] ADDR;
reg [31:0] DataOut;
 
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the cpu_data_i)
 
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
reg [31:0] DataReadLatch; // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
reg [31:0] DataReadLatch; // Data when reading register or CPU is latched one cpu_clk_i clock after the data is read.
reg RegAccessTck; // Indicates access to the registers (read or write)
reg RISCAccessTck0; // Indicates access to the RISC (read or write)
reg RISCAccessTck1; // Indicates access to the RISC (read or write)
reg RISCAccessTck2; // Indicates access to the RISC (read or write)
reg RISCAccessTck3; // Indicates access to the RISC (read or write)
reg CPUAccessTck0; // Indicates access to the CPU (read or write)
reg CPUAccessTck1; // Indicates access to the CPU (read or write)
reg CPUAccessTck2; // Indicates access to the CPU (read or write)
reg CPUAccessTck3; // Indicates access to the CPU (read or write)
reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
reg RW; // Read/Write bit
reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
reg CrcMatch_q;
 
reg RegAccess_q; // Delayed signals used for accessing the registers
reg RegAccess_q2; // Delayed signals used for accessing the registers
reg RISCAccess_q; // Delayed signals used for accessing the RISC
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
reg RISCAccess_q3; // Delayed signals used for accessing the RISC
reg CPUAccess_q; // Delayed signals used for accessing the CPU
reg CPUAccess_q2; // Delayed signals used for accessing the CPU
reg CPUAccess_q3; // Delayed signals used for accessing the CPU
 
reg wb_AccessTck; // Indicates access to the WISHBONE
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
282,31 → 307,24
wire trst;
 
 
wire [31:0] RegDataIn; // Data from registers (read data)
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
wire [31:0] RegDataIn; // Data from registers (read data)
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
 
wire RiscStall_reg; // RISC is stalled by setting the register bit
wire RiscReset_reg; // RISC is reset by setting the register bit
wire RiscStall_trace; // RISC is stalled by trace module
wire CpuStall_reg; // CPU is stalled by setting the register bit
wire CpuReset_reg; // CPU is reset by setting the register bit
wire CpuStall_trace; // CPU is stalled by trace module
wire RegisterScanChain; // Register Scan chain selected
wire RiscDebugScanChain0; // Risc Debug Scan chain selected
wire RiscDebugScanChain1; // Risc Debug Scan chain selected
wire RiscDebugScanChain2; // Risc Debug Scan chain selected
wire RiscDebugScanChain3; // Risc Debug Scan chain selected
wire WishboneScanChain; // WISHBONE Scan chain selected
wire CpuStall_read_access_0; // Stalling Cpu because of the read access (SPR read)
wire CpuStall_read_access_1; // Stalling Cpu because of the read access (SPR read)
wire CpuStall_read_access_2; // Stalling Cpu because of the read access (SPR read)
wire CpuStall_read_access_3; // Stalling Cpu because of the read access (SPR read)
wire CpuStall_write_access_0; // Stalling Cpu because of the write access (SPR write)
wire CpuStall_write_access_1; // Stalling Cpu because of the write access (SPR write)
wire CpuStall_write_access_2; // Stalling Cpu because of the write access (SPR write)
wire CpuStall_write_access_3; // Stalling Cpu because of the write access (SPR write)
wire CpuStall_access; // Stalling Cpu because of the read or write access
 
wire RiscStall_read_access_0; // Stalling RISC because of the read access (SPR read)
wire RiscStall_read_access_1; // Stalling RISC because of the read access (SPR read)
wire RiscStall_read_access_2; // Stalling RISC because of the read access (SPR read)
wire RiscStall_read_access_3; // Stalling RISC because of the read access (SPR read)
wire RiscStall_write_access_0; // Stalling RISC because of the write access (SPR write)
wire RiscStall_write_access_1; // Stalling RISC because of the write access (SPR write)
wire RiscStall_write_access_2; // Stalling RISC because of the write access (SPR write)
wire RiscStall_write_access_3; // Stalling RISC because of the write access (SPR write)
wire RiscStall_access; // Stalling RISC because of the read or write access
 
wire BitCounter_Lt4;
wire BitCounter_Eq5;
wire BitCounter_Eq32;
374,7 → 392,7
wire [47:0] Trace_Data; // Trace data
 
wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
// data is set to the risc_data_i)
// data is set to the cpu_data_i)
wire BitCounter_Lt40;
 
`endif
410,8 → 428,8
else
if(DEBUGSelected & ShiftDR)
begin
if(RiscDebugScanChain0 | RiscDebugScanChain1 |
RiscDebugScanChain2 | RiscDebugScanChain3 | WishboneScanChain)
if(CpuDebugScanChain0 | CpuDebugScanChain1 |
CpuDebugScanChain2 | CpuDebugScanChain3 | WishboneScanChain)
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
else
if(RegisterScanChain)
419,7 → 437,7
end
end
wire [73:0] RISC_Data;
wire [73:0] CPU_Data;
wire [46:0] Register_Data;
wire [73:0] WISHBONE_Data;
wire [12:0] chain_sel_data;
427,36 → 445,49
wire [1:0] wb_cntl_o;
 
 
reg select_crc_out;
reg crc_bypassed;
always @ (posedge tck or posedge trst)
begin
if(trst)
select_crc_out <= 0;
else
if( RegisterScanChain & BitCounter_Eq5 |
RiscDebugScanChain0 & BitCounter_Eq32 |
RiscDebugScanChain1 & BitCounter_Eq32 |
RiscDebugScanChain2 & BitCounter_Eq32 |
RiscDebugScanChain3 & BitCounter_Eq32 |
WishboneScanChain & BitCounter_Eq32 )
select_crc_out <=#Tp tdi;
else
if(CHAIN_SELECTSelected)
select_crc_out <=#Tp 1;
else
if(UpdateDR)
select_crc_out <=#Tp 0;
crc_bypassed <= 0;
else if (CHAIN_SELECTSelected)
crc_bypassed <=#Tp 1;
else if(
RegisterScanChain & BitCounter_Eq5 |
CpuDebugScanChain0 & BitCounter_Eq32 |
CpuDebugScanChain1 & BitCounter_Eq32 |
CpuDebugScanChain2 & BitCounter_Eq32 |
CpuDebugScanChain3 & BitCounter_Eq32 |
WishboneScanChain & BitCounter_Eq32 )
crc_bypassed <=#Tp tdi; // when write is performed.
end
 
wire [8:0] send_crc;
reg [7:0] send_crc;
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
 
assign send_crc = select_crc_out? {9{BypassRegister}} : // Calculated CRC is returned when read operation is
{CalculatedCrcOut, 1'b0} ; // performed, else received crc is returned (loopback).
// Calculated CRC is returned when read operation is performed, else received crc is returned (loopback).
always @ (crc_bypassed or CrcMatch or CrcMatch_q or BypassRegister or CalculatedCrcOut)
begin
if (crc_bypassed)
begin
if (CrcMatch | CrcMatch_q) // When crc is looped back, first bit is not inverted
send_crc = {8{BypassRegister}}; // since it caused the error. By inverting it we would
else // get ok crc.
send_crc = {8{~BypassRegister}};
end
else
begin
if (CrcMatch)
send_crc = {8{CalculatedCrcOut}};
else
send_crc = {8{~CalculatedCrcOut}};
end
end
 
assign RISC_Data = {send_crc, DataReadLatch, 33'h0};
assign Register_Data = {send_crc, DataReadLatch, 6'h0};
assign WISHBONE_Data = {send_crc, WBReadLatch, 31'h0, WBInProgress, WBErrorLatch};
assign chain_sel_data = {send_crc, 4'h0};
assign CPU_Data = {send_crc, DataReadLatch, 33'h0, 1'b0};
assign Register_Data = {send_crc, DataReadLatch, 6'h0, 1'b0};
assign WISHBONE_Data = {send_crc, WBReadLatch, 31'h0, WBInProgress, WBErrorLatch, 1'b0};
assign chain_sel_data = {send_crc, 4'h0, 1'b0};
`ifdef TRACE_ENABLED
494,8 → 525,8
else
if(DEBUGSelected)
begin
if(RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3)
TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
if(CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3)
TDOData <= #Tp CPU_Data[BitCounter]; // Data read from CPU in the previous cycle is shifted out
else
if(RegisterScanChain)
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
531,15 → 562,15
else
if(ShiftDR & DEBUGSelected)
begin
if((RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3) & BitCounter > 73)
if((CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) & BitCounter > 73)
begin
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
$display("\n%m Error: BitCounter is bigger then CPU_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
$stop;
end
else
if(RegisterScanChain & BitCounter > 46)
begin
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
$display("\n%m Error: BitCounter is bigger then Register_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
$stop;
end
else
594,7 → 625,7
/**********************************************************************************
* *
* Register read/write logic *
* RISC registers read/write logic *
* CPU registers read/write logic *
* *
**********************************************************************************/
always @ (posedge tck or posedge trst)
605,10 → 636,10
DataOut[31:0] <=#Tp 32'h0;
RW <=#Tp 1'b0;
RegAccessTck <=#Tp 1'b0;
RISCAccessTck0 <=#Tp 1'b0;
RISCAccessTck1 <=#Tp 1'b0;
RISCAccessTck2 <=#Tp 1'b0;
RISCAccessTck3 <=#Tp 1'b0;
CPUAccessTck0 <=#Tp 1'b0;
CPUAccessTck1 <=#Tp 1'b0;
CPUAccessTck2 <=#Tp 1'b0;
CPUAccessTck3 <=#Tp 1'b0;
wb_AccessTck <=#Tp 1'h0;
end
else
630,36 → 661,36
wb_AccessTck <=#Tp 1'b1; //
end
else
if(RiscDebugScanChain0)
if(CpuDebugScanChain0)
begin
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
RISCAccessTck0 <=#Tp 1'b1;
CPUAccessTck0 <=#Tp 1'b1;
end
else
if(RiscDebugScanChain1)
if(CpuDebugScanChain1)
begin
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
RISCAccessTck1 <=#Tp 1'b1;
CPUAccessTck1 <=#Tp 1'b1;
end
else
if(RiscDebugScanChain2)
if(CpuDebugScanChain2)
begin
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
RISCAccessTck2 <=#Tp 1'b1;
CPUAccessTck2 <=#Tp 1'b1;
end
else
if(RiscDebugScanChain3)
if(CpuDebugScanChain3)
begin
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
RISCAccessTck3 <=#Tp 1'b1;
CPUAccessTck3 <=#Tp 1'b1;
end
end
else
666,10 → 697,10
begin
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
wb_AccessTck <=#Tp 1'b0;
RISCAccessTck0 <=#Tp 1'b0;
RISCAccessTck1 <=#Tp 1'b0;
RISCAccessTck2 <=#Tp 1'b0;
RISCAccessTck3 <=#Tp 1'b0;
CPUAccessTck0 <=#Tp 1'b0;
CPUAccessTck1 <=#Tp 1'b0;
CPUAccessTck2 <=#Tp 1'b0;
CPUAccessTck3 <=#Tp 1'b0;
end
end
 
709,8 → 740,8
wb_sel_o = 4'hx;
end
// Synchronizing the RegAccess signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
// Synchronizing the RegAccess signal to cpu_clk_i clock
dbg_sync_clk1_clk2 syn1 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(RegAccessTck), .sync_out(RegAccess)
);
 
719,24 → 750,24
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
);
 
// Synchronizing the RISCAccess0 signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn3 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(RISCAccessTck0), .sync_out(RISCAccess0)
// Synchronizing the CPUAccess0 signal to cpu_clk_i clock
dbg_sync_clk1_clk2 syn3 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(CPUAccessTck0), .sync_out(CPUAccess0)
);
 
// Synchronizing the RISCAccess1 signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(RISCAccessTck1), .sync_out(RISCAccess1)
// Synchronizing the CPUAccess1 signal to cpu_clk_i clock
dbg_sync_clk1_clk2 syn4 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(CPUAccessTck1), .sync_out(CPUAccess1)
);
 
// Synchronizing the RISCAccess2 signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn5 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(RISCAccessTck2), .sync_out(RISCAccess2)
// Synchronizing the CPUAccess2 signal to cpu_clk_i clock
dbg_sync_clk1_clk2 syn5 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(CPUAccessTck2), .sync_out(CPUAccess2)
);
 
// Synchronizing the RISCAccess3 signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn6 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(RISCAccessTck3), .sync_out(RISCAccess3)
// Synchronizing the CPUAccess3 signal to cpu_clk_i clock
dbg_sync_clk1_clk2 syn6 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(CPUAccessTck3), .sync_out(CPUAccess3)
);
 
 
743,37 → 774,37
 
 
 
// Delayed signals used for accessing registers and RISC
always @ (posedge risc_clk_i or posedge wb_rst_i)
// Delayed signals used for accessing registers and CPU
always @ (posedge cpu_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RegAccess_q <=#Tp 1'b0;
RegAccess_q2 <=#Tp 1'b0;
RISCAccess_q <=#Tp 1'b0;
RISCAccess_q2 <=#Tp 1'b0;
RISCAccess_q3 <=#Tp 1'b0;
CPUAccess_q <=#Tp 1'b0;
CPUAccess_q2 <=#Tp 1'b0;
CPUAccess_q3 <=#Tp 1'b0;
end
else
begin
RegAccess_q <=#Tp RegAccess;
RegAccess_q2 <=#Tp RegAccess_q;
RISCAccess_q <=#Tp RISCAccess0 | RISCAccess1 | RISCAccess2 | RISCAccess3;
RISCAccess_q2 <=#Tp RISCAccess_q;
RISCAccess_q3 <=#Tp RISCAccess_q2;
CPUAccess_q <=#Tp CPUAccess0 | CPUAccess1 | CPUAccess2 | CPUAccess3;
CPUAccess_q2 <=#Tp CPUAccess_q;
CPUAccess_q3 <=#Tp CPUAccess_q2;
end
end
 
// Chip select and read/write signals for accessing RISC
assign RiscStall_write_access_0 = RISCAccess0 & ~RISCAccess_q2 & RW;
assign RiscStall_read_access_0 = RISCAccess0 & ~RISCAccess_q2 & ~RW;
assign RiscStall_write_access_1 = RISCAccess1 & ~RISCAccess_q2 & RW;
assign RiscStall_read_access_1 = RISCAccess1 & ~RISCAccess_q2 & ~RW;
assign RiscStall_write_access_2 = RISCAccess2 & ~RISCAccess_q2 & RW;
assign RiscStall_read_access_2 = RISCAccess2 & ~RISCAccess_q2 & ~RW;
assign RiscStall_write_access_3 = RISCAccess3 & ~RISCAccess_q2 & RW;
assign RiscStall_read_access_3 = RISCAccess3 & ~RISCAccess_q2 & ~RW;
assign RiscStall_access = (RISCAccess0 | RISCAccess1 | RISCAccess2 | RISCAccess3) & ~RISCAccess_q3;
// Chip select and read/write signals for accessing CPU
assign CpuStall_write_access_0 = CPUAccess0 & ~CPUAccess_q2 & RW;
assign CpuStall_read_access_0 = CPUAccess0 & ~CPUAccess_q2 & ~RW;
assign CpuStall_write_access_1 = CPUAccess1 & ~CPUAccess_q2 & RW;
assign CpuStall_read_access_1 = CPUAccess1 & ~CPUAccess_q2 & ~RW;
assign CpuStall_write_access_2 = CPUAccess2 & ~CPUAccess_q2 & RW;
assign CpuStall_read_access_2 = CPUAccess2 & ~CPUAccess_q2 & ~RW;
assign CpuStall_write_access_3 = CPUAccess3 & ~CPUAccess_q2 & RW;
assign CpuStall_read_access_3 = CPUAccess3 & ~CPUAccess_q2 & ~RW;
assign CpuStall_access = (CPUAccess0 | CPUAccess1 | CPUAccess2 | CPUAccess3) & ~CPUAccess_q3;
 
 
reg wb_Access_wbClk_q;
871,50 → 902,50
end
 
 
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
// Whan enabled, TRACE stalls CPU while saving data to the trace buffer.
`ifdef TRACE_ENABLED
assign risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
assign cpu_stall_o = CpuStall_access | CpuStall_reg | CpuStall_trace ;
`else
assign risc_stall_o = RiscStall_access | RiscStall_reg;
assign cpu_stall_o = CpuStall_access | CpuStall_reg;
`endif
 
assign reset_o = RiscReset_reg;
assign reset_o = CpuReset_reg;
 
 
`ifdef TRACE_ENABLED
always @ (RiscStall_write_access_0 or RiscStall_write_access_1 or
RiscStall_write_access_2 or RiscStall_write_access_2 or
RiscStall_read_access_0 or RiscStall_read_access_1 or
RiscStall_read_access_2 or RiscStall_read_access_3 or opselect_trace)
always @ (CpuStall_write_access_0 or CpuStall_write_access_1 or
CpuStall_write_access_2 or CpuStall_write_access_2 or
CpuStall_read_access_0 or CpuStall_read_access_1 or
CpuStall_read_access_2 or CpuStall_read_access_3 or opselect_trace)
`else
always @ (RiscStall_write_access_0 or RiscStall_write_access_1 or
RiscStall_write_access_2 or RiscStall_write_access_3 or
RiscStall_read_access_0 or RiscStall_read_access_1 or
RiscStall_read_access_2 or RiscStall_read_access_3)
always @ (CpuStall_write_access_0 or CpuStall_write_access_1 or
CpuStall_write_access_2 or CpuStall_write_access_3 or
CpuStall_read_access_0 or CpuStall_read_access_1 or
CpuStall_read_access_2 or CpuStall_read_access_3)
`endif
begin
if(RiscStall_write_access_0)
if(CpuStall_write_access_0)
opselect_o = `DEBUG_WRITE_0;
else
if(RiscStall_read_access_0)
if(CpuStall_read_access_0)
opselect_o = `DEBUG_READ_0;
else
if(RiscStall_write_access_1)
if(CpuStall_write_access_1)
opselect_o = `DEBUG_WRITE_1;
else
if(RiscStall_read_access_1)
if(CpuStall_read_access_1)
opselect_o = `DEBUG_READ_1;
else
if(RiscStall_write_access_2)
if(CpuStall_write_access_2)
opselect_o = `DEBUG_WRITE_2;
else
if(RiscStall_read_access_2)
if(CpuStall_read_access_2)
opselect_o = `DEBUG_READ_2;
else
if(RiscStall_write_access_3)
if(CpuStall_write_access_3)
opselect_o = `DEBUG_WRITE_3;
else
if(RiscStall_read_access_3)
if(CpuStall_read_access_3)
opselect_o = `DEBUG_READ_3;
else
`ifdef TRACE_ENABLED
925,21 → 956,21
end
 
 
// Latching data read from RISC or registers
always @ (posedge risc_clk_i or posedge wb_rst_i)
// Latching data read from CPU or registers
always @ (posedge cpu_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
DataReadLatch[31:0]<=#Tp 0;
else
if(RISCAccess_q & ~RISCAccess_q2)
DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
if(CPUAccess_q & ~CPUAccess_q2)
DataReadLatch[31:0]<=#Tp cpu_data_i[31:0];
else
if(RegAccess_q & ~RegAccess_q2)
DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
end
 
assign risc_addr_o = ADDR;
assign risc_data_o = DataOut;
assign cpu_addr_o = ADDR;
assign cpu_data_o = DataOut;
 
 
 
951,14 → 982,14
`ifdef TRACE_ENABLED
 
// Synchronizing the trace read buffer signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
// Synchronizing the trace read buffer signal to cpu_clk_i clock
dbg_sync_clk1_clk2 syn4 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
);
 
 
 
always @(posedge risc_clk_i or posedge wb_rst_i)
always @(posedge cpu_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
ReadTraceBuffer_q <=#Tp 0;
1015,7 → 1046,7
* *
**********************************************************************************/
dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(risc_clk_i),
.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(cpu_clk_i),
.bp(bp_i), .reset(wb_rst_i),
`ifdef TRACE_ENABLED
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
1035,8 → 1066,8
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
`endif
.risc_stall(RiscStall_reg), .risc_stall_all(risc_stall_all_o), .risc_sel(risc_sel_o),
.risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o), .wb_cntl_o(wb_cntl_o)
.cpu_stall(CpuStall_reg), .cpu_stall_all(cpu_stall_all_o), .cpu_sel(cpu_sel_o),
.cpu_reset(CpuReset_reg), .mon_cntl_o(mon_cntl_o), .wb_cntl_o(wb_cntl_o)
 
);
 
1054,7 → 1085,6
**********************************************************************************/
wire AsyncResetCrc = trst;
wire SyncResetCrc = UpdateDR_q;
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
 
assign BitCounter_Lt4 = BitCounter<4;
assign BitCounter_Eq5 = BitCounter==5;
1067,71 → 1097,98
`endif
 
 
wire EnableCrcIn = ShiftDR &
// wire EnableCrcIn = ShiftDR &
// ( (CHAIN_SELECTSelected & BitCounter_Lt4) |
// ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
// ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
// ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
// ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
// ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
// ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
// );
 
wire EnableCrc = ShiftDR &
( (CHAIN_SELECTSelected & BitCounter_Lt4) |
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
((DEBUGSelected & RiscDebugScanChain0) & BitCounter_Lt65)|
((DEBUGSelected & RiscDebugScanChain1) & BitCounter_Lt65)|
((DEBUGSelected & RiscDebugScanChain2) & BitCounter_Lt65)|
((DEBUGSelected & RiscDebugScanChain3) & BitCounter_Lt65)|
((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
);
 
wire EnableCrcOut= ShiftDR &
(
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
((DEBUGSelected & RiscDebugScanChain0) & BitCounter_Lt65)|
((DEBUGSelected & RiscDebugScanChain1) & BitCounter_Lt65)|
((DEBUGSelected & RiscDebugScanChain2) & BitCounter_Lt65)|
((DEBUGSelected & RiscDebugScanChain3) & BitCounter_Lt65)|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
`ifdef TRACE_ENABLED
|
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
`endif
);
);
 
// wire EnableCrcOut= ShiftDR &
// (
// ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
// ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
// ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
// ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
// ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
// ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
// `ifdef TRACE_ENABLED
// |
// ((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
// `endif
// );
 
// Calculating crc for input data
dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
//dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrc), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
.crc_out(CalculatedCrcIn), .clk(tck));
 
// Calculating crc for output data
dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
//dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrc), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
.crc_out(CalculatedCrcOut), .clk(tck));
 
 
// Generating CrcMatch signal
reg [3:0] crc_cnt;
always @ (posedge tck or posedge trst)
begin
if (trst)
crc_cnt <= 0;
else if (Exit1DR)
crc_cnt <=#Tp 0;
// else if ((~EnableCrcIn) & ShiftDR)
else if ((~EnableCrc) & ShiftDR)
crc_cnt <=#Tp crc_cnt + 1'b1;
end
 
 
// Generating CrcMatch signal.
always @ (posedge tck or posedge trst)
begin
if(trst)
CrcMatch <=#Tp 1'b0;
else
if(Exit1DR)
CrcMatch <=#Tp 1'b1;
else if (SelectDRScan)
CrcMatch <=#Tp 1'b1;
// else if ((~EnableCrcIn) & ShiftDR)
else if ((~EnableCrc) & ShiftDR)
begin
if(CHAIN_SELECTSelected)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
else
begin
if(RegisterScanChain)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
else
if(RiscDebugScanChain0 | RiscDebugScanChain1 | RiscDebugScanChain2 | RiscDebugScanChain3)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
else
if(WishboneScanChain)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
end
if (tdi != CalculatedCrcIn[crc_cnt])
CrcMatch <=#Tp 1'b0;
end
end
 
 
// Generating CrcMatch_q signal.
always @ (posedge tck or posedge trst)
begin
CrcMatch_q <=#Tp CrcMatch;
end
 
// Active chain
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
assign RiscDebugScanChain0 = Chain == `RISC_DEBUG_CHAIN_0;
assign RiscDebugScanChain1 = Chain == `RISC_DEBUG_CHAIN_1;
assign RiscDebugScanChain2 = Chain == `RISC_DEBUG_CHAIN_2;
assign RiscDebugScanChain3 = Chain == `RISC_DEBUG_CHAIN_3;
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
assign CpuDebugScanChain0 = Chain == `CPU_DEBUG_CHAIN_0;
assign CpuDebugScanChain1 = Chain == `CPU_DEBUG_CHAIN_1;
assign CpuDebugScanChain2 = Chain == `CPU_DEBUG_CHAIN_2;
assign CpuDebugScanChain3 = Chain == `CPU_DEBUG_CHAIN_3;
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
 
`ifdef TRACE_ENABLED
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
1149,9 → 1206,9
* *
**********************************************************************************/
`ifdef TRACE_ENABLED
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
.LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
.Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(cpu_data_i), .OpSelect(opselect_trace),
.LsStatus(lsstatus_i), .IStatus(istatus_i), .CpuStall_O(CpuStall_trace),
.Mclk(cpu_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
.WpTrigger(WpTrigger),
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
/trunk/rtl/verilog/dbg_registers.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2003/09/17 14:38:57 simons
// WB_CNTL register added, some syncronization fixes.
//
// Revision 1.11 2003/07/31 14:01:53 simons
// Lapsus fixed.
//
105,7 → 108,7
WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
LSSStopValid, IStopValid,
`endif
risc_stall, risc_stall_all, risc_sel, risc_reset, mon_cntl_o, wb_cntl_o
cpu_stall, cpu_stall_all, cpu_sel, cpu_reset, mon_cntl_o, wb_cntl_o
);
 
parameter Tp = 1;
168,16 → 171,16
output RecordINSTR;
`endif
 
output risc_stall;
output risc_stall_all;
output [`RISC_NUM-1:0] risc_sel;
output risc_reset;
output cpu_stall;
output cpu_stall_all;
output [`CPU_NUM-1:0] cpu_sel;
output cpu_reset;
output [3:0] mon_cntl_o;
output [1:0] wb_cntl_o;
 
wire MODER_Acc = (address == `MODER_ADR) & access;
wire RISCOP_Acc = (address == `RISCOP_ADR) & access;
wire RISCSEL_Acc = (address == `RISCSEL_ADR) & access;
wire CPUOP_Acc = (address == `CPUOP_ADR) & access;
wire CPUSEL_Acc = (address == `CPUSEL_ADR) & access;
wire MON_CNTL_Acc = (address == `MON_CNTL_ADR) & access;
wire WB_CNTL_Acc = (address == `WB_CNTL_ADR) & access;
`ifdef TRACE_ENABLED
189,8 → 192,8
 
wire MODER_Wr = MODER_Acc & rw;
wire RISCOP_Wr = RISCOP_Acc & rw;
wire RISCSEL_Wr = RISCSEL_Acc & rw;
wire CPUOP_Wr = CPUOP_Acc & rw;
wire CPUSEL_Wr = CPUSEL_Acc & rw;
wire MON_CNTL_Wr = MON_CNTL_Acc & rw;
wire WB_CNTL_Wr = WB_CNTL_Acc & rw;
`ifdef TRACE_ENABLED
203,8 → 206,8
 
wire MODER_Rd = MODER_Acc & ~rw;
wire RISCOP_Rd = RISCOP_Acc & ~rw;
wire RISCSEL_Rd = RISCSEL_Acc & ~rw;
wire CPUOP_Rd = CPUOP_Acc & ~rw;
wire CPUSEL_Rd = CPUSEL_Acc & ~rw;
wire MON_CNTL_Rd = MON_CNTL_Acc & ~rw;
wire WB_CNTL_Rd = WB_CNTL_Acc & ~rw;
`ifdef TRACE_ENABLED
216,8 → 219,8
 
 
wire [31:0] MODEROut;
wire [2:1] RISCOPOut;
wire [`RISC_NUM-1:0] RISCSELOut;
wire [2:1] CPUOPOut;
wire [`CPU_NUM-1:0] CPUSELOut;
wire [3:0] MONCNTLOut;
wire [1:0] WB_CNTLOut;
 
237,21 → 240,21
`endif
 
 
reg RiscStallBp;
reg CpuStallBp;
always @(posedge clk or posedge reset)
begin
if(reset)
RiscStallBp <= 1'b0;
CpuStallBp <= 1'b0;
else
if(bp) // Breakpoint sets bit
RiscStallBp <= 1'b1;
CpuStallBp <= 1'b1;
else
if(RISCOP_Wr) // Register access can set or clear bit
RiscStallBp <= data_in[0];
if(CPUOP_Wr) // Register access can set or clear bit
CpuStallBp <= data_in[0];
end
 
dbg_register #(2, 0) RISCOP (.data_in(data_in[2:1]), .data_out(RISCOPOut[2:1]), .write(RISCOP_Wr), .clk(clk), .reset(reset));
dbg_register #(`RISC_NUM, 1) RISCSEL (.data_in(data_in[`RISC_NUM-1:0]), .data_out(RISCSELOut), .write(RISCSEL_Wr), .clk(clk), .reset(reset));
dbg_register #(2, 0) CPUOP (.data_in(data_in[2:1]), .data_out(CPUOPOut[2:1]), .write(CPUOP_Wr), .clk(clk), .reset(reset));
dbg_register #(`CPU_NUM, 1) CPUSEL (.data_in(data_in[`CPU_NUM-1:0]), .data_out(CPUSELOut), .write(CPUSEL_Wr), .clk(clk), .reset(reset));
dbg_register #(4, `MON_CNTL_DEF) MONCNTL (.data_in(data_in[3:0]), .data_out(MONCNTLOut[3:0]), .write(MON_CNTL_Wr), .clk(clk), .reset(reset));
dbg_register #(2, 0) WBCNTL (.data_in(data_in[1:0]), .data_out(WB_CNTLOut[1:0]), .write(WB_CNTL_Wr), .clk(clk), .reset(reset));
 
270,9 → 273,9
begin
if(MODER_Rd) data_out<= #Tp MODEROut;
else
if(RISCOP_Rd) data_out<= #Tp {29'h0, RISCOPOut[2:1], risc_stall};
if(CPUOP_Rd) data_out<= #Tp {29'h0, CPUOPOut[2:1], cpu_stall};
else
if(RISCSEL_Rd) data_out<= #Tp {{(32-`RISC_NUM){1'b0}}, RISCSELOut};
if(CPUSEL_Rd) data_out<= #Tp {{(32-`CPU_NUM){1'b0}}, CPUSELOut};
else
if(MON_CNTL_Rd) data_out<= #Tp {28'h0, MONCNTLOut};
else
334,10 → 337,10
assign RecordINSTR = RECSELOut[6];
`endif
 
assign risc_stall = bp | RiscStallBp; // bp asynchronously sets the risc_stall, then RiscStallBp (from register) holds it active
assign risc_stall_all = RISCOPOut[2]; // this signal is used to stall all the cpus except the one that is selected in riscsel register
assign risc_sel = RISCSELOut;
assign risc_reset = RISCOPOut[1];
assign cpu_stall = bp | CpuStallBp; // bp asynchronously sets the cpu_stall, then CpuStallBp (from register) holds it active
assign cpu_stall_all = CPUOPOut[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register
assign cpu_sel = CPUSELOut;
assign cpu_reset = CPUOPOut[1];
assign mon_cntl_o = MONCNTLOut;
assign wb_cntl_o = WB_CNTLOut;
 
/trunk/rtl/verilog/tap_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/10/21 09:48:31 simons
// Mbist support added.
//
// Revision 1.7 2002/11/06 14:30:10 mohor
// Trst active high. Inverted on higher layer.
//
84,7 → 87,7
tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,
 
// TAP states
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR, SelectDRScan,
// Instructions
IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected, MBISTSelected,
96,7 → 99,17
bs_chain_i,
 
// From Mbist Chain
mbist_so_i
mbist_so_i,
 
// Selected chains
RegisterScanChain,
CpuDebugScanChain0,
CpuDebugScanChain1,
CpuDebugScanChain2,
CpuDebugScanChain3,
WishboneScanChain
 
 
);
 
116,6 → 129,7
output UpdateDR;
output UpdateDR_q;
output CaptureDR;
output SelectDRScan;
 
// Instructions
output IDCODESelected;
133,6 → 147,15
// From Mbist Chain
input mbist_so_i;
 
// Selected chains
input RegisterScanChain;
input CpuDebugScanChain0;
input CpuDebugScanChain1;
input CpuDebugScanChain2;
input CpuDebugScanChain3;
input WishboneScanChain;
 
 
reg tdo_pad_o;
 
// TAP states
174,11 → 197,7
wire TMS;
wire tdi;
 
wire RiscDebugScanChain;
wire WishboneScanChain;
wire RegisterScanChain;
 
 
assign trst = trst_pad_i; // trst_pad_i is active high !!! Inverted on higher layer
assign tck = tck_pad_i;
assign TMS = tms_pad_i;
429,9 → 448,11
 
 
//TDO is changing on the falling edge of tck
always @ (negedge tck)
always @ (negedge tck or posedge trst)
begin
if(ShiftIR)
if (trst)
TDOInstruction <= #Tp 1'b0;
else if(ShiftIR)
TDOInstruction <= #Tp JTAG_IR[0];
end
 
464,15 → 485,15
end
else
if(CHAIN_SELECTSelected & ShiftDR)
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
JTAG_DR_IN[11:0] <= #Tp {tdi, JTAG_DR_IN[11:1]};
else
if(DEBUGSelected & ShiftDR)
begin
if(RiscDebugScanChain | WishboneScanChain)
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
if(CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3 | WishboneScanChain)
JTAG_DR_IN[72:0] <= #Tp {tdi, JTAG_DR_IN[72:1]};
else
if(RegisterScanChain)
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
JTAG_DR_IN[45:0] <= #Tp {tdi, JTAG_DR_IN[45:1]};
end
end
495,9 → 516,11
**********************************************************************************/
reg TDOBypassed;
 
always @ (posedge tck)
always @ (posedge tck or posedge trst)
begin
if(ShiftDR)
if (trst)
BypassRegister<=#Tp 1'b0;
else if(ShiftDR)
BypassRegister<=#Tp tdi;
end
 
/trunk/rtl/verilog/dbg_defines.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2003/10/21 09:48:31 simons
// Mbist support added.
//
// Revision 1.12 2003/09/17 14:38:57 simons
// WB_CNTL register added, some syncronization fixes.
//
100,14 → 103,14
//`define TRACE_ENABLED // Uncomment this define to activate the trace
 
// Define number of cpus supported by the dbg interface
`define RISC_NUM 2
`define CPU_NUM 2
 
// Define IDCODE Value
`define IDCODE_VALUE 32'h14951185
 
// Define master clock (RISC clock)
//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
// Define master clock (CPU clock)
//`define CPU_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
`define CPU_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
 
// Length of the Instruction register
`define IR_LENGTH 4
156,14 → 159,14
 
// Chains
`define GLOBAL_BS_CHAIN 4'b0000
`define RISC_DEBUG_CHAIN_2 4'b0001
`define RISC_TEST_CHAIN 4'b0010
`define CPU_DEBUG_CHAIN_2 4'b0001
`define CPU_TEST_CHAIN 4'b0010
`define TRACE_TEST_CHAIN 4'b0011
`define REGISTER_SCAN_CHAIN 4'b0100
`define WISHBONE_SCAN_CHAIN 4'b0101
`define RISC_DEBUG_CHAIN_0 4'b0110
`define RISC_DEBUG_CHAIN_1 4'b0111
`define RISC_DEBUG_CHAIN_3 4'b1000
`define CPU_DEBUG_CHAIN_0 4'b0110
`define CPU_DEBUG_CHAIN_1 4'b0111
`define CPU_DEBUG_CHAIN_3 4'b1000
 
// Registers addresses
`define MODER_ADR 5'h00
170,8 → 173,8
`define TSEL_ADR 5'h01
`define QSEL_ADR 5'h02
`define SSEL_ADR 5'h03
`define RISCOP_ADR 5'h04
`define RISCSEL_ADR 5'h05
`define CPUOP_ADR 5'h04
`define CPUSEL_ADR 5'h05
`define RECSEL_ADR 5'h10
`define MON_CNTL_ADR 5'h11
`define WB_CNTL_ADR 5'h12
182,6 → 185,6
`define TSEL_DEF 32'h00000000
`define QSEL_DEF 32'h00000000
`define SSEL_DEF 32'h00000000
`define RISCOP_DEF 2'h0
`define CPUOP_DEF 2'h0
`define RECSEL_DEF 7'h0
`define MON_CNTL_DEF 4'h0
/trunk/rtl/verilog/dbg_trace.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.5 2001/10/19 11:40:01 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
79,7 → 82,7
`include "dbg_defines.v"
 
// module Trace
module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,
module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, CpuStall_O,
Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,
WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
152,7 → 155,7
 
 
output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
output RiscStall_O; // CPU stall (stalls the RISC)
output CpuStall_O; // CPU stall (stalls the RISC)
output [39:0] TraceChain; // Scan shain from the trace module
 
reg TraceEnable_d;
163,8 → 166,8
reg [`TRACECOUNTERWIDTH:0] Counter;
reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
reg RiscStall;
reg RiscStall_q;
reg CpuStall;
reg CpuStall_q;
reg [`OPSELECTWIDTH-1:0] StallCounter;
 
reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
302,7 → 305,7
 
/**********************************************************************************
* *
* RiscStall, counter and pointers generation *
* CpuStall, counter and pointers generation *
* *
**********************************************************************************/
reg BufferFullDetected;
310,8 → 313,8
 
wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
wire IncrementCounter = RiscStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
wire IncrementPointer = RiscStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
wire IncrementCounter = CpuStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
wire IncrementPointer = CpuStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
 
wire WriteSample = IncrementPointer;
 
330,7 → 333,7
Qualifier_mclk<=#Tp Qualifier;
BufferFull_q<=#Tp BufferFull;
BufferFull_2q<=#Tp BufferFull_q;
RiscStall_q <=#Tp RiscStall_O;
CpuStall_q <=#Tp CpuStall_O;
end
 
 
341,7 → 344,7
 
//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
 
wire SyncSetCpuStall = RiscStall_O & ~RiscStall_q |
wire SyncSetCpuStall = CpuStall_O & ~CpuStall_q |
Qualifier_mclk & TriggerLatch &
(
(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
355,7 → 358,7
( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
);
 
assign RiscStall_O = FirstCpuStall | RiscStall;
assign CpuStall_O = FirstCpuStall | CpuStall;
 
 
always @(posedge Mclk or posedge Reset)
405,13 → 408,13
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
RiscStall<=#Tp 0;
CpuStall<=#Tp 0;
else
if(SyncResetCpuStall)
RiscStall<=#Tp 0;
CpuStall<=#Tp 0;
else
if(SyncSetCpuStall)
RiscStall<=#Tp 1;
CpuStall<=#Tp 1;
end
 
 
420,7 → 423,7
if(ResetStallCounter)
StallCounter<=#Tp 0;
else
if(RiscStall_q & (~BufferFull | ContinMode))
if(CpuStall_q & (~BufferFull | ContinMode))
StallCounter<=#Tp StallCounter+1;
end
 

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